[PATCH v4 4/7] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe, and then these limits need to be

[PATCH v4 4/7] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe, and then these limits need to be