Port the lsgpio tool to the latest GPIO uAPI.
Signed-off-by: Kent Gibson
---
tools/gpio/lsgpio.c | 102
1 file changed, 47 insertions(+), 55 deletions(-)
diff --git a/tools/gpio/lsgpio.c b/tools/gpio/lsgpio.c
index b08d7a5e779b..0a993d535707 100644
-
Update uAPI documentation to deprecate v1 structs and ioctls.
Signed-off-by: Kent Gibson
---
include/uapi/linux/gpio.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/uapi/linux/gpio.h b/include/uapi/linux/gpio.h
index 3f6db33014f0..92a74c245534 100644
---
Extend gpio-event-mon to support monitoring multiple lines.
This would require multiple lineevent requests to implement using uAPI v1,
but can be performed with a single line request using uAPI v2.
Signed-off-by: Kent Gibson
---
tools/gpio/gpio-event-mon.c | 41 --
Add support for debouncing monitored lines to gpio-event-mon.
Signed-off-by: Kent Gibson
---
tools/gpio/gpio-event-mon.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/tools/gpio/gpio-event-mon.c b/tools/gpio/gpio-event-mon.c
index 5da980f78881..b64427d78942
Port the gpio-event-mon tool to the latest GPIO uAPI.
Signed-off-by: Kent Gibson
---
tools/gpio/gpio-event-mon.c | 89 +++--
1 file changed, 45 insertions(+), 44 deletions(-)
diff --git a/tools/gpio/gpio-event-mon.c b/tools/gpio/gpio-event-mon.c
index 1a303a81aee
Rename nlines to num_lines to be consistent with other usage for fields
describing the number of entries in an array.
Signed-off-by: Kent Gibson
---
tools/gpio/gpio-utils.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tools/gpio/gpio-utils.c b/tools/
Port the gpio-hammer tool to the latest GPIO uAPI.
Signed-off-by: Kent Gibson
---
tools/gpio/gpio-hammer.c | 27 +-
tools/gpio/gpio-utils.c | 109 +--
tools/gpio/gpio-utils.h | 48 +
3 files changed, 112 insertions(+), 72 deletions(
Hi Arnd,
Thanks.
There is one small fix for the v5 set. One of the DTS file names got
broken when I rebased on a different machine.
I'll send a patch for that later today.
Cheer,
Daniel
On Fri, 24 Jul 2020 at 23:37, Arnd Bergmann wrote:
>
> On Fri, Jul 10, 2020 at 11:46 AM Daniel Palmer wrot
On Sat, Jul 25, 2020 at 3:30 AM Tetsuo Handa
wrote:
>
> Since syzkaller continues various test cases until the kernel crashes,
> syzkaller tends to examine more locking dependencies than normal systems.
> As a result, syzbot is reporting that the fuzz testing was terminated
> due to hitting upper
Hello,
syzbot found the following issue on:
HEAD commit:e0145983 Merge branch 'fix-bpf_get_stack-with-PEBS'
git tree: bpf-next
console output: https://syzkaller.appspot.com/x/log.txt?x=16ce401f10
kernel config: https://syzkaller.appspot.com/x/.config?x=2b7b67c0c1819c87
dashboard li
On Fri, Jul 24, 2020 at 12:19 AM Anup Patel wrote:
>
> We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
> RISC-V NoMMU kernel).
>
> The CLINT MMIO device provides three things:
> 1. 64bit free running counter register
> 2. 64bit per-CPU time compare registers
> 3. 32bit per-CPU i
On Fri, Jul 24, 2020 at 12:19 AM Anup Patel wrote:
>
> We add DT bindings documentation for CLINT device.
>
> Signed-off-by: Anup Patel
> Reviewed-by: Palmer Dabbelt
> Tested-by: Emil Renner Berhing
> ---
> .../bindings/timer/sifive,clint.yaml | 60 +++
> 1 file change
On Sat, 25 Jul 2020 03:03:52 +
Mazin Rezk wrote:
> > Am 24.07.20 um 19:33 schrieb Kees Cook:
> >
> > > There was a fix to disable the async path for this driver that
> > > worked around the bug too, yes? That seems like a safer and more
> > > focused change that doesn't revert the SLUB defe
syzbot has bisected this issue to:
commit 5a781ccbd19e4664babcbe4b4ead7aa2b9283d22
Author: Vinicius Costa Gomes
Date: Sat Sep 29 00:59:43 2018 +
tc: Add support for configuring the taprio scheduler
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=149057ef10
start commi
1) Fix RCU locaking in iwlwifi, from Johannes Berg.
2) mt76 can access uninitialized NAPI struct, from Felix Fietkau.
3) Fix race in updating pause settings in bnxt_en, from Vasundhara Volam.
4) Propagate error return properly during unbind failures in ax88172a,
from George Kennedy.
5) Fix
On Wed, 15 Jul 2020 16:30:08 PDT (-0700), Atish Patra wrote:
Currently, initrd_start/end are computed during early_init_dt_scan
but used during arch_setup. We will get the following panic if initrd is used
and CONFIG_DEBUG_VIRTUAL is turned on.
[0.00] [ cut here ]
The RTC unit in the Ingenic SoCs has two clock sources, one
is from an external 32.768kHz clock, and the other is from an
external 24MHz/48MHz main clock that is divided by 512. The
choice of these two clocks is controlled by the ERCS bit in
the OPCR register. The RNG unit will also use this clock.
The "JZ4780_CLK_LCD0PIXCLK" and the "JZ4780_CLK_LCD1PIXCLK"
in the "jz4780.h" and the new added "JZ4780_CLK_EXCLK_DIV512"
in the previous patch is too long, add tabs to other lines
to align them.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
include/dt-bindings/clock/jz4780-cg
On Wed, 15 Jul 2020 16:30:06 PDT (-0700), Atish Patra wrote:
The trap vector is set only in trap_init which may be too late in some
cases. Early ioremap/efi spits many warning messages which may be useful.
Setup the trap vector early so that any warning/bug can be handled before
generic code inv
On Wed, 15 Jul 2020 16:30:07 PDT (-0700), Atish Patra wrote:
Currently, maximum number of mapper pages are set to the pfn calculated
from the memblock size of the memblock containing kernel. This will work
until that memblock spans the entire memory. However, it will be set to
a wrong value if th
1.Add RTC related clocks bindings for the JZ4780 SoC,
the X1000 SoC, and the X1830 SoC.
2.Add "_CLK_EXCLK_DIV512" and "_CLK_RTC" for
the JZ4780 SoC, the X1000 SoC, and the X1830 SoC.
周琰杰 (Zhou Yanjie) (3):
dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.
dt-bindings: cl
Add RTC related clocks bindings for the JZ4780 SoC, the X1000 SoC,
and the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
include/dt-bindings/clock/jz4780-cgu.h | 2 ++
include/dt-bindings/clock/x1000-cgu.h | 2 ++
include/dt-bindings/clock/x1830-cgu.h
On Wed, 15 Jul 2020 16:30:09 PDT (-0700), Atish Patra wrote:
Currently, maximum physical memory allowed is equal to -PAGE_OFFSET.
That's why we remove any memory blocks spanning beyond that size. However,
it is done only for memblock containing linux kernel which will not work
if there are multip
On 2020-07-24 2:36 p.m., Kees Cook wrote:
v3:
- add reviews/acks
- add "IMA: Add support for file reads without contents" patch
- trim CC list, in case that's why vger ignored v2
v2: [missing from lkml archives! (CC list too long?) repeating changes here]
- fix issues in firmware test suite
- add
On Fri, Jul 24, 2020 at 12:19 AM Anup Patel wrote:
>
> Right now the RISC-V timer driver is convoluted to support:
> 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for
>clocksource and SBI timer calls for clockevent device.
> 2. Linux RISC-V M-mode (without MMU) where it will use
On Saturday, July 25, 2020 12:59 AM, Duncan <1i5t5.dun...@cox.net> wrote:
> On Sat, 25 Jul 2020 03:03:52 +
> Mazin Rezk mn...@protonmail.com wrote:
>
> > > Am 24.07.20 um 19:33 schrieb Kees Cook:
> > >
> > > > There was a fix to disable the async path for this driver that
> > > > worked around
On 2020/07/25 13:48, Dmitry Vyukov wrote:
>> diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c
>> index 29a8de4..85ba7eb 100644
>> --- a/kernel/locking/lockdep.c
>> +++ b/kernel/locking/lockdep.c
>> @@ -1349,7 +1349,11 @@ static int add_lock_to_list(struct lock_class *this,
>> /*
>>
On Fri, Jul 24, 2020 at 10:12 PM Palmer Dabbelt wrote:
>
> On Wed, 15 Jul 2020 16:30:06 PDT (-0700), Atish Patra wrote:
> > The trap vector is set only in trap_init which may be too late in some
> > cases. Early ioremap/efi spits many warning messages which may be useful.
> >
> > Setup the trap ve
On Fri, Jul 24, 2020 at 10:12 PM Palmer Dabbelt wrote:
>
> On Wed, 15 Jul 2020 16:30:08 PDT (-0700), Atish Patra wrote:
> > Currently, initrd_start/end are computed during early_init_dt_scan
> > but used during arch_setup. We will get the following panic if initrd is
> > used
> > and CONFIG_DEBUG
allyesconfig
powerpc rhel-kconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a014-20200724
x86_64 randconfig-a016-20200724
x86_64 randconfig-a015-20200724
x86_64
On Sat, Jul 25, 2020 at 12:01:55PM +0800, penghao wrote:
> From: "peng...@deepin.com"
>
> TI024Gen3 USB-audio is controlled by TI024Gen3,when TI024Gens
> enter sleep mode, USB-audio will disconnect from USB bus port,
> so disabled the /sys/bus/usb/*/power/wakeup Fixesimmediately
> wakup form
On Sat, Jul 25, 2020 at 01:55:19AM +0530, Anant Thazhemadam wrote:
> Coding style issues found were rectified
>
> Signed-off-by: Anant Thazhemadam
> ---
> drivers/staging/rtl8188eu/core/rtw_security.c | 92 ++-
> 1 file changed, 47 insertions(+), 45 deletions(-)
>
> diff --git a
> From: Dinghao Liu
> Date: Fri, 24 Jul 2020 16:06:57 +0800
>
> > If req->ctype does not match any of NIX_AQ_CTYPE_CQ,
> > NIX_AQ_CTYPE_SQ or NIX_AQ_CTYPE_RQ, pointer bmap will remain
> > uninitialized and be accessed in test_bit(), which can lead
> > to kernal crash.
>
> This can never happen.
On Fri, Jul 24, 2020 at 06:28:53PM -0300, Daniel Gutson wrote:
> Currently, intel-spi has a module argument that controls whether the driver
> attempts to turn the SPI flash chip writeable. The default value
> is FALSE (don't try to make it writeable).
> However, this flag applies only for a number
linked in:
[1.643137] CPU: 0 PID: 32 Comm: kworker/0:1 Not tainted
5.8.0-rc6-next-20200724-00051-g89ba619726de #1
[1.652693] Hardware name: Raspberry Pi 4 Model B Rev 1.2 (DT)
[1.658637] Workqueue: events deferred_probe_work_func
[1.663870] pstate: 6005 (nZCv daif -PAN -UAO BTYPE
This patchset fix some bug:
patch 1:clear the debug registers when remove driver
patch 2:intercept invalid input when using decompress
patch 3:replace the return value '-EBUSY' with '-EAGAIN' when
device is busy
patch 4:initialize the 'curr_qm_qp_num' when probe device
This patchset depends on
As before, when the ZIP device is too busy to creat a request, it will
return '-EBUSY'. But the crypto process think the '-EBUSY' means a
successful request and wait for its completion.
So replace '-EBUSY' with '-EAGAIN' to show crypto this request is failed.
Fixes: 62c455ca853e("crypto: hisilico
From: Sihang Chen
The 'qm->curr_qm_qp_num' is not initialized, which will result in failure
to write the current_q file.
Signed-off-by: Sihang Chen
Signed-off-by: Yang Shen
Reviewed-by: Zhou Wang
---
drivers/crypto/hisilicon/zip/zip_main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/
From: Zhou Wang
The zero length input will cause a call trace when use GZIP decompress
like this:
Unable to handle kernel paging request at virtual address
...
lr : get_gzip_head_size+0x7c/0xd0 [hisi_zip]
Judge the input length and return '-EINVAL' when input is invalid.
From: Hao Fang
ZIP debug registers aren't cleared even if its driver is removed,
so add a clearing operation when remove driver.
Signed-off-by: Hao Fang
Signed-off-by: Yang Shen
Reviewed-by: Zhou Wang
---
drivers/crypto/hisilicon/zip/zip_main.c | 18 ++
1 file changed, 18 ins
Greg KH writes:
> On Wed, Jun 24, 2020 at 08:59:40AM +, Zhang, Qiang wrote:
>> Hello, Greg KH
>> Please have you review the patch?
>
> I am not the gadget driver maintainer :)
>
> Give Felipe a chance to catch up...
It has been in my testing/next for a while, actually :-)
--
balbi
signa
Hi,
周琰杰 (Zhou Yanjie) writes:
> Add support for probing the phy-jz4770 driver on the JZ4780 SoC,
> the X1000 SoC and the X1830 SoC from Ingenic.
>
> Tested-by: 周正 (Zhou Zheng)
> Co-developed-by: 漆鹏振 (Qi Pengzhen)
> Signed-off-by: 漆鹏振 (Qi Pengzhen)
> Signed-off-by: 周琰杰 (Zhou Yanjie)
It would
ING: CPU: 0 PID: 32 at kernel/cfi.c:30
> __cfi_check_fail+0x54/0x5c
> [1.640021] Modules linked in:
> [1.643137] CPU: 0 PID: 32 Comm: kworker/0:1 Not tainted
> 5.8.0-rc6-next-20200724-00051-g89ba619726de #1
> [1.652693] Hardware name: Raspberry Pi 4 Model B Rev 1.2 (
On Sat, Jul 25, 2020 at 02:09:14PM +0800, 彭浩 wrote:
> This email message is intended only for the use of the individual or entity
> who
> /which is the intended recipient and may contain information that is
> privileged
> or confidential. If you are not the intended recipient, you are hereby
> n
"Ramuthevar,Vadivel MuruganX"
writes:
> From: Ramuthevar Vadivel Murugan
>
> Add support for USB PHY on Intel LGM SoC.
>
> Signed-off-by: Ramuthevar Vadivel Murugan
>
use drivers/phy/ instead.
--
balbi
signature.asc
Description: PGP signature
gt; > [1.626435] CFI failure (target: dwc2_set_bcm_params+0x0/0x4):
> > [1.632408] WARNING: CPU: 0 PID: 32 at kernel/cfi.c:30
> > __cfi_check_fail+0x54/0x5c
> > [1.640021] Modules linked in:
> > [1.643137] CPU: 0 PID: 32 Comm: kworker/0:1 Not tainted
dwc2_set_bcm_params+0x0/0x4):
>> [1.632408] WARNING: CPU: 0 PID: 32 at kernel/cfi.c:30
>> __cfi_check_fail+0x54/0x5c
>> [1.640021] Modules linked in:
>> [1.643137] CPU: 0 PID: 32 Comm: kworker/0:1 Not tainted
>> 5.8.0-rc6-next-20200724-00051-g89ba619726de #1
&g
> [1.643137] CPU: 0 PID: 32 Comm: kworker/0:1 Not tainted
>> > 5.8.0-rc6-next-20200724-00051-g89ba619726de #1
>> > [1.652693] Hardware name: Raspberry Pi 4 Model B Rev 1.2 (DT)
>> > [1.658637] Workqueue: events deferred_probe_work_func
>> &g
Add the missing unlock before return from function mtdchar_compat_ioctl()
in the error handling case.
Fixes: 210bec567936 ("mtd: properly check all write ioctls for permissions")
Reported-by: Hulk Robot
Signed-off-by: Wei Yongjun
---
drivers/mtd/mtdchar.c | 6 --
1 file changed, 4 insertion
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 23ee3e4e5bd27bdbc0f1785eef7209ce872794c7
commit: 7505576d1c1ac0cfe85fdf90999433dd8b673012 MIPS: add support for SGI
Octane (IP30)
date: 9 months ago
config: mips-randconfig-r013-20200725 (attached as .conf
Fix typo in parameter description.
Fixes: d76271d22694 ("drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort
Subsystem")
Reported-by: Hulk Robot
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/d
On Sat, Jul 25, 2020 at 06:34:16AM +, Wei Yongjun wrote:
> Add the missing unlock before return from function mtdchar_compat_ioctl()
> in the error handling case.
>
> Fixes: 210bec567936 ("mtd: properly check all write ioctls for permissions")
> Reported-by: Hulk Robot
> Signed-off-by: Wei Yo
Fixes the filename for the 70mai midrive d08 dts.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c7ecc52c60..caf4a47ba799 100644
--- a/arch/arm/boot/dt
From: Yangtao Li
Add support for a100 in the sunxi-ng CCU framework.
Signed-off-by: Yangtao Li
---
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile |2 +
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++
drivers/clk/sunxi-ng/ccu-
For compound instrumentation and assert accesses, skew the watchpoint
delay to be longer if randomized. This is useful to improve race
detection for such accesses.
For compound accesses we should increase the delay as we've aggregated
both read and write instrumentation. By giving up 1 call into t
Add missing CONFIG_KCSAN_IGNORE_ATOMICS checks for the builtin atomics
instrumentation.
Signed-off-by: Marco Elver
---
v2:
* Add {} for readability.
Added to this series, as it would otherwise cause patch conflicts.
---
kernel/kcsan/core.c | 30 ++
1 file changed, 22
Add support for compounded read-write instrumentation if supported by
the compiler. Adds the necessary instrumentation functions, and a new
type which is used to generate a more descriptive report.
Furthermore, such compounded memory access instrumentation is excluded
from the "assume aligned writ
This series adds support for enabling compounded read-write
instrumentation, if supported by the compiler (Clang 12 will be the
first compiler to support the feature). The new instrumentation is
emitted for sets of memory accesses in the same basic block to the same
address with at least one read a
Introduce read-write instrumentation hooks, to more precisely denote an
operation's behaviour.
KCSAN is able to distinguish compound instrumentation, and with the new
instrumentation we then benefit from improved reporting. More
importantly, read-write compound operations should not implicitly be
Use the new instrument_read_write() where appropriate.
Signed-off-by: Marco Elver
---
include/asm-generic/bitops/instrumented-atomic.h | 6 +++---
include/asm-generic/bitops/instrumented-lock.h | 2 +-
include/asm-generic/bitops/instrumented-non-atomic.h | 6 +++---
3 files changed, 7
Adds the new __tsan_read_write compound instrumentation to objtool's
uaccess whitelist.
Signed-off-by: Marco Elver
Acked-by: Peter Zijlstra (Intel)
---
tools/objtool/check.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 63d8b630c67a
Use instrument_atomic_read_write() for atomic RMW ops.
Signed-off-by: Marco Elver
---
v2:
* Update inline comment.
---
include/asm-generic/atomic-instrumented.h | 330 +++---
scripts/atomic/gen-atomic-instrumented.sh | 21 +-
2 files changed, 180 insertions(+), 171 deletions(-)
Changes kcsan-test module to support checking reports that include
compound instrumentation. Since we should not fail the test if this
support is unavailable, we have to add a config variable that the test
can use to decide what to check for.
Signed-off-by: Marco Elver
---
v2:
* Fix CC_HAS_TSAN_C
From: Yangtao Li
Rather than a continual nesting of 'else' clauses, just make
each 'if' a new entry under 'allOf' and get rid of the else.
Signed-off-by: Yangtao Li
Reviewed-by: Rob Herring
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 124 ++
1 file changed, 68 insertio
On Fri, Jul 24, 2020 at 08:05:47AM +0300, Jarkko Sakkinen wrote:
> Remove MODULES dependency by migrating from module_alloc() to the new
> text_alloc() API. Essentially these changes provide preliminaries for
> allowing to compile a static kernel with a proper tracing support.
>
> The same API can
From: Yangtao Li
Add device tree binding Documentation details for A100 pinctrl driver,
which has a r pin controller and a pin controller with more irq lines.
Signed-off-by: Yangtao Li
Reviewed-by: Rob Herring
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++
1 file
On Fri, 2020-07-24 at 06:00 +0800, Matthias Brugger wrote:
>
> On 23/07/2020 11:07, Seiya Wang wrote:
> > From: Crystal Guo
> >
> > add driver setting to support mt8192 wdt
> >
> > Signed-off-by: Crystal Guo
> > ---
> > drivers/watchdog/mtk_wdt.c | 5 +
> > 1 file changed, 5 insertions(
On Tue, 21 Jul 2020 22:24:55 +0900 Masami Hiramatsu wrote:
>
>
> Hi Jisheng,
Hi,
>
> Would you be still working on this series?
I will rebase the implementation on the latest code, then try to address
your comments and Mark's comments. I will send out patches in this weekend.
>
> If you
On Thu, Jul 23, 2020 at 02:21:08PM +0530, Srikar Dronamraju wrote:
> A new sched_domain_topology_level was added just for Power9. However the
> same can be achieved by merging powerpc_topology with power9_topology
> and makes the code more simpler especially when adding a new sched
> domain.
>
> C
From: Yangtao Li
This commit introduces support for the pin controller on A100.
Signed-off-by: Yangtao Li
---
drivers/pinctrl/sunxi/Kconfig | 10 +
drivers/pinctrl/sunxi/Makefile| 2 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 +++
drivers/pinctrl/s
On Thu, Jul 23, 2020 at 02:21:10PM +0530, Srikar Dronamraju wrote:
> Move topology fixup based on the platform attributes into its own
> function which is called just before set_sched_topology.
>
> Cc: linuxppc-dev
> Cc: LKML
> Cc: Michael Ellerman
> Cc: Nicholas Piggin
> Cc: Anton Blanchard
> … introduced as a side ef another …
Would the following wording variant be more appropriate?
… introduced as a side effect of another …
How do you think about to replace the wording “…, I believe …”
by an imperative description?
Regards,
Markus
From: Yangtao Li
Add a binding for A100's SID controller.
Signed-off-by: Yangtao Li
Reviewed-by: Rob Herring
---
.../nvmem/allwinner,sun4i-a10-sid.yaml| 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
a/Documentation/devicetree/bindings/nvmem/allw
On Wed, Jul 22, 2020 at 12:27:47PM +0530, Srikar Dronamraju wrote:
> * Gautham R Shenoy [2020-07-22 11:51:14]:
>
> > Hi Srikar,
> >
> > > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> > > index 72f16dc0cb26..57468877499a 100644
> > > --- a/arch/powerpc/kernel/smp.c
> > > +
From: Yangtao Li
Add a binding for A100's ths controller.
Signed-off-by: Yangtao Li
Reviewed-by: Rob Herring
---
.../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/thermal/allw
On Thu, Jul 23, 2020 at 02:21:11PM +0530, Srikar Dronamraju wrote:
> Current code assumes that cpumask of cpus sharing a l2-cache mask will
> always be a superset of cpu_sibling_mask.
>
> Lets stop that assumption. cpu_l2_cache_mask is a superset of
> cpu_sibling_mask if and only if shared_cache
From: Yangtao Li
For sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of
calculation. On the other hand, the newer SOC may store other data in
the space other than 12bit sensor data. Add mask operation to read data
to avoid conversion error.
Signed-off-by: Yangtao Li
---
drive
From: Yangtao Li
This patch add thermal sensor controller support for A100,
which is similar to the previous ones.
Signed-off-by: Yangtao Li
---
drivers/thermal/sun8i_thermal.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal
From: Yangtao Li
The AXP803 can be used both using the RSB proprietary bus, or a more
traditional I2C bus.
Let's add that possibility.
Signed-off-by: Yangtao Li
Acked-by: Chen-Yu Tsai
---
drivers/mfd/axp20x-i2c.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/axp20x-i2c.c
On Fri, Jul 24, 2020 at 11:44:02AM +0530, Paras Sharma wrote:
> To correct the logic to detect whether the QUP HW version is greater
> than 2.5.
The subject line and here does not make any sense. Can you reword this
as what the problem is and why you need to change this?
>
> Signed-off-by: Par
When recording with cache-misses and arm_spe_x event, i found that
it will just fail without showing any error info if i put cache-misses
after 'arm_spe_x' event.
[root@localhost 0620]# perf record -e cache-misses -e \
arm_spe_0/ts_enable=1,pct_enable=1,pa_enable=1,load_filter=1,\
jitter=1,store_f
- Firstly, the function auxtrace_record__init() will be invoked only
once, the variable "arm_spe_pmus" will not be used afterwards, thus
we don't need to check "arm_spe_pmus" is NULL or not;
- Another reason is, even though SPE is micro-architecture dependent,
but so far it only supports "sta
v1 -> v2:
- Optimize code in patch 1 as Mathieu adviced.
- Fix memleak in patch 2.
- Detail the commit info to explain the reason.
This patch set fixes perf record failure when we mix arm_spe_x event
with other events in specific order.
Wei Li (2):
perf tools: Fix record failure when mixed w
On Wed, Jul 22, 2020 at 12:23:44AM +, benbjiang(蒋彪) wrote:
>
>
> > +/*
> > + * This function takes care of adjusting the min_vruntime of siblings of
> > + * a core during coresched enable/disable.
> > + * This is called in stop machine context so no need to take the rq lock.
> Hi,
>
> IMHO,
Hi,
On 07/07/20 00:04, Peng Liu wrote:
> 'commit 840d719604b0 ("sched/deadline: Update rq_clock of later_rq when
> pushing a task")'
> introduced the update_rq_clock() to fix the "used-before-update" bug.
>
> 'commit f4904815f97a ("sched/deadline: Fix double accounting of rq/running bw
> in pus
From: Yangtao Li
There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses
"allwinner,sun9i-a80-nmi".
Let's fix it.
Signed-off-by: Yangtao Li
Acked-by: Rob Herring
---
.../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Joachim Fenkes
On BMCs with lower timer resolution than 1ms, msleep(1) will take
way longer than 1ms, so looping 10k times won't wait for 10s but
significantly longer.
Fix this by using jiffies like the rest of the code.
Fixes: 9f4a8a2d7f9d ("fsi/sbefifo: Add driver for the SBE FIFO")
Sig
Two SBE FIFO fixes by Joachim.
Joachim Fenkes (2):
fsi/sbefifo: Clean up correct FIFO when receiving reset request from
SBE
fsi/sbefifo: Fix reset timeout
drivers/fsi/fsi-sbefifo.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
--
2.27.0
From: Joachim Fenkes
When the SBE requests a reset via the down FIFO, that is also the
FIFO we should go and reset ;)
Fixes: 9f4a8a2d7f9d ("fsi/sbefifo: Add driver for the SBE FIFO")
Signed-off-by: Joachim Fenkes
Signed-off-by: Joel Stanley
---
drivers/fsi/fsi-sbefifo.c | 2 +-
1 file changed
On Thu, Jul 23, 2020 at 10:12:36AM -0700, Florian Fainelli wrote:
> On 7/23/20 12:37 AM, Krzysztof Kozlowski wrote:
> > The specific drivers in drivers/memory usually go via architecture (e.g.
> > ARM SoC) maintainers but the generic parts (of_memory.[ch]) lacked any
> > care.
> >
> > Signed-off-b
On Thu, Jul 23, 2020 at 08:42:25AM +0100, David Howells wrote:
> Jarkko Sakkinen wrote:
>
> > Why f1774cb8956a lacked any possible testing? It extends ABI anyway.
> >
> > I think it is a kind of change that would require more screening before
> > getting applied.
>
> Yeah. It went in via a rou
From: Yangtao Li
Add a binding for A100's nmi controller.
Signed-off-by: Yangtao Li
Acked-by: Rob Herring
---
.../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/allwinner
Hi James, Bjorn,
The Card reader(10ec:5287) is a combo chip with Ethernet(10ec:8168), we think
it is not cause by setting our device config space in idle time.
We dis/enable the ASPM(setting config space) at busy/idle time, it can make our
R/W performances well not a work around function
PCI Hos
From: Yangtao Li
Allwinner A100 have a mv64xxx i2c interface available to be used.
Signed-off-by: Yangtao Li
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c
We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
RISC-V NoMMU kernel).
The CLINT MMIO device provides three things:
1. 64bit free running counter register
2. 64bit per-CPU time compare registers
3. 32bit per-CPU inter-processor interrupt registers
Unlike other timer devices, CLI
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Reviewed-by: Atish Patra
---
arch/riscv/include/asm/clint.h | 25
arch/riscv/include/asm/sm
The current RISC-V timer driver is convoluted and implements two
distinct timers:
1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
clocksource is implemented using TIME CSR and clockevent device
is implemented using SBI Timer calls.
2. M-mode timer: This is for Linux RISC-V
From: Yangtao Li
Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds
the basical DTSI file of it, including the clock, i2c, pins, sid, ths,
nmi, and UART support.
Signed-off-by: Yangtao Li
---
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++
1 file change
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Tested-by: Emil Renner Berhing
---
.../bindings/timer/sifive,clint.yaml | 60 +++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bind
Right now the RISC-V timer driver is convoluted to support:
1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for
clocksource and SBI timer calls for clockevent device.
2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO
counter register for clocksource and CLINT MMIO
101 - 200 of 1414 matches
Mail list logo
