OMAP L3 driver needs reg address space for its operation and
hence its a required property.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
.../devicetree/bindings/arm/omap/l3-noc.txt|1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm
Add missing OMAP keypad reg property information.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ff09720..e539258 100644
--- a/arch
GIC is not part of OCP space so move the gic dt node out of ocp
dt address space.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch
It has been decided to not duplicate banked modules dt nodes and that is
how the current arch timer dt extraction code is.
Update the OMAP5 dt file accordingly.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi | 19 +++
1 file changed, 7
To be able to run kernel in HYP mode, virtual timer and gic node information
needs to be popullated.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi
From: Rajendra Nayak
Specify both secure as well as nonsecure PPI IRQ for arch
timer. This fixes the following errors seen on DT OMAP5 boot..
[0.00] arch_timer: No interrupt available, giving up
Cc: Benoit Cousson
Signed-off-by: Rajendra Nayak
Signed-off-by: Santosh Shilimkar
On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap.
Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB
memory.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5-evm.dts |2 +-
1 file changed, 1 insertion
base if no sysc (2013-03-19
17:11:39 +0530)
Lokesh Vutla (1):
ARM: dts: OMAP5: Add watchdog timer node
Rajendra Nayak (1):
ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer
Santosh Shilimkar (9):
ARM: dts: om
+ Tero,
On Monday 18 March 2013 09:08 PM, Paul Walmsley wrote:
>
> Here are some basic OMAP test results for Linux v3.9-rc3.
> Logs and other details at:
>
> http://www.pwsan.com/omap/testlogs/test_v3.9-rc3/20130314094808/
>
>
> Test summary
>
>
Thanks for the summary Paul. A
_suspend" in the
> bootargs.
>
> These patches are developed on 3.8 custom kernel containing omap5
> supend/resume support.
>
> Cc: Santosh Shilimkar
Thanks Sourav for sorting out the issue. With update of changelog
suggested by Kevin on patch 1, Feel free to add,
Acked-
On Monday 18 March 2013 10:36 PM, Will Deacon wrote:
> On Mon, Mar 18, 2013 at 03:46:28PM +0000, Santosh Shilimkar wrote:
>> On Monday 18 March 2013 08:37 PM, Will Deacon wrote:
>>> That really sucks :( Does this affect all OMAP-based boards?
>>>
>> All OMAP4
On Tuesday 19 March 2013 05:41 AM, Greg Kroah-Hartman wrote:
> On Thu, Mar 14, 2013 at 03:07:01PM +0530, Santosh Shilimkar wrote:
>> (Looping Greg KH.)
>>
>> Greg,
>>
[..]
>>>
>> Sorry for not CC'ing first place
>> The subject patch is
On Monday 18 March 2013 08:37 PM, Will Deacon wrote:
> Hi Santosh,
>
> On Mon, Mar 18, 2013 at 06:51:30AM +, Santosh Shilimkar wrote:
>> On Friday 15 March 2013 10:30 AM, Will Deacon wrote:
>>> Furthermore, I was under the impression that hw_breakpoint did actually
On Friday 15 March 2013 10:30 AM, Will Deacon wrote:
> On Thu, Mar 14, 2013 at 01:08:00PM +0530, Santosh Shilimkar wrote:
>> Will,
>
> Hi guys,
>
> I'm out of the office at the moment and have really terrible connectivity,
> so I can't do too much until next w
On Friday 15 March 2013 06:15 PM, Benoit Cousson wrote:
> Hi Santosh,
>
> On 03/15/2013 11:24 AM, Santosh Shilimkar wrote:
>> Benoit,
>>
>> On Wednesday 20 February 2013 09:08 PM, Santosh Shilimkar wrote:
>>> Few updates for OMAP5 found during testing OMAP5 D
Benoit,
On Wednesday 20 February 2013 09:08 PM, Santosh Shilimkar wrote:
> Few updates for OMAP5 found during testing OMAP5 DT builds. Couple
> of patches were already posted on the list. The series also contains
> a patch which adds DMA request, IRQ lines and IO address space
> D
On Wednesday 20 February 2013 08:57 PM, Santosh Shilimkar wrote:
> From: Rajendra Nayak
>
> OMAP5 does not have freqsel either, so add the missing
> checks for !soc_is_omap54xx()
>
> Reported-by: Archit Taneja
> Signed-off-by: Rajendra Nayak
> ---
> arch/arm/m
On Friday 15 March 2013 02:28 AM, Nishanth Menon wrote:
> The following series arose from trying to use BeagleBoard-XM (OMAP3 variant)
> for doing CPU DVFS using cpufreq-cpu0. This series will eventually result in
> migrating the cpufreq support only through device tree (part of the effort
> to mig
On Thursday 14 March 2013 04:59 PM, Hiremath, Vaibhav wrote:
>
>> -Original Message-
>> From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
>> ow...@vger.kernel.org] On Behalf Of Paul Walmsley
>> Sent: Tuesday, March 12, 2013 10:10 PM
>> To: linux-omap@vger.kernel.org
>> Cc: linux-a
On Thursday 14 March 2013 03:58 PM, Mark Rutland wrote:
> On Thu, Mar 14, 2013 at 07:45:14AM +0000, Santosh Shilimkar wrote:
>> On Wednesday 13 March 2013 09:48 PM, Mark Rutland wrote:
>>> On Wed, Mar 13, 2013 at 03:44:03PM +, Santosh Shilimkar wrote:
>>>> On We
(Looping Greg KH.)
Greg,
On Wednesday 20 February 2013 09:14 PM, Santosh Shilimkar wrote:
> On Wednesday 20 February 2013 08:54 PM, Kevin Hilman wrote:
>> Santosh Shilimkar writes:
>>
>>> UART IP slave idle handling now taken care by runtime pm backend(hwmod
>
On Wednesday 13 March 2013 09:48 PM, Mark Rutland wrote:
> On Wed, Mar 13, 2013 at 03:44:03PM +0000, Santosh Shilimkar wrote:
>> On Wednesday 13 March 2013 05:55 PM, Mark Rutland wrote:
>>> On Wed, Mar 13, 2013 at 11:24:01AM +, Santosh Shilimkar wrote:
>>>> On We
ere OSSR is mandatory.
>> Sorry about this and thanks for catching this.
> Thanks for confirming..:)
>
Can you please queue this one for 3.9-rc2+ ? Without this patch
CPUIDLE is unusable on OMAP4 devices because of those flood
of warning messages.
I was also wondering whether we should ju
On Wednesday 13 March 2013 10:16 PM, Benoit Cousson wrote:
> Hi Sourav,
>
> I've just applied your branch after a minor subject cleanup for consistency.
>
> git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
> for_3.10/dts
>
Thanks for the tree Benoit. I shall update my v2
On Thursday 14 March 2013 12:01 AM, Thomas Gleixner wrote:
> On Wed, 13 Mar 2013, Santosh Shilimkar wrote:
>> On Wednesday 13 March 2013 07:49 PM, Thomas Gleixner wrote:
>>> Though making the rating of the dummy lower is definitely a good
>>> thing, so a real hardwa
On Wednesday 13 March 2013 11:12 PM, Kevin Hilman wrote:
> Santosh Shilimkar writes:
>
>> Kevin,
>>
>> On Wednesday 13 February 2013 02:25 PM, Santosh Shilimkar wrote:
>>> Current CPU PM code code make use of common cpu_suspend() path for all the
>>>
On Wednesday 13 March 2013 05:55 PM, Mark Rutland wrote:
> On Wed, Mar 13, 2013 at 11:24:01AM +0000, Santosh Shilimkar wrote:
>> On Wednesday 13 March 2013 03:46 PM, Mark Rutland wrote:
>>> Hi Santosh,
[..]
>>>
>>> Is the problem that the dummy timer
On Wednesday 13 March 2013 07:49 PM, Thomas Gleixner wrote:
> On Wed, 13 Mar 2013, Santosh Shilimkar wrote:
>> On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar wrote:
>>> With recent arm broadcast time clean-up from Mark Rutland, the dummy
>>> broadcast device is a
On Wednesday 13 March 2013 03:46 PM, Mark Rutland wrote:
> Hi Santosh,
>
> On Wed, Mar 13, 2013 at 09:28:22AM +, Santosh Shilimkar wrote:
>> (Forgot to CC Thomas)
>>
>> On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar wrote:
>>> With recent arm broad
(Forgot to CC Thomas)
On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar wrote:
> With recent arm broadcast time clean-up from Mark Rutland, the dummy
> broadcast device is always registered with timer subsystem. And since
> the rating of the dummy clock event is very high, it is
intended
one. So reduce the rating of the dummy clockevent so that
real broadcast device is selected when available.
Without this all the C states with C3STOP won't work since
the broad cast notifier will take an abort.
Cc: Mark Rutland
Cc: Russell King
Signed-off-by: Santosh Shilimkar
---
On Tuesday 12 March 2013 07:58 PM, Benoit Cousson wrote:
> On 03/12/2013 06:07 AM, Santosh Shilimkar wrote:
>> On Tuesday 12 March 2013 04:35 AM, Nishanth Menon wrote:
>>> commit 5553f9e (cpufreq: instantiate cpufreq-cpu0 as a platform_driver)
>>> now forces platform
, for SoCs that wish to link up using device tree, instead
> of platform device, provide compatibility string match:
> compatible = "cpufreq,cpu0";
>
> Cc: "Rafael J. Wysocki"
> Cc: Santosh Shilimkar
> Cc: Shawn Guo
> Cc: linux-ker...@vger.kernel.org
>
ever, the clock node is registered.
> Allow for clk names to be provided as string so as to be used when needed.
> Example (for OMAP3630):
> cpus {
> cpu@0 {
> clock-name = "cpufreq_ck";
> };
> };
>
> Cc: "Rafael J. Wysocki"
> C
Kevin,
On Wednesday 13 February 2013 02:25 PM, Santosh Shilimkar wrote:
> Current CPU PM code code make use of common cpu_suspend() path for all the
> CPU power states which is not optimal. In fact cpu_suspend() path is needed
> only when we put CPU power domain to off state where the CP
ot converted to litte endian format.
> Correcting the same here.
>
> Signed-off-by: Lokesh Vutla
> ---
Looks fine.
Acked-by: Santosh Shilimkar
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So the errata is limited to only 'EMIF_4D' version and not applicable
for next EMIF version used in OMAP5 devices, right ? If yes, would be good
to just mention that in already good changelog.
> + WARN_ONCE(1,
> + "REG_LP_MODE = LP_MODE_PWR_DN(4) is pr
gs));
> + memcpy(temp, pd->timings, size);
> pd->timings = temp;
> } else {
> dev_warn(dev, "%s:%d: allocation error\n", __func__,
>
Patch as such looks good to me.
Acked-b
arting */
> + if (pm_power_off) {
> + kernel_power_off();
> + } else {
> + WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
> + kernel_restart("SDRAM Over-temp Emergency restart");
> +
hutdown
> events (equivalent to Spec specified thermal shutdown events for
> "extended" parts).
>
Make sense.
> Reported-by: Richard Woodruff
> Signed-off-by: Nishanth Menon
> Signed-off-by: Lokesh Vutla
> ---
Thanks for the fix.
Acked-by: Santosh Shilimkar
--
kesh Vutla
> ---
Acked-by: Santosh Shilimkar
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grammed in at init time.
>
> Signed-off-by: Nishanth Menon
> Signed-off-by: Ambresh K
> Signed-off-by: Lokesh Vutla
> ---
Acked-by: Santosh Shilimkar
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meout) - 3;
> }
>
> switch (lpmode) {
>
So just make changelog verbose as well as add a
comment about the calculation in the code.
Otherwise, patch looks fine to me.
Acked-by: Santosh Shilimkar
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On Monday 04 March 2013 11:59 PM, Nishanth Menon wrote:
> On 11:17-20130302, Santosh Shilimkar wrote:
>> On Saturday 02 March 2013 01:07 AM, Nishanth Menon wrote:
>>> On 17:40-20130301, Santosh Shilimkar wrote:
>>>> Enables MPUSS ES2 power management mode using ES
On Saturday 02 March 2013 05:55 AM, Nishanth Menon wrote:
> On 17:41-20130301, Santosh Shilimkar wrote:
>> The OMAP5 idle driver can re-use OMAP4 CPUidle driver implementation thanks
>> to compatible MPUSS design.
>>
>> Though unlike OMAP4, on OMAP5 devices, MPUSS C
On Saturday 02 March 2013 05:26 AM, Nishanth Menon wrote:
> On 17:41-20130301, Santosh Shilimkar wrote:
>> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
>> b/arch/arm/mach-omap2/cpuidle44xx.c
>> index 9de47a7..df81243 100644
>> --- a/arch/arm/mach-omap2/cpuidle44xx.c
&
On Saturday 02 March 2013 05:13 AM, Nishanth Menon wrote:
> On 17:41-20130301, Santosh Shilimkar wrote:
>> When the entire MPUSS cluster is powered down in device off state, L2 cache
>> memory looses it's content and hence while targetting such a state,
>> l2 cache n
On Saturday 02 March 2013 03:23 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> While waking up CPU from off state using clock domain force wakeup, restore
>> the CPU power state to ON state before putting CPU clock domain under
>> hardware control.
On Saturday 02 March 2013 03:06 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> Add power management code to handle the CPU off mode. Separate
>> suspend finisher is used for OMAP5(Cortex-A15) because it doesn't
>> use SCU power status regi
On Saturday 02 March 2013 01:42 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> With consolidated code, now we can add the .init_late hook for
>> OMAP5 to enable power management and mux initialization.
>>
>> Signed-off-by: Santosh Shilimka
On Saturday 02 March 2013 01:12 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> In addition to the standard power-management technique, the OMAP5
>> MPU subsystem also employs an SR3-APG (mercury) power management
>> technology to reduce leaka
On Saturday 02 March 2013 01:07 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> Enables MPUSS ES2 power management mode using ES2_PM_MODE in
>> AMBA_IF_MODE register.
>>
>> 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
On Friday 01 March 2013 11:13 PM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> diff --git a/arch/arm/mach-omap2/pm44xx.c
>> b/arch/arm/mach-omap2/pm_omap4plus.c
>> similarity index 74%
>> rename from arch/arm/mach-omap2/pm44xx.c
>&
ister access will fail. To prevent such hangs, test for
> this case and warn if this is detected.
>
> Signed-off-by: Jon Hunter
> ---
Acked-by: Santosh Shilimkar
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by: Jon Hunter
> ---
Cool.
Acked-by: Santosh Shilimkar
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On Friday 01 March 2013 06:43 PM, Nishanth Menon wrote:
> On 18:39-20130301, Santosh Shilimkar wrote:
>> On Friday 01 March 2013 06:34 PM, Nishanth Menon wrote:
>>> $subject - warm reset
>>>
>> ok
>>> On 17:41-20130301, Santosh Shilimkar wrote:
>>&g
On Friday 01 March 2013 06:34 PM, Nishanth Menon wrote:
> $subject - warm reset
>
ok
> On 17:41-20130301, Santosh Shilimkar wrote:
>> From: Nishanth Menon
>>
>> OMAP5 and OMAP4 have different device instance offsets.
>>
>> So to handle them properly,
basic power management code build
and initialise on OMAP5 devices.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/Makefile |9 +-
arch/arm/mach-omap2/{pm44xx.c => pm_omap4plus.c} | 87 +---
.../mach-omap2/{sleep44xx.S => sleep_omap4plus.S}
without much benefit.
Signed-off-by: Nishanth Menon
santosh.shilim...@ti.com: Refreshed patch against 3.8
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/prminst44xx.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/prminst44xx.c
b/arch
platform code for idle driver movement.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/common.h |5 -
arch/arm/mach-omap2/cpuidle44xx.c |3 ++-
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 14 --
3 files changed, 2 insertions(+), 20 deletions
When the entire MPUSS cluster is powered down in device off state, L2 cache
memory looses it's content and hence while targetting such a state,
l2 cache needs to be flushed to main memory.
Add the necessary low power code support for the same.
Signed-off-by: Santosh Shilimkar
---
arch/arm
- CPU0 ON(WFI) + CPU1 ON(WFI) + MPUSS ON
C2 - CPU0 CSWR + CPU1 CSWR + MPUSS CSWR
C3 - CPU0 OFF + CPU1 Force OFF + MPUSS OSWR
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/Kconfig|1 +
arch/arm/mach-omap2/Makefile |4
Add power management code to handle the CPU off mode. Separate
suspend finisher is used for OMAP5(Cortex-A15) because it doesn't
use SCU power status register and external PL310 L2 cache which makes
code flow bit different.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap-
With consolidated code, now we can add the .init_late hook for
OMAP5 to enable power management and mux initialization.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/board-generic.c |1 +
arch/arm/mach-omap2/common.h|3 ++-
arch/arm/mach-omap2/io.c|8
/arm/mach-omap2/cpuidle44xx.c
@@ -1,7 +1,7 @@
/*
- * OMAP4 CPU idle Routines
+ * OMAP4PLUS CPU idle Routines
*
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2013 Texas Instruments, Inc.
* Santosh Shilimkar
* Rajendra Nayak
*
@@ -22,15 +22,16 @@
#include "
devices first.
So update the code accordingly.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/cpuidle44xx.c |1 +
arch/arm/mach-omap2/omap-smp.c| 12 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
b/arch/arm/mach
In MPUSS OSWR(Open Switch Retention), entire CPU cluster is powered down
except L2 cache memory. For MPUSS OSWR state, both CPU's needs to be in
power off state.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |2 ++
arch/arm/mach-omap2/omap-sec
.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap-secure.h|2 ++
arch/arm/mach-omap2/omap-wakeupgen.c | 14 ++
arch/arm/mach-omap2/omap-wakeupgen.h |1 +
3 files changed, 17 insertions(+)
diff --git a/arch/arm/mach-omap2/omap-secure.h
b/arch/arm/mach-omap2
In addition to the standard power-management technique, the OMAP5
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU.
Signed-off-by: Santosh
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2
clock-domain to avoid issues.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/pm_omap4plus.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm_omap4plus.c
b/arch/arm/mach-omap2/pm_omap4plus.c
index 95d2712
OMAP5 and future OMAP based SOCs has backward compatible MPUSS
IP block with OMAP4. It's programming model is mostly similar.
Hence consolidate the OMAP MPUSS code so that it can be re-used
on OMAP5 and future SOCs.
No functional change.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-
OMAP5432 Panda
devices with suspend and CPUIdle. On OMAP5 DT build though, there is an
issue with UART wakeup from suspend as discussed already on lists.
Nishanth Menon (1):
ARM: OMAP5: PM: handle device instance for for coldreset
Santosh Shilimkar (14):
ARM: OMAP4+: PM: Consolidate MPU subsystem PM
On Monday 25 February 2013 08:32 PM, Jon Hunter wrote:
On 02/25/2013 06:09 AM, Santosh Shilimkar wrote:
OMAP4460 ROM code bug needs the GIC distributor and local timer
bases to be available for the bug work around. In current code, dt
case these bases are not initialized leading to failure of
: Sourav Poddar
Tested-by: Sourav Poddar
Signed-off-by: Santosh Shilimkar
---
Posting this one seperatly but will add along with rest of
my fixes so that it doesn't get lost on the list.
arch/arm/mach-omap2/omap4-common.c | 32
1 file changed, 32 insertions(+)
On Monday 25 February 2013 04:26 PM, Benoit Cousson wrote:
Hi Santosh,
On 02/20/2013 04:38 PM, Santosh Shilimkar wrote:
Patch adds the OCP address space for all missing hwmod from existing
DT file. Note that the compatible isn't added by purpose to ensure that for
these hwmod, devices ar
On Thursday 21 February 2013 06:25 PM, Sergei Shtylyov wrote:
Hello.
On 20-02-2013 19:18, Santosh Shilimkar wrote:
The smp_wmb() here is out of placed
s/placed/place/
and redundant. So remove it. It is
a left over of the pain_release
Sure it's not 'pen_release'?
On Thursday 21 February 2013 06:22 PM, Sergei Shtylyov wrote:
Hello.
On 20-02-2013 19:27, Santosh Shilimkar wrote:
OMAP5 clockdata has different sys clock clock node name. Fix the timer
code
One "clock" too many. :-)
Indeed. Will fix that.
Regards
Santosh
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On Wednesday 20 February 2013 09:57 PM, Felipe Balbi wrote:
Hi,
On Wed, Feb 20, 2013 at 09:33:32PM +0530, Santosh Shilimkar wrote:
default:
/* Unknown default to latest silicon rev as default*/
- omap_revision = OMAP5430_REV_ES1_0
On Wednesday 20 February 2013 09:39 PM, Tony Lindgren wrote:
Hi,
* Santosh Shilimkar [130220 07:21]:
On OMAP platform, FIQ is reserved for secure environment only. If at all
the FIQ needs to be disabled, it involves going through security
API call. Hence the local_fiq_[enable/disable]() in
On Wednesday 20 February 2013 08:59 PM, Felipe Balbi wrote:
Hi,
On Wed, Feb 20, 2013 at 08:57:07PM +0530, Santosh Shilimkar wrote:
case 0xb998:
switch (rev) {
case 0:
- default:
omap_revision = OMAP5432_REV_ES1_0
On Wednesday 20 February 2013 09:12 PM, Felipe Balbi wrote:
Hi,
On Wed, Feb 20, 2013 at 09:08:54PM +0530, Santosh Shilimkar wrote:
Patch adds the code for extracting the module ocp address space from device
tree blob in case the hwmod address space look up fails.
IMHO you should lookup on DT
On Wednesday 20 February 2013 08:54 PM, Kevin Hilman wrote:
Santosh Shilimkar writes:
UART IP slave idle handling now taken care by runtime pm backend(hwmod layer)
so remove the hackery from the driver.
Tested-by: Vaibhav Bedia
Tested-by: Sourav Poddar
Signed-off-by: Rajendra nayak
Signed
Patch adds the OCP address space for all missing hwmod from existing
DT file. Note that the compatible isn't added by purpose to ensure that for
these hwmod, devices are not getting created.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi |
: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 6609754..4c9d984 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -41,8 +41,9
Patch adds the code for extracting the module ocp address space from device
tree blob in case the hwmod address space look up fails.
The idea is to remove the address space data from hwmod and extract it from
DT blob.
Cc: Benoit Cousson
Signed-off-by: Rajendra Nayak
Signed-off-by: Santosh
To be able to run kernel in HYP mode, virtual timer and gic node information
needs to be popullated.
Cc: Marc Zyngier
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm
It has been decided to not duplicate banked modules dt nodes and that is
how the current arch timer dt extraction code is.
Update the OMAP5 dt file accordingly.
Cc: Marc Zyngier
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi | 19
GIC is not part of OCP space so move the gic dt node out of ocp
dt address space.
Cc: Marc Zyngier
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts
Add missing OMAP keypad reg property information.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fa0c66b..269a328 100644
--- a/arch
On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap.
Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB
memory.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5-evm.dts |2 +-
1 file changed, 1 insertion
files. It has been tested on OMAP5
and OMAP4 devices.
Rajendra Nayak (1):
ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer
Santosh Shilimkar (7):
ARM: dts: omap5-evm: Update available memory to 2032 MB
ARM: dts: OMAP5: Align the local timer dt node as per the current
binding code
From: Rajendra Nayak
OMAP5 does not have freqsel either, so add the missing
checks for !soc_is_omap54xx()
Reported-by: Archit Taneja
Signed-off-by: Rajendra Nayak
---
arch/arm/mach-omap2/dpll3xxx.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap
Allow prm init to success on OMAP5 SOCs.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/prm44xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index c05a343..1aae198 100644
--- a/arch/arm/mach
Errata i688 is also applicable for OMAP5 based devices. Update the
code so that it can be enabled on OMAP5 devices.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/Kconfig |2 +-
arch/arm/mach-omap2/io.c|9 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff
On OMAP5 es2 WakeupGen SAR register layout offset have changed.
Update the layout accordingly.
Reported-by: Menon, Nishanth
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap4-sar-layout.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm
Update SAR RAM base address for OMAP5 based devices.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap4-common.c | 10 --
arch/arm/mach-omap2/omap54xx.h |1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch
From: Tero Kristo
Make use of 'prm_base' so that prm read_inst/write_inst can work on
OMAP5 devices.
Signed-off-by: Tero Kristo
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/prm44xx.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/
OMAP5 clockdata has different sys clock clock node name. Fix the timer code
to take care of it.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/timer.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
Update OMAP5 ES2 idcode and make ES2 as default detection.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/id.c | 16 +---
arch/arm/mach-omap2/soc.h |2 ++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2
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