Hi Arnd,
On Wednesday 07 May 2014 03:00 PM, Arnd Bergmann wrote:
On Wednesday 07 May 2014 14:14:55 Kishon Vijay Abraham I wrote:
+static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
+
+dra7xx_pcie_writel(dra7xx-base
Hi,
On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
In DRA7, the cpu sees 32bit address, but the pcie controller can
Hi Arnd,
On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
In DRA7, the cpu sees 32bit address, but the pcie controller
Hi Arnd,
On Tuesday 13 May 2014 06:17 PM, Arnd Bergmann wrote:
On Tuesday 13 May 2014 18:01:59 Kishon Vijay Abraham I wrote:
On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote
hi Arnd,
On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote:
On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote:
If you have a case where the outbound translation is a 256MB (i.e. 28bit)
section of the CPU address space
Hi Arnd,
On Wednesday 14 May 2014 06:15 PM, Arnd Bergmann wrote:
On Wednesday 14 May 2014 11:14:45 Kishon Vijay Abraham I wrote:
hi Arnd,
On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote:
On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
On Tuesday 13 May 2014 18:56:23 Kishon Vijay
Hi Roger,
On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote:
Hi Kishon,
On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
APLL used by PCIE phy can either use external clock as input or the clock
from DPLL. Added support for the APLL to use external clock as input here.
Cc
On Wednesday 14 May 2014 06:53 PM, Roger Quadros wrote:
Hi Kishon,
On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Typo in $subject
s/clocks/clock
Will fix
Hi Nishanth,
On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote:
On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Roger,
On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote:
Hi Kishon,
On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
APLL
Hi Nishant,
On Thursday 15 May 2014 05:16 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 4:25 AM, Roger Quadros rog...@ti.com wrote:
On 05/15/2014 12:15 PM, Kishon Vijay Abraham I wrote:
Hi Nishanth,
On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote:
On Wed, May 14, 2014 at 10:19
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi Nishant,
On Thursday 15 May 2014 05:16 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 4:25 AM, Roger Quadros rog...@ti.com wrote:
On 05/15/2014 12
Hi,
On Thursday 15 May 2014 06:03 PM, Nishanth Menon wrote:
On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Nishant,
On Thursday 15 May 2014
Hi Arnd,
On Wednesday 14 May 2014 06:15 PM, Arnd Bergmann wrote:
On Wednesday 14 May 2014 11:14:45 Kishon Vijay Abraham I wrote:
hi Arnd,
On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote:
On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
On Tuesday 13 May 2014 18:56:23 Kishon Vijay
Hi,
On Thursday 15 May 2014 06:03 PM, Nishanth Menon wrote:
On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Nishant,
On Thursday 15 May 2014
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis
-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 69 +++
1 file changed, 69 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index eaeccaf..1239f0d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm
Added *resets* and *reset-names* properies for PCIe dt node.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 ++
1 file changed, 2 insertions(+)
diff
Get reset nodes from dt and use reset framework APIs to reset PCIe.
This is needed since reset is handled by the SoC.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt |4
drivers/pci/host/pci-dra7xx.c
...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e1bd052..3d8c9c2 100644
--- a/arch/arm
...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3c7e7f2..eaeccaf 100644
--- a/arch/arm/boot
...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24
1 file changed, 24
...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f0ca46d..3c7e7f2 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b
: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pcie
Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 59 +++
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile|1 +
drivers/pci
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham
...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index c767687..55e95c5 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
: Change the parent of apll_pcie_in_clk_mux to
dpll_pcie_ref_m2ldo_ck
Kishon Vijay Abraham I (16):
phy: phy-omap-pipe3: Add support for PCIe PHY
phy: pipe3: insert delay to enumerate in GEN2 mode
PCI: designware: Configuration space should be specified in 'reg'
PCI: designware: use
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Roger Quadros rog
Hi,
On Thursday 29 May 2014 12:41 PM, Mohit KUMAR DCG wrote:
Hello Kishon,
-Original Message-
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Thursday, May 29, 2014 12:08 PM
To: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org
Hi,
On Thursday 29 May 2014 12:18 PM, Jingoo Han wrote:
On Thursday, May 29, 2014 3:38 PM, Kishon Vijay Abraham I wrote:
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings
Hi,
On Wednesday 11 June 2014 12:32 AM, Dan Carpenter wrote:
Hello Kishon Vijay Abraham I,
The patch 00a0b1d58af873d8: usb: musb: omap: Add device tree support
for omap musb glue, from Sep 11 2012, leads to the following static
checker warning:
drivers/usb/musb/omap2430.c:569
Hi Arnd,
On Thursday 29 May 2014 12:08 PM, Kishon Vijay Abraham I wrote:
In DRA7, the cpu sees 32bit address, but the pcie controller can see only
28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller
in the designware driver.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis
Hi Tero,
On Thursday 19 June 2014 04:40 PM, Tero Kristo wrote:
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
From: Keerthy j-keer...@ti.com
Add divider table to optfclk_pciephy_div clock. The Documentation
for divider clock can be found at ../clock/ti/divider.txt
This patch
Hi Tero,
On Thursday 19 June 2014 04:42 PM, Tero Kristo wrote:
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Why? Needs a better changelog also.
Figure 26-22
Hi Tero,
On Thursday 19 June 2014 04:46 PM, Tero Kristo wrote:
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
You can drop the node documentation ref, and rather
Hi,
On Thursday 19 June 2014 04:50 PM, Tero Kristo wrote:
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Drop the ref to the binding doc and rather
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
This module is needed for the SATA and PCIe PHYs.
Signed-off-by: Roger Quadros rog...@ti.com
Tested-by: Roger Quadros rog...@ti.com
I used this patch for testing PCIe.
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Please find
/
Kishon Vijay Abraham I (2):
arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
arch/arm/mach-omap2/cm2_7xx.h |4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 112 +
arch/arm/mach-omap2
Abraham I kis...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
arch/arm/mach-omap2/cm2_7xx.h |4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +
arch
Hi Roger,
On Monday 30 June 2014 04:30 PM, Roger Quadros wrote:
On some SoCs e.g. J6 the 3.3V supply to the USB2 PHY can be
powered down when the PHY is not in use. Add regulator
management code to control this power line.
Signed-off-by: Roger Quadros rog...@ti.com
---
Hi,
On Tuesday 01 July 2014 03:43 PM, Roger Quadros wrote:
On 07/01/2014 12:56 PM, Kishon Vijay Abraham I wrote:
Hi Roger,
On Monday 30 June 2014 04:30 PM, Roger Quadros wrote:
On some SoCs e.g. J6 the 3.3V supply to the USB2 PHY can be
powered down when the PHY is not in use. Add regulator
On Tuesday 01 July 2014 03:55 PM, Roger Quadros wrote:
On 07/01/2014 01:20 PM, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 01 July 2014 03:43 PM, Roger Quadros wrote:
On 07/01/2014 12:56 PM, Kishon Vijay Abraham I wrote:
Hi Roger,
On Monday 30 June 2014 04:30 PM, Roger Quadros wrote
Hi Roger,
On Wednesday 02 July 2014 05:33 PM, Roger Quadros wrote:
If probe fails then we need to call pm_runtime_disable() to balance
out the previous pm_runtime_enable() call. Else it will cause
unbalanced pm_runtime_enable() call in the succeding probe call.
This anomaly was observed
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v1
On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index b03cfe4..7148e7c 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 7148e7c..f5dca1f 100644
--- a/arch/arm/boot/dts
...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm
-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 69 +++
1 file changed, 69 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index cbaf47d..b6060d3 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm
...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 961be6b..e4999e4 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b
...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 41 +
1 file
robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot
...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3ff6d7c..fe5db55 100644
--- a/arch/arm
):
ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div
clock
ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to
dpll_pcie_ref_m2ldo_ck
Kishon Vijay Abraham I (6):
ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
ARM: dts: dra7xx-clocks
On Wednesday 16 July 2014 01:43 AM, Paul Walmsley wrote:
On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
Added hwmod data for pcie1 and pcie2 subsystem present
On Tuesday 15 July 2014 12:48 PM, Tony Lindgren wrote:
* Kishon Vijay Abraham I kis...@ti.com [140714 03:44]:
[1] is split into separate series in order for individual subsystem
Maintainers to pick up the patches. This series handles the PCIe
dt data for DRA7.
This series has better commit
at 02:38:27PM -0800, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [131216 13:31]:
On Mon, Dec 16, 2013 at 09:23:43PM +0530, Kishon Vijay Abraham I wrote:
After the platform devices are created using PLATFORM_DEVID_AUTO, the
device names given in usb_bind_phy (in board file) does not match
Hi,
On Thursday 21 August 2014 10:13 PM, Tony Lindgren wrote:
Commit 30a70b026b4cd (usb: musb: fix obex in g_nokia.ko causing kernel
panic) attempted to fix runtime PM handling for PHYs that are on the
I2C bus. Commit 3063a12be2b0 (usb: musb: fix PHY power on/off) then
changed things around
Hi Tony,
On Thursday 28 August 2014 04:58 AM, Tony Lindgren wrote:
We don't need twl4030_phy_power() any longer now that we have
the runtime PM calls. Let's get rid of it as it's confusing.
No functional changes, just move the code and use res instead
of ret as we are not returning that
Hi Tony,
On Thursday 04 September 2014 10:37 PM, Tony Lindgren wrote:
* Kishon Vijay Abraham I kis...@ti.com [140904 06:51]:
Hi Tony,
On Thursday 28 August 2014 04:58 AM, Tony Lindgren wrote:
We don't need twl4030_phy_power() any longer now that we have
the runtime PM calls. Let's get rid
Hi,
On Tuesday 07 October 2014 03:49 PM, Vivek Gautam wrote:
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
On Thursday 30 October 2014 04:39 AM, Rabin Vincent wrote:
Unless I'm missing something, this patch appears to have still not been
picked up. It would be nice if it can go in for 3.18 so that we have
working USB on pandaboard again at least in that release.
Tony, would you mind carrying
) copied, 2.6423 s, 39.7 MB/s
Write throughput
./dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 oflag=sync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 9.3556 s, 11.2 MB/s
Balaji T K (1):
mmc: omap_hsmmc: add tuning support
Kishon Vijay Abraham I (1):
ARM: dts: dra72-evm
) copied, 2.6423 s, 39.7 MB/s
Write throughput
./dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 oflag=sync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 9.3556 s, 11.2 MB/s
Balaji T K (1):
mmc: omap_hsmmc: add tuning support
Kishon Vijay Abraham I (1):
ARM: dts: dra72-evm
host caps field.
Signed-off-by: Viswanath Puttagunta vi...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[ kis...@ti.com : Set the functional clock to 192MHz if the contoller
supports HS200 ]
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/mmc/host
Set the maximum operating frequency of MMC2 to 192MHz.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index abbaaa7..5cc1110 100644
From: Viswanath Puttagunta vi...@ti.com
set SDR104, SDR50, DDR50 and HS200 capability flags to caps/caps2 by reading
MMCHS_CAPA2 register.
Signed-off-by: Viswanath Puttagunta vi...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
From: Viswanath Puttagunta vi...@ti.com
set SDR104, SDR50, DDR50 and HS200 capability flags to caps/caps2 by reading
MMCHS_CAPA2 register.
Signed-off-by: Viswanath Puttagunta vi...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Set the maximum operating frequency of MMC2 to 192MHz.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index abbaaa7..5cc1110 100644
host caps field.
Signed-off-by: Viswanath Puttagunta vi...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[ kis...@ti.com : Set the functional clock to 192MHz if the contoller
supports HS200 ]
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/mmc/host
Hi,
Sorry for sending this multiple times. There was some problem with my mail
configuration which I have fixed now.
Thanks
Kishon
On Thursday 13 November 2014 08:24 PM, Kishon Vijay Abraham I wrote:
Added HS200 to improve EMMC throughput for dra72.
With HS200
==
Read
) copied, 2.6423 s, 39.7 MB/s
Write throughput
./dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 oflag=sync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 9.3556 s, 11.2 MB/s
Balaji T K (1):
mmc: omap_hsmmc: add tuning support
Kishon Vijay Abraham I (1):
ARM: dts: dra72-evm
On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
The series has dependency on
a) [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
b) [GIT PULL] Samsung
and the hsmmc driver takes care of enabling
and disabling it. In the case of 'reboot', during shutdown path as part of it's
cleanup process the hsmmc driver disables this regulator. This makes MMC boot
not functional.
Fixed it by driving high all the pcf lines.
Signed-off-by: Kishon Vijay Abraham I
On Tuesday 16 December 2014 02:20 AM, Nishanth Menon wrote:
On 12/12/2014 02:06 AM, Kishon Vijay Abraham I wrote:
The reset values for all the PCF lines are high and hence on shutdown
we should drive all the lines high in order to bring it to the reset state.
This is actually required since
Hi Roger,
On Friday 19 December 2014 05:35 PM, Roger Quadros wrote:
Failed test case: Boot without SATA drive connected. Suspend/resume
the board and then connect SATA drive. It fails to enumerate.
Due to Errata i783 SATA Lockup After SATA DPLL Unlock/Relock
we can't allow SATA DPLL to be
On Tuesday 16 December 2014 02:52 PM, Vignesh R wrote:
Since phyid is no longer used by pcie driver, this field can be dropped
from the DT.
Signed-off-by: Vignesh R vigne...@ti.com
Acked-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 2 --
1 file changed, 2
No functional change. Modified few things so that there are no
code duplication while implementing chained TRB.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/dwc3/ep0.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers
dwc3 can do only max packet aligned transfers. So in case request length
is not max packet aligned and is bigger than DWC3_EP0_BOUNCE_SIZE
two chained TRBs is required to handle the transfer.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
*) Did eumeration testing with g_zero in kernel
: _wait_target_disable failed
Fix it by removing .modulemode from pcie1/2 hwmods and, in that
way, prevent clockdomain ctrl register writing from HWMOD core.
Looks correct except for one change.
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Grygorii Strashko grygorii.stras
+tero
Hi,
On Monday 09 February 2015 08:22 PM, grygorii.stras...@linaro.org wrote:
On 02/09/2015 09:24 PM, Kishon Vijay Abraham I wrote:
Hi,
On Monday 09 February 2015 03:58 PM, grygorii.stras...@linaro.org wrote:
Hi Kishon,
On 02/09/2015 04:50 PM, Kishon Vijay Abraham I wrote:
On Tuesday
...@linaro.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 103 +++--
1 file changed, 24 insertions(+), 79 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index
Now that we don't have hwmod entry for pcie PHY remove the
ti,hwmod property from PCIE PHY's
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index
Hi Roger,
On Friday 19 December 2014 05:35 PM, Roger Quadros wrote:
On system suspend, the runtime_suspend() driver hook doesn't get
called and so the clocks are not disabled in the driver.
This causes the L3INIT_960M_GFCLK and L3INIT_480M_GFCLK to remain
active on the DRA7 platform while in
Hi Roger,
On Thursday 08 January 2015 04:47 PM, Roger Quadros wrote:
Failed test case: Boot without SATA drive connected. Suspend/resume
the board and then connect SATA drive. It fails to enumerate.
Due to Errata i783 SATA Lockup After SATA DPLL Unlock/Relock
we can't allow SATA DPLL to be
resets used here in mainline. I'll send an updated patch for
mainline.
Thanks
Kishon
- Paul
From 0f9a1ee083a7adbb2c867d5c8d25d7e5fcb38b07 Mon Sep 17 00:00:00 2001
From: Kishon Vijay Abraham I kis...@ti.com
Date: Thu, 12 Feb 2015 09:29:31 -0700
Subject: [PATCH] ARM: DRA7: hwmod_data: Fix hwmod
Hi,
On Monday 09 February 2015 03:58 PM, grygorii.stras...@linaro.org wrote:
Hi Kishon,
On 02/09/2015 04:50 PM, Kishon Vijay Abraham I wrote:
On Tuesday 03 February 2015 09:21 PM, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Now DRA7xx pcie1/2
Hi,
On Thursday 18 December 2014 07:41 PM, Nishanth Menon wrote:
On 12/18/2014 12:18 AM, Kishon Vijay Abraham I wrote:
On Tuesday 16 December 2014 02:20 AM, Nishanth Menon wrote:
On 12/12/2014 02:06 AM, Kishon Vijay Abraham I wrote:
The reset values for all the PCF lines are high and hence
Hi,
On Wednesday 18 March 2015 05:51 PM, Linus Walleij wrote:
On Mon, Mar 16, 2015 at 9:46 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Wednesday 14 January 2015 05:28 PM, Linus Walleij wrote:
#include linux/reboot.h
static int foo_reboot_handler(struct notifier_block
Hi Tony,
On Wednesday 18 March 2015 05:42 AM, Tony Lindgren wrote:
Add a minimal driver for dm816x USB. This makes USB work on dm816x
without any other changes needed as it can use the existing musb_dsps
glue layer for the USB controller.
Note that this phy is different from dm814x and am335x.
a...@arndb.de
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Praneeth Bajjuri prane...@ti.com
---
drivers/bus/omap-ocp2scp.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/bus
Added a new compatible string ti,am437x-ocp2scp for OCP2SCP module.
This is needed since except for the OCP2SCP used in AM437x, SYNC2 value
in OCP2SCP TIMING should be changed whereas the default value is sufficient
in AM437x.
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Kishon Vijay Abraham
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