Added S3C64XX SPI controller driver.
Each SPI controller has exactly one CS line and as such doesn't
provide for multi-cs. We implement a workaround to support
multi-cs by _not_ configuring the mux'ed CS pin for each SPI
controller. The CS mechanism is assumed to be fully machine
specific - the dr
Platform devices for SPI Controller of S3C64XX are defined
and exported for machines to include.
Also, controller setup helper functions are defined for
machine code to set runtime configuration of the controller
and the bus.
Signed-off-by: Jassi Brar
---
arch/arm/plat-s3c/include/plat/devs.h |
Request for comments on following patches for
S3C64XX SPI controller driver.
These patches apply against
4aaa2a7de99092ff63037bdd29055ad6b208ac98
of http://www.fluff.org/git/bjdooks/linux.git next-s3c
Regards.
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Defined special 48MHz clock sources for SPI-0,1.
Signed-off-by: Jassi Brar
---
arch/arm/plat-s3c64xx/clock.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index 7a36e89..7b9d79c 100644
--- a/arch
As an illustration of using the newly implemented SPI driver,
'spidev' master device has been enabled on SMDK6410.
Signed-off-by: Jassi Brar
---
arch/arm/mach-s3c6410/mach-smdk6410.c | 47 +
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/arch/ar
Added SPI controller register base.
Signed-off-by: Jassi Brar
---
arch/arm/mach-s3c6400/include/mach/map.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h
b/arch/arm/mach-s3c6400/include/mach/map.h
index fc8b223..25f5593 100644
We need a way to pass controller specific information to the
SPI device driver. For that purpose a new header is made.
Signed-off-by: Jassi Brar
---
arch/arm/plat-s3c64xx/include/plat/spi.h | 71 ++
1 files changed, 71 insertions(+), 0 deletions(-)
create mode 1006
On Fri, Nov 20, 2009 at 10:42 PM, Marek Szyprowski
wrote:
> From: Kyungmin Park
>
> We decided to use 0x3000' as base memory address on S5PC1XX SoCs
> (s5pc100 and s5pc110).
you might as well want to explain the reason behind it, if any?
> A patch to u-boot that configures SMDKC100 board and
From: Pawel Osciak
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds common framebuffer device helpers and register defines
for S5PC110 sub-platform.
Signed-off-by: Pawel Osciak
Signed
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch enables S5PC110 sub-platform.
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowski
---
arch/arm/Kconfig
From: Kyungmin Park
Add entries for the ARM S5PC100 and ARM S5PC110 architectures that are
currently being maintained by ourself.
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowski
---
MAINTAINERS | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds common SDHCI platform helper for S5PC110 sub-platform.
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowsk
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds gpiolib support for S5PC110 sub-platform.
Signed-off-by: Marek Szyprowski
Signed-off-by: Byungho Min
Signed-off-by: Kyungmin Park
---
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds required I2C platform helpers. S5PC110 SoCs has 3 I2C
controllers.
Signed-off-by: Kyungmin Park
Signed-off-by: Byu
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds clocks and plls definition for S5PC110 SoCs.
Signed-off-by: Kyungmin Park
Signed-off-by: Byungho Min
Signed-off-b
This patch removes all useless definitions from plat/s5pc100.h and
introduces new common plat/s5pc1xx.h include.
Signed-off-by: Marek Szyprowski
Signed-off-by: Kyungmin Park
---
arch/arm/mach-s5pc100/cpu.c |2 +-
arch/arm/mach-s5pc100/include/plat/regs-clock.h |8 ++-
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds interrupt support on S5PC110 SoCs. Unlike S5PC100,
S5PC110 has 4 VICs, so the S5PC110 specifi virtual memory area is
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds support for SMDKC110 evaluation board. The board can be
obtained from Meritech (http://www.meritech.co.kr).
Signed-
S5PC100 GPIOlib support has been rewriten to make it possible to reuse
most of the common code in the upcoming S5PC110 sub-platform.
Signed-off-by: Marek Szyprowski
Signed-off-by: Kyungmin Park
---
arch/arm/mach-s5pc100/Makefile |1 +
arch/arm/mach-s5pc100/gpio-chips.c
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds CPU initialization code for S5PC110 sub-platform.
Signed-off-by: Kyungmin Park
Signed-off-by: Byungho Min
Signed-
From: Pawel Osciak
Framebuffer register blocks on S5PC100 and S5PC110 differ only slightly.
This patch moves all register definitions that are common for S5PC100
and S5PC110 to plat-s3c/plat/regs-fb-v5.h.
Signed-off-by: Pawel Osciak
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowski
From: Kyungmin Park
CLK_OTHER register block is specific for S5PC100 SoC, so move the
definition to mach-s5pc100/cpu.c. Size of CLK and PWR register block is
different on S5PC100 and S5PC110, thus new defines are introduced.
Clock and pll hierarchy is completely different between S5PC100 and
S5P
From: Kyungmin Park
Samsung S5PC110 SoCs have UART that differs a bit from the one known
from the previous Samsung SoCs. This patch adds support for this new
driver.
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowski
---
arch/arm/plat-s3c/include/plat/regs-serial.h | 31 ++
dr
From: Kyungmin Park
Samsung S5PC110 SoC are newer Samsung SoCs. Like S5PC100 they are based
on CortexA8 ARM CPU, but have much more powerfull integrated periperals.
This patch adds register map for S5PC110 sub-platform.
Signed-off-by: Kyungmin Park
Signed-off-by: Byungho Min
Signed-off-by: Mar
Hello,
This preliminary patch series adds support for Samsung S5PC110 SoC.
S5PC110 belongs to S5PC1XX family (CortexA8 ARM core), but differs in
many places from the S5PC100 SoC: new memory map, different clock
hierarchy, new gpio banks and much more powerful integrated peripherals.
Such differenc
From: Kyungmin Park
All device helpers that are defined in plat-s5pc1xx are S5PC100
specific. This patch moves them to mach-s5pc100 directory to make use of
newly created sub-platform support.
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowski
---
arch/arm/mach-s5pc100/Kconfig
From: Kyungmin Park
All includes that are common for S5PC100 and S5PC110 are moved to
plat-s5pc1xx/include/mach, so they can be used by both sub-platforms.
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowski
---
.../include/mach/gpio-core.h |2 +-
.../includ
From: Kyungmin Park
We decided to use 0x3000' as base memory address on S5PC1XX SoCs
(s5pc100 and s5pc110).
A patch to u-boot that configures SMDKC100 board and sets base memory
as 0x3000' has been already posted.
Signed-off-by: Kyungmin Park
Signed-off-by: Marek Szyprowski
---
arch/a
From: Kyungmin Park
Samsung S5PC100 and S5PC110 SoCs differs a lot in register map and other
core platform definitions, so it is not possible to have both SoCs in
the current platform framework without runtime hacks. To address this
issue a sub-platform has been introduced, so each SoC in sub-pla
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