On 09/20, Jernej Skrabec wrote:
> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
>
> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Icenowy Zheng
> ---
Acked-by: Stephen Boyd
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On 10/09, Icenowy Zheng wrote:
>
>
> 于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard
> 写到:
> >On Fri, Oct 06, 2017 at 06:33:31AM +, Icenowy Zheng wrote:
> >> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration
> >register,
> >> which is intended to be accessed by the dwmac-sun
rman
> Signed-off-by: Chen-Yu Tsai
> Tested-by: Icenowy Zheng
> ---
Acked-by: Stephen Boyd
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usting the CPUX clock.
>
> Signed-off-by: Icenowy Zheng
> ---
Acked-by: Stephen Boyd
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On 03/07, Maxime Ripard wrote:
> So far, divider_round_rate only considers the parent clock returned by
> clk_hw_get_parent.
>
> This works fine on clocks that have a single parents, this doesn't work on
> muxes, since we will only consider the first parent, while other parents
> may totally be ab
On 10/11, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> new file mode 100644
> index ..c0e96bf6d104
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +
> +static int sun50i_a64_ccu_probe(struct platfo
On 09/09, Maxime Ripard wrote:
> index 106cba27c331..964f22091a10 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
> obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
> obj-$(CONFIG_SUN8I_A33_CCU)
On 05/12, Maxime Ripard wrote:
>
> diff --git a/drivers/clk/sunxi/clk-sun4i-display.c
> b/drivers/clk/sunxi/clk-sun4i-display.c
> index 70803aa7028c..9780fac6d029 100644
> --- a/drivers/clk/sunxi/clk-sun4i-display.c
> +++ b/drivers/clk/sunxi/clk-sun4i-display.c
> @@ -128,8 +128,8 @@ static void _
On 05/10, Priit Laes wrote:
> On Mon, 2016-05-09 at 15:39 -0700, Stephen Boyd wrote:
> > On 05/09, Stephen Boyd wrote:
> > >
> > >
> > > Ok I applied this one to clk-next.
> > >
> > And I squashed this in to silence the following checker warn
On 05/10, Maxime Ripard wrote:
> Hi Stephen,
>
> On Mon, May 09, 2016 at 03:39:24PM -0700, Stephen Boyd wrote:
> > On 05/09, Stephen Boyd wrote:
> > >
> > > Ok I applied this one to clk-next.
> > >
> >
> > And I squashed this in to silen
On 05/09, Stephen Boyd wrote:
>
> Ok I applied this one to clk-next.
>
And I squashed this in to silence the following checker warning.
drivers/clk/sunxi/clk-sun4i-display.c:110:33: warning: Variable
length array is used.
---8<---
diff --git a/drivers/clk/sunxi/clk-sun4i-display.
On 05/08, Maxime Ripard wrote:
> Hi Stephen,
>
> On Fri, May 06, 2016 at 03:30:02PM -0700, Stephen Boyd wrote:
> > On 04/25, Maxime Ripard wrote:
> > > The A10 SoCs and its relatives has a special clock controller to drive the
> > > display engines (both frontend
Signed-off-by: Maxime Ripard
> Acked-by: Rob Herring
> ---
Acked-by: Stephen Boyd
Unless I can merge this into clk-next? Wasn't clear to me.
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On 04/19, Maxime Ripard wrote:
>
> I have a bunch of other clock patches that need this, so I guess it
> would be easier if applied it directly with your acked-by, or if you
> could apply it and give a stable branch I can base my future PR on.
Ok. I pushed it to stable branch 'clk-composite-unreg
Add a driver for the channel 1 clock.
>
> Signed-off-by: Maxime Ripard
> Acked-by: Rob Herring
> ---
Acked-by: Stephen Boyd
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; Acked-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
Acked-by: Stephen Boyd
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On 03/23, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/clk-sun4i-display.c
> b/drivers/clk/sunxi/clk-sun4i-display.c
> new file mode 100644
> index ..af7d1faebdec
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-display.c
> @@ -0,0 +1,262 @@
> +#include
> +#include
> +#in
e A13 / R8 SoCs.
>
> Signed-off-by: Maxime Ripard
> Acked-by: Chen-Yu Tsai
> Acked-by: Rob Herring
> ---
Acked-by: Stephen Boyd
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On 03/23, Maxime Ripard wrote:
> The composite clock didn't have any unregistration function, which forced
> us to use clk_unregister directly on it.
>
> While it was already not great from an API point of view, it also meant
> that we were leaking the clk_composite structure allocated in
> clk_re
On 03/19, Rob Herring wrote:
> On Thu, Mar 17, 2016 at 07:43:42PM +1100, yassinjaf...@gmail.com wrote:
> > From: Yassin Jaffer
> >
> > This patch adds a composite clock type consisting of
> > a clock gate, mux, configurable dividers, and a reset control.
> >
> > Signed-off-by: Yassin Jaffer
> >
On 03/30, Boris Brezillon wrote:
> diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c
> index ebcd738..49ec5b1 100644
> --- a/drivers/clk/clk-pwm.c
> +++ b/drivers/clk/clk-pwm.c
> @@ -28,15 +28,29 @@ static inline struct clk_pwm *to_clk_pwm(struct clk_hw
> *hw)
> static int clk_pwm_prepar
gt; config and not the current state.
>
> This is part of the rework allowing the PWM framework to support
> hardware readout and expose real PWM state even when the PWM has
> just been requested (before the user calls pwm_config/enable/disable()).
>
> Signed-off-by: Boris Brez
On 03/30, Boris Brezillon wrote:
> @@ -74,6 +74,23 @@ enum pwm_polarity {
> PWM_POLARITY_INVERSED,
> };
>
> +/**
> + * struct pwm_args - PWM arguments
> + * @period: reference period
> + * @polarity: reference polarity
> + *
> + * This structure describe board-dependent arguments attached
On 01/14, Maxime Ripard wrote:
> From: Matthias Brugger
>
> Some devices like SoCs from Mediatek need to use the clock
> through a regmap interface.
> This patch adds regmap support for the simple multiplexer clock,
> the divider clock and the clock gate code.
>
> Signed-off-by: Matthias Brugger
On 11/06, Maxime Ripard wrote:
> Hi Stephen,
>
> Thanks for your feedback!
>
> On Fri, Oct 30, 2015 at 02:29:02PM -0700, Stephen Boyd wrote:
> > > +
> > > + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> > > + if (!mux)
> > [..]
> > > +
On 10/30, Maxime Ripard wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its own clock (and own clock controller).
>
> Add a driver for the c
On 10/30, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index a9e1a5885846..40c32ffd912c 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -9,8 +9,9 @@ obj-y += clk-a10-mod1.o
> obj-y += clk-a10-pll2.o
> obj-y += clk-
On 10/30, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/clk-sun4i-display.c
> b/drivers/clk/sunxi/clk-sun4i-display.c
> new file mode 100644
> index ..f13b095c6d7a
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-display.c
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright 2015 Maxim
On 10/07, Maxime Ripard wrote:
> On Mon, Oct 05, 2015 at 11:09:29AM -0700, Stephen Boyd wrote:
> > On 10/05, Maxime Ripard wrote:
> > >
> > > Actually, the logic is also reversed.
> > >
> > > The divider driver will always try to find some rate that
On 10/05, Maxime Ripard wrote:
> Hi,
>
> On Fri, Oct 02, 2015 at 01:43:08PM -0700, Stephen Boyd wrote:
> > On 09/29, Maxime Ripard wrote:
> > > +
> > > + if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)
> > > +
On 09/29, Maxime Ripard wrote:
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU Gen
On 09/29, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/clk-a10-codec.c
> b/drivers/clk/sunxi/clk-a10-codec.c
> new file mode 100644
> index ..aaeccf8cde39
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-a10-codec.c
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright 2013 Emilio López
> + *
On 09/29, Maxime Ripard wrote:
> diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
> new file mode 100644
> index ..61097e365d55
> --- /dev/null
> +++ b/drivers/clk/clk-multiplier.c
> @@ -0,0 +1,176 @@
> +/*
> + * Copyright (C) 2015 Maxime Ripard
> + *
> + * This
On 09/18, Maxime Ripard wrote:
> The R8 is a new Allwinner SoC based on the A13. While both are very
> similar, there's still a few differences. Introduce a new compatible to
> deal with them.
>
> Signed-off-by: Maxime Ripard
> ---
Acked-by: Stephen Boyd
BTW, why is th
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