As part of our effort to move pinctrl/GPIO interlocking into the
driver where it belongs, this patch drops the definition and usage
of the mmc0_cd_pin_reference_design pinmux setting for the default
mmc0 card detect GPIO pin.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun4i-a10-a1000.dts
On Wed, Apr 19, 2017 at 11:36 PM, wrote:
> 在 2017-04-19 13:09，Chen-Yu Tsai 写道：
>>
>> As part of our effort to move pinctrl/GPIO interlocking into the
>> driver where it belongs, this patch drops the definition and usage
>> of the mmc0_cd_pin_reference_design pin
On Fri, Apr 21, 2017 at 3:59 AM, Priit Laes wrote:
> On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
>> Hi Priit,
>>
>> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
>> > > > +/* Not documented on A10 */
>> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-
On Tue, Apr 18, 2017 at 12:22 PM, Chen-Yu Tsai wrote:
> The pinmux setting nodes all have an address element in their node
> names, however the pinctrl node does not have #address-cells.
>
> Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi,
> dropping
; supply which gets various data from the PMIC, such as the battery status
>> (charging, discharging, full, dead), current max limit, current current,
>> battery capacity (in percentage), voltage max and min limits, current
>> voltage and battery capacity (in Ah).
>>
>>
defers if a backend was not registered.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 6 +-
drivers/gpu/drm/sun4i/sun4i_backend.h | 4
drivers/gpu/drm/sun4i/sun4i_drv.c | 2 ++
drivers/gpu/drm/sun4i/sun4i_drv.h | 4 +++-
drivers/gpu/drm/sun4i
ers for hardware that uses them.
The WiP HDMI driver will be the first.
While this series enables the second display pipeline, there's no
usable output at the moment. For the A31, the second TCON's panel
interface uses the same pins as the Ethernet controller. However
Ethernet is used on most
tcon0 contains a muxing register used to mux tcon output to downstream
hdmi or mipi dsi encoders. tcon0 must be available for the mux to be
configured.
Whether the display subsystem is enabled or not is now solely controlled
by the display-engine node.
Signed-off-by: Chen-Yu Tsai
---
arch/arm
Save a pointer to the backend's underlying device tree node in its
data structure. This will be used later for downstream tcons to find
and match their respective upstream backends.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 1 +
drivers/gpu/drm/
initializing the CRTC.
This patch figures out the backend's ID from the device tree and stores
it in the backend's data structure. It does this by looking at the "reg"
property of any remote endpoints connected to the backend's input port.
Signed-off-by: Chen-Yu Tsai
-
ely search upwards through the of_graph to find
the matching backend.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 55 +++---
1 file changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu
The tcons and backends have a one-to-one relationship. Their IDs,
or indexes in the documentation, are also the same.
Copy the ID from the associated backend and save it in the tcon
structure. This will later be used when we add support for the
output data path muxes.
Signed-off-by: Chen-Yu Tsai
Now that we support multiple instances of backends, the trailing 0
implying only one backend no longer makes sense.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b
it is supposed to use or program.
This patch adds the constraint that local endpoint IDs must be the index
or number of the remote endpoint's hardware block, for all components
in the display pipeline up to the TCONs.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/di
The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display
frontends, backends, and tcons each. The relationship between the
backends and tcons are 1:1, but the frontends can feed either backend.
Add device nodes and of graph nodes describing this relationship.
Signed-off-by: Chen-Yu
Hi,
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
> controller.
>
> That HDMI controller is able to do audio and CEC, but those have been left
> out for now.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/
On Mon, Apr 24, 2017 at 8:24 PM, Corentin Labbe
wrote:
> On Wed, Apr 12, 2017 at 02:41:53PM +0200, Maxime Ripard wrote:
>> On Wed, Apr 12, 2017 at 01:13:55PM +0200, Corentin Labbe wrote:
>> > The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
>> > connections. It is very similar to
On Tue, Apr 25, 2017 at 12:01 AM, Icenowy Zheng wrote:
> As axp20x-regulator now supports AXP803, add a cell for it.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Chen-Yu Tsai
> ---
> Changes in v4:
> - Added a trailing comma for new cell, for easier further cell addi
The sun4i DRM driver now uses 2 lists to track backends and tcons.
During the switch, the original tcon pointer was not removed.
As it is now unused, remove it, so other new drivers can't accidentally
use it.
Signed-off-by: Chen-Yu Tsai
---
As mentioned in the cover letter, please squash
x27;s internals.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 2 --
drivers/gpu/drm/sun4i/sun4i_tcon.c | 6 ++
drivers/gpu/drm/sun4i/sun4i_tv.c | 2 --
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
b/drivers/gpu/drm/su
the TCON clocks back inside the TCON driver.
Patch 3 cleans up a DRM driver debug message.
Regards
ChenYu
Chen-Yu Tsai (3):
drm/sun4i: Drop unused tcon pointer
drm/sun4i: Set TCON clock inside sun4i_tconX_mode_set
drm/sun4i: backend: Clarify sun4i_backend_layer_enable debug message
sun4i_backend_layer_enable can be called to enable or disable a layer.
However the debug message always says "Enable", which is confusing.
This patch makes the debug message vary according to the enable state.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c
On Wed, Apr 26, 2017 at 2:50 PM, Maxime Ripard
wrote:
> Hi Chen-Yu,
>
> On Fri, Apr 21, 2017 at 11:17:17PM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
>> wrote:
>> > The earlier Allwinner SoCs (A10, A10s, A20,
On Fri, Apr 28, 2017 at 5:24 PM, Menion wrote:
> Hello again
> I have modified the sun50i-h5-orangepi-pc2.dts
>
> r_gpio_keys {
> compatible = "gpio-keys";
>
> sw4 {
> label = "sw4";
> ---linux,code = <0x100>;
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm
locks that checks the
timing mode bit.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_phase.c | 47
drivers/clk/sunxi-ng/ccu_phase.h | 16 ++
2 files changed, 63 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_phase.c b/drivers/cl
the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock
ase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 911 +
drivers/cl
The datasheets for Allwinner SoCs set strict requirements on the
stability of the external crystal oscillators. Add the accuracy
for the main 24MHz oscillator to the device tree.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git
participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33
) offsets. Some differences include:
- D1/D2 style PLL clocks
- divisible audio module clocks
- new timing mode for mmc2 module clock
Regards
ChenYu
Chen-Yu Tsai (8):
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
clk: Provide option to query hardware for clk phase
On some hardware, the clk phase is tied to the parent clk's
rate and some clk delay programmed into the hardware. As the
parent clk rate changes, so does the clk phase.
Add a clk flag specifying not to use the cached clk phase,
but always query the hardware for it.
Signed-off-by: Chen-Yu
d A31/A31s clocks")
Cc: sta...@vger.kernel.org # 4.9.x-
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 89e68d29bf45..df
On some hardware, the clk phase is tied to the parent clk's
rate and some clk delay programmed into the hardware. As the
parent clk rate changes, so does the clk phase.
Add a clk flag specifying not to use the cached clk phase,
but always query the hardware for it.
Signed-off-by: Chen-Yu
styled (like the A80) clocks at
old (like A3x) offsets. Some differences include:
- D1/D2 style PLL clocks
- divisible audio module clocks
- new timing mode for mmc2 module clock
Regards
ChenYu
Chen-Yu Tsai (8):
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
clk: Provi
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm
the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock
ase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 911 +
drivers/cl
locks that checks the
timing mode bit.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_phase.c | 47
drivers/clk/sunxi-ng/ccu_phase.h | 16 ++
2 files changed, 63 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_phase.c b/drivers/cl
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a
The datasheets for Allwinner SoCs set strict requirements on the
stability of the external crystal oscillators. Add the accuracy
for the main 24MHz oscillator to the device tree.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git
participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> One of the possible output of the display pipeline, on the SoCs that have
> it, is the HDMI controller.
>
> Add a binding for it.
>
> Signed-off-by: Maxime Ripard
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 21 +++
On Wed, May 3, 2017 at 6:17 PM, Olliver Schinagl wrote:
> Hey Jamie,
>
> Several years ago you wrote the glue-code [0] for the DW 8250 IP. Over the
> years various 'fixes' have been applied to resolve certain 'weird' problems
> that Tim tried to fix with [1].
>
> After going over the datasheets an
gt; +
> +long divider_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate, const struct clk_div_table
> *table,
> + u8 width, unsigned long flags)
> +{
> + return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate,
Hi,
On Thu, May 4, 2017 at 4:34 AM, Maxime Ripard
wrote:
> Hi,
>
> On Wed, May 03, 2017 at 11:16:53AM +0800, Chen-Yu Tsai wrote:
>> The MMC clocks on newer SoCs, such as the A83T and H3, support the
>> "new timing mode". Under this mode, the output of the clock is
-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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For
let's
> just use it.
>
> Signed-off-by: Maxime Ripard
Otherwise,
Acked-by: Chen-Yu Tsai
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s at all.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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ed to do the reverse operation, we need to split out
> that code into a function that will be shared.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
Seems this would conflict with my "clk: sunxi-ng: Support multiple variable
pre-dividers" patch though. We'll se
anything.
>
> In order to be less confusing, and easier to use for downstream users,
> change the function name to something hopefully clearer, and return the
> adjusted rate instead of changing the pointer.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
--
You recei
> clk_hw_get_rate(parent));
> +
> + tmp_rate = round(cm, parent, &parent_rate, req->rate, data);
>
> - tmp_rate = round(cm, parent, &adj_parent_rate, req->rate,
> data);
> + /*
> +
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The video PLLs are used directly by the HDMI controller. Export them so
> that we can use them in our DT node.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
--
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at is needed is which TCON and encoder
are supposed to be muxed together. This is going to be per SoC type anyway.
I have something in the works, though it's not finished yet.
I think this works for now.
Acked-by: Chen-Yu Tsai
> +{
> + if (!tcon->quirks->
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> Even though that mux is undocumented, it seems like it needs to be set to 1
> when using composite, and 0 when using HDMI.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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; Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> It appears that the total vertical resolution needs to be doubled when
> we're not in interlaced. Make sure that is the case.
I think the total vertical resolution needs to be doubled in all cases.
It just happens that you should've been usin
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The generic connectors such as hdmi-connector doesn't have any driver in,
> so if they are added to the component list, we will be waiting forever for
> a non-existing driver to probe.
>
> Add a list of the connectors we want to ignore when bu
best_div = j;
> + goto out;
> + }
> +
> + if (abs(rate - rounded / i) <
> + abs(rate - best_parent / best_div)) {
> + best_parent = rounded;
&
#size-cells = <0>;
> +
> + hdmi_in: port@0 {
> + #address-cells = <1>;
> +
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The A10s Olinuxino has an HDMI connector. Make sure we can use it.
>
> Acked-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
> arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 29 +-
> 1 file c
On Thu, May 4, 2017 at 4:44 PM, Olliver Schinagl wrote:
> Hey Maxime,
>
> On 04-05-17 10:43, Maxime Ripard wrote:
>>
>> On Wed, May 03, 2017 at 04:40:02PM +0200, Olliver Schinagl wrote:
>>>
>>> This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
>>> storage.
>>> https://www.olim
> b/drivers/gpu/drm/sun4i/sun4i_tv.c
> index 542da220818b..a9cad00d4ee8 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tv.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
> @@ -22,10 +22,10 @@
> #include
> #include
>
> -#include &quo
ayers_init function name is still hardcoded and will be
> changed in the next patch), so that we can finally gain support for the
> mixer in DE2, which will has different layers.
... which has ...
>
> Signed-off-by: Icenowy Zheng
Otherwise,
Reviewed-by: Chen-Yu Tsai
--
You received t
e
> EXPORT_SYMBOL from backend code to layer code.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
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On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> As sun4i-backend is now a dedicated module, add an Kconfig option for
> it to make it optional, since some build may only use other engines.
>
> Signed-off-by: Icenowy Zheng
> ---
> Splited out patch.
>
> drivers/gpu/drm/sun4i/Kconfig | 10
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> Allwinner V3s SoC have a display engine which have a different pipeline
> with older SoCs.
>
> Add document for it (new compatibles and the new "mixer" part).
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Rob Herring
> ---
> Changes in v4:
>
m/boot/dts/sun8i-v3s.dtsi
> @@ -297,6 +297,15 @@
> function = "i2c0";
> };
>
> + lcd_rgb666_pins: lcd_rgb666@0 {
Drop the trailing "@0". Otherwise,
Acked-by: Chen-Yu
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
> which have RGB LCD output.
Please also mention that it only has one mixer.
For the subject, you could just say "Add device nodes for the display pipeline".
>
> Add devic
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> Allwinner V3s SoC features a TCON without channel 1.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
--
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"li
On Thu, May 4, 2017 at 9:49 PM, Icenowy Zheng wrote:
> From: Icenowy Zheng
Do you want to update your author email address?
>
> Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
> like A20.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
Same here.
For the subject
On Fri, May 5, 2017 at 12:52 AM, wrote:
> 在 2017-05-04 21:05，Maxime Ripard 写道：
>>
>> On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
>>>
>>> Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
>>> with mixers to do graphic processing and feed data to TCON, like
On Fri, May 5, 2017 at 4:36 PM, wrote:
> 在 2017-05-05 10:56，Chen-Yu Tsai 写道：
>>
>> On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
>>>
>>> As we are going to add support for the Allwinner DE2 engine in sun4i-drm
>>> driver, we will finally ha
On Thu, May 4, 2017 at 3:55 PM, Chen-Yu Tsai wrote:
> On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
> wrote:
>> The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
>> controller.
>>
>> That HDMI controller is able to do audio and CEC, but those
On Sat, May 13, 2017 at 11:02 PM, wrote:
> 在 2017-05-13 00:06，Maxime Ripard 写道：
>>
>> Hi Jernej,
>>
>> The patch content looks fine, but there's a few things that would need
>> to be addressed.
>>
>> On Wed, May 10, 2017 at 06:46:30PM +0200, Jernej Skrabec wrote:
>>>
>>> This commit adds support
On Thu, May 11, 2017 at 9:42 PM, Quentin Schulz
wrote:
> This adds support in X-Powers AXP20X and AXP22X battery driver for a
> fixed battery in DT.
>
> It will take the minimum supported voltage by the battery as defined in
> the battery DT node and set the V_OFF register to this value, telling
>
the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Signed-off-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33
- new timing mode for mmc2 module clock
Regards
ChenYu
Chen-Yu Tsai (6):
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
clk: sunxi-ng: Support multiple variable pre-dividers
clk: sunxi-ng: Add driver for A83T CCU
ARM: sun8i: a83t: Add CCU device nodes
ARM: sun8i: a
The datasheets for Allwinner SoCs set strict requirements on the
stability of the external crystal oscillators. Add the accuracy
for the main 24MHz oscillator to the device tree.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a
ase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/Kconfig | 11 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 910 +
drivers/cl
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm
the "correct" R_INTC, which we will use for A64
> SoC.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Rob Herring
The subject prefix might need a bit of work, but otherwise
Reviewed-by: Chen-Yu Tsai
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On Thu, May 18, 2017 at 3:39 PM, Maxime Ripard
wrote:
> On Thu, May 18, 2017 at 11:58:06AM +0800, Chen-Yu Tsai wrote:
>> +/*
>> + * MMC2 supports both old and new timing modes. When the new timing
>> + * mode is active, the output clock rate is halved by two. Here we
>>
d-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
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On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
> The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.
>
> Add its device node.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
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On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
> Allwinner A64 SoC features a R_INTC controller, which controls the NMI
> line, and this interrupt line is usually connected to the AXP PMIC.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen
On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
> As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
> like the old DTSI files for AXP20x/22x, for the common parts of the
> PMIC.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Mark Brown
Reviewe
Hi,
On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
> Add support of AXP803 regulators in the Pine64 device tree, in order to
> enable many future functionalities, e.g. Wi-Fi.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v6:
> - Rebased on next-20170517.
>
> .../arm64/boot/dts/allw
Hi,
On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
> The Wi-Fi module of Pine64 is powered via DLDO4 and ELDO1 (the latter
> one provides I/O voltage).
>
> Add device node for it.
>
> Although the Wi-Fi module is an external module which should be inserted
> to a header, according to my pe
On Fri, May 19, 2017 at 11:00 AM, Icenowy Zheng wrote:
>
>
> 于 2017年5月19日 GMT+08:00 上午10:54:21, Chen-Yu Tsai 写到:
>>Hi,
>>
>>On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
>>> Add support of AXP803 regulators in the Pine64 device tree, in order
>>
s a mix of new styled (like the A80) clocks at
old (like A3x) offsets. Some differences include:
- D1/D2 style PLL clocks
- divisible audio module clocks
- new timing mode for mmc2 module clock
Regards
ChenYu
Chen-Yu Tsai (6):
dt-bindings: clock: sunxi-ccu: Add compatible string for A
participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33
the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Signed-off-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm
The datasheets for Allwinner SoCs set strict requirements on the
stability of the external crystal oscillators. Add the accuracy
for the main 24MHz oscillator to the device tree.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a
ase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/Kconfig | 11 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 922 +
drivers/cl
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