Hi,
> Subject: [PATCH V1] ASoC: fsl_ssi: refine ipg clock usage in this module
>
> Move the ipg clock enable and disable operation to startup and shutdown,
> that is only enable ipg clock when ssi is working. we don't need to enable
> ipg clock in probe.
> Another register accessing need the ipg
How about the following :
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 5ae777a..d42f18c 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -15,7 +15,7 @@ config SND_SOC_FSL_ASRC
config SND_SOC_FSL_SAI
tristate "Synchronous Audio Interface (SAI) module s
> > > Lars-Peter Clausen & Arnd
> > >
> > > The purpose of Arnd's patch is same with me, which is to resolve the build
> > > error when SND_SOC_IMX_PCM_DMA=m & SND_SOC_FSL_SSI/SAI/ESAI/SPDIF=y, the
> > > error is "undefined reference to `imx_pcm_dma_init'".
> > > But Arnd's patch didn't involve thi
> Subject: Re: [alsa-devel] [PATCH V1 1/3] ASoC: fsl: Kconfig: remove dependence
> of SND_IMX_SOC for SND_SOC_IMX_PCM_DMA
>
> On Mon, Aug 18, 2014 at 06:52:46PM +0200, Lars-Peter Clausen wrote:
> > On 08/18/2014 10:38 AM, Shengjiu Wang wrote:
> > >Build kernel with SND_SOC_IMC_PCM_DMA=m && SND_IMX
> -Original Message-
> From: Nicolin Chen [mailto:nicoleots...@gmail.com]
> Sent: Thursday, July 17, 2014 9:22 PM
> To: broo...@kernel.org
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; alsa-
> de...@alsa-project.org; ti...@tabi.org; Xiubo Li-B47053; Wang Shengjiu-B02247
> Subject: [PATCH v4] ASoC: fsl_sai: Add clock controls for SAI
>
> The SAI mainly has the following clocks:
> bus clock
> control and configure registers and to generate synchronous
> interrupts and DMA requests.
>
> mclk1, mclk2, mclk3
> to generate the bit clock when the recei
> Subject: Re: [PATCH v2 2/2] ARM: dts: Append clock bindings for sai2 on VF610
> platform
>
> Hi Shawn,
>
>Thanks for the comments, but...
>
> On Wed, Apr 02, 2014 at 09:03:04PM +0800, Shawn Guo wrote:
> > On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote:
> > > Since we added f
> Subject: Re: [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI
>
> Hi Xiubo,
>
> On Fri, Apr 04, 2014 at 05:24:39PM +0800, Xiubo Li-B47053 wrote:
> > Hi,
> >
> > I have test this series on my Vybrid-TWR board and it works happily.
>
> You just checked the wrong version. I've sent a mail to
Hi,
I have test this series on my Vybrid-TWR board and it works happily.
[...]
> diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> index 3847d2a..2d749df 100644
> --- a/sound/soc/fsl/fsl_sai.c
> +++ b/sound/soc/fsl/fsl_sai.c
> @@ -428,5 +428,18 @@ static int fsl_sai_startup(struct
>
> Is that possible for you to test those two clock patches for fsl_sai?
>
> I think most of us are waiting for your reply to it. And I'd really
> like to move on to append clock dividing code into the driver so both
> of vybrid and imx can easily enable the DAI master mode.
>
Certainly, I wi
> Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
>
> The BCP bit in TCR4/RCR4 register rules as followings:
> 0 Bit clock is active high with drive outputs on rising edge
> and sample inputs on falling edge.
> 1 Bit clock is active low with drive outputs on falling
> @@ -1752,6 +1793,22 @@ static int fsl_diu_probe(struct platform_device *pdev)
> goto error;
> }
>
> + if (!diu_ops.set_pixel_clock) {
> + data->pixelclk_reg = of_iomap(np, 1);
> + if (!data->pixelclk_reg) {
> + dev_err(&pdev->de
> Subject: [PATCH] ASoC: fsl_sai: Fix buggy configurations in trigger()
>
> The current trigger() has two crucial problems:
> 1) The DMA request enabling operations (FSL_SAI_CSR_FRDE) for Tx and Rx are
>now totally exclusive: It would fail to run simultaneous Tx-Rx cases.
> 2) The TERE disabli
> > So let's just ignore the clearance of these bits in isr().
> >
> > +
> > SAI Transmit Control Register (I2S1_TCSR) : 32 : R/W : _h
>
> I'm talking about FWF and FRF bits, not TCSR as a register.
>
> > -
> >
> > I have checked in the Vybrid and LS1 SoC datasheets, and they are
> > > > > > > + if (xcsr & FSL_SAI_CSR_FWF)
> > > > > > > + dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
> > > > > > > +
> > > > > > > + if (xcsr & FSL_SAI_CSR_FRF)
> > > > > > > + dev_dbg(dev, "isr: Transmit FIFO watermark has been
> > > reached\n");
> > > > > > > +
> > >
> Subject: Re: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag
>
> On Thu, Mar 27, 2014 at 10:53:50AM +0800, Xiubo Li-B47053 wrote:
> > > On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
> > > > > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > > > > + regmap_w
> On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
> > > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > > + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
> > > +
> > > + if (xcsr & FSL_SAI_CSR_WSF)
> > > + dev_dbg(dev, "isr: Start of Tx word detected\n");
> > > +
> >
> + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
> +
> + if (xcsr & FSL_SAI_CSR_WSF)
> + dev_dbg(dev, "isr: Start of Tx word detected\n");
> +
> + if (xcsr & FSL_SAI_CSR_SEF)
> + dev_dbg(dev, "isr: Tx Frame
Hi Mark,
> Subject: Re: [PATCH] ASoC: fsl_sai: Fix one bug for hardware limitation.
>
> On Thu, Dec 26, 2013 at 10:57:22AM +0800, Xiubo Li wrote:
> > This is maybe one bug or a limitation of the hardware that the {T,R}CR2's
> > Synchronous Mode bits must be set as late as possible, or the SAI dev
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