Bits 48:51 in the PVR for POWER9 represent different chip types (scale
up vs out and 12 vs 24 core). Current chips have 0 here, but could be
non-zero in the future.
This changes the POWER9 DD1 mask to correctly ignore these bits 48:51.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cput
Michael Neuling writes:
> Bits 48:51 in the PVR for POWER9 represent different chip types (scale
> up vs out and 12 vs 24 core). Current chips have 0 here, but could be
> non-zero in the future.
>
> This changes the POWER9 DD1 mask to correctly ignore these bits 48:51.
>
> Signed-off-by: Michael
On Wed, 2017-06-07 at 17:24 +1000, Michael Ellerman wrote:
> Michael Neuling writes:
>
> > Bits 48:51 in the PVR for POWER9 represent different chip types (scale
> > up vs out and 12 vs 24 core). Current chips have 0 here, but could be
> > non-zero in the future.
> >
> > This changes the POWER9
Michael Neuling writes:
> On Wed, 2017-06-07 at 17:24 +1000, Michael Ellerman wrote:
>> Michael Neuling writes:
>>
>> > Bits 48:51 in the PVR for POWER9 represent different chip types (scale
>> > up vs out and 12 vs 24 core). Current chips have 0 here, but could be
>> > non-zero in the future.