Re: Memory Corruption in Linux kernel MPC8347 revision 3

Hi Boris, When you are running the memory test make sure Data cahe and Instruction caches are enabled. Also check your BAT setting, there also Cache enable BIT shall be set. As the burst transcation will happen only when cache is enabled. How abt ECC...? Bhupi On 7/17/07, Boris Shteinbock

Re: PageFault when I write in the Serial registers, MMU ?

Hi, You could call *io_block_mapping* function from your setup.c file that will add the entry into MMU. regards Bhupi On 7/11/07, Nicolas Mederle <[EMAIL PROTECTED]> wrote: Hi, I am porting linux on a custom board equipped with a PPC750, and I will like to have some advices on the MMU

Re: ARCH=ppc or ARCH=powerpc

Hi, All the new development is happening in arch/powerpc architecure. So it is good to use this architecure if you are upgrading the kernel. But it might not work with kernel 1.1.2, As arch/powerpc need a structure like open firmware for the parameters. If you want to stick to 1.1.2 u-boot ver

Re: ML403 gigabit ethernet bandwidth - 2.6 kernel

Hi, We need to findout where is the bottlenect. 1. Run vmstat on the ML403 board and find out the percentage CPU is busy when you are transferring the file. That will show if cpu is busy or not. 2. Run oprofile and find out which are the routines eating away the cpu time. Once we have data from

Re: Regarding MPC8540 IRQ Issue

nction one in each trial. But in none of them it jumped to interrupt handler. Please let me know whether this is the one you said to try or anything else. ? Thanks Sudheer Bhupender Saharan wrote: Hi Sudhir, >From the PCI dump it looks like IRQ PIN register is 0. During enumeration when BIOS

Re: Regarding MPC8540 IRQ Issue

Hi Sudhir, From the PCI dump it looks like IRQ PIN register is 0. During enumeration when BIOS sees that IRQ PIN register is 0, it would not allocate any interrupt for this card and that's why you are seeing IRQ Line register also as 0 value. We need to do some work around for this. IN the dr

Re: Problems with access to PCI on MVME3100

Hi Johan, From the pci log it looks like that BAR registers are not mapped properly by the BIOS/U-boot. Looks like you have 3 BARS which are asking for memory, But that are not spaced apart propoerly. Mean physical address difference between BAR0 and BAR2 shall be 512 Megabyte, but that is not

Re: Down when i get date from rtc by "hwclock --hctosys"

Hi Leo, Looks like your system is unstable when the cache is enabed. It might have nothing to do with generic RTC driver. Can you run cachebench or another memory benchmarks tools on the system and see if memory sub system is OK. Regards Bhupi On 5/17/07, liChunlin <[EMAIL PROTECTED]> wrote: