Re: [Mesa-dev] [PATCH 1/4] i965: Track last location of bo used for the batch

2017-07-07 Thread Chris Wilson
Quoting Daniel Vetter (2017-07-07 10:55:49) > On Mon, Jun 19, 2017 at 11:06:47AM +0100, Chris Wilson wrote: > > Borrow a trick from anv, and use the last known index for the bo to skip > > a search of the batch->exec_bo when adding a new relocation. In defence > > against the bo being used in multi

Re: [Mesa-dev] [PATCH 2/4] i965: Use I915_EXEC_NO_RELOC

2017-07-07 Thread Daniel Vetter
On Mon, Jun 19, 2017 at 11:06:48AM +0100, Chris Wilson wrote: > If we correctly fill the batch with the right relocation value, and that > matches the expected location of the object, we can then tell the kernel > it can forgo checking each individual relocation by only checking > whether the objec

Re: [Mesa-dev] [PATCH 1/4] i965: Track last location of bo used for the batch

2017-07-07 Thread Daniel Vetter
On Mon, Jun 19, 2017 at 11:06:47AM +0100, Chris Wilson wrote: > Borrow a trick from anv, and use the last known index for the bo to skip > a search of the batch->exec_bo when adding a new relocation. In defence > against the bo being used in multiple batches simultaneously, we check > that this slo

Re: [Mesa-dev] [PATCH 1/4] i965: Track last location of bo used for the batch

2017-07-07 Thread Daniel Vetter
On Mon, Jun 19, 2017 at 11:06:47AM +0100, Chris Wilson wrote: > Borrow a trick from anv, and use the last known index for the bo to skip > a search of the batch->exec_bo when adding a new relocation. In defence > against the bo being used in multiple batches simultaneously, we check > that this slo

Re: [Mesa-dev] [EGL android: accquire fence implementation] i965: Queue the buffer with a sync fence for Android OS

2017-07-07 Thread Chris Wilson
Quoting Zhongmin Wu (2017-07-07 09:07:06) > Before we queued the buffer with a invalid fence (-1), it will > make some benchmarks failed to test such as flatland. Create a fence, pass fence-fd to android? Instead of forcing a lot of busy work and using up another precious resource for everyone els

Re: [Mesa-dev] [PATCH 2/7] intel: Fix clflushing on modern (Baytrail+) Atom CPUs.

2017-07-07 Thread Daniel Vetter
On Wed, Jul 05, 2017 at 01:56:49PM -0700, Kenneth Graunke wrote: > Thanks to Chris Wilson for pointing this out. > > Cc: Jason Ekstrand > --- > src/intel/common/gen_clflush.h | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/src/intel/common/gen_clflush.h b/src/intel/common/

Re: [Mesa-dev] [PATCH 1/7] intel: Move clflush helpers from anv to common/gen_clflush.h.

2017-07-07 Thread Daniel Vetter
On Wed, Jul 05, 2017 at 01:56:48PM -0700, Kenneth Graunke wrote: > I want to use these in the OpenGL driver as well. > > Cc: Jason Ekstrand Reviewed-by: Daniel Vetter > --- > src/intel/common/gen_clflush.h | 56 > ++ > src/intel/vulkan/anv_batch_chain.

Re: [Mesa-dev] [PATCH 7/7] i965: Fix asynchronous mappings on !LLC platforms.

2017-07-07 Thread Daniel Vetter
On Thu, Jul 06, 2017 at 10:51:49PM -0700, Kenneth Graunke wrote: > On Wednesday, July 5, 2017 2:24:55 PM PDT Chris Wilson wrote: > > Quoting Kenneth Graunke (2017-07-05 21:56:54) > > In the meantime, s/else if (!bo->cache_coherent)/if (!bo->cache_coherent)/ > > Oh? I can do that. I figured that

Re: [Mesa-dev] [PATCH] [rfc] radv: offset images by a differing amount.

2017-07-07 Thread Dave Airlie
On 7 Jul. 2017 19:29, "Christian König" wrote: What tilling format have the destination textures? Sounds like the offset is just added so that we distribute memory accesses more equally over memory channels. >From the traces i think tile index mode was 10. Dave. Regards, Christian. Am 07.

Re: [Mesa-dev] [PATCH] swr/rast: Correctly allocate SWR_STATS memory as cacheline aligned

2017-07-07 Thread Emil Velikov
On 6 July 2017 at 19:55, Tim Rowley wrote: > Cacheline alignment of SWR_STATS to prevent sharing of cachelines > between threads (performance). > > Gets rid of gcc-7.1 warning about using c++17's over-aligned new > feature. > Thank you! > Cc: mesa-sta...@lists.freedesktop.org > --- > src/gallium

Re: [Mesa-dev] [PATCH] [rfc] radv: offset images by a differing amount.

2017-07-07 Thread Christian König
What tilling format have the destination textures? Sounds like the offset is just added so that we distribute memory accesses more equally over memory channels. Regards, Christian. Am 07.07.2017 um 09:18 schrieb Dave Airlie: From: Dave Airlie (this patch doesn't seem to work fully, hopeful

Re: [Mesa-dev] [PATCH 7/7] i965: Fix asynchronous mappings on !LLC platforms.

2017-07-07 Thread Chris Wilson
Quoting Kenneth Graunke (2017-07-07 06:51:49) > On Wednesday, July 5, 2017 2:24:55 PM PDT Chris Wilson wrote: > > Quoting Kenneth Graunke (2017-07-05 21:56:54) > > > --- > > > src/mesa/drivers/dri/i965/brw_bufmgr.c | 15 +-- > > > 1 file changed, 13 insertions(+), 2 deletions(-) > > >

Re: [Mesa-dev] [PATCH mesa] build systems: move git_sha1_gen.sh to bin/

2017-07-07 Thread Emil Velikov
On 6 July 2017 at 21:08, Eric Engestrom wrote: > There was no reason for this script to live outside the scripts > directory. > > Suggested-by: Brian Paul > Signed-off-by: Eric Engestrom Either place seems fine to me. Patch looks good,so Reviewed-by: Emil Velikov -Emil ___

Re: [Mesa-dev] [PATCH 6/7] i965: Don't use PREAD for glGetBufferSubData().

2017-07-07 Thread Chris Wilson
Quoting Kenneth Graunke (2017-07-07 06:19:07) > On Thursday, July 6, 2017 4:21:28 AM PDT Chris Wilson wrote: > > Quoting Kenneth Graunke (2017-07-05 21:56:53) > > > diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c > > > b/src/mesa/drivers/dri/i965/intel_buffer_objects.c > > > index a9

Re: [Mesa-dev] [PATCHv2] etnaviv: Add support for ETC2 texture compression

2017-07-07 Thread Wladimir
On Thu, Jul 6, 2017 at 4:01 PM, Wladimir wrote: > That the SRGB formats fail is expected (they're simply using RGB, this > is mentioned in the patch message), the discrepancy between > gc2000/gc3000 on RGB(A) is interesting, though, I'll look into it. I've not been able to figure this out. I've

[Mesa-dev] [EGL android: accquire fence implementation] i965: Queue the buffer with a sync fence for Android OS

2017-07-07 Thread Zhongmin Wu
Before we queued the buffer with a invalid fence (-1), it will make some benchmarks failed to test such as flatland. Now we get the out fence during the flushing buffer and then pass it to SurfaceFlinger in eglSwapbuffer function. Change-Id: Ic0773c19788d612a98d1402f5b5619dab64c1bc2 Tracked-On: h

Re: [Mesa-dev] [PATCH] etnaviv: fix refcnt initialization in etna_screen

2017-07-07 Thread Lucas Stach
Am Donnerstag, den 06.07.2017, 23:18 +0200 schrieb Aleksander Morgado: > Despite being a member of the etna_screen struct, 'refcnt' is used by > the winsys-specific logic to track the reference count of the object > managed in a hash table. When the count reaches zero, the pipe screen > is removed

[Mesa-dev] [PATCH] ddebug: fix parsing of the pipelined mode

2017-07-07 Thread Samuel Pitoiset
Trivial. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/ddebug/dd_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/ddebug/dd_screen.c b/src/gallium/drivers/ddebug/dd_screen.c index a5d2be1402..14e6f6b011 100644 --- a/src/gallium/drivers/dd

Re: [Mesa-dev] [PATCH 5/6] radeonsi: use slot indexes for bindless handles

2017-07-07 Thread Samuel Pitoiset
On 07/05/2017 01:42 PM, Nicolai Hähnle wrote: On 04.07.2017 15:05, Samuel Pitoiset wrote: Using VRAM address as bindless handles is not a good idea because we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize because it has no information about the pointer. Instead, use slots inde

[Mesa-dev] [PATCH] [rfc] radv: offset images by a differing amount.

2017-07-07 Thread Dave Airlie
From: Dave Airlie (this patch doesn't seem to work fully, hopefully AMD can tell us more info on the rules, and how to calculate the magic). It appears that to get full access to memory bandwidth with MRT rendering the pro vulkan driver seems to offset each image by 0x3800. I'm not sure how that

Re: [Mesa-dev] [PATCH 1/8] mesa: check for allocation failures in _mesa_new_texture_object()

2017-07-07 Thread Samuel Pitoiset
On 07/06/2017 08:06 PM, Andres Gomez wrote: It looks like we could want patches 1 and 3-8 from this series into -stable (?) These are not critical fixes, your call. On Wed, 2017-06-21 at 11:04 +0200, Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset --- src/mesa/main/texobj.c | 7 +

Re: [Mesa-dev] [PATCH 2/2] ac/nir: Fix ordering of parameters for image atomic cmpswap intrinsics

2017-07-07 Thread Alex Smith
Thanks. Yes, first patch is superseded. FWIW, James filed a bug against the CTS to add OpAtomicCompareExchange tests a couple of weeks ago: https://github.com/KhronosGroup/VK-GL-CTS/issues/47 On 7 July 2017 at 00:00, Bas Nieuwenhuizen wrote: > Thanks! Pushed and cc'd it to stable. > > Not pushin

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