Hi,
On (Mon) 25 Nov 2013 [10:07:40], Gal Hammer wrote:
> Fix a bug that was introduced in commit 386a5a1e. A removal of a device
> set the chr handlers to NULL. However when the device is plugged back,
> its read callback is not restored so data can't be transfter from the
> host to the guest via
On Thu, Nov 21, 2013 at 9:06 PM, Gerd Hoffmann wrote:
> On Do, 2013-11-21 at 13:12 +1000, Dave Airlie wrote:
>> On Wed, Nov 20, 2013 at 10:02 PM, Gerd Hoffmann wrote:
>> > On Mi, 2013-11-20 at 15:52 +1000, Dave Airlie wrote:
>> >> From: Dave Airlie
>> >>
>> >> This is a virtio-vga device built o
On 12/05/13 13:41, Stefan Weil wrote:
See https://bugs.launchpad.net/bugs/1258168
This fixes the compile issue I have seen so
Tested-by: Don Slutz
-Don Slutz
libcacard/vscclient.c: In function 'do_socket_read':
libcacard/vscclient.c:410: warning: implicit declaration of function
'g_warn
On 12/05/13 16:24, Richard Henderson wrote:
On 12/06/2013 04:18 AM, Paolo Bonzini wrote:
$ gcc -shared -o f.so f.c -fPIE -fPIC
/usr/bin/ld: /tmp/ccQc9els.o: relocation R_X86_64_PC32 against `f' can not be
used when making a shared object; recompile with -fPIC
/usr/bin/ld: final link failed: Bad
On Thu, Dec 5, 2013 at 6:52 PM, Gerd Hoffmann wrote:
> Hi,
>
>> > Hmm, why does it depend on the UI? Wasn't the plan to render into a
>> > dma-buf no matter what? Then either read the rendered result from the
>> > dmabuf (non-gl UI like vnc) or let the (gl-capable) UI pass the dma-buf
>> > to
Reviewed-by: Wenchao Xia
In qemu-1.4.x, When performing migrate_cancel on hmp, Sometimes
s->state is incorrrectly saved to MIG_STATE_ERROR instead of
MIG_STATE_CANCELLED.
If the migrate_fd_cancel in main thread is scheduled to run before
the thread buffered_file_thread calls migrate_fd_put_buffer, The
s->state will be mod
On 12/05/2013 08:08 AM, Paolo Bonzini wrote:
> Il 02/12/2013 17:43, Liu, Jinsong ha scritto:
>> From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
>> From: Liu Jinsong
>> Date: Fri, 29 Nov 2013 01:27:00 +0800
>> Subject: [PATCH 1/4] X86: Intel MPX definiation
>>
>> Signed-off-b
From: Mike Day
This enables hotplug for PHB bridges. Upon hotplug we generate the
OF-nodes required by PAPR specification and IEEE 1275-1994
"PCI Bus Binding to Open Firmware" for the device.
We associate the corresponding FDT for these nodes with the DrcEntry
corresponding to the slot, which wi
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> +if (invert) {
> +tcg_gen_not_i64(tcg_rm, tcg_rm);
> +}
> +
> +tcg_rd = cpu_reg(s, rd);
> +tcg_rn = cpu_reg(s, rn);
> +
> +switch (opc) {
> +case 0: /* AND, BIC */
> +case 3: /* ANDS, BICS */
> +tcg_gen_and_i
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> This patch adds support for C3.4.4 Logical (immediate),
> which include AND, ANDS, ORR, EOR.
>
> Signed-off-by: Alexander Graf
> [claudio: adapted to new decoder, function renaming,
> removed a TCG temp variable]
Reserve 32 entries of type PCI in each PHB's initial FDT. This
advertises to guests that each PHB is DR-capable device with
physical hotpluggable slots. This is necessary for allowing
hotplugging of devices to it later via bus rescan or guest rpaphp
hotplug module.
Each entry is assigned a name of
On 5 December 2013 22:33, Michael Roth wrote:
> Some kernels program a 0 address for io regions. PCI 3.0 spec
> sectio 6.2.5.1 doesn't seem to disallow this.
Hmm. The last PCI spec I looked at said 0 wasn't a valid MMIO
address, so the variant of this patch I wrote a while back made it
a per PCI
Signed-off-by: Michael Roth
---
hw/ppc/spapr_pci.c | 111
1 file changed, 111 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 5c099a8..6e7ee31 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -577,6 +577,11
On 12/05/2013 04:09 PM, Peter Maydell wrote:
> On 5 December 2013 22:51, Richard Henderson wrote:
>> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>>> +switch (opcode) {
>>> +case 2: /* UDIV */
>>> +handle_div(s, FALSE, sf, rm, rn, rd);
>>> +break;
>>> +case 3: /* SDIV *
Signed-off-by: Michael Roth
---
hw/pci/pci.c |3 ++-
include/hw/pci/pci.h |1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index ed32059..f15bbb0 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -103,7 +103,8 @@ static const VMStateDes
On Friday, December 6, 2013, Peter Maydell wrote:
> On 5 December 2013 22:51, Richard Henderson >
> wrote:
> > On 12/06/2013 10:51 AM, Peter Maydell wrote:
> >> +switch (opcode) {
> >> +case 2: /* UDIV */
> >> +handle_div(s, FALSE, sf, rm, rn, rd);
> >> +break;
> >> +ca
On 12/06/2013 12:09 PM, Peter Maydell wrote:
> On 5 December 2013 22:51, Richard Henderson wrote:
>> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>>> +switch (opcode) {
>>> +case 2: /* UDIV */
>>> +handle_div(s, FALSE, sf, rm, rn, rd);
>>> +break;
>>> +case 3: /* SDIV *
On 5 December 2013 22:51, Richard Henderson wrote:
> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>> +switch (opcode) {
>> +case 2: /* UDIV */
>> +handle_div(s, FALSE, sf, rm, rn, rd);
>> +break;
>> +case 3: /* SDIV */
>> +handle_div(s, TRUE, sf, rm, rn, rd);
>>
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana
>
> this patch adds support for the CLS instruction.
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper-a64.c| 10 ++
> target-arm/helper-a64.h|2 ++
> target-ar
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana
>
> this patch introduces wrappers for the clrsb builtins,
> which count the leading redundant sign bits.
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> include/qemu/host-utils.h | 32 +++
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana
>
> This patch implements the C3.4.2 Bitfield instructions:
> SBFM, BFM, UBFM.
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/translate-a64.c | 54
> ++
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana
>
> This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/translate-a64.c | 73
> +
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> This adds support for the C5.6.147 RBIT instruction.
>
> Signed-off-by: Alexander Graf
> [claudio: adapted to new decoder, use bswap64,
> make RBIT part standalone from the rest of the patch,
> splitting R
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana
>
> This patch adds support for decoding 1-src data processing insns,
> and the first user, C5.6.40 CLZ (count leading zeroes).
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper-a64.
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> This adds 2-src variable shift register instructions:
> C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
>
> Signed-off-by: Alexander Graf
> [claudio: adapted to new decoder, use enums for shift types]
> Signed-off
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> +switch (opcode) {
> +case 2: /* UDIV */
> +handle_div(s, FALSE, sf, rm, rn, rd);
> +break;
> +case 3: /* SDIV */
> +handle_div(s, TRUE, sf, rm, rn, rd);
> +break;
What are these all-caps TRUE/FALSE? stdboo
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> This patch adds emulation support for the EXTR instruction.
>
> Signed-off-by: Alexander Graf
>
> [claudio: adapted for new decoder, removed a few temporaries,
> fixed the 32bit bug, added checks for more
>
From: Nathan Fontenot
This extends the data structures currently used to report EPOW events to
gets via the check-exception RTAS interfaces to also include event types
for hotplug/unplug events.
This is currently undocumented and being finalized for inclusion in PAPR
specification, but we implem
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> Add support for the instructions described in
> "C3.4.6 PC-rel. addressing" (ADR and ADRP).
>
> Signed-off-by: Alexander Graf
> [claudio: adapted to new decoder structure]
> Signed-off-by: Claudio Fontana
> ---
> target-a
From: Tyrel Datwyler
We don't actually rely on this interface to surface hotplug events, and
instead rely on the similar-but-interrupt-driven check-exception RTAS
interface used for EPOW events. However, the existence of this interface
is needed to ensure guest kernels initialize the event-report
On 12/06/2013 11:31 AM, Peter Maydell wrote:
> On 5 December 2013 22:26, Richard Henderson wrote:
>> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>>> +if (cond >= 0x0e) { /* condition "always" */
>>> +tcg_src = read_cpu_reg(s, rn, sf);
>>> +tcg_gen_mov_i64(tcg_rd, tcg_src);
>>
Some kernels program a 0 address for io regions. PCI 3.0 spec
sectio 6.2.5.1 doesn't seem to disallow this.
Signed-off-by: Michael Roth
---
hw/pci/pci.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index f15bbb0..fe5729c 100644
--- a/hw/pci/p
From: Mike Day
Signed-off-by: Mike Day
Signed-off-by: Michael Roth
---
hw/ppc/spapr_pci.c | 93
include/hw/ppc/spapr.h | 28 +++
2 files changed, 121 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 7
Similar to memory_region_find, but only search for overlaps among
regions that are a child of the region passed in. This is useful
for finding free ranges within a parent range to map to, in
addition to the use-cases similarly served by memory_region_find.
Signed-off-by: Michael Roth
---
include
From: Tyrel Datwyler
This uses extension of existing EPOW interrupt/event mechanism
to notify userspace tools like librtas/drmgr to handle
in-guest configuration/cleanup operations in response to
device_add/device_del.
Userspace tools that don't implement this extension will need
to be run manua
From: Nathan Fontenot
Signed-off-by: Nathan Fontenot
Signed-off-by: Michael Roth
---
hw/ppc/spapr_pci.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 1046ec8..8df44a3 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spap
From: Nathan Fontenot
This add entries to the root OF node to advertise our PHBs as being
DR-capable in according with PAPR specification.
Each PHB is given a name of PHB, advertised as a PHB type,
and associated with a power domain of -1 (indicating to guests that
power management is handled au
Signed-off-by: Michael Roth
---
hw/ppc/spapr.c | 36
include/hw/ppc/spapr.h |2 ++
2 files changed, 38 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0607559..2250ee1 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -277,6 +
From: Mike Day
Signed-off-by: Mike Day
Signed-off-by: Michael Roth
---
hw/ppc/spapr_pci.c | 70
include/hw/ppc/spapr.h |7 -
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
ind
These patches are based on ppc-next, and can also be obtained from:
https://github.com/mdroth/qemu/commits/spapr-pci-hotplug-v2-ppc-next
v2:
* re-ordered patches to fix build bisectability (Alexey)
* replaced g_warning with DPRINTF in RTAS calls for guest errors (Alexey)
* replaced g_warnin
On 5 December 2013 22:26, Richard Henderson wrote:
> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>> +if (cond >= 0x0e) { /* condition "always" */
>> +tcg_src = read_cpu_reg(s, rn, sf);
>> +tcg_gen_mov_i64(tcg_rd, tcg_src);
>
> I wonder if it's worth adding that 0x0[ef] case to
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> +if (cond >= 0x0e) { /* condition "always" */
> +tcg_src = read_cpu_reg(s, rn, sf);
> +tcg_gen_mov_i64(tcg_rd, tcg_src);
I wonder if it's worth adding that 0x0[ef] case to the generic condition
processing rather than keep replicati
From: Claudio Fontana
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 73 +++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git
From: Alexander Graf
Add support for the instructions described in "C3.5.10 Logical
(shifted register)".
We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems
a better tradeoff than having to rework the whole 32 bit de
From: Claudio Fontana
this patch adds support for the CLS instruction.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
target-arm/helper-a64.c| 10 ++
target-arm/helper-a64.h|2 ++
target-arm/translate-a64.c | 20 +++-
3 files changed, 3
From: Alexander Graf
This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder, use enums for shift types]
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
targ
From: Alexander Graf
Add support for the instructions described in
"C3.4.6 PC-rel. addressing" (ADR and ADRP).
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana
---
target-arm/translate-a64.c | 25 +++--
1 file chang
From: Alexander Graf
This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder adding the 2-src decoding level,
always zero-extend result in 32bit mode]
Signed-off-by: Claudio Fo
From: Claudio Fontana
This patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ (count leading zeroes).
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
target-arm/helper-a64.c|5 +
target-arm/helper-a64.h|1 +
target-
The first chunk of A64 decoder patches have now made it through
code review, so as promised here's the next chunk. This is a
grabbag of miscellaneous logic and bit-twiddling operations,
plus some other minor stuff like ADR and conditional-select.
(Set three is probably going to be loads and stores
From: Claudio Fontana
this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
include/qemu/host-utils.h | 32
1 file changed, 32 insertions(+)
diff -
From: Claudio Fontana
This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 56 ++--
1 file changed, 54 in
From: Alexander Graf
This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable]
Signed-off-by: Claudio Fontana
[PMM: cleaned up some unneces
From: Alexander Graf
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf
[claudio: adapted for new decoder, removed a few temporaries,
fixed the 32bit bug, added checks for more
unallocated cases]
Signed-off-by: Claudio Fontana
Signed
From: Claudio Fontana
This patch implements the C3.4.2 Bitfield instructions:
SBFM, BFM, UBFM.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 54 ++--
1 file changed, 52 insertions(+), 2 deletions(-)
diff
From: Alexander Graf
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,
splitting REV into a separate patch]
Signed-off-by: Claudio Fontana
S
Create vexpress specific pflash registration
function which properly configures the device-width
of 16 bits (2 bytes) for the NOR flash on the
vexpress platform. This change is required for
buffered flash writes to work properly.
Signed-off-by: Roy Franz
---
hw/arm/vexpress.c | 44 +++
Now that we know how wide each flash device that makes up the bank is,
return status for each device in the bank. Leave existing code
that treats 32 bit wide banks as composed of two 16 bit devices as otherwise
we may break configurations that do not set the device_width propery.
Signed-off-by: R
This change fixes the CFI query responses to handle NOR device
widths that are different from the bank width. Support is also
added for multi-width devices in a x8 configuration. This is
typically x8/x16 devices, but the CFI specification mentions
x8/x32 devices so those should be supported as we
This patchset fixes buffered flash writes on the VExpress
platform. Buffered writes should now work properly on platforms whose
flash interface width is different from the device width. The default
is for the device-width to be set to 0, so platforms
that can benefit from this change will need to
For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, but also its maximum
width. The maximum width addressing mode is used for multi-width
parts no matter which width they are configured for. The most common
case is x16 parts that als
Rename the 'width' member of the pflash_t structure
in preparation for adding a bank_width member.
Signed-off-by: Roy Franz
Reviewed-by: Peter Maydell
---
hw/block/pflash_cfi01.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw
Fix NOR flash manufacturer and device ID reading. This now
properly takes into account device widths and device max widths
as required. The reading of these IDs uses the same max_width
dependent addressing as CFI queries.
The old code remains for chips that don't specify a device width,
as the n
The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes. This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs to be able to deter
On 12/06/2013 04:18 AM, Paolo Bonzini wrote:
> $ gcc -shared -o f.so f.c -fPIE -fPIC
> /usr/bin/ld: /tmp/ccQc9els.o: relocation R_X86_64_PC32 against `f' can not be
> used when making a shared object; recompile with -fPIC
> /usr/bin/ld: final link failed: Bad value
> collect2: ld returned 1 exit s
On 12/06/2013 04:45 AM, Tom Musta wrote:
> This patch adds the Single Precision VSX Scalar Fused Multiply-Add
> instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,
> xsnmaddmsp, xsnmsubasp, xsnmsubmsp.
>
> The existing VSX_MADD() macro is modified to support rounding of the
> inter
Commit 0f66998 added the command line option -enable-fips for qemu 1.2;
but as of at least qemu 1.6, the 'query-command-line-options' QMP
monitor command does not report it. This is particularly annoying since
the command line option is conditional - it is present in Linux builds
but absent in BSD
On 12/06/2013 01:39 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> This patch adds emulation for the compare and branch insns,
> CBZ and CBNZ.
>
> Signed-off-by: Alexander Graf
> [claudio: adapted to new decoder,
> compare with immediate 0,
> introduce read_cpu_reg to get
On 12/06/2013 01:39 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> Implement the B and BL instructions (PC relative branches and calls).
>
> For convenience in managing TCG temporaries which might be generated
> if a source register is the zero-register XZR, we provide a simple
> mechanism
On 12/05/2013 10:53 AM, Paolo Bonzini wrote:
> Il 14/11/2013 11:37, Michael S. Tsirkin ha scritto:
>> Several changes that affect compatibility between 1.8 and 1.7 are
>> already planned, so we need pc compat structures in place.
>>
>> Signed-off-by: Michael S. Tsirkin
>
> Is this patch in any tr
On 12/05/13 10:18, Paolo Bonzini wrote:
Il 04/12/2013 02:32, Don Slutz ha scritto:
Any hints or pointers about the bug in RHEL5 binutils? I can try and
make a patch to auto detect this.
Actually it's RHEL5 GCC:
$ cat f.c
void *
f(unsigned char *buf, int len)
{
return (void*)0L;
}
void
On 05.12.2013 19:35, Max Reitz wrote:
On 05.12.2013 18:41, Max Reitz wrote:
[…]
Second, if specifying a reference to an existing device should really
be supported, bdrv_open() should ideally not call bdrv_file_open()
anymore, but a function bdrv_find_ref() instead which resolves a
BlockdevRe
Am 05.12.2013 19:03, schrieb Don Slutz:
> On 12/05/13 12:24, Stefan Weil wrote:
[...]
>> @@ -760,7 +760,7 @@ main(
>> g_io_channel_unref(channel_stdin);
>> g_io_channel_unref(channel_socket);
>> -g_byte_array_unref(socket_to_send);
>> +g_byte_array_free(socket_to_send);
>>
See https://bugs.launchpad.net/bugs/1258168
libcacard/vscclient.c: In function 'do_socket_read':
libcacard/vscclient.c:410: warning: implicit declaration of function
'g_warn_if_reached'
libcacard/vscclient.c:410: warning: nested extern declaration of
'g_warn_if_reached'
libcacard/vscclient.c: In
On 05.12.2013 18:41, Max Reitz wrote:
[…]
Second, if specifying a reference to an existing device should really
be supported, bdrv_open() should ideally not call bdrv_file_open()
anymore, but a function bdrv_find_ref() instead which resolves a
BlockdevRef structure (for simplicity, it appears
Hi All,
I am looking for a way to emulate avoton processor. Is there
any pre-defined configuration to simulate an avoton based board with qemu?
At this point of time, I am trying to experiment with the various i2c
SoC, LPC of the processor.
Any pointers to jump start with this would be
Hi All,
I am looking for a way to emulate avoton processor. Is there
any pre-defined configuration to simulate an avoton based board with qemu?
At this point of time, I am trying to experiment with the various i2c
SoC, LPC of the processor.
Any pointers to jump start with this would be
On 12/05/13 12:24, Stefan Weil wrote:
See https://bugs.launchpad.net/bugs/1258168
libcacard/vscclient.c: In function 'do_socket_read':
libcacard/vscclient.c:410: warning: implicit declaration of function
'g_warn_if_reached'
libcacard/vscclient.c:410: warning: nested extern declaration of
'g_wa
This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel
---
Changes since v1:
- refactored AES code:
* use precomputed lookup tables for AESMC and AESIMC
* squash leaf functions add_sub_shift() and m
Il 14/11/2013 11:37, Michael S. Tsirkin ha scritto:
> Several changes that affect compatibility between 1.8 and 1.7 are
> already planned, so we need pc compat structures in place.
>
> Signed-off-by: Michael S. Tsirkin
Is this patch in any tree? Also, you mentioned you would pick up
Marcelo's 1
Hi everyone,
Quite recently, I sent a series to qemu-devel which allowed it to use
blkdebug and blkverify in some kind of a “native” QMP mode; that is,
there was no need to parse the filename anymore, instead everything
could be passed through the blockdev options.
The image filename could e
Quoting Alexey Kardashevskiy (2013-12-04 20:30:15)
> On 12/05/2013 12:19 PM, Michael Roth wrote:
> > Signed-off-by: Michael Roth
> > ---
> > hw/ppc/spapr.c | 36
> > include/hw/ppc/spapr.h |2 ++
> > 2 files changed, 38 insertions(+)
> >
> > dif
Quoting Alexey Kardashevskiy (2013-12-04 20:47:52)
> On 12/05/2013 12:19 PM, Michael Roth wrote:
> > From: Mike Day
> >
> > Signed-off-by: Mike Day
> > Signed-off-by: Michael Roth
> > ---
> > hw/ppc/spapr_pci.c | 72
> >
> > include/hw/pp
Am 05.12.2013 18:24, schrieb Stefan Weil:
> See https://bugs.launchpad.net/bugs/1258168
>
> libcacard/vscclient.c: In function 'do_socket_read':
> libcacard/vscclient.c:410: warning: implicit declaration of function
> 'g_warn_if_reached'
> libcacard/vscclient.c:410: warning: nested extern declarat
See https://bugs.launchpad.net/bugs/1258168
libcacard/vscclient.c: In function 'do_socket_read':
libcacard/vscclient.c:410: warning: implicit declaration of function
'g_warn_if_reached'
libcacard/vscclient.c:410: warning: nested extern declaration of
'g_warn_if_reached'
libcacard/vscclient.c: In
Signed-off-by: Benoit Canet
---
block.c | 32
blockdev.c| 13 +
hmp.c | 2 +-
include/block/block.h | 3 +++
qapi-schema.json | 9 +++--
qmp-commands.hx | 3 ++-
6 files changed, 54 insertion
Add the minimum of code to prepare for the following patches.
Signed-off-by: Benoit Canet
Reviewed-by: Eric Blake
---
block.c | 72 ++-
block/blkverify.c | 2 +-
block/iscsi.c | 2 +-
block/vmdk.c |
Signed-off-by: Benoit Canet
---
blockdev.c | 47 ---
hmp.c| 4 +++-
qapi-schema.json | 13 ++---
qmp-commands.hx | 11 ++-
4 files changed, 63 insertions(+), 12 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index
Signed-off-by: Benoit Canet
---
block.c | 16
blockdev.c| 5 +
include/block/block.h | 1 +
qapi-schema.json | 11 +++
qmp-commands.hx | 19 +++
5 files changed, 52 insertions(+)
diff --git a/block.c b/block.c
in
Signed-off-by: Benoit Canet
---
block.c | 68 +--
block/blkverify.c | 2 +-
include/block/block.h | 18 ++---
include/block/block_int.h | 12 ++---
4 files changed, 84 insertions(+), 16 deletions(-)
diff --git
Signed-off-by: Benoit Canet
---
blockdev.c | 13 +
hmp.c| 2 +-
qapi-schema.json | 10 --
qmp-commands.hx | 3 ++-
4 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index 5abf303..5bc9ddc 100644
--- a/blockdev.c
+++ b/
Signed-off-by: Benoit Canet
---
block.c | 44 +++-
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/block.c b/block.c
index 4f6b36a..61f5ba0 100644
--- a/block.c
+++ b/block.c
@@ -873,6 +873,7 @@ int bdrv_file_open(BlockDriverState **pbs, cons
This partial series start to add some node-name manipulation from QMP.
In particular it will allow to take snapshots of quorum files.
I propose reviewing it and merging if it's ok so quorum can be enabled and
merged and I could start enable other block filter feature while writing next
features. (Q
On Thu, Dec 05, 2013 at 02:40:00PM -0200, Marcelo Tosatti wrote:
> On Thu, Dec 05, 2013 at 05:02:02PM +0100, Paolo Bonzini wrote:
> > Il 05/12/2013 16:42, Fernando Luis Vazquez Cao ha scritto:
> > > (2013/12/05 22:53), Paolo Bonzini wrote:
> > >> Il 05/12/2013 14:15, Fernando Luis Vazquez Cao ha sc
Quoting Alexey Kardashevskiy (2013-12-04 20:33:55)
> On 12/05/2013 12:19 PM, Michael Roth wrote:
> > From: Mike Day
> >
> > Signed-off-by: Mike Day
> > Signed-off-by: Michael Roth
> > ---
> > hw/ppc/spapr_pci.c | 83
> >
> > include/hw/pp
On Thu, Dec 05, 2013 at 05:02:02PM +0100, Paolo Bonzini wrote:
> Il 05/12/2013 16:42, Fernando Luis Vazquez Cao ha scritto:
> > (2013/12/05 22:53), Paolo Bonzini wrote:
> >> Il 05/12/2013 14:15, Fernando Luis Vazquez Cao ha scritto:
> >>> /*
> >>> * KVM is yet unable to synchroni
Il 02/12/2013 17:45, Liu, Jinsong ha scritto:
> From 4a2eb0a8467b4f278e59d2df209a1bc03349d088 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong
> Date: Tue, 3 Dec 2013 06:28:20 +0800
> Subject: [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug
>
> EBX of cpuid(0xD, 0) is dynamic per XCR0 features enab
Il 05/12/2013 16:26, Liu, Jinsong ha scritto:
> Sorry, those macro seems too opaque to me, I try several ways but fail.
> Would you help me to add incremental patch based on current patches?
Something like this (untested):
diff --git a/target-i386/machine.c b/target-i386/machine.c
index ca8be7d..
Il 02/12/2013 17:46, Liu, Jinsong ha scritto:
> From e9ba40b3d1820b8ab31431c73226ee3ed485edd1 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong
> Date: Tue, 3 Dec 2013 07:02:27 +0800
> Subject: [PATCH 3/4] KVM/X86: Intel MPX vmx and msr handle
>
> Signed-off-by: Xudong Hao
> Signed-off-by: Liu Jinson
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