corrected typo, it's bitwise.
On 5/28/24 14:18, Harsh Prateek Bora wrote:
- (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value &
~(cs->nr_threads - 1))
+ (POWERPC_CPU(cs)->env.core_index)
Dont we want to keep the bitwise & with ~(cs->nr_threads - 1) ?
How's it taken care ?
In function kvm_virtio_pci_vector_use_one(), the function will only use
the irqfd/vector for itself. Therefore, in the undo label, the failing
process is incorrect.
To fix this, we can just remove this label.
Fixes: f9a09ca3ea ("vhost: add support for configure interrupt")
Cc:
On 5/27/24 10:02, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
On 5/26/24 17:56, Nicholas Piggin wrote:
The way SMT thread siblings are matched is clunky, using hard-coded
logic that checks the PIR SPR.
Change that to use a new core_index variable in the CPUPPCState,
where all siblings have the same core_index. CPU realize routines have
flexibility in
On 5/27/24 10:02, Jamin Lin wrote:
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and realize
On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
This patch adds the extioi virt extension support so that the IRQ can
route to 256 vcpus.
v4:
- Put patch3 ahead of patch2;
- patch1 Introduce two IRQ model(Extended IRQ model and Virt extended IRQ
model);
- Link to v3:
Remove myself from audio (both devices and backend) entries.
Flip status to "Orphan" for entries which have nobody else listed.
Cc: Manos Pitsidianakis
Cc: Matias Ezequiel Vara Larsen
Cc: Thomas Huth
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 30 ++
1 file
Remove myself from usb entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Manos Pitsidianakis
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Use MemTxAttrs interface read_with_attrs/write_with_attrs
for virt_iocsr_misc_ops.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 36
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index
Remove myself from spice and ui entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Manos Pitsidianakis
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Remove myself from virtio-gpu entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Manos Pitsidianakis
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
On LoongArch, IRQs can be routed to four vcpus with hardware extended
IRQ model. This patch adds the virt extension definition so that
the IRQ can route to 256 vcpus.
1.Extended IRQ model:
|
+---+ +-|+ +---+
This patch adds a new board attribute 'v-eiointc'.
A value of true enables the virt extended I/O interrupt controller.
VMs working in kvm mode have 'v-eiointc' enabled by default.
Signed-off-by: Song Gao
---
include/hw/loongarch/virt.h | 1 +
target/loongarch/cpu.h | 1 +
I have not found much time to work on qemu due to being busy with
firmware (edk2 for the most part). Time to update the MAINTAINERS
file entries to match reality.
I drop spice, ui, audio and usb due to lack of time.
I drop virtio-gpu, I don't follow recent development (venus etc.)
close enough
On 5/26/24 17:56, Nicholas Piggin wrote:
The chip_pir chip class method allows the platform to set the PIR
processor identification register. Extend this to a more general
ID function which also allows the TIR to be set. This is in
preparation for "big core", which is a more complicated
On 5/27/24 10:02, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
> > +fn read_type(mut fobj: ) -> Result
> > +{
> > +let mut tbuf = [0u8; 8];
> > +if let Err(e) = fobj.read_exact( tbuf) {
> > +if e.kind() == ErrorKind::UnexpectedEof {
> > +return Ok(RecordType::Empty);
> > +} else {
> > +
Add numa test case for loongarch system, it passes to run
with command "make check-qtest".
Signed-off-by: Bibo Mao
---
tests/qtest/meson.build | 2 +-
tests/qtest/numa-test.c | 53 +
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git
Add loongarch virt machine to the graph. It is a modified copy of
the existing riscv virtmachine in riscv-virt-machine.c
It contains a generic-pcihost controller, and an extra function
loongarch_config_qpci_bus() to configure GPEX pci host controller
information, such as ecam and pio_base
> > +/*
> > + * Refer to the description of ALLOWED_TYPES in
> > + * scripts/tracetool/__init__.py.
>
> Please don't reference the Python implementation because this will not
> age well. It may bitrot if the Python code changes or if the Python
> implementation is deprecated then the source file
This patch implements insert/remove software breakpoint process.
For RISC-V, GDB treats single-step similarly to breakpoint: add a
breakpoint at the next step address, then continue. So this also
works for single-step debugging.
Implement kvm_arch_update_guest_debug(): Set the control flag
when
If the breakpoint belongs to the userspace then set the ret value.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c
This series implements QEMU KVM Guest Debug on RISC-V, with which we
could debug RISC-V KVM guest from the host side, using software
breakpoints.
This series is based on riscv-to-apply.next branch (v9.0.0) and is also
available at:
To enable the KVM GUEST DEBUG for RISC-V at QEMU side.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
configs/targets/riscv64-softmmu.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/targets/riscv64-softmmu.mak
On 5/28/24 08:28, Harsh Prateek Bora wrote:
On 5/26/24 17:56, Nicholas Piggin wrote:
The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed
On 5/28/24 09:10, Harsh Prateek Bora wrote:
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
This will allow different settings and checks for different
machine types with later changes.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 35 ++-
1 file
Hello Aditya
On 5/28/24 09:05, Aditya Gupta wrote:
Power11 core is same as Power10, use the existing functionalities to
introduce a Power11 chip and machine, with Power10 chip as parent of
Power11 chip, thus going through similar class_init paths
This patch should come last, after all the
Hi Stefan,
[snip]
> > diff --git a/scripts/simpletrace-rust/.rustfmt.toml
> > b/scripts/simpletrace-rust/.rustfmt.toml
> > new file mode 100644
> > index ..97a97c24ebfb
> > --- /dev/null
> > +++ b/scripts/simpletrace-rust/.rustfmt.toml
> > @@ -0,0 +1,9 @@
> > +brace_style =
Currently, PCI link devices (PNP0C0F) are always created within the
scope of the PCI root complex. However, RISC-V needs PCI link devices to
be outside the scope of the PCI host bridge to properly enable the probe
order. This matches the example given in the ACPI specification section
6.2.13.1 as
PLIC and APLIC should be in namespace as well. So, add them using the
defined HID.
Signed-off-by: Sunil V L
---
hw/riscv/virt-acpi-build.c | 47 ++
1 file changed, 47 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index
RISC-V is going to use new HID RSCV0003 for generi UART. So, update the
HID.
Signed-off-by: Sunil V L
---
hw/riscv/virt-acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 47ec78e432..7f80368415 100644
This series adds few updates to RISC-V ACPI namespace for virt platform.
1) PCI Link devices need to be created outside the scope of the PCI root
complex to ensure correct probe ordering by the OS. This matches the
example given in ACPI spec as well.
2) Add PLIC and APLIC as platform devices as
To enable the KVM GUEST DEBUG for RISC-V at QEMU side.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
configs/targets/riscv64-softmmu.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/targets/riscv64-softmmu.mak
This series implements QEMU KVM Guest Debug on RISC-V, with which we
could debug RISC-V KVM guest from the host side, using software
breakpoints.
This series is based on riscv-to-apply.next branch (v9.0.0) and is also
available at:
This patch implements insert/remove software breakpoint process.
For RISC-V, GDB treats single-step similarly to breakpoint: add a
breakpoint at the next step address, then continue. So this also
works for single-step debugging.
Implement kvm_arch_update_guest_debug(): Set the control flag
when
If the breakpoint belongs to the userspace then set the ret value.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c
This can be used to force-synchronize the time in guest after a long
stop-cont pause, which can be useful for serverless-type workload.
Also add a comment to highlight the fact that this (and one other QMP
command) only works for the MC146818 RTC controller.
Acked-by: Philippe Mathieu-Daudé
On 5/27/24 8:01 PM, Philippe Mathieu-Daudé wrote:
Hi Daniil,
On 21/5/24 10:08, Daniil Tatianin wrote:
Could you please take a look at this revision? I think I've taken
everyone's feedback into account.
Sorry for the delay, I missed your patch since you didn't Cc me
(Markus asked me to look
On 5/28/24 09:05, Aditya Gupta wrote:
Skiboot/OPAL patches are in discussion upstream [1], with corresponding
commits in github repository [2].
Update skiboot.lid, with binary built from 'upstream_power11' branch
of skiboot repository with Power11 enablement patches [2].
---
This patch can be
Hi Zhiwei,
On Tue, May 28, 2024 at 8:57 AM LIU Zhiwei wrote:
>
> Hi Alexandre,
>
> I have sent the patch set about Zabha before last week.
Sorry I did not check!
>
> https://lore.kernel.org/all/fed99165-58da-458c-b68f-a9717fc15...@linux.alibaba.com/T/
>
> Welcome to review it and give
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
This will allow different settings and checks for different
machine types with later changes.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 35 ++-
1 file changed, 30 insertions(+), 5 deletions(-)
diff
Add sPAPR CPU Core definition for Power11
Cc: David Gibson (reviewer:sPAPR (pseries))
Cc: Harsh Prateek Bora (reviewer:sPAPR (pseries))
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by:
Power11 has the same PCR (Processor Compatibility Register) value, as
Power10.
Due to this, QEMU considers Power11 as a valid compat-mode for Power10,
ie. earlier it was possible to run QEMU with '-M
pseries,max-compat-mode=power11 --cpu power10'
Same PCR also introduced a regression where `-M
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Overview
Add support for Power11 pseries and powernv machine types, to emulate VMs
running on Power11.
As Power11 core is same as Power10, hence much of the code has been reused from
Power10.
Power11 was added in Linux in:
commit c2ed087ed35c ("powerpc: Add Power11 architected
Power11 core is same as Power10, use the existing functionalities to
introduce a Power11 chip and machine, with Power10 chip as parent of
Power11 chip, thus going through similar class_init paths
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc:
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Introduce 'PnvChipClass::logical_pvr' to know corresponding logical PVR
of a PowerPC CPU.
This helps to have a one-to-one mapping between PVR and logical PVR for
a CPU, and used in a later commit to handle cases where PCR of two
generations of Power chip is same, which causes regressions with
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by:
On 5/27/24 17:58, Philippe Mathieu-Daudé wrote:
Hi,
On 27/5/24 10:02, Jamin Lin wrote:
AST2700 fmc/spi controller's address decoding unit is 64KB
and only bits [31:16] are used for decoding. Introduce seg_to_reg
and reg_to_seg handlers for ast2700 fmc/spi controller.
In addition, adds ast2700
Hi Alexandre,
I have sent the patch set about Zabha before last week.
https://lore.kernel.org/all/fed99165-58da-458c-b68f-a9717fc15...@linux.alibaba.com/T/
Welcome to review it and give comments.
Thanks,
Zhiwei
On 2024/5/28 13:45, Alexandre Ghiti wrote:
From: Gianluca Guida
Add Zabha
On 5/27/24 18:06, Philippe Mathieu-Daudé wrote:
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
AST2700 support the maximum dram size is 8GiB
and has a "DMA DRAM Side Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
SPRC/SPRD were recently added to all BookS CPUs supported, but
they are only tested on POWER9 and POWER10, so restrict them to
those CPUs.
Hope you mean to restrict to P9/10 for both spapr and pnv or just pnv ?
SPR indirect scratch
On 21/05/2024 14.53, Alex Bennée wrote:
As Centos Stream 8 goes out of support we need to update. To do this
powertools is replaced by crb and we don't over specify the python3 we
want.
Signed-off-by: Alex Bennée
---
tests/vm/centos.aarch64 | 10 +-
1 file changed, 5 insertions(+),
On 21/05/2024 14.53, Alex Bennée wrote:
From the website:
"After May 31, 2024, CentOS Stream 8 will be archived and no further
updates will be provided."
We have updated a few bits but there are still references that need
fixing.
Signed-off-by: Alex Bennée
---
docs/devel/testing.rst | 8
On 5/24/2024 1:39 AM, Daniel Henrique Barboza wrote:
...
+/* 5.4 Features control register (32bits) */
+#define RISCV_IOMMU_REG_FCTL0x0008
Looks like doesn't support RISCV_IOMMU_FCTL_BE?
If so, need to implement it as read-only? along with other 2 bits.
IIUC,
diff --git
I just noticed that there is a typo in the subject:
s/warnigns/warnings/
On 28/05/2024 02.42, Nicholas Piggin wrote:
Reviewed-by: Thomas Huth
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
On 28/05/2024 02.42, Nicholas Piggin wrote:
The spapr QEMU machine defaults is useful outside libqos, so create a
new header for ppc specific qtests and move it there.
Signed-off-by: Nicholas Piggin
---
tests/qtest/libqos/libqos-spapr.h | 7 ---
tests/qtest/ppc-util.h| 19
On 5/28/24 03:34, Jamin Lin wrote:
Hi Cedric,
On 5/27/24 10:02, Jamin Lin wrote:
AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
Side
Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram address, new
On 28/05/2024 02.42, Nicholas Piggin wrote:
As Fabiano points out, this test isn't flaky it just can't run under
gitlab CI since runners have a very small shm size.
Suggested-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 18 +-
1 file
On 5/28/24 03:26, Jamin Lin wrote:
Hi Philippe, Cedric
On 27/5/24 13:18, Cédric Le Goater wrote:
On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up
Hi Stefan,
On Mon, May 27, 2024 at 03:59:44PM -0400, Stefan Hajnoczi wrote:
> Date: Mon, 27 May 2024 15:59:44 -0400
> From: Stefan Hajnoczi
> Subject: Re: [RFC 0/6] scripts: Rewrite simpletrace printer in Rust
>
> On Mon, May 27, 2024 at 04:14:15PM +0800, Zhao Liu wrote:
> > Hi maintainers and
On 5/26/24 17:56, Nicholas Piggin wrote:
The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed by the chiptod, which limits programming the
From: Glenn Miles
The LPC HC irq status register bits are set when an LPC IRQSER input is
asserted. These irq status bits drive the PSI irq to the CPU interrupt
controller. The LPC HC irq status bits are cleared by software writing
to the register with 1's for the bits to clear.
Existing
The POWER8 LPC ISA device irqs all get combined and reported to the line
connected the PSI LPCHC irq. POWER9 changed this so only internal LPC
host controller irqs use that line, and the device irqs get routed to
4 new lines connected to PSI SERIRQ0-3.
POWER9 also introduced a new feature that
On 5/26/24 17:56, Nicholas Piggin wrote:
This helps move core state from CPU to core structures.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_core.h | 1 +
hw/ppc/pnv_core.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/ppc/pnv_core.h
Here is v2 of the POWER9 PSI serirq patch with changes suggested by
Cedric and some other things. But also in front of that we have a fix
from Glenn for a lost interrupt problem.
I rebased Glenn's patch and also changed some comments and changelog
a bit so any bugs or silly comments are probably
From: Minwoo Im
This patch adds support for MCQ defined in UFSHCI 4.0. This patch
utilized the legacy I/O codes as much as possible to support MCQ.
MCQ operation & runtime register is placed at 0x1000 offset of UFSHCI
register statically with no spare space among four registers (48B):
From: Minwoo Im
This patch is a prep patch for the following MCQ support patch for
hw/ufs. This patch updated minimal mandatory fields to support MCQ
based on UFSHCI 4.0.
Signed-off-by: Minwoo Im
Reviewed-by: Jeuk Kim
Message-Id: <20240528023106.856777-2-minwoo...@samsung.com>
Signed-off-by:
/pull-ufs-20240528
for you to fetch changes up to 71a82d3f0555e65c98df129ce0e38b2aa5681ec0:
hw/ufs: Add support MCQ of UFSHCI 4.0 (2024-05-28 14:42:32 +0900)
Add support MCQ of UFSHCI 4.0
On Mon, May 27, 2024 at 05:15:05PM GMT, Cédric Le Goater wrote:
> On 5/27/24 09:10, Aditya Gupta wrote:
> > Power11 core is same as Power10, use the existing functionalities to
> > introduce a Power11 chip and machine, with Power10 chip as parent of
> > Power11 chip, thus going through similar
Hi Mads,
On Mon, May 27, 2024 at 12:49:06PM +0200, Mads Ynddal wrote:
> Date: Mon, 27 May 2024 12:49:06 +0200
> From: Mads Ynddal
> Subject: Re: [RFC 0/6] scripts: Rewrite simpletrace printer in Rust
> X-Mailer: Apple Mail (2.3774.600.62)
>
> Hi,
>
> Interesting work. I don't have any
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