On Fri, 17 Jun 2022 13:18:38 +0100
Joao Martins wrote:
> On 6/16/22 15:23, Igor Mammedov wrote:
> > On Fri, 20 May 2022 11:45:31 +0100
> > Joao Martins wrote:
> >
> >> It is assumed that the whole GPA space is available to be DMA
> >> addressable, wit
On Fri, 17 Jun 2022 12:13:45 +0100
Joao Martins wrote:
> On 6/16/22 14:30, Igor Mammedov wrote:
> > On Fri, 20 May 2022 11:45:30 +0100
> > Joao Martins wrote:
> >
> >> Use the pre-initialized pci-host qdev and fetch the
> >> pci-hole64-size int
On Fri, 17 Jun 2022 11:51:44 +0100
Jonathan Cameron wrote:
> On Thu, 16 Jun 2022 16:45:00 +0200
> Igor Mammedov wrote:
>
> > On Mon, 16 May 2022 16:51:34 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > From: Ben Widawsky
> > >
>
On Mon, 16 May 2022 16:51:34 -0400
"Michael S. Tsirkin" wrote:
> From: Ben Widawsky
>
> CXL host bridges themselves may have MMIO. Since host bridges don't have
> a BAR they are treated as special for MMIO. This patch includes
> i386/pc support.
> Also hook up the device reset now that we
On Fri, 20 May 2022 11:45:32 +0100
Joao Martins wrote:
> The added enforcing is only relevant in the case of AMD where the
> range right before the 1TB is restricted and cannot be DMA mapped
> by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
> or possibly other kinds of IOMMU
n may be desired and the CPU wasn't configured
> with a big enough phys-bits, print an error message to the user
> and do not make the relocation of the above-4g-region if phys-bits
> is too low.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Joao Martins
> ---
> hw/
AMD platforms).
with comments below fixed
Reviewed-by: Igor Mammedov
> Signed-off-by: Joao Martins
> ---
> hw/i386/pc_piix.c| 5 -
> hw/i386/pc_q35.c | 6 +++---
> hw/pci-host/i440fx.c | 3 +--
> include/hw/pci-host/i440fx.h | 2 +-
te to i440fx.
>
> This is in preparation to determine that host-phys-bits are
> enough and for pci-hole64-size to be considered to relocate
> ram-above-4g to be at 1T (on AMD platforms).
modulo nit blow
Reviewed-by: Igor Mammedov
>
> Signed-off-by: Joao Martins
> ---
> hw/i386/pc.
for relocating ram-above-4g to be
> dynamically start at 1T on AMD platforms.
possibly needs to be rebased on top of current master to include cxl_base
with comments fixed
Reviewed-by: Igor Mammedov
>
> Signed-off-by: Joao Martins
> ---
> hw/i386/acpi-build.c | 2 +
On Mon, 30 May 2022 11:40:47 +0800
Robert Hoo wrote:
suggest to put this patch as the 1st in series
(well you can rebase it on current master and
post that right away for merging since it doesn't
really depend on other patches, and post new patches on
top (whenever they are ready) will use
On Mon, 30 May 2022 11:40:45 +0800
Robert Hoo wrote:
> Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which
> depricates corresponding _DSM Functions defined by PMEM _DSM Interface spec
> [2].
>
> In this implementation, we do 2 things
> 1. Generalize the QEMU<->ACPI BIOS
On Mon, 30 May 2022 11:40:44 +0800
Robert Hoo wrote:
> The Intel Optane PMem DSM Interface, Version 2.0 [1], is the up-to-date
> spec for NVDIMM _DSM definition, which supports revision_id == 2.
>
> Nevertheless, Rev.2 of NVDIMM _DSM has no functional change on those Label
> Data _DSM
On Mon, 30 May 2022 11:40:42 +0800
Robert Hoo wrote:
> Signed-off-by: Robert Hoo
> Reviewed-by: Jingqi Liu
Reviewed-by: Igor Mammedov
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/tests/qtest/bios-table
On Wed, 15 Jun 2022 18:23:28 +0530
ritul guru wrote:
> Came across below link about QEMU to pass acpi tables to guest OS.
> https://wiki.qemu.org/Features/ACPITableGeneration
that link a bit outdated (project was completed but than later QEMU
moved on to built-in library for composing ACPI
On Tue, 14 Jun 2022 11:50:43 +0200
David Hildenbrand wrote:
> On 14.06.22 10:54, Igor Mammedov wrote:
> > On Mon, 13 Jun 2022 16:09:53 +0100
> > Stefan Hajnoczi wrote:
> >
> >> On Mon, Jun 13, 2022 at 05:01:10PM +0200, Julia Suvorova wrote:
> >>&
ip umbrella) and merge it
>
> Michael or Igor can merge it:
>
> $ scripts/get_maintainer.pl -f hw/mem/nvdimm.c
> Xiao Guangrong (maintainer:NVDIMM)
> "Michael S. Tsirkin" (supporter:ACPI/SMBIOS)
> Igor Mammedov (supporter:ACPI/SMBIOS)
> Ani Sinha (reviewer:ACPI/SMBIOS)
> qemu-devel@nongnu.org (open list:All patches CC here)
>
> Stefan
b9 qmp_x_exit_preconfig (qemu-system-x86_64 +
> 0x3471b9)
> #11 0x558c345497d9 qemu_init (qemu-system-x86_64 + 0x3497d9)
> #12 0x558c344e54c2 main (qemu-system-x86_64 + 0x2e54c2)
> #13 0x7fb109a7e34d __libc_start_main (libc.so.6 + 0x2534d)
> #14 0x558c
On Thu, 26 May 2022 22:40:05 +0800
Gavin Shan wrote:
> Hi Igor,
>
> On 5/26/22 8:25 PM, Igor Mammedov wrote:
> > On Wed, 18 May 2022 17:21:40 +0800
> > Gavin Shan wrote:
> >
> >> The {socket, cluster, core} IDs detected from Linux guest aren't
> &
On Fri, 20 May 2022 11:56:02 +0200
Li Zhang wrote:
> When no memory backend is specified in machine options,
> a default memory device will be added with default_ram_id.
> However, if a memory backend object is added in QEMU options
> and id is the same as default_ram_id, a coredump happens.
>
On Thu, 9 Jun 2022 11:30:14 +0200
Igor Mammedov wrote:
> On Wed, 8 Jun 2022 09:53:05 -0400
> Igor Mammedov wrote:
>
> > Changelog:
> > since v1:
> > * add tis 2.0 clarification to commit message (Ani Sinha)
> > * rebase on top of pci tree
> &g
0x08, // Length
+)
+ IRQNoFlags ()
+{8}
+})
+}
}
}
Signed-off-by: Igor Mammedov
---
v3:
update DSDT.cxl blob as well
---
tests/qtest/bios-tables-test-allowed-diff.h | 32
Signed-off-by: Igor Mammedov
---
v3:
- count in DSDT.cxl that just was merged upstream
---
tests/qtest/bios-tables-test-allowed-diff.h | 32 +
1 file changed, 32 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed
On Wed, 8 Jun 2022 09:53:05 -0400
Igor Mammedov wrote:
> Changelog:
> since v1:
> * add tis 2.0 clarification to commit message (Ani Sinha)
> * rebase on top of pci tree
> * pick up acks
tests fail due to new cxl testcase,
so I need to fixup whitelisting/blob u
0x20, // Length
-)
-IRQNoFlags ()
- {6}
- })
-}
-}
-
Scope (\_SB)
{
Scope (PCI0)
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/q35/DSDT.applesmc | Bi
.
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 34 --
hw/tpm/tpm_tis_isa.c | 32
2 files changed, 32 insertions(+), 34 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw
prologue/epilogue AML for each enumerated PCI
device.
Expected AML change is contextual, where ISA devices are moved
from separately declared _SB.PCI0.ISA scope , directly under
Device(ISA) node.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 16
the last remaining dependency on ISA in acpi-build.c
is iapc_boot_arch_8042() which pulls in in isa.h
in its own header hw/input/i8042.h. Clean up
not longer needed direct inclusion of isa.h in
acpi-build.c
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 1 -
1
tpm-tis 2.0, is not a PCI device but ISA one, move it
under ISA scope to fix incorrect placement.
Fixes: 24cf5413aa0 (acpi: Make TPM 2.0 with TIS available as MSFT0101)
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 3 +--
1 file changed
Device (ISA.TPM)
-{
- Name (_HID, EisaId ("PNP0C31")) // _HID: Hardware ID
-Name (_UID, One) // _UID: Unique ID
-Name (_STA, 0x0F) // _STA: Status
...
-}
Signed-off-by: Igor Mammedov
Acked-b
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/rtc/mc146818rtc.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index f235c2ddbe..ef9765bb8f 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
Signed-off-by: Igor Mammedov
Acked-by: Ani Sinha
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..7b3bf9a207 100644
--- a/tests/qtest
8
-}
-
-Name (_STA, 0x0F) // _STA: Status
-Method (RDPT, 0, NotSerialized)
-{
-Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */
-Return (Local0)
-}
-
-Method (WRPT, 1, NotSerialized)
-{
-PEPT = Arg0
-
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6b496480d2..1204b6da05 100644
--- a/hw/i386/acpi-build.c
+++ b
convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices
to a generic approach (i.e. make devices provide its own AML blobs
like it is done with other ISA devices (ex. KBD))
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
include/hw/acpi/ipmi.h | 9 ++--
hw/acpi/ipmi
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 7d238218ca..56498bbcc8 100644
--- a/tests/qtest/bios-tables-test.c
is a partial conversion, as it only fetches
AML from slave devices attached to its I2C bus.
The conversion will be completed when PCI bus is
switched to use AcpiDevAmlIf and build_smb0() could be
dropped.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/i2c/smbus_ich9.c | 15
0x08, // Length
+)
+ IRQNoFlags ()
+{8}
+})
+}
}
}
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 31
tests/data/acpi/pc/DSDT
.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
include/hw/misc/pvpanic.h | 9 -
hw/i386/acpi-build.c | 37 --
hw/misc/pvpanic-isa.c | 42 +++
3 files changed, 42 insertions(+), 46 deletions(-)
diff
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 31 +
1 file changed, 31 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..d95f4b25c4 100644
--- a/tests/qtest
-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
include/hw/isa/isa.h | 14 --
hw/i386/acpi-build.c | 22 --
hw/misc/applesmc.c | 29 +
3 files changed, 29 insertions(+), 36 deletions(-)
diff --git a/include/hw/isa/isa.h b/include/hw
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.pvpanic-isa| 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.pvpanic-isa
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest
ype
Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision
}
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
tests/qtest/bios-tables-test.c | 16
1 file changed, 16 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index
by default we do not version ACPI AML as it's considered
a part of firmware. Drop do_not_add_smb_acpi that blocked
SMBUS AML description on 3.1 and older machine types without
providing justification.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
we can keep this bit if anyone can
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index d896840270..7d238218ca 100644
--- a/tests/qtest/bios-tables-test.c
0x00, ResourceProducer, , Exclusive,
)
})
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/q35/DSDT.ipmismbus | Bin 8391 -> 8378 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/b
.. which will be used by follow up smbus-ipmi test-case
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.ipmismbus | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.ipmismbus
diff --git a/tests
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/char/serial-isa.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c
index 7a7ed239cd..141a6cb168 100644
--- a/hw/char/serial-isa.c
+++ b/hw/char/serial-isa.c
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/input/pckbd.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 4efdf75620..45c40fe3f3 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -29,7 +29,7
Settings
{
I2cSerialBusV2 (0x, ControllerInitiated, 0x000186A0,
- AddressingMode7Bit, "\\_SB.PCI0.SMB0",
+ AddressingMode7Bit, "^",
0x00, ResourceProducer, , Exclusive,
)
})
Signed-off-by: Igor Mammedov
Ack
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b4687d1cc8 100644
--- a/tests/qtest/bios-tables-test
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.applesmc | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.applesmc
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
include/hw/isa/isa.h | 1 -
hw/isa/isa-bus.c | 12 +---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 034d706ba1..5c5a3d43a7 100644
--- a/include/hw/isa/isa.h
prologue/epilogue AML for each enumerated PCI device.
Expected AML change is contextual, where ISA devices are moved from
separately declared _SB.PCI0.ISA scope, directly under Device(ISA)
node.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 30
Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision
}
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/q35/DSDT.ipmismbus | Bin 0 -> 8391 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.
To allow incremental conversion from ISADeviceClass::build_aml
to AcpiDevAmlIf, add support for the later without removing
the former. Once conversion is complete, another commit will
drop ISADeviceClass::build_aml related code.
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/char/parallel.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/char/parallel.c b/hw/char/parallel.c
index f735a6cd7f..1c9ca47820 100644
--- a/hw/char/parallel.c
+++ b/hw/char/parallel.c
@@ -28,7
. It will
allow get rid of some data-mining and ad-hoc AML building,
by asking device(s) to generate its own AML blob like it's
done for ISA devices.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
include/hw/acpi/acpi_aml_interface.h | 40
hw/acpi/acpi_interface.c
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/block/fdc-isa.c | 16 ++--
hw/i386/acpi-build.c | 1 -
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c
index fa20450747..fee1ca68a8 100644
--- a/hw/block/fdc-isa.c
for devices
that were missing them.
Igor Mammedov (35):
acpi: add interface to build device specific AML
acpi: make isa_build_aml() support AcpiDevAmlIf interface
acpi: fdc-isa: replace ISADeviceClass::build_aml with
AcpiDevAmlIfClass:build_dev_aml
acpi: parallel port: replace
On Mon, 6 Jun 2022 13:38:57 +0200
Julia Suvorova wrote:
> On Thu, Jun 2, 2022 at 5:20 PM Igor Mammedov wrote:
> >
> > On Fri, 27 May 2022 18:56:50 +0200
> > Julia Suvorova wrote:
> >
> > > The new test is run with a large number of cpus and
On Mon, 6 Jun 2022 12:52:00 +0200
Julia Suvorova wrote:
> On Thu, Jun 2, 2022 at 5:04 PM Igor Mammedov wrote:
> >
> > On Fri, 27 May 2022 18:56:48 +0200
> > Julia Suvorova wrote:
> >
> > > Introduce the 64-bit entry point. Since we no longer have a to
On Mon, 6 Jun 2022 13:11:36 +0200
Julia Suvorova wrote:
> On Thu, Jun 2, 2022 at 4:35 PM Igor Mammedov wrote:
> >
> > On Thu, 2 Jun 2022 16:31:25 +0200
> > Igor Mammedov wrote:
> >
> > > On Tue, 31 May 2022 14:40:15 +0200
> > > Julia Suvorova wro
On Fri, 27 May 2022 18:56:50 +0200
Julia Suvorova wrote:
> The new test is run with a large number of cpus and checks if the
> core_count field in smbios_cpu_test (structure type 4) is correct.
>
> Choose q35 as it allows to run with -smp > 255.
>
> Signed-off-by: Julia Suvorova
> ---
>
On Fri, 27 May 2022 18:56:48 +0200
Julia Suvorova wrote:
> Introduce the 64-bit entry point. Since we no longer have a total
> number of structures, stop checking for the new ones at the EOF
> structure (type 127).
>
> Signed-off-by: Julia Suvorova
> ---
> tests/qtest/bios-tables-test.c | 101
On Thu, 2 Jun 2022 16:31:25 +0200
Igor Mammedov wrote:
> On Tue, 31 May 2022 14:40:15 +0200
> Julia Suvorova wrote:
>
> > On Sat, May 28, 2022 at 6:34 AM Ani Sinha wrote:
> > >
> > >
> > >
> > > On Fri, 27 May 2022, Julia Suvorova wro
; > > +uint16_t core_count2;
> > > +uint16_t core_enabled2;
> > > +uint16_t thread_count2;
> >
> > I would add a comment along the lines of
> > /* section 7.5, table 21 smbios spec version 3.0.0 */
>
> Ok
With Ani's comment fixed
Paolo,
can you pick this up if it looks fine, please?
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
> Igor Mammedov (2):
> x86: cpu: make sure number of addressable IDs for processor cores
> meets the spec
> x86: cpu: fixup number of addressable IDs for logica
On Fri, 27 May 2022 06:18:43 +0800
maobibo wrote:
> On 5/26/22 16:42, Igor Mammedov wrote:
> > On Tue, 24 May 2022 16:18:01 +0800
> > Xiaojuan Yang wrote:
> >
> > commit message needs pointers to specification,
> > + in patch comments that point to spec
On Wed, 18 May 2022 12:29:25 -0400
"Michael S. Tsirkin" wrote:
> On Tue, May 17, 2022 at 10:13:51AM +0200, Gerd Hoffmann wrote:
> > That problem isn't new and we already have a bunch of aml_* stubs
> > because of that. I expect it'll work just fine, at worst we'll
> > have to add a stub or two
On Thu, 26 May 2022 19:37:47 +0800
Gavin Shan wrote:
> Hi Igor, Yanan and maintainers,
>
> On 5/18/22 5:21 PM, Gavin Shan wrote:
> > The {socket, cluster, core} IDs detected from Linux guest aren't
> > matching with what have been provided in PPTT. The flag used for
> > 'ACPI Processor ID
On Wed, 18 May 2022 17:21:40 +0800
Gavin Shan wrote:
> The {socket, cluster, core} IDs detected from Linux guest aren't
> matching with what have been provided in PPTT. The flag used for
> 'ACPI Processor ID valid' is missed for {socket, cluster, core}
> nodes.
To permit this flag set on no
On Tue, 24 May 2022 16:18:01 +0800
Xiaojuan Yang wrote:
commit message needs pointers to specification,
+ in patch comments that point to specific chapters
within the spec for newly introduced registers
> From: Song Gao
>
> Signed-off-by: Xiaojuan Yang
> Signed-off-by: Song Gao
> ---
>
On Tue, 24 May 2022 14:48:29 -0500
"Moger, Babu" wrote:
> On 5/24/22 10:19, Igor Mammedov wrote:
> > On Tue, 24 May 2022 11:10:18 -0400
> > Igor Mammedov wrote:
> >
> > CCing AMD folks as that might be of interest to them
>
> I am trying to recr
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
CCing AMD folks as that might be of interest to them
> Igor Mammedov (2):
> x86: cpu: make sure number of addressable IDs for processor cores
> meets the spec
> x86: cpu: fixup number of addressable IDs for logica
Igor Mammedov (2):
x86: cpu: make sure number of addressable IDs for processor cores
meets the spec
x86: cpu: fixup number of addressable IDs for logical processors
sharing cache
target/i386/cpu.c | 20
1 file changed, 16 insertions(+), 4 deletions
ubset of
bits of the initial APIC ID.
"
ensure that values stored in EAX[31-26] always meets this condition.
Signed-off-by: Igor Mammedov
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 35c3475e6c..bbe37dc
/0x590
start_secondary+0x5b/0x150
secondary_startup_64_no_verify+0xc2/0xcb
Fix it by capping max number of logical processors to vcpus/socket
as it was configured, which fixes the issue.
Signed-off-by: Igor Mammedov
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2088311
---
PS
On Mon, 16 May 2022 16:46:29 -0400
"Michael S. Tsirkin" wrote:
> On Mon, May 16, 2022 at 11:26:03AM -0400, Igor Mammedov wrote:
> > .. and clean up not longer needed conditionals in DSTD build code
> > pvpanic-isa AML will be fetched and included when ISA bridge will
&
On Wed, 18 May 2022 16:06:47 +0200
Paolo Bonzini wrote:
> On 5/18/22 15:31, Daniel P. Berrangé wrote:
> > When picking defaults there is never a perfect answer, it
> > is more a matter of the least-worst option.
> >
> > It is pretty clear that nthreads=1 is terrible for any
> > large VMs.
On Wed, 18 May 2022 14:33:12 +0530
Ani Sinha wrote:
> On Mon, May 16, 2022 at 8:57 PM Igor Mammedov wrote:
> >
> > tpm-tis, is not a PCI device but ISA one, move it
> > under ISA scope to fix incorrect placement.
>
> This description is a little misleading. What w
On Wed, 18 May 2022 15:30:07 +0530
Ani Sinha wrote:
> On Mon, May 16, 2022 at 8:56 PM Igor Mammedov wrote:
> >
> > There is already ISADeviceClass::build_aml() callback which
> > builds device specific AML blob for some ISA devices.
> > To extend the same
a divide
> by zero error if we continued with other validation checks. Hence, we should
> simply return from this function upon validation failure.
>
> CC: Peter Maydell
> CC: Eric DeVolder
> Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
> ---
> hw/acpi/erst.c | 3 ++
On Thu, 19 May 2022 13:53:49 +0700
Suravee Suthikulpanit wrote:
> On 5/13/22 6:23 PM, Michael S. Tsirkin wrote:
> > On Mon, May 09, 2022 at 09:12:49AM +0200, Igor Mammedov wrote:
> >> On Wed, 4 May 2022 08:16:39 -0500
> >> Suravee Suthikulpanit wrote:
> >>
On Wed, 18 May 2022 08:20:56 +0800
Robert Hoo wrote:
> On Fri, 2022-05-06 at 11:23 +0200, Igor Mammedov wrote:
> >
> > >
> > > No, sorry, I didn't explain it clear.
> > > No extra interface/ABI but these 3 must _LS{I,R,W} nvdimm-sub-
> > &g
On Wed, 18 May 2022 12:29:25 -0400
"Michael S. Tsirkin" wrote:
> On Tue, May 17, 2022 at 10:13:51AM +0200, Gerd Hoffmann wrote:
> > That problem isn't new and we already have a bunch of aml_* stubs
> > because of that. I expect it'll work just fine, at worst we'll
> > have to add a stub or two
On Tue, 17 May 2022 20:46:50 +0200
Paolo Bonzini wrote:
> On 5/17/22 14:38, dzej...@gmail.com wrote:
> > From: Jaroslav Jindrak
> >
> > Prior to the introduction of the prealloc-threads property, the amount
> > of threads used to preallocate memory was derived from the value of
> > smp-cpus
On Tue, 17 May 2022 17:33:54 +0100
Daniel P. Berrangé wrote:
> On Tue, May 17, 2022 at 05:12:28PM +0200, Igor Mammedov wrote:
> > On Tue, 17 May 2022 14:38:58 +0200
> > dzej...@gmail.com wrote:
> >
> > > From: Jaroslav Jindrak
> > >
> > > P
On Mon, 16 May 2022 16:47:20 -0400
"Michael S. Tsirkin" wrote:
> On Mon, May 16, 2022 at 11:25:35AM -0400, Igor Mammedov wrote:
> >
> > Series is excerpt form larger refactoring that does
> > the same for PCI devices, but it's too large at this
> > point
On Mon, 16 May 2022 16:46:29 -0400
"Michael S. Tsirkin" wrote:
> On Mon, May 16, 2022 at 11:26:03AM -0400, Igor Mammedov wrote:
> > .. and clean up not longer needed conditionals in DSTD build code
> > pvpanic-isa AML will be fetched and included when ISA bridge will
&
On Tue, 17 May 2022 14:38:58 +0200
dzej...@gmail.com wrote:
> From: Jaroslav Jindrak
>
> Prior to the introduction of the prealloc-threads property, the amount
> of threads used to preallocate memory was derived from the value of
> smp-cpus passed to qemu, the amount of physical cpus of the
Device (ISA.TPM)
-{
- Name (_HID, EisaId ("PNP0C31")) // _HID: Hardware ID
-Name (_UID, One) // _UID: Unique ID
-Name (_STA, 0x0F) // _STA: Status
...
-}
Signed-off-by: Igor Mammedov
---
te
.
Signed-off-by: Igor Mammedov
---
include/hw/misc/pvpanic.h | 9 -
hw/i386/acpi-build.c | 37 --
hw/misc/pvpanic-isa.c | 42 +++
3 files changed, 42 insertions(+), 46 deletions(-)
diff --git a/include/hw/misc
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.pvpanic-isa| 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.pvpanic-isa
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.applesmc | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.applesmc
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios
.. which will be used by follow up smbus-ipmi test-case
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.ipmismbus | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.ipmismbus
diff --git a/tests
by default we do not version ACPI AML as it's considered
a part of firmware. Drop do_not_add_smb_acpi that blocked
SMBUS AML description on 3.1 and older machine types without
providing justification.
Signed-off-by: Igor Mammedov
---
we can keep this bit if anyone can prove/report adverse effect
prologue/epilogue AML for each enumerated PCI
device.
Expected AML change is contextual, where ISA devices are moved
from separately declared _SB.PCI0.ISA scope , directly under
Device(ISA) node.
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 16 +++-
hw/isa/piix3.c | 17
the last remaining dependency on ISA in acpi-build.c
is iapc_boot_arch_8042() which pulls in in isa.h
in its own header hw/input/i8042.h. Clean up
not longer needed direct inclusion of isa.h in
acpi-build.c
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion
convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices
to a generic approach (i.e. make devices provide its own AML blobs
like it is done with other ISA devices (ex. KBD))
Signed-off-by: Igor Mammedov
---
include/hw/acpi/ipmi.h | 9 ++--
hw/acpi/ipmi-stub.c| 2 +-
hw/acpi
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..7b3bf9a207 100644
--- a/tests/qtest/bios-tables-test
901 - 1000 of 11116 matches
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