'id' of memory-backend-{file,ram} is not only for '-numa''s reference, but
also other parameters like '-device nvdimm'.
More clearly call out this to avoid misinterpretation.
Signed-off-by: Robert Hoo
---
qemu-options.hx | 6 +++---
1 file changed, 3 insertio
As it's been marked deprecated since v5.2, now I think it's time remove it
from code.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 118 --
1 file changed, 118 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
ind
On Tue, 2021-04-27 at 16:55 -0400, Eduardo Habkost wrote:
> On Thu, Apr 22, 2021 at 05:42:16PM +0800, Robert Hoo wrote:
> > As it's been marked deprecated since v5.2, now I think it's time
> > remove it
> > from code.
> >
> > Signed-off-by: Robert Ho
As it's been marked deprecated since v5.2, now I think it's time remove it
from code.
Signed-off-by: Robert Hoo
---
P.S.
Since previously no its deprecation info was recorded in
docs/system/deprecated.rst, nothing to update it.
---
docs/system/removed-features.rst | 5 ++
target/
As it's been marked deprecated since v5.2, now I think it's time remove it
from code.
Signed-off-by: Robert Hoo
---
(Sorry, forgot to append changelog in last send.)
Changelog:
v2:
Update removed-features.rst.
Since previously no its deprecation info was recorded in
d
On Wed, 2021-04-28 at 11:24 -0400, Eduardo Habkost wrote:
> On Wed, Apr 28, 2021 at 10:41:13AM +0800, Robert Hoo wrote:
> > As it's been marked deprecated since v5.2, now I think it's time
> > remove it
> > from code.
> >
> > Signed-off-by: Rober
As it's been marked deprecated since v5.2, now I think it's time remove it
from code.
Signed-off-by: Robert Hoo
---
Changelog:
v3:
Update deprecated.rst. (Sorry for my carelessness in last search. I
sware I did search.)
v2:
Update removed-features.rst.
---
docs/system/depr
moval has come.
> Extra points for telling us in a reply. "We should remove, but I
> can't
> do it myself right now" is a valid answer. Let's review the file:
>
> System emulator command line arguments
> --
>
[.
Ping for review ...
Thanks.
On Thu, 2021-04-22 at 16:42 +0800, Robert Hoo wrote:
> 'id' of memory-backend-{file,ram} is not only for '-numa''s
> reference, but
> also other parameters like '-device nvdimm'.
> More clearly call out this to avoid mi
On Wed, 2020-09-09 at 14:15 -0400, Eduardo Habkost wrote:
> Hi,
>
> Thanks for the patch, and sorry for taking so long to review
> this. I'm finally getting to the patches that were postponed to
> 5.2.
>
> Comments and questions below:
>
> On Thu, Jun 11, 2020
On Fri, 2020-09-11 at 10:00 -0400, Eduardo Habkost wrote:
> On Fri, Sep 11, 2020 at 02:22:51PM +0800, Robert Hoo wrote:
> > On Wed, 2020-09-09 at 14:15 -0400, Eduardo Habkost wrote:
> > > Hi,
> > >
> > >
> > > > @@ -1129,6 +1130,12 @@ void mach
On Mon, 2020-09-14 at 13:38 +, Eduardo Habkost wrote:
> On Mon, Sep 14, 2020 at 06:50:09PM +0800, Robert Hoo wrote:
> > On Fri, 2020-09-11 at 10:00 -0400, Eduardo Habkost wrote:
> > > On Fri, Sep 11, 2020 at 02:22:51PM +0800, Robert Hoo wrote:
> > > > On Wed, 2020
On Mon, 2020-02-24 at 08:13 -0800, Richard Henderson wrote:
> On 2/23/20 11:07 PM, Robert Hoo wrote:
> > Inspired by your suggestion, I'm thinking go further: use immediate
> > rather than a global variable, so that saves 1 memory(/cache)
> > access.
> >
: handle the case in select_accel_fn(), and have a
global variable alongside buffer_accel)
3. Changes avx512f configuration option's default status to disabled.
4. Ran 'make check-unit' on this patch, on both a Ivybridge machine and a
CascadeLake machine.
Robert Hoo (2):
configur
/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Robert Hoo
---
configure | 41 +
1 file changed, 41 insertions(+)
diff --git a/configure b/configure
index d57261e..a0b41ce 100755
--- a
.
buffer_zero_avx2()).
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 64
2 files changed, 58 insertions(+), 9 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 6930170..09fc245
anges avx512f configuration option's default status to disabled.
4. Ran 'make check-unit' on this patch, on both a Ivybridge machine and a
CascadeLake machine.
Robert Hoo (2):
configure: add configure option avx512f_opt
util: add util function buffer_zero_avx512()
-programming-reference.pdf
Signed-off-by: Robert Hoo
---
configure | 41 +
1 file changed, 41 insertions(+)
diff --git a/configure b/configure
index d57261e..a0b41ce 100755
--- a/configure
+++ b/configure
@@ -1395,6 +1395,11 @@ for opt do
;;
--enable-avx2
.
buffer_zero_avx2()).
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 67 +---
2 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 6930170..09fc245 100644
--- a
On Fri, 2020-02-28 at 18:09 -0800, Richard Henderson wrote:
> On 2/27/20 6:24 PM, Robert Hoo wrote:
> > if ((bv & 6) == 6 && (b & bit_AVX2)) {
> > cache |= CACHE_AVX2;
> > }
> > +
.
buffer_zero_avx2()).
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 74 +---
2 files changed, 67 insertions(+), 10 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 6930170..09fc245 100644
--- a
e the case in select_accel_fn(), and have a
global variable alongside buffer_accel)
3. Changes avx512f configuration option's default status to disabled.
4. Ran 'make check-unit' on this patch, on both a Ivybridge machine and a
CascadeLake machine.
Robert Hoo (2):
configure: add configu
-programming-reference.pdf
Signed-off-by: Robert Hoo
Reviewed-by: Richard Henderson
---
configure | 41 +
1 file changed, 41 insertions(+)
diff --git a/configure b/configure
index d57261e..a0b41ce 100755
--- a/configure
+++ b/configure
@@ -1395,6 +1395,11 @@ for
Hi, Ping for comments:)
On Thu, 2020-06-11 at 10:47 +0800, Robert Hoo wrote:
> Complement versioned CPU model framework with the ability of marking
> some
> versions deprecated. When that CPU model is chosen, get some warning.
> The
> warning message is customized, e.g. telling
).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and
KVM_GET_MSRS system ioctl
x86: defi
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/cpu.c| 7 ++---
target/i386/kvm.c| 72
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 27 ++-
target/i386/cpu.h | 12
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/target/i386
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 172 +-
1 file changed
On Fri, 2018-08-17 at 17:52 +0200, Paolo Bonzini wrote:
> On 10/08/2018 16:06, Robert Hoo wrote:
> > x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only.
>
> This should also grow support for MSR feature words.
>
> My suggestion is that you add another patch after
even more important that you follow the backwards-
> > > compatibility rules and
> > > not rename or delete any previously-mandatory members, since
> > > libvirt CAN'T
> > > introspect if such changes have happened.
> > >
> >
> > [Robert Hoo]
>
On Sun, 2018-09-02 at 19:46 +0800, Robert Hoo wrote:
Ping ... :-)
> KVM side has added the framework (kvm.git:d1d93fa90) to support MSR
> based features.
> Here is the QEMU part, including data structure changes/expanding,
> referring
> functions changes, and the imp
On Thu, 2018-09-20 at 00:07 -0300, Eduardo Habkost wrote:
> Hi,
>
> Thanks for the patch and sorry for taking so long to review it.
Never mind. I understand you're really busy. :-)
>
> On Sun, Sep 02, 2018 at 07:46:06PM +0800, Robert Hoo wrote:
> > Add kvm_get_suppo
On Thu, 2018-09-20 at 00:13 -0300, Eduardo Habkost wrote:
> On Sun, Sep 02, 2018 at 07:46:07PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert Ho
On Thu, 2018-09-20 at 14:22 -0300, Eduardo Habkost wrote:
> On Thu, Sep 20, 2018 at 03:45:42PM +0800, Robert Hoo wrote:
> [...]
> > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > > index a252c26..0160e97 100644
> > > > --- a/target/
On Thu, 2018-09-20 at 14:18 -0300, Eduardo Habkost wrote:
> On Thu, Sep 20, 2018 at 05:55:48PM +0800, Robert Hoo wrote:
> > On Thu, 2018-09-20 at 00:13 -0300, Eduardo Habkost wrote:
> > > On Sun, Sep 02, 2018 at 07:46:07PM +0800, Robert Hoo wrote:
> > > > Note R
.
Robert Hoo (5):
i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs
i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
i386: Add CPUID bit for PCONFIG
i386: Add CPUID bit for WBNOINVD
i386: Add new CPU model Icelake-{Server,Client}
target/i386/cpu.c
://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 4
target/i386/kvm.c | 27 ++-
target/i386/machine.c | 40
3
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1e69e68..3134af4 100644
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Reference:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Reference:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2
ned-off-by: Robert Hoo
---
target/i386/cpu.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 821b7bd..2613e1a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2276,6 +2276,122
On Mon, 2018-06-25 at 13:51 +0200, Paolo Bonzini wrote:
> On 25/06/2018 05:39, Robert Hoo wrote:
> > IA32_PRED_CMD MSR gives software a way to issue commands that affect the
> > state
> > of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
> >
On Mon, 2018-06-25 at 14:06 +0200, Paolo Bonzini wrote:
> On 25/06/2018 05:39, Robert Hoo wrote:
> > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
> > SPEC_CTRL.
> >
> > Signed-off-by: Robert Hoo
> > ---
> > target/i386/cpu.c | 2
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e6c2f8a..953098c 100644
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 4
target/i386/kvm.c | 27 ++-
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/target/i386
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 953098c..c2c3cdb 100644
ned-off-by: Robert Hoo
---
target/i386/cpu.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 92bfbbc..ff3273a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2382,6 +2382,122
.
Changelog:
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert Hoo (5):
i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs
i386: Add CPUID bit and feature words for IA32_ARCH_CAPABIL
On Wed, 2018-06-27 at 14:03 -0300, Eduardo Habkost wrote:
> On Wed, Jun 27, 2018 at 07:27:20PM +0800, Robert Hoo wrote:
> > IA32_PRED_CMD MSR gives software a way to issue commands that affect the
> > state
> > of indirect branch predictors. Enumerated by CPUID.
On Thu, 2018-06-28 at 15:28 -0300, Eduardo Habkost wrote:
> On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote:
> > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
> > SPEC_CTRL.
> >
> > Signed-off-by: Robert Hoo
>
> Based on kern
On Thu, 2018-06-28 at 16:20 +0200, Paolo Bonzini wrote:
> On 28/06/2018 11:25, Robert Hoo wrote:
> >>> +uint64_t pred_cmd;
> >>> +uint64_t arch_capabilities;
> >> What's the purpose of those CPUX86State fields, if the migration
> >> se
On Tue, 2018-07-03 at 11:06 +0200, Paolo Bonzini wrote:
> On 03/07/2018 10:48, Robert Hoo wrote:
> >>
> >> However, I suggest adding it to the FeatureWord enum, since everything
> >> that handles FeatureWord applies to this new kind of MSR as well.
> >>
On Tue, 2018-07-03 at 15:38 +0200, Paolo Bonzini wrote:
> On 03/07/2018 13:07, Robert Hoo wrote:
> >> FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
> >> FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
> >> +FEATURE_WORDS_NUM_CPUID,
>
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f787ef..9407071 100644
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b0b87c3..7f787ef 100644
ake CPU model itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
Signed-off-by: Robert Hoo
---
tar
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
].
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..ae97005 100644
--- a
.
Fix some patch format error and update some trivial patch descrptions.
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert Hoo (5):
i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABIL
On Fri, 2018-08-17 at 00:10 -0300, Eduardo Habkost wrote:
[trim...]
> > +
> > typedef struct FeatureWordInfo {
> > -/* feature flags names are taken from "Intel Processor Identification
> > and
> > +FeatureWordType type;
> > + /* feature flags names are taken from "Intel Processor Ident
On Sat, 2018-08-18 at 11:10 +0800, Robert Hoo wrote:
> On Fri, 2018-08-17 at 00:10 -0300, Eduardo Habkost wrote:
> [trim...]
> > > +
> > > typedef struct FeatureWordInfo {
> > > -/* feature flags names are taken from "Intel Processor
> > > Ide
On Fri, 2018-08-17 at 10:18 -0300, Eduardo Habkost wrote:
> Thanks for the patch, comments below:
>
> On Fri, Aug 10, 2018 at 10:06:28PM +0800, Robert Hoo wrote:
> > Add kvm_get_supported_feature_msrs() to get supported MSR feature index
> > list.
> > Add kvm_arch_get
On Fri, 2018-08-17 at 10:28 -0300, Eduardo Habkost wrote:
> On Fri, Aug 10, 2018 at 10:06:29PM +0800, Robert Hoo wrote:
> > Add an util function feature_word_description(), which help construct the
> > string
> > describing the feature word (bot
On Fri, 2018-08-17 at 17:52 +0200, Paolo Bonzini wrote:
> On 10/08/2018 16:06, Robert Hoo wrote:
> > x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only.
>
> This should also grow support for MSR feature words.
>
> My suggestion is that you add another patch after
On Sat, 2018-08-18 at 12:05 -0300, Eduardo Habkost wrote:
> > > >
> > > > int kvm_has_pit_state2(void)
> > > > {
> > > > @@ -420,6 +421,41 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s,
> > > > uint32_t function,
> > > > return ret;
> > > > }
> > > >
> > > > +uint32_t kvm_arch_
On Thu, 2018-08-23 at 14:11 -0300, Eduardo Habkost wrote:
> On Thu, Aug 23, 2018 at 02:28:28PM +0800, Robert Hoo wrote:
> > On Sat, 2018-08-18 at 12:05 -0300, Eduardo Habkost wrote:
> [...]
> > > We don't want QEMU to refuse to run if the kernel doesn't have
> >
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..ae97005 100644
--- a/target/i386
ake CPU model itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
Signed-off-by: Robert Hoo
---
tar
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 878b1ce..b83d0a9 100644
expression frame work from CPUID features
only to MSR bit included as well.
Fix some patch format error and update some trivial patch descrptions.
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert H
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 3 ++-
target/i386/cpu.h | 1 +
2 files changed, 3 insertions(+), 1 del
On Tue, 2018-07-03 at 08:00 -0300, Eduardo Habkost wrote:
> On Tue, Jul 03, 2018 at 03:35:13PM +0800, Robert Hoo wrote:
> > On Thu, 2018-06-28 at 15:28 -0300, Eduardo Habkost wrote:
> > > On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote:
> > > > Support o
On Fri, 2018-07-13 at 10:11 -0400, konrad.w...@oracle.com wrote:
> (Apologies if this comes out as HTML, using Thunderbird instead of mutt
> here)..
>
> > +uint64_t pred_cmd;
> > +uint64_t arch_capabilities;
>
> Could this be 'arch_cap' ?
>
> >
> > /* End of state preserved by
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 78
2 files changed, 80 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..0cf792f 100644
--- a/include/sysemu/kvm.h
KVM side has added the framework (kvm.git:d1d93fa90) to support MSR based
features.
Here is the QEMU part, including data structure changes/expanding, referring
functions changes, and the implementations on
KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl.
Robert Hoo (3):
x86
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 76 +--
1 file changed, 57 insertions(+), 19 deletions
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 78
2 files changed, 80 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..0cf792f 100644
--- a/include/sysemu/kvm.h
style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
Change other funcitons referring to feature_word_info[]
include/sysemu
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 76 +--
1 file changed, 57 insertions(+), 19 deletions
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 77 +--
1 file changed, 58 insertions(+), 19 deletions
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 79
2 files changed, 81 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..97d8d9d 100644
--- a/include/sysemu/kvm.h
mp;3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
----
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
Change o
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2
On Fri, 2018-08-10 at 10:17 -0500, Eric Blake wrote:
> On 08/10/2018 09:06 AM, Robert Hoo wrote:
>
> In the subject: s/funcitons/functions/
>
> Also, it may be worth using a topic prefix (most of our commit messages
> resemble:
>
> topic: Description of patch
>
wrapper (g_strdup_printf) instead of native
(sprintf).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data struc
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 80
2
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 31 ++-
target/i386/cpu.h | 8
target/i386/kvm.c | 11 +++
3 files changed, 49 insertions(+), 1
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 188 +++---
1 file changed
ible
> impact.
>
> Include a test case that should detect the problem if we introduce
> a similar bug again.
>
> Fixes: c7a88b52f62b ("i386: Add new model of Cascadelake-Server")
> Fixes: 8a11c62da914 ("i386: Add new CPU model Icelake-
> {Server,Clien
Thanks Richard:-)
Sorry for late reply.
On Thu, 2020-02-13 at 10:20 -0800, Richard Henderson wrote:
> On 2/12/20 11:52 PM, Robert Hoo wrote:
> > And initialize buffer_is_zero() with it, when Intel AVX512F is
> > available on host.
> >
> > This function utiliz
And initialize buffer_is_zero() with it, when Intel AVX512F is
available on host.
This function utilizes Intel AVX512 fundamental instructions which
perform over previous AVX2 instructions.
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 56
1. Add avx512_opt option and enable it when host has the ability
2. Implement new buffer_zero_avx512() with AVX512F instructions
Robert Hoo (2):
configure: add configure option avx512f_opt
util: add function buffer_zero_avx512()
configure| 39
-programming-reference.pdf
Signed-off-by: Robert Hoo
---
configure | 39 +++
1 file changed, 39 insertions(+)
diff --git a/configure b/configure
index 115dc38..9bf8de0 100755
--- a/configure
+++ b/configure
@@ -1382,6 +1382,11 @@ for opt do
;;
--enable-avx2
On Thu, 2020-02-13 at 11:30 +0100, Paolo Bonzini wrote:
> On 13/02/20 08:52, Robert Hoo wrote:
> > +
> > +}
> > +#pragma GCC pop_options
> > +#endif
> > +
> > +
> > /* Note that for test_buffer_is_zero_next_accel, the most
> > prefer
PCONFIG is not supposed to be exposed to guest. These 2 patches fix this.
Robert Hoo (2):
i386: remove the new CPUID 'PCONFIG' from Icelake-Server CPU model
Revert "i386: Add CPUID bit for PCONFIG"
target/i386/cpu.c | 5 ++---
target/i386/cpu.h | 1 -
2 files changed
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 677a3bd..b6113d0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2613,8 +2613,7 @@ static X86CPUDefinition builtin_x86_defs
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