On 10/15/21 7:54 AM, Matheus K. Ferst wrote:
While Appendix B does guarantee that "0" is and always will be an invalid
instruction, I
wonder if the test itself would be clearer (i.e. self-documenting the intent)
using
SIGTRAP and "trap".
r~
It would be better, but cpu_loop is currently
On 14/10/2021 20:43, Richard Henderson wrote:
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On 10/14/21 3:32 PM,
On Thu, Oct 14, 2021 at 07:32:31PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> We should use cpu_read_xer/cpu_write_xer to save/restore the complete
> register since some of its bits are in other fields of CPUPPCState. A
> test is added to prevent future regressions.
>
On 10/14/21 3:32 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
We should use cpu_read_xer/cpu_write_xer to save/restore the complete
register since some of its bits are in other fields of CPUPPCState. A
test is added to prevent future regressions.
Fixes: da91a00f191f
From: Matheus Ferst
We should use cpu_read_xer/cpu_write_xer to save/restore the complete
register since some of its bits are in other fields of CPUPPCState. A
test is added to prevent future regressions.
Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")
Signed-off-by:
