Signed-off-by: Lluís Vilanova
---
include/exec/cpu_ldst_template.h | 17 +++
include/exec/cpu_ldst_useronly_template.h | 14
tcg/tcg-op.c | 34 ++---
trace-events | 13 +
Peter Maydell writes:
> On 23 February 2016 at 18:22, Lluís Vilanova wrote:
>> Signed-off-by: Lluís Vilanova
>> +### Guest events, keep at bottom
>> +
>> +# @vaddr: Access' virtual address.
>> +# @size : Access' size (bytes).
>> +# @store: Whether the access is a store.
>> +#
>> +# Start virtua
On 03/17/2016 12:22 PM, Lluís Vilanova wrote:
> M, the endianness seems more of a vCPU property than one of the memory
> access.
On the contrary. Plenty of cpus have endian-swapping load/store insns: x86
(haswell's movbe), powerpc, sparcv9, s390. Maybe others I've forgotten.
r~
Peter Maydell writes:
> On 17 March 2016 at 19:22, Lluís Vilanova wrote:
>> M, the endianness seems more of a vCPU property than one of the memory
>> access. A separate event could be added for that (e.g., at vCPU
>> initalization/hot-plug and whenever it is dynamically changed like in ARM).
On 17 March 2016 at 19:22, Lluís Vilanova wrote:
> M, the endianness seems more of a vCPU property than one of the memory
> access. A separate event could be added for that (e.g., at vCPU
> initalization/hot-plug and whenever it is dynamically changed like in ARM).
We've chosen to implement i
On 18 March 2016 at 18:50, Lluís Vilanova wrote:
> Peter Maydell writes:
>> Trying to trace physaddrs is very tricky -- in the case of
>> a TLB hit there is no guarantee you can still identify the
>> physaddr of what you're accessing (the guest might have
>> changed the page tables and not invalid
On 23 February 2016 at 18:22, Lluís Vilanova wrote:
> Signed-off-by: Lluís Vilanova
> +### Guest events, keep at bottom
> +
> +# @vaddr: Access' virtual address.
> +# @size : Access' size (bytes).
> +# @store: Whether the access is a store.
> +#
> +# Start virtual memory access (before any poten
Peter Maydell writes:
> On 18 March 2016 at 18:50, Lluís Vilanova wrote:
>> Peter Maydell writes:
>>> Trying to trace physaddrs is very tricky -- in the case of
>>> a TLB hit there is no guarantee you can still identify the
>>> physaddr of what you're accessing (the guest might have
>>> changed t
On 20 March 2016 at 18:09, Lluís Vilanova wrote:
> Oh! Yes, I seem to remember that code path now, I checked it a
> really long time ago. I was assuming that whenever this event is
> enabled at compile time, I would have to modify QEMU's TLB to store
> the guest physical address (then used by the
Peter Maydell writes:
> On 20 March 2016 at 18:09, Lluís Vilanova wrote:
>> Oh! Yes, I seem to remember that code path now, I checked it a
>> really long time ago. I was assuming that whenever this event is
>> enabled at compile time, I would have to modify QEMU's TLB to store
>> the guest physic
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