Update image size after addition of new environment handling.
Signed-off-by: Heiko Schocher
---
board/sc3/config.mk |2 +-
include/configs/sc3.h |5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/board/sc3/config.mk b/board/sc3/config.mk
index 1bdf5e4..a46b197 100
I'm working on a project porting the latest version of u-boot to a
dm365evm based board from Appro [1]. The board is a bit different, but
most of the changes are to the /include/configs/.h file. Should
I contribute the code when it's working? How should i proceed? This
board came with a old version
flashes getting larger, users more impatient.
Signed-off-by: Kim Phillips
---
drivers/mtd/cfi_flash.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 3267c5d..38d0ca5 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/driv
continuation of commit 2ecc2262d66a286e3aac79005bcb5f461312dea8
"net ppc: fix ethernet device names with spaces" (currently in
u-boot-net.git) for QE based parts.
Signed-off-by: Kim Phillips
---
doc/README.kmeter1|2 +-
drivers/qe/uec.c |2 +-
drivers/qe/uec_phy.
On Sun, 25 Jul 2010 23:45:02 +0200
Wolfgang Denk wrote:
> Could you please also test the code from the current (rebased) version
> in the "hashtable" branch of the git://git.denx.de/u-boot-testing.git
> repo?
>
> I have adresses the problem of early environment accesses, and at
> least on the bo
On 7/27/10 12:06 AM, Xiangfu Liu wrote:
> what about split this patch to two:
> one is all *.lds files,
> the other one is for the argument,
Sounds good.
> I have one question here. if we decete the board cpu by
> CONFIG_CPU_LITTLE_ENDIAN.
> why we need check the toolchina again.
The answer is d
Hi TC,
I am looking to use the QSPI for MCF5270 and noticed that the cf_spi driver
only stubs this part.
Any chance there are CF_QSPI driver code written somewhere but just not
submitted upstream?
Sorry for overloading the question, any pointers to where I can find it for
uClinux also?
Thanks
Apologies for the oversight, here's the non line-wrapped version.
Fix optimization bug for doubly-indirect block pointers
Doubly-indirect block numbers are compared against the first-level
indirect block when checking for a cached copy. This is causing the
doubly-indirect block to be re-read eac
Fix optimization bug for doubly-indirect block pointers
Doubly-indirect block numbers are compared against the first-level
indirect block when checking for a cached copy. This is causing the
doubly-indirect block to be re-read each time it is accessed.
Repairing this reduces load time for a 70M f
On Sunday, July 25, 2010 16:40:14 Mike Frysinger wrote:
> On Sunday, July 25, 2010 16:06:31 Reinhard Meyer wrote:
> > Mike Frysinger wrote:
> > > On Saturday, July 24, 2010 02:11:16 Reinhard Meyer wrote:
> > >> I would like to generalize that driver and make it also
> > >> CONFIG_NET_MULTI-able.
>
On Jul 14, 2010, at 10:15 AM, Kumar Gala wrote:
> From: york
>
> Enabled SPD
> Enabled DDR2
> Enabled hwconfig
>
> Signed-off-by: York Sun
> ---
> Makefile |1 +
> board/freescale/p2020ds/ddr.c | 56 ++---
> board/freescale/p202
On Jul 14, 2010, at 10:15 AM, Kumar Gala wrote:
> From: york
>
> Changes for P2020DS DDR applies to other 8xxx platform
>
> Signed-off-by: York Sun
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 14 +++---
> arch/powerpc/cpu/mpc8xxx/ddr/options.c |1 +
> 2 files changed, 8 i
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
> From: york
>
> Enabled registered DIMMs using data from SPD. RDIMMs have registers
> which need to be configured before using. The register configuration
> words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
> should read thos
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
> From: york
>
> For 85xx silicon which supports address hashing, it can be activated by
> hwconfig.
>
> Signed-off-by: York Sun
> ---
> arch/powerpc/cpu/mpc85xx/ddr-gen3.c |2 ++
> arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
> From: york
>
> Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
> rank with 512MB each rank.
>
> Also check dimm size and rank size for memory controller interleaving
>
> Signed-off-by: York Sun
> ---
> arch/powerpc/cpu/mpc8xx
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
> From: york
>
> Previous code presumes each DIMM has up to two rank (chip select). Newer
> DDR controller supports up to four chip select on one DIMM.
>
> Signed-off-by: York Sun
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 52
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
> Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with
> hwconfig parameters. The syntax is
>
>setenv hwconfig "fsl_ddr:ctlr_intlv=,bank_intlv="
>
> The mode values for memory controller interleaving are
>cacheline
>p
On Jul 17, 2010, at 10:22 PM, Jerry Van Baren wrote:
> On 07/10/2010 09:25 AM, Kumar Gala wrote:
>> If we are creating reference (handles) to nodes in a device tree we need
>> to first create a new phandle in node and this needs a new phandle
>> value. So we search through the whole dtb to find
On Jul 15, 2010, at 11:52 AM, Kumar Gala wrote:
> The CoreNet style platforms can have a L3 cache that fronts the memory
> controllers. Enable that cache as well as add information into the
> device tree about it.
>
> Signed-off-by: Kumar Gala
> Signed-off-by: Dave Liu
> Signed-off-by: Becky
On Jul 15, 2010, at 12:56 PM, Kumar Gala wrote:
> On the new QorIQ/CoreNet based platforms we need to initialize the
> "portals" as access into the Data Path subystem as well as Logical IO
> Device Numbers (LIODN) that are used for the IOMMU (PAMU).
>
> Signed-off-by: Kumar Gala
> Signed-off-by
On Jul 15, 2010, at 5:15 PM, Kumar Gala wrote:
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/cpu/mpc85xx/cmd_errata.c |4 +++-
> arch/powerpc/cpu/mpc85xx/cpu_init.c |7 +++
> arch/powerpc/cpu/mpc85xx/release.S|6 ++
> arch/powerpc/include/asm/processor.h |1 +
> 4 f
On Jul 15, 2010, at 5:15 PM, Kumar Gala wrote:
> Signed-off-by: Scott Wood
> Signed-off-by: Emil Medve
> Signed-off-by: Ed Swarthout
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/cpu/mpc85xx/cmd_errata.c |4 +
> arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 283 ++
On Jul 15, 2010, at 5:15 PM, Kumar Gala wrote:
> Add support for initializing the SERDES blocks on CoreNet style QoriQ
> devices and the p4080 specific SERDES tables to know which actual
> componetns are enabled.
>
> Additionally, split out the Frame Manger (FMAN) into its specific ethernet
> po
Add support for the P4080DS board, with the following features:
* 36-bit only
* Boots from NOR flash
* FMAN drivers NOT supported
* SPD DDR initialization
Signed-off-by: Ed Swarthout
Signed-off-by: Emil Medve
Signed-off-by: Becky Bruce
Signed-off-by: Ashish Kalra
Signed-off-by: Stuart Yoder
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
> From: york
>
> If 36-bit is enabled, move INIT_RAM_ADDR physical address higher
> to free lowest 4GB address space.
>
> Signed-off-by: York Sun
> ---
> board/freescale/p2020ds/tlb.c |8
> include/configs/P2020DS.h | 11 ++
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
> From: york
>
> If 36-bit physical address is used, move the INIT_RAM_ADDR to higher
> address. This frees the low 4GB address space for better use.
>
> Signed-off-by: York Sun
> ---
> arch/powerpc/cpu/mpc85xx/start.S |7 +++
> 1 files c
On Jul 21, 2010, at 11:31 AM, Peter Tyser wrote:
> Hi Kumar,
> That's great to see official 4080 board support! I had a few comments
> below. I haven't dug into the 4080 much, so take them with a grain of
> salt.
>
>
>
>> +#ifdef CONFIG_PHYS_64BIT
>> +puts("36-bit Addressing\n");
>> +#en
Dear all:
We are Microelectronic Design and Applications (DMA) research group
from University Carlos III of Madrid (Spain). At the moment, we are
developing our own computational hardware platform, based on AMCC
Sequoia board.
In the past, we used U-Boot 1.3.3 with AMCC Sequoia board, and PPC
From: Matthias Fuchs
Update image size after addition of new environment handling.
Signed-off-by: Matthias Fuchs
---
board/esd/canbt/config.mk |8 +---
include/configs/CANBT.h |6 +++---
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/board/esd/canbt/config.mk b/b
From: Matthias Fuchs
Update image size and default environment
after addition of new environment handling.
Signed-off-by: Matthias Fuchs
---
board/esd/pmc440/config.mk |2 +-
include/configs/PMC440.h |8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/board/es
From: Matthias Fuchs
Update image size after addition of new environment handling.
Signed-off-by: Matthias Fuchs
---
board/esd/ar405/config.mk |9 +
include/configs/AR405.h | 10 +-
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/board/esd/ar405/config.m
From: Matthias Fuchs
Fix building various esd boards in u-boot-testing repo's
hastable branch.
Matthias Fuchs (3):
ppc4xx: Fix building of AR405 board
ppc4xx: Fix building of CANBT board
ppc4xx: Fix building of PMC440 board
board/esd/ar405/config.mk |9 +
board/esd/canbt/con
Are you using a serial writer or a JTAG?
DM355 has a second stage bootloader called UBL, have you got that working?
On Mon, Jul 26, 2010 at 11:20 AM, yaojin liu wrote:
> hi:
> i use the GUN tools. flash_utils.tar.gz
> now I can read the flash ID,(K9F1208U0C):ID =
> 0x00EC0x00760x00A50
Hi Shinya
thanks for the links and patch.
comment inline :)
On 07/21/2010 10:08 PM, Shinya Kuribayashi wrote:
> Little endian build is one of the outstanding issues for MIPS ports[1].
>
> There are several technical issues, 1) lack of powerful configration
> infrastructure (it's drastically impro
Hi Wolfgang,
I could think of some situations where the new env command
is helpful. But more during development than for production systems.
Switching between environment profiles would be cool. And a "env default -f"
behavior that keeps MAC addresses and serial# is also on my wishlist.
I did so
On Sunday, July 25, 2010, Reinhard Meyer
wrote:
> Mike Frysinger wrote:
>
> On Sunday, July 25, 2010 20:07:31 Reinhard Meyer wrote:
>
>
> I can rename the current driver to like "enc28j60_lpc2292.c" and make the
> two affected boards use it, so they still compile and work. I can't do
> those board
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hi:
i use the GUN tools. flash_utils.tar.gz
now I can read the flash ID,(K9F1208U0C):ID =
0x00EC0x00760x00A50x00C0
but i cannot write data to page, so i cannot use UBOOT! Therefor i doubt
that uboot also has the same problem?
i have tried several days, but cannot figure it out yet!
On Jul 15, 2010, at 12:05 AM, Kumar Gala wrote:
> Add basic structures for Frame Manager on P4080/P3041/P5020 devices
>
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/include/asm/fsl_fman.h | 212 +
> arch/powerpc/include/asm/immap_85xx.h |1 +
> 2 files c
On Jul 21, 2010, at 12:42 AM, Kumar Gala wrote:
> * Added PCIE4 address, offset, DEVDISR & LAW target ID
> * Added new p4080 DDR registers and defines to immap
> * Add missing corenet platform DEVDISR related defines
> * Updated ccsr_gur to include LIODN registers
> * Add RCWSR defines
> * Added
just use new arm-gcc. >4.x
2010/7/25 Zheng Zhang
> Hi everyone,
> I am porting uboot 1.3.4 to my s3c2440 board, the cross compiler is
> arm-linux-gcc 3.3.2, and met a problem as following:
>
>cd /home/Fedora/Desktop/utu2440/u-boot-1.3.4 && arm-linux-ld
> -Bstatic -T
> /home/Fedora/Deskto
On AT91 the watchdog mode register can only be written once after reset.
If this register is written by u-boot e.g. a Linux driver can't
reconfigure the watchdog later. If the watchdog is left untouched this
is possible. Without touching the mode register the watchdog has a default
setup and u-boot
Dear Alexander Stein,
In message
<1280136874-20303-1-git-send-email-alexander.st...@systec-electronic.com> you
wrote:
> This allows Linux to initialize and use the watchdog with the included
> driver.
Please explain why this is needed. It may be clear to you, but no to
most other readers.
> +-
This allows Linux to initialize and use the watchdog with the included
driver.
Signed-off-by: Alexander Stein
---
Changes in v2:
* Add a new specific option CONFIG_SKIP_WATCHDOG_INIT
* Add some documentation
README |5 +
arch/arm/cpu/arm926ejs/at91/l
Dear Alexander Stein,
please always keep the mailing list on Cc: - thanks.
In message <201007260810.47268.alexander.st...@systec-electronic.com> you wrote:
>
> > I can see the intention, but this should not depend on "val" being
> > defined or not - and it needs explicit documentation (in the RE
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