Hi,
On Monday 16 October 2017 07:50 PM, Felipe Balbi wrote:
>
> Hi,
>
> Faiz Abbas writes:
>> Hi Felipe,
>>
>> On Monday 16 October 2017 07:25 PM, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>> Marek Vasut writes:
On 10/16/2017 07:21 AM, Faiz Abbas wrote:
> A flush of the cache is required b
Hi,
Faiz Abbas writes:
> Hi Felipe,
>
> On Monday 16 October 2017 07:25 PM, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Marek Vasut writes:
>>> On 10/16/2017 07:21 AM, Faiz Abbas wrote:
A flush of the cache is required before any outbound DMA access can
take place. The minimum size that can
Hi Felipe,
On Monday 16 October 2017 07:25 PM, Felipe Balbi wrote:
>
> Hi,
>
> Marek Vasut writes:
>> On 10/16/2017 07:21 AM, Faiz Abbas wrote:
>>> A flush of the cache is required before any outbound DMA access can
>>> take place. The minimum size that can be flushed from the cache is
>>> one
On 10/13/2017 03:08 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Generic firmware loader framework contains some common functionality
> which is reusable by any specific file system firmware loader.
>
> Signed-off-by: Tien Fong Chee
> ---
> common/Makefile | 2 +
> comm
Hi,
Marek Vasut writes:
> On 10/16/2017 07:21 AM, Faiz Abbas wrote:
>> A flush of the cache is required before any outbound DMA access can
>> take place. The minimum size that can be flushed from the cache is
>> one cache line size. Therefore, any buffer allocated for DMA should
>> be in multipl
Ben, All,
On Thu, Oct 12, 2017 at 9:32 PM, Matt Weber
wrote:
> If building in a sandboxed environment where a
> alternate python interpreter is desired. Allow
> configuring of the PYTHON variable to specify
> the interpreter to invoke setup.py.
>
Ignore, I was not against the latest codebase for
Hi Eugeniy,
On Mon, 2017-10-16 at 16:21 +0300, Eugeniy Paltsev wrote:
> The HSDK can manage some pins via CREG registers block.
>
> Signed-off-by: Eugeniy Paltsev
> ---
> Changes v1->v2:
> * Use linux debug function (debug -> pr_debug, errror -> pr_err)
> as uboot "error" was removed.
>
>
The HSDK can manage some pins via CREG registers block.
Signed-off-by: Eugeniy Paltsev
---
Changes v1->v2:
* Use linux debug function (debug -> pr_debug, errror -> pr_err)
as uboot "error" was removed.
MAINTAINERS | 6 +++
drivers/gpio/Kconfig | 7 +++
drive
Please run get_maintainer on this patch. I think you need to include a
few more people.
On 10/13/2017 03:08 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add code necessary into the FPGA driver framework in U-Boot
> so it can be used via the 'fpga' command for programing Arria 1
Hi Eugeniy,
On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> The HSDK can manage some pins via CREG registers block.
>
> Signed-off-by: Eugeniy Paltsev
> ---
> MAINTAINERS | 6 +++
> drivers/gpio/Kconfig | 7 +++
> drivers/gpio/Makefile | 1 +
Log:
"
MMC Device 1 not found
*** Warning - No MMC card found, using default environment
"
Add alias node for usdhc.
Cleaned up board usb code.
Test:
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Mass Storage (480 Mb/s, 500mA)
With CONFIG_CMD_GPIO compilation reports error.
common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory
#include
^
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/gpio.h | 1 +
1 file changed, 1 insertion(+)
create mode 100644 arch/arc/include
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Otavio
> Salvador
> Sent: Monday, October 16, 2017 8:08 PM
> To: Peng Fan
> Cc: Fabio Estevam ; U-Boot Mailing List b...@lists.denx.de>
> Subject: Re: [U-Boot] [PATCH] imx: mx6slevk: fix mmc breakage
On Mon, Oct 16, 2017 at 7:29 AM, Peng Fan wrote:
> Log:
> "
> MMC Device 1 not found
> *** Warning - No MMC card found, using default environment
> "
> Add alias node for usdhc.
> CONFIG_BLK and CONFIG_DM_USB are enabled.
>
> Test:
> => usb tree
> USB device tree:
> 1 Hub (480 Mb/s, 0mA
On 10/16/2017 07:21 AM, Faiz Abbas wrote:
> A flush of the cache is required before any outbound DMA access can
> take place. The minimum size that can be flushed from the cache is
> one cache line size. Therefore, any buffer allocated for DMA should
> be in multiples of cache line size.
>
> Thus,
On 15.10.2017 03:00, Florian Fainelli wrote:
Enable CONFIG_B53_SWITCH, define the CPU/management port number (8) and
enable all 5 ports of the switch to be usable.
Signed-off-by: Florian Fainelli
Reviewed-by: Stefan Roese
Thanks,
Stefan
___
U-Boot
On 15.10.2017 03:00, Florian Fainelli wrote:
Add a b53_reg read/write command which allows inspecting the switch
registers. Because the Broadcom BCM53xx registers have different sizes,
we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain
expected results.
Signed-off-by: Florian Fa
On 15.10.2017 03:00, Florian Fainelli wrote:
Make sure that we pad small packets to a minimum length of 60 bytes
(without FCS). This is necessary to interface with Ethernet switches
that will reject RUNT frames unless padded correctly.
Signed-off-by: Florian Fainelli
Reviewed-by: Stefan Roese
On 15.10.2017 03:00, Florian Fainelli wrote:
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar
to the Marvell MV88E617x. This takes care of configuring the minimum
amount out of the switch hardware such that each user visible port
(configurable) and the CPU port can forward p
Log:
"
MMC Device 1 not found
*** Warning - No MMC card found, using default environment
"
Add alias node for usdhc.
CONFIG_BLK and CONFIG_DM_USB are enabled.
Test:
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Mass Storage (480 Mb/
On Fri, Oct 13, 2017 at 02:29:20PM -0700, Benjamin Young wrote:
> Encountered an issue where fastboot can't write to NAND on a CHIP_pro,
> the symbol was neither present in the board's config header, nor the
> Kconfig, this patch puts it in the Kconfig and defaults on when
> SUNXI_NAND is selected.
As per data sheet, S25FS512S support uniform sector option
or erase size of 256 kbytes and Page Programming buffer of
256 or 512 Bytes. So, flag SECT_4K has no significance for
this flash.
Signed-off-by: Suresh Gupta
Signed-off-by: Rajat Srivastava
---
drivers/mtd/spi/spi_flash_ids.c | 2 +-
1
The S25FS-S family physical sectors may be configured as a hybrid
combination of eight 4-kB parameter sectors at the top or bottom
of the address space with all but one of the remaining sectors
being uniform size.
The default status of the flash is the hybrid architecture.
The parameter sectors and
The S25FS-S family physical sectors may be configured as a hybrid
combination of eight 4-kB parameter sectors at the top or bottom
of the address space with all but one of the remaining sectors
being uniform size. The default status of the flash is the hybrid
architecture.
Since the parameter sect
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