On 3/2/19 4:47 AM, Dinh Nguyen wrote:
> Read the cache properties of the L2 cache controller from the device
> tree and configure it.
>
> Signed-off-by: Dinh Nguyen
I really hoped there would be a small fix for the latency configuration
I can apply for the current release.
Regarding the PL310 D
Read the cache properties of the L2 cache controller from the device
tree and configure it.
Signed-off-by: Dinh Nguyen
---
arch/arm/include/asm/pl310.h | 4
arch/arm/mach-socfpga/misc.c | 45 +---
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git
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