On Tue, Apr 24, 2012 at 7:53 PM, Thierry Reding
thierry.red...@avionic-design.de wrote:
Some hardware requires the data buffers to be cacheline-aligned to make
sure DMA operations can be properly executed.
This patch uses the ALLOC_CACHE_ALIGN_BUFFER macro to allocate buffers
with proper
* Simon Glass wrote:
On Tue, Apr 24, 2012 at 7:53 PM, Thierry Reding
thierry.red...@avionic-design.de wrote:
Some hardware requires the data buffers to be cacheline-aligned to make
sure DMA operations can be properly executed.
This patch uses the ALLOC_CACHE_ALIGN_BUFFER macro to
Some hardware requires the data buffers to be cacheline-aligned to make
sure DMA operations can be properly executed.
This patch uses the ALLOC_CACHE_ALIGN_BUFFER macro to allocate buffers
with proper alignment. The same was already done for EFI partitions in
commit f75dd58 part_efi: dcache:
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