From: Hou Zhiqiang
The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.
Signed-off-by: Hou Zhiqiang
---
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
On Tue, Oct 30, 2018 at 10:21 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The LS2080A has 8GB region for each PCIe controller, while the
> other platforms have 32GB.
>
> Signed-off-by: Hou Zhiqiang
> ---
> arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 7 +++
> 1 file changed, 7 inserti
> Kushwaha ; Mingkai Hu
> ; M.h. Lian
> Subject: Re: [U-Boot] [PATCH 1/8] armv8: fsl-layerscpae: correct the PCIe
> controllers' region size
>
> On Tue, Oct 30, 2018 at 10:21 PM Z.q. Hou wrote:
> >
> > From: Hou Zhiqiang
> >
> > The LS2080A has 8GB
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