On 11/29/2017 10:48 AM, York Sun wrote:
> On 11/08/2017 10:45 PM, Xiaowei Bao wrote:
>>
>> Hi York,
>>
>> For the general pcie devices, it will not bring delay, because the RC access
>> these
>> devices can get the link up state correctly, usually, if the slot have the
>> device,
>> return the
On 11/08/2017 10:45 PM, Xiaowei Bao wrote:
>
> Hi York,
>
> For the general pcie devices, it will not bring delay, because the RC access
> these
> devices can get the link up state correctly, usually, if the slot have the
> device,
> return the L0 state, if the slot have not device, return
elesis.co.nz; u-boot@lists.denx.de; Z.q. Hou
> <zhiqiang@nxp.com>; hamish.mar...@alliedtelesis.co.nz; M.h. Lian
> <minghuan.l...@nxp.com>
> Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state
> judgement more specific
>
> On 11/08/2017 01:30 PM, Jo
ngkai...@nxp.com>;
>>> tony.obr...@alliedtelesis.co.nz; u-boot@lists.denx.de; Z.q. Hou
>>> <zhiqiang@nxp.com>; York Sun <york@nxp.com>; Xiaowei Bao
>>> <xiaowei....@nxp.com>; hamish.mar...@alliedtelesis.co.nz; M.h. Lian
>>> <mi
enx.de; Z.q. Hou
> > <zhiqiang@nxp.com>; York Sun <york@nxp.com>; Xiaowei Bao
> > <xiaowei@nxp.com>; hamish.mar...@alliedtelesis.co.nz; M.h. Lian
> > <minghuan.l...@nxp.com>
> > Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link sta
-boot@lists.denx.de; Z.q. Hou
> <zhiqiang@nxp.com>; York Sun <york@nxp.com>; Xiaowei Bao
> <xiaowei@nxp.com>; hamish.mar...@alliedtelesis.co.nz; M.h. Lian
> <minghuan.l...@nxp.com>
> Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state
ork@nxp.com>; Xiaowei Bao
<xiaowei@nxp.com>; hamish.mar...@alliedtelesis.co.nz; M.h. Lian
<minghuan.l...@nxp.com>
Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement
more specific
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
> CA
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
> CAUTION: This email originated from outside of the organization. Do not click
> links or open attachments unless you recognize the sender and know the
> content is safe.
>
>
> For some special reset times for longer pcie devices, the pcie
For some special reset times for longer pcie devices, the pcie device
may on polling compliance state, the RC considers the pcie device is
link up, but the pcie device is not link up, only the L0 state is link
up state.
Signed-off-by: Bao Xiaowei
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