Hi Marek, Lukasz,
On 31.07.23 10:06, Lukasz Majewski wrote:
On Sat, 29 Jul 2023 15:30:10 +0200
Marek Vasut wrote:
The MXS starts with CPSR V bit set, which makes the CPU jump to high
vectors in case of an exception. Those high vectors are located at
0x, which is where the BootROM
On Sat, 29 Jul 2023 15:30:10 +0200
Marek Vasut wrote:
> The MXS starts with CPSR V bit set, which makes the CPU jump to high
> vectors in case of an exception. Those high vectors are located at
> 0x, which is where the BootROM exception table is located as
> well. U-Boot should handle
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