This chip is compatible with other RTL8168 chips and can be found on the
NVIDIA Cardhu and Beaver boards.
Signed-off-by: Thierry Reding
---
drivers/net/rtl8169.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index c217e6f..c87ea74 100644
--- a
This chip is compatible with the existing driver, except that it uses
BAR2 instead of BAR1 for the I/O memory region. Using this patch I can
use the PCIe ethernet interface on the CompuLab Trimslice to boot from
the network.
Signed-off-by: Thierry Reding
---
drivers/net/rtl8169.c | 18
I no longer work for Avionic Design and don't have access to hardware,
so I'll pass on maintainership to Alban.
Acked-by: Alban Bedel
Signed-off-by: Thierry Reding
---
Hi Tom,
I assume this is something you'd want to take through the Tegra tree?
Thierry
boards.cfg | 6 +++---
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.
Signed-off-by: Thierry Reding
---
Changes in v2:
- new patch
arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c
From: Jimmy Zhang
The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.
Signed-off-by: Jimmy Zhang
Reviewed-by: Tom Warren
Signed-off-by: Thierry Reding
---
Changes in v2:
- clean up
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.
Signed-off-by: Thierry Reding
---
Changes in v3:
- don't leak PLLX_BASE bits into PLLX_MISC
Changes in v2:
- new patch
arch/arm/cpu/arm720t/tegra-common/cpu.c | 6 +-
1 file changed, 5 insertions(
On Mon, Sep 30, 2013 at 02:25:57PM -0700, Tom Warren wrote:
> Thierry,
>
> > -Original Message-
> > From: Thierry Reding [mailto:thierry.red...@gmail.com]
> > Sent: Monday, September 23, 2013 1:08 PM
> > To: Tom Warren
> > Cc: u-boot@lists.denx.de
>
From: Jimmy Zhang
The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.
Signed-off-by: Jimmy Zhang
Reviewed-by: Tom Warren
Signed-off-by: Thierry Reding
---
Changes in v3:
- none
On Tue, Oct 08, 2013 at 12:42:51AM +0200, Tom Warren wrote:
> No real HW change on T124 for 90% of the toys, so just include
> a common T1x4 header file (based on T114 headers), and if a new
> register/bit is needed, add it at the end. Some headers (clk_rst,
> clock-tables, pinmux, etc.) had too ma
On Tue, Oct 08, 2013 at 12:42:52AM +0200, Tom Warren wrote:
> Minor changes to support T124 chip and sku IDs.
SKU is an abbreviation, therefore should be uppercase.
Thierry
---
This email message is for the sole use
On Tue, Oct 08, 2013 at 12:42:53AM +0200, Tom Warren wrote:
> This provides SPL support for T124 boards - AVP
> early init, plus CPU (A15) init/jump to main U-Boot.
>
> Change-Id: I721f83f1d5fa549e0698e0cc76ab3e5ea11ba895
> Signed-off-by: Tom Warren
> ---
> arch/arm/cpu/arm720t/tegra-common/cpu.
On Thu, Oct 17, 2013 at 11:29:06AM +0200, Alban Bedel wrote:
> On Mon, 23 Sep 2013 17:23:12 -0700
> Tom Warren wrote:
>
> > It's fine as-is for now. Send a V2 with any changes Stephen, et al requested
> > (if any), and I'll get it into tegra-next when I return from vacation
> > next Monday (assum
On Thu, Oct 17, 2013 at 08:59:22AM -0600, Stephen Warren wrote:
> On 10/17/2013 04:50 AM, Thierry Reding wrote:
> > On Thu, Oct 17, 2013 at 11:29:06AM +0200, Alban Bedel wrote:
> >> On Mon, 23 Sep 2013 17:23:12 -0700 Tom Warren
> >> wrote:
> >>
> >>
| 3 ++
> arch/arm/cpu/tegra-common/vpr.c | 35 +++
> arch/arm/include/asm/arch-tegra/ap.h| 9 ++
> arch/arm/include/asm/arch-tegra124/mc.h | 49
> +
> 5 files changed, 97 insertions(+)
> create mode 100644
t; > ourselves. Any pointer in the right directions would be greatly
> > appreciated.
>
> I don't believe anyone is actively working on this at present. It would
> be great to have this support in place.
>
> If you want to take a crack at it yourself, I suggest the foll
From: Thierry Reding
Disabling the data cache is no longer required to boot Dalmore, so
enable it. This results in notably better performance when loading
and booting the Linux kernel.
Signed-off-by: Thierry Reding
---
include/configs/dalmore.h | 3 ---
1 file changed, 3 deletions(-)
diff
From: Thierry Reding
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-o
On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote:
> On 07/18/2013 01:13 PM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
> > isn't true for Tegra114, however, w
* Wolfgang Denk wrote:
> Dear p.asawathepme...@gmail.com,
>
> please keep the mailing list on Cc:
>
> And please do not top post / full quote.
>
>
> In message
> <1583190526-1317236653-cardhu_decombobulator_blackberry.rim.net-1201398-@b16.c9.bise6.blackberry>
> you wrote:
> >
> > I'm using ub
gt; cc: Stefan Roese
> cc: Tom Rini
> cc: Wolfgang Denk
> cc: Thierry Reding
> cc: Tom Warren
> cc: Stephen Warren
> cc: Stefano Babic
> ---
> include/configs/lwmon5.h |1 -
> include/configs/mcx.h|1 -
> include/configs/omap3_b
ed is Seaboard, which runs at a 1366x768
resolution. As it happens this is the maximum resolution supported and
also the default that is used to initialize the framebuffer before the
configuration from DT is available.
Signed-off-by: Thierry Reding
---
drivers/video/tegra.c | 4 ++--
1 file chang
The Medcom-Wide has a 15" LCD panel with a resolution of 1366x768
pixels. Add a corresponding panel description to the device tree and
enable LCD support in the configuration.
Signed-off-by: Thierry Reding
---
board/avionic-design/dts/tegra20-medcom-wide.dts
The TEC ships with a 7" LCD panel that provides a resolution of 800x480
pixels. Add a corresponding panel description to the device tree and
enable LCD support in the configuration.
Signed-off-by: Thierry Reding
---
board/avionic-design/dts/tegra20-tec.dts
On Fri, Aug 14, 2015 at 04:10:32PM +0800, Bin Meng wrote:
> Hi,
>
> On Sun, Aug 9, 2015 at 11:08 PM, Simon Glass wrote:
> > Hi Stephen,
> >
> > On 6 August 2015 at 13:03, Stephen Warren wrote:
> >> On 08/05/2015 05:45 PM, Simon Glass wrote:
> >>>
> >>> Hi Stephen,
> >>>
> >>> On 5 August 2015 at
On Fri, Aug 14, 2015 at 04:44:28PM +0800, Bin Meng wrote:
> Hi Thierry,
>
> On Fri, Aug 14, 2015 at 4:32 PM, Thierry Reding wrote:
> > On Fri, Aug 14, 2015 at 04:10:32PM +0800, Bin Meng wrote:
> >> Hi,
> >>
> >> On Sun, Aug 9, 2015 at 11:08
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> Signed-off-by: Stephen Warren
> ---
> v2: Use named constants for PMIC I2C and register addresses.
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/tegra210-p2371-.dt
On Wed, Aug 19, 2015 at 11:41:09AM -0600, Stephen Warren wrote:
> On 08/19/2015 07:56 AM, Thierry Reding wrote:
> >On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
> >>From: Stephen Warren
> >>
> >>Signed-off-by: Stephen Warren
> >>---
From: Thierry Reding
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding
---
arch/arm/cpu/armv8/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu
From: Thierry Reding
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the
From: Thierry Reding
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and
From: Thierry Reding
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and
From: Thierry Reding
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and
From: Thierry Reding
While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be
From: Thierry Reding
GCC 5.1 starts warning for comparisons such as !a > 0, assuming that the
negation was meant to apply to the whole expression rather than just the
left operand.
Indeed the comparison in the FIT loadable code is confusingly written,
though it does end up doing the right th
From: Thierry Reding
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud
Cc: Marc Zyngier
Signed-off-by: Thierry Reding
---
arch/arm/include/asm/armv8/mmu.h | 4 ++--
1 file changed, 2
From: Thierry Reding
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier
Suggested-by: Mark Rutland
Cc: Albert Aribaud
Cc: Mark Rutland
Cc: Marc
From: Thierry Reding
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud
Cc: Marc Zyngier
Signed-off-by: Thierry Reding
---
arch/arm/cpu/armv8/cache_v8.c
On Thu, Aug 20, 2015 at 11:46:41PM +, Marcel Ziswiler wrote:
> On 20 Aug 2015 22:09, Stephen Warren wrote:
>
> > Hopefully the process was to copy the Linux Tegra30 DT verbatim?
>
> No, the T20 one is far from verbatim neither. So I just did the
> adjustments analogous by comparing the T20 a
On Fri, Aug 21, 2015 at 06:37:37PM -0600, Simon Glass wrote:
[...]
> I have serious doubts about the wisdom of requiring a contributor to
> completely re-architect the existing display system in U-Boot. It's a
> big job. Perhaps we can settle for following along the same lines and
> not making thin
On Mon, Aug 24, 2015 at 10:58:48AM -0600, Simon Glass wrote:
> +Nikita
>
> Hi Thierry,
>
> On 24 August 2015 at 04:12, Thierry Reding wrote:
> > On Fri, Aug 21, 2015 at 06:37:37PM -0600, Simon Glass wrote:
> > [...]
> >> I have serious doubts about the
On Tue, Aug 25, 2015 at 10:03:13AM -0600, Simon Glass wrote:
> On 25 August 2015 at 05:02, Thierry Reding wrote:
> > On Mon, Aug 24, 2015 at 10:58:48AM -0600, Simon Glass wrote:
> >> On 24 August 2015 at 04:12, Thierry Reding wrote:
[...]
> >> > SOR is an even
On Mon, Aug 24, 2015 at 10:03:35PM +, Marcel Ziswiler wrote:
> On 21 Aug 2015 11:29, Thierry Reding wrote:
> > Perhaps a good idea would be to simply copy what we have in the kernel
> > and see where (if at all) U-Boot breaks down and fix it to work properly
> > with &q
On Fri, Oct 23, 2015 at 11:30:04AM -0600, Stephen Warren wrote:
> On 10/23/2015 09:47 AM, Simon Glass wrote:
> >Hi Stephen,
> >
> >On 21 October 2015 at 14:16, Stephen Warren wrote:
> >>On 10/17/2015 11:49 AM, Simon Glass wrote:
> >>>
> >>>This is not supported with driver model, so print a messag
On Wed, Oct 28, 2015 at 11:59:04AM -0600, Stephen Warren wrote:
> On 10/18/2015 10:57 PM, Alexandre Courbot wrote:
> >T210's GPU secure firmware loading requires a write-protected region
> >to be set up.
> >
> >This patch reserves the upper 256KB of RAM as the WPR region and locks
> >it so the kern
On Mon, Nov 09, 2015 at 08:19:48AM -0700, Stephen Warren wrote:
> On 11/09/2015 07:36 AM, Thierry Reding wrote:
> >On Wed, Oct 28, 2015 at 11:59:04AM -0600, Stephen Warren wrote:
> >>On 10/18/2015 10:57 PM, Alexandre Courbot wrote:
> >>>T210's GPU secure firmware
On Mon, Jul 20, 2015 at 01:41:00PM +0200, Mirza Krak wrote:
> From: Mirza Krak
>
> Add the device tree node for the SPI controllers found on Tegra20 SOCs.
>
> Signed-off-by: Mirza Krak
>
> ---
> arch/arm/dts/tegra20.dtsi | 44
> 1 file changed, 44
On Wed, Jul 22, 2015 at 04:56:10PM -0600, Stephen Warren wrote:
> From: Thierry Reding
>
> Some SoCs come with a custom timer interface, so allow them to use that
> instead.
>
> swarren notes: I did consider reworking this patch so the Makefile only
> compiles g
From: Thierry Reding
ARMv8 requires an architected timer to be present, so it can be used
instead of the Tegra US timer. This allows for better code reuse.
Signed-off-by: Thierry Reding
---
include/configs/tegra-common.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs
From: Thierry Reding
A subsequent patch will enable the use of the architected timer on
ARMv8. Doing so implies that udelay() will be backed by this timer
implementation, and hence the architected timer must be ready when
udelay() is first called. The first time udelay() is used is while
On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote:
> On 07/24/2015 04:01 PM, Tom Warren wrote:
> >Based on Venice2, incorporates Stephen Warren's
> >latest P2571 pinmux table.
> >
> >With Thierry Reding's 64-bit build fixes, this
> >will build and and boot in 64-bit on my P2571
> >(whe
On Wed, Jul 29, 2015 at 10:09:57AM -0600, Stephen Warren wrote:
> On 07/29/2015 05:07 AM, Thierry Reding wrote:
> >On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote:
> >>On 07/24/2015 04:01 PM, Tom Warren wrote:
> >>>Based on Venice2, incorporates Step
On Wed, Jul 29, 2015 at 01:47:58PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> Additionally, ARM64 devices typically run a secure monitor in EL3 and
> U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
> code and data. These carve-outs are located at the top of 32
On Thu, Jul 30, 2015 at 12:13:06PM -0600, Stephen Warren wrote:
> On 07/29/2015 05:02 PM, Simon Glass wrote:
> >Hi Stephen,
> >
> >On 29 July 2015 at 13:48, Stephen Warren wrote:
> >>
> >
> >Commit message?
>
> I guess I can add one, but there really much useful additional information I
> can giv
On Sun, Aug 02, 2015 at 03:27:53PM -0600, Simon Glass wrote:
> Hi,
>
> On 27 July 2015 at 11:13, Simon Glass wrote:
> > Hi,
> >
> > On 23 July 2015 at 10:51, Stephen Warren wrote:
> >> From: Thierry Reding
> >>
> >> Signed-off-by: Thierry R
On Sun, Aug 02, 2015 at 06:13:50PM -0600, Simon Glass wrote:
> This reverts commit 5b34436035fc862b5e8d0d2c3eab74ba36f1a7f4.
>
> This function has a few problems. It calls fdt_parent_offset() which as
> mentioned in code review is very slow.
>
> https://patchwork.ozlabs.org/patch/499482/
> https:
On Tue, Aug 04, 2015 at 09:23:27AM -0600, Stephen Warren wrote:
> On 08/04/2015 08:26 AM, Thierry Reding wrote:
> ... [ discussion of new fdtdec_get_addr_size() implementation]
> >So what this does is really fix parsing of address and size cells in the
> >general case, though i
From: Thierry Reding
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 St
From: Thierry Reding
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 St
On Wed, Sep 09, 2015 at 08:37:34PM -0700, Stephen Warren wrote:
> On 09/08/2015 02:38 AM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Enabling a PLL while IDDQ is high. The Linux kernel checks for this
>
> Is there some word missing in/at-the-end-of that f
On Tue, Sep 08, 2015 at 03:58:38PM +, Tom Warren wrote:
> Thierry,
>
> > -Original Message-
> > From: Thierry Reding [mailto:thierry.red...@gmail.com]
> > Sent: Tuesday, September 08, 2015 2:38 AM
> > To: Tom Warren
> > Cc: Nicolas Chauvet; u-boot@l
er sent it out because I never managed to get
PCIe to work. Anyway:
Reviewed-by: Thierry Reding
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On Mon, Oct 05, 2015 at 04:59:17PM -0600, Stephen Warren wrote:
[...]
> It'd be nice if "git format-patch -C" recognized this as a copy, since
> that's why I created a separate patch, but it doesn't seem to:-(
Have you tried tuning the behaviour by passing the similarity index to
-C? I've had some
On Tue, Jul 14, 2015 at 01:48:45PM -0600, Simon Glass wrote:
> +Scott, Masahiro
>
> Hi Thierry,
>
> On 25 March 2015 at 17:23, Simon Glass wrote:
> > Hi Thierry,
> >
> > On 8 September 2014 at 09:02, Simon Glass wrote:
> >> Applied to u-boot-fdt/next, thanks!
> >
> > Did you submit these patche
On Wed, Jul 15, 2015 at 01:35:26PM +0200, Albert ARIBAUD wrote:
> Hello Thierry,
>
> On Wed, 15 Jul 2015 13:17:18 +0200, Thierry Reding
> wrote:
> > On Tue, Jul 14, 2015 at 01:48:45PM -0600, Simon Glass wrote:
> > > +Scott, Masahiro
> > >
> > > Hi Th
On Tue, Feb 24, 2015 at 08:23:55AM +0100, Jan Kiszka wrote:
> On 2015-02-20 10:36, Jan Kiszka wrote:
> > On 2015-02-19 10:14, Thierry Reding wrote:
> >> On Wed, Feb 18, 2015 at 09:34:53AM -0700, Stephen Warren wrote:
> >>> On 02/17/2015 11:13 PM, Jan Kiszka wro
On Wed, Feb 18, 2015 at 09:14:03AM +0100, Jan Kiszka wrote:
[...]
> +ENTRY(psci_cpu_off)
> + bl psci_cpu_off_common
> +
> + mrc p15, 0, r1, c0, c0, 5 @ MPIDR
> + and r1, r1, #7 @ number of CPUs in cluster
> +
> + get_csr_reg r1, r2, r3
> +
> +
On Wed, Feb 18, 2015 at 09:14:03AM +0100, Jan Kiszka wrote:
[...]
> diff --git a/arch/arm/cpu/armv7/tegra124/ap.c
> b/arch/arm/cpu/armv7/tegra124/ap.c
[...]
> +void ap_pm_init(void)
> +{
> + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
> + struct pmc_ctlr *pmc = (struct pm
On Wed, Mar 11, 2015 at 11:12:25AM -0400, Tom Rini wrote:
> * PGP Signed by an unknown key
>
> On Mon, Mar 09, 2015 at 08:00:18AM +0100, Jan Kiszka wrote:
>
> > In this case the secure code lives in RAM, and hence the memory node in
> > the device tree needs to be adjusted. This avoids that the O
+
> arch/arm/mach-tegra/tegra124/ap.c | 55 +
> board/nvidia/common/board.c | 4 +
> include/configs/jetson-tk1.h| 5 ++
> 20 files changed, 428 insertions(+), 98 deletions(-)
> create mo
On Thu, Mar 19, 2015 at 07:43:35AM -0600, Simon Glass wrote:
> Hi Hanna,
>
> On 18 March 2015 at 11:17, Hanna Hawa wrote:
> > Hi Simon,
> >
> >
> >
> > My name is Hanna, I’m working in Software team in Marvell with Yehuda.
> >
> >
> >
> > I’m trying to run U-Boot with FDT in 64Bit.
> >
> > I’ve i
From: Thierry Reding
This is mostly useful for debugging the early boot process. Often boards
can provide some low-level code that outputs a character on some debug
port prior to passing the early setup code. Allow boards to implement an
early_putc() function that will be used to redirect printf
From: Thierry Reding
Use the physical address of the debug serial port from the configuration
to provide an early_putc() implementation that can be used with the new
early console support.
Cc: Tom Warren
Signed-off-by: Thierry Reding
---
board/nvidia/common/board.c | 22
From: Thierry Reding
Fix an pointer to integer cast size mismatch warning by casting to
unsigned long instead of unsigned int and fix up the corresponding
printf format string to use %lx instead of %x.
Also remove a pointless cast producing a size mismatch warning.
Cc: Simon Glass
Cc: Tom
From: Thierry Reding
This fixes some build errors and warnings caused by inline assembly and
pointer to integer cast size mismatches. The inline assembly build error
in config_cache() is easy to fix because the code isn't meaningful on 64
bit ARM. For the assembly-level rese
From: Thierry Reding
Explicitly cast the result of a pointer arithmetic to unsigned int so
that it matches the corresponding printf format string. While at it, use
%p to print a buffer address rather than %x and an explicit cast (which
causes a warning in this case because it's cast to uns
From: Thierry Reding
Fix a couple of pointer to integer size mismatch warnings by casting
pointers to unsigned long rather than unsigned int.
Cc: Pantelis Antoniou
Cc: Tom Warren
Signed-off-by: Thierry Reding
---
drivers/mmc/tegra_mmc.c | 6 +++---
1 file changed, 3 insertions(+), 3
From: Thierry Reding
Turn ioaddr into an unsigned long rather than a sized 32-bit variable.
While at it, fix a couple of pointer to integer cast size mismatch
warnings by casting through unsigned long going from pointers to
integers and vice versa.
Cc: Joe Hershberger
Signed-off-by: Thierry
From: Thierry Reding
Fix a couple of pointer to integer size mismatch warnings by casting
pointers to unsigned long rather than unsigned int.
Cc: Heiko Schocher
Signed-off-by: Thierry Reding
---
drivers/i2c/tegra_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
From: Thierry Reding
Fix a type mismatch in a printf format string.
Cc: Marek Vasut
Signed-off-by: Thierry Reding
---
drivers/usb/eth/asix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 11811094ede8..1cd179baaea7
From: Thierry Reding
Use the %pa specifier to print physical addresses rather than %x. The
latter causes build warnings on 64-bit.
Cc: Tom Warren
Cc: Tom Rini
Signed-off-by: Thierry Reding
---
drivers/pci/pci_tegra.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
From: Thierry Reding
Cast pointers to unsigned long instead of a sized 32-bit type to avoid
pointer to integer cast size mismatch warnings.
Cc: Tom Warren
Cc: Marek Vasut
Signed-off-by: Thierry Reding
---
drivers/usb/host/ehci-tegra.c | 8
1 file changed, 4 insertions(+), 4
From: Thierry Reding
Fix a printf format mismatch warning seen on 64-bit builds.
Cc: Łukasz Majewski
Cc: Marek Vasut
Signed-off-by: Thierry Reding
---
drivers/usb/gadget/f_mass_storage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/f_mass_storage.c
From: Thierry Reding
Fix a slew of pointer to integer cast size mismatch warnings caused by
this driver explicitly casting pointers to 32-bit integers. While it is
true that the hardware can only deal with 32-bit addresses, truncating
using a cast isn't the right solution because the po
From: Thierry Reding
Use the %lx printf specifier to print unsigned long variables to avoid a
build warning on 64-bit.
Cc: Simon Glass
Signed-off-by: Thierry Reding
---
lib/fdtdec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index
From: Thierry Reding
Fix a slew of pointer to integer cast size mismatch warnings caused by
this driver explicitly casting pointers to 32-bit integers. While it is
true that the hardware can only deal with 32-bit addresses, truncating
using a cast isn't the right solution because the po
From: Thierry Reding
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
While at it, fix the values for the shareability attribute field to
match the documentation.
Cc: Albert Aribaud
Cc: Marc Zyngier
From: Thierry Reding
While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.
Fix this by making the
From: Thierry Reding
Implement early malloc() support in a similar way as on 32-bit ARM. This
is required for 64-bit Tegra SoCs that initialize from the device tree
just like the earlier 32-bit SoCs.
Cc: Albert Aribaud
Cc: Marc Zyngier
Signed-off-by: Thierry Reding
---
arch/arm/include/asm
From: Thierry Reding
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud
Cc: Marc Zyngier
Signed-off-by: Thierry Reding
---
arch/arm/cpu/armv8/cache_v8.c
From: Thierry Reding
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier
Suggested-by: Mark Rutland
Cc: Albert Aribaud
Cc: Mark Rutland
Cc: Marc
From: Thierry Reding
Some SoCs come with a custom timer interface, so allow them to use that
instead.
Cc: Albert Aribaud
Cc: Marc Zyngier
Signed-off-by: Thierry Reding
---
arch/arm/cpu/armv8/generic_timer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv8
From: Thierry Reding
Drivers that need to parse addresses from the device tree will want to
reuse this function rather than duplicating it.
Cc: Simon Glass
Signed-off-by: Thierry Reding
---
include/fdtdec.h | 8
lib/fdtdec.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion
From: Thierry Reding
The fdtdec_get_pci_addr() implementation uses fdt_addr_to_cpu() to read
cells from an FDT blob. That is wrong because cells are always 32 bits
wide, irrespective of the architecture's address bus width, which does
not apply to fdt_addr_t.
Besides reading the wrong re
From: Thierry Reding
The current implementation of fdtdec_get_addr_size() assumes that the
sizes of fdt_addr_t and fdt_size_t match the number of cells specified
by the #address-cells and #size-cells properties. However, there is no
reason why that needs to be the case, so the function
From: Thierry Reding
The source command uses an unsigned long to iterate over the 32-bit
lengths array contained in the legacy image format. On architectures
where unsigned long is 64-bit this fails to find the correct entry
point of a script.
Cc: Tom Rini
Signed-off-by: Thierry Reding
From: Thierry Reding
The bootz command doesn't work with Linux kernel images on 64-bit ARM.
The replacement command with the same interface and functionality is
booti.
Cc: Dennis Gilmore
Cc: Tom Rini
Signed-off-by: Thierry Reding
---
include/config_distro_defaults.h | 4
1 file ch
From: Thierry Reding
Reuse the 32-bit ARM client architecture and identify ARMv8 specifically
by setting the BOOTP VCI string.
Cc: Dennis Gilmore
Cc: Tom Rini
Signed-off-by: Thierry Reding
---
include/config_distro_defaults.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
From: Thierry Reding
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.
Cc: Tom Warren
Signed-off-by: Thierry Reding
---
include/configs/tegra-common.h | 4
1
From: Thierry Reding
Move various selects from the TEGRA symbol to the symbols for 32-bit
Tegra boards. This is necessary because these settings do not extend
to U-Boot for 64-bit Tegra SoCs. Also tie the private libgcc build
to SPL, it isn't needed on 64-bit Tegra.
Cc: Tom Warren
Signe
From: Thierry Reding
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.
Cc: Tom Warren
Signed-off-by: Thierry Reding
---
arch/arm/mach-tegra/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
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