Looks like there is suffecient buffering on usrp for timed transmit with a
slim (1 gig) interface.
Not so for rx though...
On Dec 8, 2017 1:05 PM, "John Malsbury"
wrote:
> I have an urgent need to do a quick finite burst/acquisition app with an
> X310.
I have an urgent need to do a quick finite burst/acquisition app with an
X310. Basically, I'd like to perform a timed transmission of 2e6 complex
samples to the radio, and do an aligned acquisition of 2e6 samples from the
receiver at exactly the same sample clock cycle. I need to do this from a
Note that the CBX lower frequency "limit" is around 1.2GHz
while the UBX is quite happy tuning down to 10MHz.
There are many powerful ambient signal sources between
10MHz and 1.2GHz. I suspect you are seeing those.
Nonlinearity being what it is, I have seen AM broadcast signals
appear in the
Well, per usual, I believe I've figured this out with some more digging...
1. If I run a python program that includes my OOT module, the blocks are
registered correctly with the block_ctrl_base_factory, and the
initialization call to ettus.device3 will correctly correlate my FPGA CE
with the OOT
Hi Kyle,
Thank you for the good information. We will be increasing the timeout in
the next release of UHD, so the issues should be resolved soon.
Regards,
Michael
On Wed, Nov 15, 2017 at 9:19 AM, Guilbert, Kyle J via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Greetings,
>
> I am
On 12/08/2017 09:18 AM, Mark Koenig via USRP-users wrote:
I am mainly looking at frequencies above 2 GHz, would adjusting the
dB_clock_rate be something that may help with the noise floor and help
my SNR? For reasons beyond my control, I am currently using UHD rev
003.009.007. I hope this
Hi All,
I'm having trouble getting an OOT RFNoC block controller to register
correctly with the rfnoc block factory. The goal here is to create a block
controller class that attaches to the FPGA CE.
I've traced this operation down to the block_ctrl_base_factory.cpp, which
exposes the
I am mainly looking at frequencies above 2 GHz, would adjusting the
dB_clock_rate be something that may help with the noise floor and help my SNR?
For reasons beyond my control, I am currently using UHD rev 003.009.007. I
hope this not an issue.
Thank you
Mark
From: Mark Koenig
P.S. Obviously i have compiled 2 instances of the block into the FPGA
image, maybe i need to add some unique identification at this point?
On 8 December 2017 at 12:42, Mark Luscombe wrote:
> Hi,
>
> I've found that if i add a second instance of the same RFNoC block to a
>
Hi,
I've found that if i add a second instance of the same RFNoC block to a GRC
signal flow it fails to compile, complaining that there are duplicate
connections to the first instance of the RFNoC block. This happens with
either my own RFNoC blocks or Ettus RFNoC blocks. Am i missing something as
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