[PATCH v1] driver: spi: add bcm iproc qspi support.
From: Rayagonda Kokatanur IPROC qspi driver supports both BSPI and MSPI modes. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Bharat Gooty --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/iproc_qspi.c | 736 +++ drivers/spi/iproc_qspi.h | 18 + 4 files changed, 761 insertions(+) create mode 100644 drivers/spi/iproc_qspi.c create mode 100644 drivers/spi/iproc_qspi.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e12699bec7..3253d6badf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -178,6 +178,12 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config IPROC_QSPI + bool "QSPI driver for BCM iProc QSPI Controller" + help + This selects the BCM iProc QSPI controller. + This driver support spi flash single, quad and memory reads. + config KIRKWOOD_SPI bool "Marvell Kirkwood SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d2f24bccef..8697631870 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o obj-$(CONFIG_ICH_SPI) += ich.o +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c new file mode 100644 index 00..89c6a56858 --- /dev/null +++ b/drivers/spi/iproc_qspi.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020-2021 Broadcom + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "iproc_qspi.h" + +/* 175MHz */ +#define QSPI_AXI_CLK 17500 +#define QSPI_DEF_SCK_FREQ 5000 +#define QSPI_WAIT_TIMEOUT_MS 200U +#define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3)) + +/* Chip attributes */ +#define SPBR_MIN 8U +#define SPBR_MAX 255U +#define NUM_CDRAM 16U + +#define CDRAM_PCS0 2 +#define CDRAM_CONT BIT(7) +#define CDRAM_BITS_EN BIT(6) +#define CDRAM_QUAD_MODEBIT(8) +#define CDRAM_RBIT_INPUT BIT(10) +#define MSPI_SPE BIT(6) +#define MSPI_CONT_AFTER_CMDBIT(7) + +/* Register fields */ +#define MSPI_SPCR0_MSB_BITS_8 0x0020 +#define BSPI_RAF_CONTROL_START_MASK0x0001 +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x0001 +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK0x0002 +#define BSPI_BITS_PER_PHASE_ADDR_MARK 0x0001 +#define BSPI_BITS_PER_CYCLE_DATA_SHIFT 0 +#define BSPI_BITS_PER_CYCLE_ADDR_SHIFT 16 +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT3 +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT1 +#define BSPI_STRAP_OVERRIDE_SHIFT 0 + +/* MSPI registers */ +#define MSPI_SPCR0_LSB_REG 0x000 +#define MSPI_SPCR0_MSB_REG 0x004 +#define MSPI_SPCR1_LSB_REG 0x008 +#define MSPI_SPCR1_MSB_REG 0x00c +#define MSPI_NEWQP_REG 0x010 +#define MSPI_ENDQP_REG 0x014 +#define MSPI_SPCR2_REG 0x018 +#define MSPI_STATUS_REG0x020 +#define MSPI_CPTQP_REG 0x024 +#define MSPI_TXRAM_REG 0x040 +#define MSPI_RXRAM_REG 0x0c0 +#define MSPI_CDRAM_REG 0x140 +#define MSPI_WRITE_LOCK_REG0x180 +#define MSPI_DISABLE_FLUSH_GEN_REG 0x184 + +/* BSPI registers */ +#define BSPI_REVISION_ID_REG 0x000 +#define BSPI_SCRATCH_REG 0x004 +#define BSPI_MAST_N_BOOT_CTRL_REG 0x008 +#define BSPI_BUSY_STATUS_REG 0x00c +#define BSPI_INTR_STATUS_REG 0x010 +#define BSPI_B0_STATUS_REG 0x014 +#define BSPI_B0_CTRL_REG 0x018 +#define BSPI_B1_STATUS_REG 0x01c +#define BSPI_B1_CTRL_REG 0x020 +#define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024 +#define BSPI_FLEX_MODE_ENABLE_REG 0x028 +#define BSPI_BITS_PER_CYCLE_REG0x02C +#define BSPI_BITS_PER_PHASE_REG0x030 +#define BSPI_CMD_AND_MODE_BYTE_REG 0x034 +#define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038 +#define BSPI_XOR_VALUE_REG 0x03C +#define
[PATCH v1 2/2] pinctrl: single: Add request() api
From: Bharat Gooty
Add pinctrl_ops->request api to configure pctrl
pad register in gpio mode.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Bharat Gooty
---
drivers/pinctrl/pinctrl-single.c | 34
1 file changed, 34 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 0f96cd5870..8fc07e3498 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -250,6 +250,39 @@ static int single_get_pin_muxing(struct udevice *dev,
unsigned int pin,
return 0;
}
+static int single_request(struct udevice *dev, int pin, int flags)
+{
+ struct single_priv *priv = dev_get_priv(dev);
+ struct single_pdata *pdata = dev_get_plat(dev);
+ struct single_gpiofunc_range *frange = NULL;
+ struct list_head *pos, *tmp;
+ phys_addr_t reg;
+ int mux_bytes = 0;
+ u32 data;
+
+ /* If function mask is null, needn't enable it. */
+ if (!pdata->mask)
+ return -ENOTSUPP;
+
+ list_for_each_safe(pos, tmp, >gpiofuncs) {
+ frange = list_entry(pos, struct single_gpiofunc_range, node);
+ if ((pin >= frange->offset + frange->npins) ||
+ pin < frange->offset)
+ continue;
+
+ mux_bytes = pdata->width / BITS_PER_BYTE;
+ reg = pdata->base + pin * mux_bytes;
+
+ data = single_read(dev, reg);
+ data &= ~pdata->mask;
+ data |= frange->gpiofunc;
+ single_write(dev, data, reg);
+ break;
+ }
+
+ return 0;
+}
+
static struct single_func *single_allocate_function(struct udevice *dev,
unsigned int group_pins)
{
@@ -587,6 +620,7 @@ const struct pinctrl_ops single_pinctrl_ops = {
.get_pin_name = single_get_pin_name,
.set_state = single_set_state,
.get_pin_muxing = single_get_pin_muxing,
+ .request = single_request,
};
static const struct udevice_id single_pinctrl_match[] = {
--
2.17.1
--
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with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
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destroy any printed copy of it.
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v1 1/2] pinctrl: single: Parse gpio details from dt
From: Bharat Gooty
Parse different gpio properties from dt as part of probe
function. This detail is required to enable pinctrl pad
later when gpio lines are requested.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Bharat Gooty
---
drivers/pinctrl/pinctrl-single.c | 52
1 file changed, 52 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index cf9ad3670f..0f96cd5870 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -44,11 +45,27 @@ struct single_func {
unsigned int *pins;
};
+/**
+ * struct single_gpiofunc_range - pin ranges with same mux value of gpio fun
+ * @offset: offset base of pins
+ * @npins: number pins with the same mux value of gpio function
+ * @gpiofunc: mux value of gpio function
+ * @node: list node
+ */
+struct single_gpiofunc_range {
+ u32 offset;
+ u32 npins;
+ u32 gpiofunc;
+ struct list_head node;
+};
+
/**
* struct single_priv - private data
* @bits_per_pin: number of bits per pin
* @npins: number of selectable pins
* @pin_name: temporary buffer to store the pin name
+ * @functions: list pin functions
+ * @gpiofuncs: list gpio functions
*/
struct single_priv {
#if (IS_ENABLED(CONFIG_SANDBOX))
@@ -58,6 +75,7 @@ struct single_priv {
unsigned int npins;
char pin_name[PINNAME_SIZE];
struct list_head functions;
+ struct list_head gpiofuncs;
};
/**
@@ -454,6 +472,36 @@ static int single_get_pins_count(struct udevice *dev)
return priv->npins;
}
+static int single_add_gpio_func(struct udevice *dev)
+{
+ struct single_priv *priv = dev_get_priv(dev);
+ const char *propname = "pinctrl-single,gpio-range";
+ const char *cellname = "#pinctrl-single,gpio-range-cells";
+ struct single_gpiofunc_range *range;
+ struct ofnode_phandle_args gpiospec;
+ int ret, i;
+
+ for (i = 0; ; i++) {
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), propname,
+cellname, 0, i, );
+ /* Do not treat it as error. Only treat it as end condition. */
+ if (ret) {
+ ret = 0;
+ break;
+ }
+ range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
+ if (!range) {
+ ret = -ENOMEM;
+ break;
+ }
+ range->offset = gpiospec.args[0];
+ range->npins = gpiospec.args[1];
+ range->gpiofunc = gpiospec.args[2];
+ list_add_tail(>node, >gpiofuncs);
+ }
+ return ret;
+}
+
static int single_probe(struct udevice *dev)
{
struct single_pdata *pdata = dev_get_plat(dev);
@@ -461,6 +509,7 @@ static int single_probe(struct udevice *dev)
u32 size;
INIT_LIST_HEAD(>functions);
+ INIT_LIST_HEAD(>gpiofuncs);
size = pdata->offset + pdata->width / BITS_PER_BYTE;
#if (CONFIG_IS_ENABLED(SANDBOX))
@@ -483,6 +532,9 @@ static int single_probe(struct udevice *dev)
priv->npins *= (pdata->width / priv->bits_per_pin);
}
+ if (single_add_gpio_func(dev))
+ dev_dbg(dev, "gpio functions are not added\n");
+
dev_dbg(dev, "%d pins\n", priv->npins);
return 0;
}
--
2.17.1
--
This electronic communication and the information and any files transmitted
with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
laws, or otherwise restricted from disclosure to anyone else. If you are
not the intended recipient or the person responsible for delivering the
e-mail to the intended recipient, you are hereby notified that any use,
copying, distributing, dissemination, forwarding, printing, or copying of
this e-mail is strictly prohibited. If you received this e-mail in error,
please return the e-mail to the sender, delete it from your computer, and
destroy any printed copy of it.
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v1 0/2] pinctrl single: GPIO support
From: Bharat Gooty pinctrl-single:- Add support to parse "pinctrl-single,gpio-range" and "#pinctrl-single,gpio-range-cells" DT properties Add pinctrl_ops request() Bharat Gooty (2): pinctrl: single: Parse gpio details from dt pinctrl: single: Add request() api drivers/pinctrl/pinctrl-single.c | 86 1 file changed, 86 insertions(+) -- 2.17.1 -- This electronic communication and the information and any files transmitted with it, or attached to it, are confidential and are intended solely for the use of the individual or entity to whom it is addressed and may contain information that is confidential, legally privileged, protected by privacy laws, or otherwise restricted from disclosure to anyone else. If you are not the intended recipient or the person responsible for delivering the e-mail to the intended recipient, you are hereby notified that any use, copying, distributing, dissemination, forwarding, printing, or copying of this e-mail is strictly prohibited. If you received this e-mail in error, please return the e-mail to the sender, delete it from your computer, and destroy any printed copy of it. smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v1 1/2] net: brcm: netXtreme driver
From: Bharat Gooty
Broadcom bnxt L2 driver support. Used by the Broadcom
iproc platforms.
Signed-off-by: Bharat Gooty
---
drivers/net/Kconfig |1 +
drivers/net/Makefile|1 +
drivers/net/bnxt/Kconfig|7 +
drivers/net/bnxt/Makefile |5 +
drivers/net/bnxt/bnxt.c | 2025 +++
drivers/net/bnxt/bnxt_dbg.h | 538 ++
drivers/net/bnxt/pci_ids.h | 17 +
include/broadcom/bnxt.h | 419
include/broadcom/bnxt_hsi.h | 889 +++
include/broadcom/bnxt_ver.h | 22 +
10 files changed, 3924 insertions(+)
create mode 100644 drivers/net/bnxt/Kconfig
create mode 100644 drivers/net/bnxt/Makefile
create mode 100644 drivers/net/bnxt/bnxt.c
create mode 100644 drivers/net/bnxt/bnxt_dbg.h
create mode 100644 drivers/net/bnxt/pci_ids.h
create mode 100644 include/broadcom/bnxt.h
create mode 100644 include/broadcom/bnxt_hsi.h
create mode 100644 include/broadcom/bnxt_ver.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 382639044b..ff2c1797b1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,6 +1,7 @@
source "drivers/net/phy/Kconfig"
source "drivers/net/pfe_eth/Kconfig"
source "drivers/net/fsl-mc/Kconfig"
+source "drivers/net/bnxt/Kconfig"
config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a44a7d3f56..f739f1e157 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -96,3 +96,4 @@ obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
+obj-$(CONFIG_BNXT_ETH) += bnxt/
diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig
new file mode 100644
index 00..c263616612
--- /dev/null
+++ b/drivers/net/bnxt/Kconfig
@@ -0,0 +1,7 @@
+config BNXT_ETH
+ bool "BNXT PCI support"
+ depends on DM_ETH && DM_PCI
+ help
+ This driver implements support for bnxt pci controller
+ driver of ethernet class.
+
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
new file mode 100644
index 00..a9d6ce00d5
--- /dev/null
+++ b/drivers/net/bnxt/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019-2021 Broadcom.
+
+# Broadcom nxe Ethernet driver
+obj-y += bnxt.o
diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c
new file mode 100644
index 00..144df587f7
--- /dev/null
+++ b/drivers/net/bnxt/bnxt.c
@@ -0,0 +1,2025 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 Broadcom.
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "bnxt_dbg.h"
+#include "pci_ids.h"
+
+#define bnxt_down_chip(bp) bnxt_hwrm_run(down_chip, bp, 0)
+#define bnxt_bring_chip(bp)bnxt_hwrm_run(bring_chip, bp, 1)
+
+static const char banner[] = DRV_MODULE_DESC " v" UBOOT_MODULE_VER ",";
+static const char fw_ver[] = " FW v";
+
+static int num_cards; /* Number of bnxt devices seen so far */
+
+static void display_banner(struct bnxt *bp)
+{
+ int i;
+
+ printf(banner);
+ printf(fw_ver);
+ printf("%d.%d.", bp->fw_maj, bp->fw_min);
+ printf("%d.%d\n", bp->fw_bld, bp->fw_rsvd);
+ printf("ETH MAC: ");
+ for (i = 0; i < ETH_ALEN; i++) {
+ printf("%02x", bp->mac_set[i]);
+ if (i != (ETH_ALEN - 1))
+ printf(":");
+ }
+
+ printf(", Port(%d), PF(%d)\n", bp->port_idx, bp->ordinal_value);
+}
+
+/* Broadcom ethernet driver PCI APIs. */
+static void bnxt_bring_pci(struct bnxt *bp)
+{
+ u16 cmd_reg = 0;
+
+ pci_read_word16(bp->pdev, PCI_VENDOR_ID, >vendor_id);
+ pci_read_word16(bp->pdev, PCI_DEVICE_ID, >device_id);
+ pci_read_word16(bp->pdev,
+ PCI_SUBSYSTEM_VENDOR_ID,
+ >subsystem_vendor);
+ pci_read_word16(bp->pdev, PCI_SUBSYSTEM_ID, >subsystem_device);
+ pci_read_word16(bp->pdev, PCI_COMMAND, >cmd_reg);
+ pci_read_byte(bp->pdev, PCICFG_ME_REGISTER, >pf_num);
+ pci_read_byte(bp->pdev, PCI_INTERRUPT_LINE, >irq);
+ bp->bar0 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ bp->bar1 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
+ bp->bar2 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
+ cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ cmd_reg |= PCI_COMMAND_INTX_DISABLE; /* disable intr */
+ pci_write_word(bp->pdev, PCI_COMMAND, cmd_reg);
+ pci_read_word16(bp->pdev, PCI_COMMAND, _reg);
+ dbg_pci(bp, __func__, cmd_reg);
+}
+
+int bnxt_free_rx_iob(struct bnxt *bp)
+{
+ unsigned int i;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_RX_IOB)))
+ return
[PATCH v1 2/2] cmd: brcm: netXtreme commands
From: Bharat Gooty
Following netXtreme commands are supported:-
Device probe, remove, supported speeds, get/set speeds and
get/set MAC address.
Signed-off-by: Bharat Gooty
---
cmd/Kconfig | 2 +
cmd/broadcom/Kconfig | 10 ++
cmd/broadcom/Makefile | 3 +-
cmd/broadcom/bnxt.c | 237 ++
4 files changed, 251 insertions(+), 1 deletion(-)
create mode 100644 cmd/broadcom/Kconfig
create mode 100644 cmd/broadcom/bnxt.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index a9fb4eead2..ef53e42f72 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1920,6 +1920,8 @@ endmenu
source "cmd/ti/Kconfig"
+source "cmd/broadcom/Kconfig"
+
config CMD_BOOTSTAGE
bool "Enable the 'bootstage' command"
depends on BOOTSTAGE
diff --git a/cmd/broadcom/Kconfig b/cmd/broadcom/Kconfig
new file mode 100644
index 00..6f16b09d14
--- /dev/null
+++ b/cmd/broadcom/Kconfig
@@ -0,0 +1,10 @@
+menu "Broadcom specific command line interface"
+
+config BNXT_ETH_CMD
+ bool "BNXT commands"
+ depends on BNXT_ETH
+ help
+ Broadcom NXS ethernet controller commands. Commands supported are:-
+ Driver probe, Driver remove, Supported speeds, get/set MAC address
and get/set Link speeds.
+
+endmenu
diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile
index 62268d98d0..0027c1c15e 100644
--- a/cmd/broadcom/Makefile
+++ b/cmd/broadcom/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
-# Copyright 2020 Broadcom
+# Copyright 2020-2021 Broadcom
obj-y += chimp_boot.o
obj-y += nitro_image_load.o
obj-y += chimp_handshake.o
+obj-$(CONFIG_BNXT_ETH_CMD) += bnxt.o
diff --git a/cmd/broadcom/bnxt.c b/cmd/broadcom/bnxt.c
new file mode 100644
index 00..b9d1e59a74
--- /dev/null
+++ b/cmd/broadcom/bnxt.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Broadcom
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int do_bnxt_set_link(struct bnxt *bp, char *link_str)
+{
+ bp->link_set = simple_strtoul(link_str, NULL, 16);
+
+ switch (bp->link_set) {
+ case LINK_SPEED_DRV_AUTONEG:
+ printf("- AutoNeg Not Supported\n");
+ return 0;
+ case LINK_SPEED_DRV_1G:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_1GB)) {
+ printf("- 1 GBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ case LINK_SPEED_DRV_10G:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_10GB)) {
+ printf("- 10 GBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ case LINK_SPEED_DRV_25G:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_25GB)) {
+ printf("- 25 GBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ case LINK_SPEED_DRV_40G:
+ printf("- 40 GBPS Not Supported\n");
+ return 0;
+ case LINK_SPEED_DRV_50G:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_50GB)) {
+ printf("- 50 GBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ case LINK_SPEED_DRV_100G:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100GB)) {
+ printf("- 100 GBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ case LINK_SPEED_DRV_200G:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_200GB)) {
+ printf("- 200 GBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ case LINK_SPEED_DRV_2_5G:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_2_5GB)) {
+ printf("- 2.5 GBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ case LINK_SPEED_DRV_100M:
+ if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100MB)) {
+ printf("- 100 MBPS: Link Speed is not supported\n");
+ return 0;
+ }
+
+ break;
+ default:
+ printf("- Invalid Link Speed specified\n");
+ return CMD_RET_USAGE;
+ }
+
+ prn_link_speed(bp->link_set, 1);
+
+ return bnxt_set_link_speed(bp);
+}
+
+static int do_bnxt_set_mac(struct bnxt *bp, char *mac_str)
+{
+ struct eth_pdata *plat = dev_get_plat(bp->pdev);
+ u8 addr[ETH_ALEN];
+ int ret = CMD_RET_USAGE;
+
+
[PATCH v1 0/2] Broadcom netXtreme driver and commands
From: Bharat Gooty Broadcom netXtreme controller supports multiple ports and multiple link speeds like 10/25/50/100G 1. Added driver support for netXtreme controller 2. Added commands to know the port used, supported speeds, configure link speeds and MAC address. Bharat Gooty (2): net: brcm: netXtreme driver cmd: brcm: netXtreme commands cmd/Kconfig |2 + cmd/broadcom/Kconfig| 10 + cmd/broadcom/Makefile |3 +- cmd/broadcom/bnxt.c | 237 drivers/net/Kconfig |1 + drivers/net/Makefile|1 + drivers/net/bnxt/Kconfig|7 + drivers/net/bnxt/Makefile |5 + drivers/net/bnxt/bnxt.c | 2025 +++ drivers/net/bnxt/bnxt_dbg.h | 538 ++ drivers/net/bnxt/pci_ids.h | 17 + include/broadcom/bnxt.h | 419 include/broadcom/bnxt_hsi.h | 889 +++ include/broadcom/bnxt_ver.h | 22 + 14 files changed, 4175 insertions(+), 1 deletion(-) create mode 100644 cmd/broadcom/Kconfig create mode 100644 cmd/broadcom/bnxt.c create mode 100644 drivers/net/bnxt/Kconfig create mode 100644 drivers/net/bnxt/Makefile create mode 100644 drivers/net/bnxt/bnxt.c create mode 100644 drivers/net/bnxt/bnxt_dbg.h create mode 100644 drivers/net/bnxt/pci_ids.h create mode 100644 include/broadcom/bnxt.h create mode 100644 include/broadcom/bnxt_hsi.h create mode 100644 include/broadcom/bnxt_ver.h -- 2.17.1 -- This electronic communication and the information and any files transmitted with it, or attached to it, are confidential and are intended solely for the use of the individual or entity to whom it is addressed and may contain information that is confidential, legally privileged, protected by privacy laws, or otherwise restricted from disclosure to anyone else. If you are not the intended recipient or the person responsible for delivering the e-mail to the intended recipient, you are hereby notified that any use, copying, distributing, dissemination, forwarding, printing, or copying of this e-mail is strictly prohibited. If you received this e-mail in error, please return the e-mail to the sender, delete it from your computer, and destroy any printed copy of it. smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v1] pci: iproc: fix compilation errors and warnings
From: Bharat Gooty
Signed-off-by: Bharat Gooty
---
drivers/pci/pcie_iproc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c
index 12ce9d525c..be03dcbd97 100644
--- a/drivers/pci/pcie_iproc.c
+++ b/drivers/pci/pcie_iproc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Broadcom
+ * Copyright (C) 2020-2021 Broadcom
*
*/
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#define EP_PERST_SOURCE_SELECT_SHIFT 2
@@ -884,7 +885,7 @@ static int iproc_pcie_map_ranges(struct udevice *dev)
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == PCI_REGION_MEM ||
hose->regions[i].flags == PCI_REGION_PREFETCH) {
- debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n",
+ debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n",
i, >regions[i].bus_start,
>regions[i].phys_start,
hose->regions[i].size);
@@ -1049,7 +1050,7 @@ static int iproc_pcie_map_dma_ranges(struct iproc_pcie
*pcie)
while (!pci_get_dma_regions(pcie->dev, , i)) {
dev_dbg(pcie->dev,
- "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n",
+ "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n",
i, regions.bus_start, regions.phys_start, regions.size);
/* Each range entry corresponds to an inbound mapping region */
--
2.17.1
--
This electronic communication and the information and any files transmitted
with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
laws, or otherwise restricted from disclosure to anyone else. If you are
not the intended recipient or the person responsible for delivering the
e-mail to the intended recipient, you are hereby notified that any use,
copying, distributing, dissemination, forwarding, printing, or copying of
this e-mail is strictly prohibited. If you received this e-mail in error,
please return the e-mail to the sender, delete it from your computer, and
destroy any printed copy of it.
smime.p7s
Description: S/MIME Cryptographic Signature
