[clang] 801ab71 - [ARM][AArch64] SLSHardening: make non-comdat thunks possible
Author: Daniel Kiss
Date: 2021-05-20T17:07:05+02:00
New Revision: 801ab71032e157eb7bcd38efeb6486742a7c53bb
URL:
https://github.com/llvm/llvm-project/commit/801ab71032e157eb7bcd38efeb6486742a7c53bb
DIFF:
https://github.com/llvm/llvm-project/commit/801ab71032e157eb7bcd38efeb6486742a7c53bb.diff
LOG: [ARM][AArch64] SLSHardening: make non-comdat thunks possible
Linker scripts might not handle COMDAT sections. SLSHardeing adds
new section for each __llvm_slsblr_thunk_xN. This new option allows
the generation of the thunks into the normal text section to handle these
exceptional cases.
,comdat or ,noncomdat can be added to harden-sls to control the codegen.
-mharden-sls=[all|retbr|blr],nocomdat.
Reviewed By: kristof.beyls
Differential Revision: https://reviews.llvm.org/D100546
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
clang/lib/Driver/ToolChains/Arch/ARM.cpp
clang/test/Driver/sls-hardening-options.c
llvm/include/llvm/CodeGen/IndirectThunks.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSLSHardening.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 4ce797f9bc73..503685ab533a 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -235,11 +235,17 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
StringRef Scope = A->getValue();
bool EnableRetBr = false;
bool EnableBlr = false;
-if (Scope != "none" && Scope != "all") {
+bool DisableComdat = false;
+if (Scope != "none") {
SmallVector Opts;
Scope.split(Opts, ",");
for (auto Opt : Opts) {
Opt = Opt.trim();
+if (Opt == "all") {
+ EnableBlr = true;
+ EnableRetBr = true;
+ continue;
+}
if (Opt == "retbr") {
EnableRetBr = true;
continue;
@@ -248,19 +254,27 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
EnableBlr = true;
continue;
}
+if (Opt == "comdat") {
+ DisableComdat = false;
+ continue;
+}
+if (Opt == "nocomdat") {
+ DisableComdat = true;
+ continue;
+}
D.Diag(diag::err_invalid_sls_hardening)
<< Scope << A->getAsString(Args);
break;
}
-} else if (Scope == "all") {
- EnableRetBr = true;
- EnableBlr = true;
}
if (EnableRetBr)
Features.push_back("+harden-sls-retbr");
if (EnableBlr)
Features.push_back("+harden-sls-blr");
+if (DisableComdat) {
+ Features.push_back("+harden-sls-nocomdat");
+}
}
// En/disable crc
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 16d72e5367f5..4ab547fabe43 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -796,11 +796,17 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
StringRef Scope = A->getValue();
bool EnableRetBr = false;
bool EnableBlr = false;
-if (Scope != "none" && Scope != "all") {
+bool DisableComdat = false;
+if (Scope != "none") {
SmallVector Opts;
Scope.split(Opts, ",");
for (auto Opt : Opts) {
Opt = Opt.trim();
+if (Opt == "all") {
+ EnableBlr = true;
+ EnableRetBr = true;
+ continue;
+}
if (Opt == "retbr") {
EnableRetBr = true;
continue;
@@ -809,13 +815,18 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
EnableBlr = true;
continue;
}
+if (Opt == "comdat") {
+ DisableComdat = false;
+ continue;
+}
+if (Opt == "nocomdat") {
+ DisableComdat = true;
+ continue;
+}
D.Diag(diag::err_invalid_sls_hardening)
<< Scope << A->getAsString(Args);
break;
}
-} else if (Scope == "all") {
- EnableRetBr = true;
- EnableBlr = true;
}
if (EnableRetBr || EnableBlr)
@@ -827,6 +838,9 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+harden-sls-retbr");
if (EnableBlr)
Features.push_back("+harden-sls-blr");
+if (DisableComdat) {
+ Features.push_back("+harden-sls-nocomdat");
+}
}
}
diff --git a/clang/test/Driver/sls-hardening-options.c
b/clang/test/Driver/sls-hardening-options.c
index c48b6
[libunwind] 9c3f6fb - [libunwind] Make the test depend on the libunwind explicitly.
Author: Daniel Kiss
Date: 2020-08-03T09:46:23+02:00
New Revision: 9c3f6fb68807c8100797b001c0621ae0c9a6d1fc
URL:
https://github.com/llvm/llvm-project/commit/9c3f6fb68807c8100797b001c0621ae0c9a6d1fc
DIFF:
https://github.com/llvm/llvm-project/commit/9c3f6fb68807c8100797b001c0621ae0c9a6d1fc.diff
LOG: [libunwind] Make the test depend on the libunwind explicitly.
Before this patch the `ninja check-unwind` won't rebuild the unwind library.
Reviewed By: jroelofs
Differential Revision: https://reviews.llvm.org/D85004
Added:
Modified:
libunwind/test/CMakeLists.txt
Removed:
diff --git a/libunwind/test/CMakeLists.txt b/libunwind/test/CMakeLists.txt
index 794a59f58f84a..2b945e6eff762 100644
--- a/libunwind/test/CMakeLists.txt
+++ b/libunwind/test/CMakeLists.txt
@@ -32,4 +32,4 @@ configure_lit_site_cfg(
add_lit_testsuite(check-unwind "Running libunwind tests"
${CMAKE_CURRENT_BINARY_DIR}
- DEPENDS ${LIBUNWIND_TEST_DEPS})
+ DEPENDS unwind ${LIBUNWIND_TEST_DEPS})
___
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[clang] 070acb1 - [Driver][ARM] parse version of arm/thumb architecture correctly
Author: Daniel Kiss
Date: 2020-07-01T12:13:52+02:00
New Revision: 070acb1d1e51ffd289a46b8f93e993635d0053b7
URL:
https://github.com/llvm/llvm-project/commit/070acb1d1e51ffd289a46b8f93e993635d0053b7
DIFF:
https://github.com/llvm/llvm-project/commit/070acb1d1e51ffd289a46b8f93e993635d0053b7.diff
LOG: [Driver][ARM] parse version of arm/thumb architecture correctly
Summary:
If you execute the following commandline multiple times, the behavior was not
always the same:
clang++ --target=thumbv7em-none-windows-eabi-coff -march=armv7-m
-mcpu=cortex-m7 -o temp.obj -c -x c++ empty.cpp
Most of the time the compilation succeeded, but sometimes clang reported this
error:
clang++: error: the target architecture 'thumbv7em' is not supported by the
target 'thumbv7em-none-windows-eabi'
The cause of the inconsistent behavior was the uninitialized variable Version.
With these commandline arguments, the variable Version was not set by
getAsInteger(),
because it cannot parse a number from the substring "7em" (of "thumbv7em").
To get a consistent behaviour, it's enough to initialize the variable Version
to zero.
Zero is smaller than 7, so the comparison will be true.
Then the command always fails with the error message seen above.
By using consumeInteger() instead of getAsInteger() we get 7 from the substring
"7em"
and the command does not fail.
Reviewers: compnerd, danielkiss
Reviewed By: danielkiss
Subscribers: danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D75453
Added:
clang/test/Driver/windows-thumbv7em.cpp
Modified:
clang/lib/Driver/ToolChains/Clang.cpp
Removed:
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 9db6bbadf566..a2cc84805c9c 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -4041,9 +4041,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
if (Triple.isOSWindows() && (Triple.getArch() == llvm::Triple::arm ||
Triple.getArch() == llvm::Triple::thumb)) {
unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
-unsigned Version;
-Triple.getArchName().substr(Offset).getAsInteger(10, Version);
-if (Version < 7)
+unsigned Version = 0;
+bool Failure =
+Triple.getArchName().substr(Offset).consumeInteger(10, Version);
+if (Failure || Version < 7)
D.Diag(diag::err_target_unsupported_arch) << Triple.getArchName()
<< TripleStr;
}
diff --git a/clang/test/Driver/windows-thumbv7em.cpp
b/clang/test/Driver/windows-thumbv7em.cpp
new file mode 100644
index ..5d7c00b31fd1
--- /dev/null
+++ b/clang/test/Driver/windows-thumbv7em.cpp
@@ -0,0 +1,8 @@
+// RUN: %clang -target thumb-none-windows-eabi-coff -mcpu=cortex-m7 -### -c %s
2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-V7
+// CHECK-V7-NOT: error: the target architecture 'thumbv7em' is not supported
by the target 'thumbv7em-none-windows-eabi'
+
+// RUN: %clang -target thumb-none-windows-eabi-coff -mcpu=cortex-m1 -### -c %s
2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-V6
+// CHECK-V6: error: the target architecture 'thumbv6m' is not supported by the
target 'thumbv6m-none-windows-eabi'
+
___
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[libunwind] 23bef7e - [libunwind] Support for leaf function unwinding.
Author: Daniel Kiss
Date: 2020-09-16T23:53:36+02:00
New Revision: 23bef7ee9923b1262326981960397e8cd95d6923
URL:
https://github.com/llvm/llvm-project/commit/23bef7ee9923b1262326981960397e8cd95d6923
DIFF:
https://github.com/llvm/llvm-project/commit/23bef7ee9923b1262326981960397e8cd95d6923.diff
LOG: [libunwind] Support for leaf function unwinding.
Unwinding leaf function is useful in cases when the backtrace finds a
leaf function for example when it caused a signal.
This patch also add the support for the DW_CFA_undefined because it marks
the end of the frames.
Ryan Prichard provided code for the tests.
Reviewed By: #libunwind, mstorsjo
Differential Revision: https://reviews.llvm.org/D83573
Added:
libunwind/test/signal_unwind.pass.cpp
libunwind/test/unwind_leaffunction.pass.cpp
Modified:
libunwind/src/DwarfInstructions.hpp
libunwind/src/DwarfParser.hpp
libunwind/test/lit.site.cfg.in
Removed:
diff --git a/libunwind/src/DwarfInstructions.hpp
b/libunwind/src/DwarfInstructions.hpp
index ee98f538d437..c39cabe1f783 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -93,7 +93,8 @@ typename A::pint_t DwarfInstructions::getSavedRegister(
case CFI_Parser::kRegisterInRegister:
return registers.getRegister((int)savedReg.value);
-
+ case CFI_Parser::kRegisterUndefined:
+return 0;
case CFI_Parser::kRegisterUnused:
case CFI_Parser::kRegisterOffsetFromCFA:
// FIX ME
@@ -117,6 +118,7 @@ double DwarfInstructions::getSavedFloatRegister(
case CFI_Parser::kRegisterIsExpression:
case CFI_Parser::kRegisterUnused:
+ case CFI_Parser::kRegisterUndefined:
case CFI_Parser::kRegisterOffsetFromCFA:
case CFI_Parser::kRegisterInRegister:
// FIX ME
@@ -140,6 +142,7 @@ v128 DwarfInstructions::getSavedVectorRegister(
case CFI_Parser::kRegisterIsExpression:
case CFI_Parser::kRegisterUnused:
+ case CFI_Parser::kRegisterUndefined:
case CFI_Parser::kRegisterOffsetFromCFA:
case CFI_Parser::kRegisterInRegister:
// FIX ME
@@ -190,6 +193,10 @@ int DwarfInstructions::stepWithDwarf(A
&addressSpace, pint_t pc,
prolog.savedRegisters[i]));
else
return UNW_EBADREG;
+} else if (i == (int)cieInfo.returnAddressRegister) {
+// Leaf function keeps the return address in register and there is
no
+// explicit intructions how to restore it.
+returnAddress =
registers.getRegister(cieInfo.returnAddressRegister);
}
}
diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp
index c98c4f92a6ad..1ce2cf2943a2 100644
--- a/libunwind/src/DwarfParser.hpp
+++ b/libunwind/src/DwarfParser.hpp
@@ -69,6 +69,7 @@ class CFI_Parser {
};
enum RegisterSavedWhere {
kRegisterUnused,
+kRegisterUndefined,
kRegisterInCFA,
kRegisterOffsetFromCFA,
kRegisterInRegister,
@@ -503,7 +504,7 @@ bool CFI_Parser::parseInstructions(A &addressSpace,
pint_t instructions,
"malformed DW_CFA_undefined DWARF unwind, reg too big");
return false;
}
- results->setRegisterLocation(reg, kRegisterUnused, initialState);
+ results->setRegisterLocation(reg, kRegisterUndefined, initialState);
_LIBUNWIND_TRACE_DWARF("DW_CFA_undefined(reg=%" PRIu64 ")\n", reg);
break;
case DW_CFA_same_value:
diff --git a/libunwind/test/lit.site.cfg.in b/libunwind/test/lit.site.cfg.in
index 8ff770fe29bc..84dae3c2bfb0 100644
--- a/libunwind/test/lit.site.cfg.in
+++ b/libunwind/test/lit.site.cfg.in
@@ -44,6 +44,10 @@ config.test_source_root =
os.path.join(config.libunwind_src_root, 'test')
# Allow expanding substitutions that are based on other substitutions
config.recursiveExpansionLimit = 10
+# Make symbols available in the tests.
+config.test_compiler_flags += " -funwind-tables "
+config.test_linker_flags += " -Wl,--export-dynamic "
+
# Infer the test_exec_root from the build directory.
config.test_exec_root = os.path.join(config.libunwind_obj_root, 'test')
diff --git a/libunwind/test/signal_unwind.pass.cpp
b/libunwind/test/signal_unwind.pass.cpp
new file mode 100644
index ..295dd75bb726
--- /dev/null
+++ b/libunwind/test/signal_unwind.pass.cpp
@@ -0,0 +1,44 @@
+// -*- C++ -*-
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// Ensure that the unwinder can cope with the signal handler.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+_Unwind_Reason_Code frame_handler(s
[clang] 95e43f8 - [AArch64] Add -mmark-bti-property flag.
Author: Daniel Kiss
Date: 2020-09-17T00:24:14+02:00
New Revision: 95e43f84b7b9c61011aece7583c0367297dd67d8
URL:
https://github.com/llvm/llvm-project/commit/95e43f84b7b9c61011aece7583c0367297dd67d8
DIFF:
https://github.com/llvm/llvm-project/commit/95e43f84b7b9c61011aece7583c0367297dd67d8.diff
LOG: [AArch64] Add -mmark-bti-property flag.
Writing the .note.gnu.property manually is error prone and hard to
maintain in the assembly files.
The -mmark-bti-property is for the assembler to emit the section with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI. To be used when C/C++ is compiled
with -mbranch-protection=bti.
This patch refactors the .note.gnu.property handling.
Reviewed By: chill, nickdesaulniers
Differential Revision: https://reviews.llvm.org/D81930
Added:
clang/test/Driver/arm64-markbti.S
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Clang.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 5b39ea513b24..d7c2496b8a5d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2385,6 +2385,9 @@ def mfix_cortex_a53_835769 : Flag<["-"],
"mfix-cortex-a53-835769">,
def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
Group,
HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+def mmark_bti_property : Flag<["-"], "mmark-bti-property">,
+ Group,
+ HelpText<"Add .note.gnu.property with BTI to assembly files (AArch64 only)">;
foreach i = {1-31} in
def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
HelpText<"Reserve the x"#i#" register (AArch64/RISC-V only)">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 51056960761d..e13ffe67af89 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -7018,6 +7018,15 @@ void ClangAs::ConstructJob(Compilation &C, const
JobAction &JA,
}
break;
+ case llvm::Triple::aarch64:
+ case llvm::Triple::aarch64_32:
+ case llvm::Triple::aarch64_be:
+if (Args.hasArg(options::OPT_mmark_bti_property)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-aarch64-mark-bti-property");
+}
+break;
+
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
AddRISCVTargetArgs(Args, CmdArgs);
diff --git a/clang/test/Driver/arm64-markbti.S
b/clang/test/Driver/arm64-markbti.S
new file mode 100644
index ..68c81d31afa3
--- /dev/null
+++ b/clang/test/Driver/arm64-markbti.S
@@ -0,0 +1,24 @@
+// When -mmark-bti-property is passed the generated file object gets BTI
marking.
+// RUN: %clang -target arm64-linux-none -mmark-bti-property -c -o - %s |
llvm-readobj -n - | FileCheck -check-prefix=CHECK -check-prefix=CHECK_GEN %s
+// RUN: %clang -target arm64-linux-none -DNOTE_PRESENT -c %s -o - |
llvm-readobj -n - | FileCheck -check-prefix=CHECK -check-prefix=CHECK_PRESET %s
+// RUN: %clang -target arm64-linux-none -mmark-bti-property -DNOTE_PRESENT -c
%s -o - | llvm-readobj -n - | FileCheck -check-prefix=CHECK
-check-prefix=CHECK_PRESET %s
+// RUN: %clang -target arm64-linux-none -mmark-bti-property -DNOTE_PRESENT -c
%s -o - 2>&1 | FileCheck -check-prefix=CHECK_WARNING %s
+//
+// CHECK_WARNING: The .note.gnu.property is not emitted because it is already
present.
+// CHECK: Name: .note.gnu.property
+// CHECK: Type: NT_GNU_PROPERTY_TYPE_0
+// CHECK_GEN: aarch64 feature: BTI
+// CHECK_PRESET: aarch64 feature: BTI, PAC
+
+#ifdef NOTE_PRESENT
+ .section .note.gnu.property, "a";
+ .balign 8;
+ .long 4;
+ .long 0x10;
+ .long 0x5
+ .asciz "GNU"
+ .long 0xc000
+ .long 4
+ .long 3
+ .long 0
+#endif
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 8cbd60d74970..30ac7f4c0d2e 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -223,26 +223,9 @@ void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) {
return;
// Emit a .note.gnu.property section with the flags.
- MCSection *Cur = OutStreamer->getCurrentSectionOnly();
- MCSection *Nt = MMI->getContext().getELFSection(
- ".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
- OutStreamer->SwitchSection(Nt);
-
- // Emit the note header.
- emitAlignment(Align(8));
- OutStreamer->emitInt32(4); // data size for "GNU\0"
- OutStreamer->emitInt32(4 * 4); // Elf_Prop size
- OutStreamer->emitInt32(ELF::NT_GNU_PROPERTY_TYPE_0);
- OutStreamer->emitBytes(StringRef("GNU", 4)); // note name
-
- // Emit the PAC/BTI properties.
- OutStreamer->emitInt32(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_
[clang] f70baaf - [AArch64] Add -mmark-bti-property flag.
Author: Daniel Kiss
Date: 2020-09-17T01:18:36+02:00
New Revision: f70baaf71f62ba8623b3522345527271add74f6b
URL:
https://github.com/llvm/llvm-project/commit/f70baaf71f62ba8623b3522345527271add74f6b
DIFF:
https://github.com/llvm/llvm-project/commit/f70baaf71f62ba8623b3522345527271add74f6b.diff
LOG: [AArch64] Add -mmark-bti-property flag.
Writing the .note.gnu.property manually is error prone and hard to
maintain in the assembly files.
The -mmark-bti-property is for the assembler to emit the section with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI. To be used when C/C++ is compiled
with -mbranch-protection=bti.
This patch refactors the .note.gnu.property handling.
Reviewed By: chill, nickdesaulniers
Differential Revision: https://reviews.llvm.org/D81930
Reland with test dependency on aarch64 target.
Added:
clang/test/Driver/arm64-markbti.S
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Clang.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 5b39ea513b24..d7c2496b8a5d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2385,6 +2385,9 @@ def mfix_cortex_a53_835769 : Flag<["-"],
"mfix-cortex-a53-835769">,
def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
Group,
HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+def mmark_bti_property : Flag<["-"], "mmark-bti-property">,
+ Group,
+ HelpText<"Add .note.gnu.property with BTI to assembly files (AArch64 only)">;
foreach i = {1-31} in
def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
HelpText<"Reserve the x"#i#" register (AArch64/RISC-V only)">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 51056960761d..e13ffe67af89 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -7018,6 +7018,15 @@ void ClangAs::ConstructJob(Compilation &C, const
JobAction &JA,
}
break;
+ case llvm::Triple::aarch64:
+ case llvm::Triple::aarch64_32:
+ case llvm::Triple::aarch64_be:
+if (Args.hasArg(options::OPT_mmark_bti_property)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-aarch64-mark-bti-property");
+}
+break;
+
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
AddRISCVTargetArgs(Args, CmdArgs);
diff --git a/clang/test/Driver/arm64-markbti.S
b/clang/test/Driver/arm64-markbti.S
new file mode 100644
index ..8eeed74810d2
--- /dev/null
+++ b/clang/test/Driver/arm64-markbti.S
@@ -0,0 +1,26 @@
+// REQUIRES: aarch64-registered-target
+
+// When -mmark-bti-property is passed the generated file object gets BTI
marking.
+// RUN: %clang -target arm64-linux-none -mmark-bti-property -c -o - %s |
llvm-readobj -n - | FileCheck -check-prefix=CHECK -check-prefix=CHECK_GEN %s
+// RUN: %clang -target arm64-linux-none -DNOTE_PRESENT -c %s -o - |
llvm-readobj -n - | FileCheck -check-prefix=CHECK -check-prefix=CHECK_PRESET %s
+// RUN: %clang -target arm64-linux-none -mmark-bti-property -DNOTE_PRESENT -c
%s -o - | llvm-readobj -n - | FileCheck -check-prefix=CHECK
-check-prefix=CHECK_PRESET %s
+// RUN: %clang -target arm64-linux-none -mmark-bti-property -DNOTE_PRESENT -c
%s -o - 2>&1 | FileCheck -check-prefix=CHECK_WARNING %s
+//
+// CHECK_WARNING: The .note.gnu.property is not emitted because it is already
present.
+// CHECK: Name: .note.gnu.property
+// CHECK: Type: NT_GNU_PROPERTY_TYPE_0
+// CHECK_GEN: aarch64 feature: BTI
+// CHECK_PRESET: aarch64 feature: BTI, PAC
+
+#ifdef NOTE_PRESENT
+ .section .note.gnu.property, "a";
+ .balign 8;
+ .long 4;
+ .long 0x10;
+ .long 0x5
+ .asciz "GNU"
+ .long 0xc000
+ .long 4
+ .long 3
+ .long 0
+#endif
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 8cbd60d74970..30ac7f4c0d2e 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -223,26 +223,9 @@ void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) {
return;
// Emit a .note.gnu.property section with the flags.
- MCSection *Cur = OutStreamer->getCurrentSectionOnly();
- MCSection *Nt = MMI->getContext().getELFSection(
- ".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
- OutStreamer->SwitchSection(Nt);
-
- // Emit the note header.
- emitAlignment(Align(8));
- OutStreamer->emitInt32(4); // data size for "GNU\0"
- OutStreamer->emitInt32(4 * 4); // Elf_Prop size
- OutStreamer->emitInt32(ELF::NT_GNU_PROPERTY_TYPE_0);
- OutStreamer->emitBytes(StringRef("GNU", 4)); // note name
-
- // E
[clang] 60e244f - Revert "[AArch64] Add -mmark-bti-property flag."
Author: Daniel Kiss
Date: 2020-09-17T01:17:23+02:00
New Revision: 60e244f82c1f97c1b7d65c06d2b0b4f634f8d696
URL:
https://github.com/llvm/llvm-project/commit/60e244f82c1f97c1b7d65c06d2b0b4f634f8d696
DIFF:
https://github.com/llvm/llvm-project/commit/60e244f82c1f97c1b7d65c06d2b0b4f634f8d696.diff
LOG: Revert "[AArch64] Add -mmark-bti-property flag."
This reverts commit 95e43f84b7b9c61011aece7583c0367297dd67d8.
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Clang.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
Removed:
clang/test/Driver/arm64-markbti.S
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d7c2496b8a5d..5b39ea513b24 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2385,9 +2385,6 @@ def mfix_cortex_a53_835769 : Flag<["-"],
"mfix-cortex-a53-835769">,
def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
Group,
HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
-def mmark_bti_property : Flag<["-"], "mmark-bti-property">,
- Group,
- HelpText<"Add .note.gnu.property with BTI to assembly files (AArch64 only)">;
foreach i = {1-31} in
def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
HelpText<"Reserve the x"#i#" register (AArch64/RISC-V only)">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index e13ffe67af89..51056960761d 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -7018,15 +7018,6 @@ void ClangAs::ConstructJob(Compilation &C, const
JobAction &JA,
}
break;
- case llvm::Triple::aarch64:
- case llvm::Triple::aarch64_32:
- case llvm::Triple::aarch64_be:
-if (Args.hasArg(options::OPT_mmark_bti_property)) {
- CmdArgs.push_back("-mllvm");
- CmdArgs.push_back("-aarch64-mark-bti-property");
-}
-break;
-
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
AddRISCVTargetArgs(Args, CmdArgs);
diff --git a/clang/test/Driver/arm64-markbti.S
b/clang/test/Driver/arm64-markbti.S
deleted file mode 100644
index 68c81d31afa3..
--- a/clang/test/Driver/arm64-markbti.S
+++ /dev/null
@@ -1,24 +0,0 @@
-// When -mmark-bti-property is passed the generated file object gets BTI
marking.
-// RUN: %clang -target arm64-linux-none -mmark-bti-property -c -o - %s |
llvm-readobj -n - | FileCheck -check-prefix=CHECK -check-prefix=CHECK_GEN %s
-// RUN: %clang -target arm64-linux-none -DNOTE_PRESENT -c %s -o - |
llvm-readobj -n - | FileCheck -check-prefix=CHECK -check-prefix=CHECK_PRESET %s
-// RUN: %clang -target arm64-linux-none -mmark-bti-property -DNOTE_PRESENT -c
%s -o - | llvm-readobj -n - | FileCheck -check-prefix=CHECK
-check-prefix=CHECK_PRESET %s
-// RUN: %clang -target arm64-linux-none -mmark-bti-property -DNOTE_PRESENT -c
%s -o - 2>&1 | FileCheck -check-prefix=CHECK_WARNING %s
-//
-// CHECK_WARNING: The .note.gnu.property is not emitted because it is already
present.
-// CHECK: Name: .note.gnu.property
-// CHECK: Type: NT_GNU_PROPERTY_TYPE_0
-// CHECK_GEN: aarch64 feature: BTI
-// CHECK_PRESET: aarch64 feature: BTI, PAC
-
-#ifdef NOTE_PRESENT
- .section .note.gnu.property, "a";
- .balign 8;
- .long 4;
- .long 0x10;
- .long 0x5
- .asciz "GNU"
- .long 0xc000
- .long 4
- .long 3
- .long 0
-#endif
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 30ac7f4c0d2e..8cbd60d74970 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -223,9 +223,26 @@ void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) {
return;
// Emit a .note.gnu.property section with the flags.
- if (auto *TS = static_cast(
- OutStreamer->getTargetStreamer()))
-TS->emitNoteSection(Flags);
+ MCSection *Cur = OutStreamer->getCurrentSectionOnly();
+ MCSection *Nt = MMI->getContext().getELFSection(
+ ".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
+ OutStreamer->SwitchSection(Nt);
+
+ // Emit the note header.
+ emitAlignment(Align(8));
+ OutStreamer->emitInt32(4); // data size for "GNU\0"
+ OutStreamer->emitInt32(4 * 4); // Elf_Prop size
+ OutStreamer->emitInt32(ELF::NT_GNU_PROPERTY_TYPE_0);
+ OutStreamer->emitBytes(StringRef("GNU", 4)); // note name
+
+ // Emit the PAC/BTI properties.
+ OutStreamer->emitInt32(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND);
+ OutStreamer->emitInt32(4); // data size
+ OutStreamer->emitInt32(Flags); // data
+ OutStreamer->emitInt32(0); // pad
+
+ OutStreamer->endSection(Nt);
+ OutStreamer->SwitchSection(Cur);
}
void AArch64AsmPrinter::
[libunwind] 5831adb - Revert "[libunwind] Support for leaf function unwinding."
Author: Daniel Kiss
Date: 2020-09-18T11:37:54+02:00
New Revision: 5831adb8c38f3fd1b17ff52984c514fc32e893f6
URL:
https://github.com/llvm/llvm-project/commit/5831adb8c38f3fd1b17ff52984c514fc32e893f6
DIFF:
https://github.com/llvm/llvm-project/commit/5831adb8c38f3fd1b17ff52984c514fc32e893f6.diff
LOG: Revert "[libunwind] Support for leaf function unwinding."
This reverts commit 23bef7ee9923b1262326981960397e8cd95d6923.
Added:
Modified:
libunwind/src/DwarfInstructions.hpp
libunwind/src/DwarfParser.hpp
libunwind/test/lit.site.cfg.in
Removed:
libunwind/test/signal_unwind.pass.cpp
libunwind/test/unwind_leaffunction.pass.cpp
diff --git a/libunwind/src/DwarfInstructions.hpp
b/libunwind/src/DwarfInstructions.hpp
index c39cabe1f783..ee98f538d437 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -93,8 +93,7 @@ typename A::pint_t DwarfInstructions::getSavedRegister(
case CFI_Parser::kRegisterInRegister:
return registers.getRegister((int)savedReg.value);
- case CFI_Parser::kRegisterUndefined:
-return 0;
+
case CFI_Parser::kRegisterUnused:
case CFI_Parser::kRegisterOffsetFromCFA:
// FIX ME
@@ -118,7 +117,6 @@ double DwarfInstructions::getSavedFloatRegister(
case CFI_Parser::kRegisterIsExpression:
case CFI_Parser::kRegisterUnused:
- case CFI_Parser::kRegisterUndefined:
case CFI_Parser::kRegisterOffsetFromCFA:
case CFI_Parser::kRegisterInRegister:
// FIX ME
@@ -142,7 +140,6 @@ v128 DwarfInstructions::getSavedVectorRegister(
case CFI_Parser::kRegisterIsExpression:
case CFI_Parser::kRegisterUnused:
- case CFI_Parser::kRegisterUndefined:
case CFI_Parser::kRegisterOffsetFromCFA:
case CFI_Parser::kRegisterInRegister:
// FIX ME
@@ -193,10 +190,6 @@ int DwarfInstructions::stepWithDwarf(A
&addressSpace, pint_t pc,
prolog.savedRegisters[i]));
else
return UNW_EBADREG;
-} else if (i == (int)cieInfo.returnAddressRegister) {
-// Leaf function keeps the return address in register and there is
no
-// explicit intructions how to restore it.
-returnAddress =
registers.getRegister(cieInfo.returnAddressRegister);
}
}
diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp
index 86c0522afd3f..fb943edfdb7e 100644
--- a/libunwind/src/DwarfParser.hpp
+++ b/libunwind/src/DwarfParser.hpp
@@ -69,7 +69,6 @@ class CFI_Parser {
};
enum RegisterSavedWhere {
kRegisterUnused,
-kRegisterUndefined,
kRegisterInCFA,
kRegisterOffsetFromCFA,
kRegisterInRegister,
@@ -506,7 +505,7 @@ bool CFI_Parser::parseInstructions(A &addressSpace,
pint_t instructions,
"malformed DW_CFA_undefined DWARF unwind, reg too big");
return false;
}
- results->setRegisterLocation(reg, kRegisterUndefined, initialState);
+ results->setRegisterLocation(reg, kRegisterUnused, initialState);
_LIBUNWIND_TRACE_DWARF("DW_CFA_undefined(reg=%" PRIu64 ")\n", reg);
break;
case DW_CFA_same_value:
diff --git a/libunwind/test/lit.site.cfg.in b/libunwind/test/lit.site.cfg.in
index 84dae3c2bfb0..8ff770fe29bc 100644
--- a/libunwind/test/lit.site.cfg.in
+++ b/libunwind/test/lit.site.cfg.in
@@ -44,10 +44,6 @@ config.test_source_root =
os.path.join(config.libunwind_src_root, 'test')
# Allow expanding substitutions that are based on other substitutions
config.recursiveExpansionLimit = 10
-# Make symbols available in the tests.
-config.test_compiler_flags += " -funwind-tables "
-config.test_linker_flags += " -Wl,--export-dynamic "
-
# Infer the test_exec_root from the build directory.
config.test_exec_root = os.path.join(config.libunwind_obj_root, 'test')
diff --git a/libunwind/test/signal_unwind.pass.cpp
b/libunwind/test/signal_unwind.pass.cpp
deleted file mode 100644
index 295dd75bb726..
--- a/libunwind/test/signal_unwind.pass.cpp
+++ /dev/null
@@ -1,44 +0,0 @@
-// -*- C++ -*-
-//===--===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-
-// Ensure that the unwinder can cope with the signal handler.
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-_Unwind_Reason_Code frame_handler(struct _Unwind_Context* ctx, void* arg) {
- (void)arg;
- Dl_info info = { 0, 0, 0, 0 };
- assert(dladdr((void*)_Unwind_GetIP(ctx), &info));
-
- // Unwind util the main is reached, above frames deeped on the platfrom and
architecture.
- if(info.dli_sname && !strcmp("main",
[libunwind] 22b615a - [libunwind] Support for leaf function unwinding.
Author: Daniel Kiss
Date: 2020-09-18T15:09:42+02:00
New Revision: 22b615a96593f13109a27cabfd1764ec4f558c7a
URL:
https://github.com/llvm/llvm-project/commit/22b615a96593f13109a27cabfd1764ec4f558c7a
DIFF:
https://github.com/llvm/llvm-project/commit/22b615a96593f13109a27cabfd1764ec4f558c7a.diff
LOG: [libunwind] Support for leaf function unwinding.
Unwinding leaf function is useful in cases when the backtrace finds a
leaf function for example when it caused a signal.
This patch also add the support for the DW_CFA_undefined because it marks
the end of the frames.
Ryan Prichard provided code for the tests.
Reviewed By: #libunwind, mstorsjo
Differential Revision: https://reviews.llvm.org/D83573
Reland with limit the test to the x86_64-linux target.
Added:
libunwind/test/signal_unwind.pass.cpp
libunwind/test/unwind_leaffunction.pass.cpp
Modified:
libunwind/src/DwarfInstructions.hpp
libunwind/src/DwarfParser.hpp
libunwind/test/lit.site.cfg.in
Removed:
diff --git a/libunwind/src/DwarfInstructions.hpp
b/libunwind/src/DwarfInstructions.hpp
index ee98f538d437..c39cabe1f783 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -93,7 +93,8 @@ typename A::pint_t DwarfInstructions::getSavedRegister(
case CFI_Parser::kRegisterInRegister:
return registers.getRegister((int)savedReg.value);
-
+ case CFI_Parser::kRegisterUndefined:
+return 0;
case CFI_Parser::kRegisterUnused:
case CFI_Parser::kRegisterOffsetFromCFA:
// FIX ME
@@ -117,6 +118,7 @@ double DwarfInstructions::getSavedFloatRegister(
case CFI_Parser::kRegisterIsExpression:
case CFI_Parser::kRegisterUnused:
+ case CFI_Parser::kRegisterUndefined:
case CFI_Parser::kRegisterOffsetFromCFA:
case CFI_Parser::kRegisterInRegister:
// FIX ME
@@ -140,6 +142,7 @@ v128 DwarfInstructions::getSavedVectorRegister(
case CFI_Parser::kRegisterIsExpression:
case CFI_Parser::kRegisterUnused:
+ case CFI_Parser::kRegisterUndefined:
case CFI_Parser::kRegisterOffsetFromCFA:
case CFI_Parser::kRegisterInRegister:
// FIX ME
@@ -190,6 +193,10 @@ int DwarfInstructions::stepWithDwarf(A
&addressSpace, pint_t pc,
prolog.savedRegisters[i]));
else
return UNW_EBADREG;
+} else if (i == (int)cieInfo.returnAddressRegister) {
+// Leaf function keeps the return address in register and there is
no
+// explicit intructions how to restore it.
+returnAddress =
registers.getRegister(cieInfo.returnAddressRegister);
}
}
diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp
index fb943edfdb7e..86c0522afd3f 100644
--- a/libunwind/src/DwarfParser.hpp
+++ b/libunwind/src/DwarfParser.hpp
@@ -69,6 +69,7 @@ class CFI_Parser {
};
enum RegisterSavedWhere {
kRegisterUnused,
+kRegisterUndefined,
kRegisterInCFA,
kRegisterOffsetFromCFA,
kRegisterInRegister,
@@ -505,7 +506,7 @@ bool CFI_Parser::parseInstructions(A &addressSpace,
pint_t instructions,
"malformed DW_CFA_undefined DWARF unwind, reg too big");
return false;
}
- results->setRegisterLocation(reg, kRegisterUnused, initialState);
+ results->setRegisterLocation(reg, kRegisterUndefined, initialState);
_LIBUNWIND_TRACE_DWARF("DW_CFA_undefined(reg=%" PRIu64 ")\n", reg);
break;
case DW_CFA_same_value:
diff --git a/libunwind/test/lit.site.cfg.in b/libunwind/test/lit.site.cfg.in
index 8ff770fe29bc..84dae3c2bfb0 100644
--- a/libunwind/test/lit.site.cfg.in
+++ b/libunwind/test/lit.site.cfg.in
@@ -44,6 +44,10 @@ config.test_source_root =
os.path.join(config.libunwind_src_root, 'test')
# Allow expanding substitutions that are based on other substitutions
config.recursiveExpansionLimit = 10
+# Make symbols available in the tests.
+config.test_compiler_flags += " -funwind-tables "
+config.test_linker_flags += " -Wl,--export-dynamic "
+
# Infer the test_exec_root from the build directory.
config.test_exec_root = os.path.join(config.libunwind_obj_root, 'test')
diff --git a/libunwind/test/signal_unwind.pass.cpp
b/libunwind/test/signal_unwind.pass.cpp
new file mode 100644
index ..5955c1b14055
--- /dev/null
+++ b/libunwind/test/signal_unwind.pass.cpp
@@ -0,0 +1,45 @@
+// -*- C++ -*-
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// Ensure that the unwinder can cope with the signal handler.
+// REQUIRES: x86_64-linux
+
+#include
+#include
+#include
+#include
+#include
[libunwind] f34ae1b - [AArch64] Add v8.5 Branch Target Identification support.
Author: Daniel Kiss Date: 2020-09-29T15:51:01+02:00 New Revision: f34ae1b9de68152de037fd3e394d196b997c4296 URL: https://github.com/llvm/llvm-project/commit/f34ae1b9de68152de037fd3e394d196b997c4296 DIFF: https://github.com/llvm/llvm-project/commit/f34ae1b9de68152de037fd3e394d196b997c4296.diff LOG: [AArch64] Add v8.5 Branch Target Identification support. The .note.gnu.property must be in the assembly file to indicate the support for BTI otherwise BTI will be disabled for the whole library. __unw_getcontext and libunwind::Registers_arm64::jumpto() may be called indirectly therefore they should start with a landing pad. Reviewed By: tamas.petz, #libunwind, compnerd Differential Revision: https://reviews.llvm.org/D77786 Added: Modified: libunwind/src/assembly.h Removed: diff --git a/libunwind/src/assembly.h b/libunwind/src/assembly.h index 4cf179e13edc..3b1e6e6d01d7 100644 --- a/libunwind/src/assembly.h +++ b/libunwind/src/assembly.h @@ -48,6 +48,24 @@ #define PPC64_OPD2 #endif +#if defined(__ARM_FEATURE_BTI_DEFAULT) + .pushsection ".note.gnu.property", "a" SEPARATOR \ + .balign 8 SEPARATOR \ + .long 4 SEPARATOR \ + .long 0x10 SEPARATOR \ + .long 0x5 SEPARATOR \ + .asciz "GNU" SEPARATOR \ + .long 0xc000 SEPARATOR /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */ \ + .long 4 SEPARATOR \ + .long 3 SEPARATOR /* GNU_PROPERTY_AARCH64_FEATURE_1_BTI AND */ \ +/* GNU_PROPERTY_AARCH64_FEATURE_1_PAC */ \ + .long 0 SEPARATOR \ + .popsection SEPARATOR +#define AARCH64_BTI bti c +#else +#define AARCH64_BTI +#endif + #define GLUE2(a, b) a ## b #define GLUE(a, b) GLUE2(a, b) #define SYMBOL_NAME(name) GLUE(__USER_LABEL_PREFIX__, name) @@ -144,7 +162,8 @@ SYMBOL_IS_FUNC(SYMBOL_NAME(name)) SEPARATOR \ PPC64_OPD1 \ SYMBOL_NAME(name): \ - PPC64_OPD2 + PPC64_OPD2 \ + AARCH64_BTI #if defined(__arm__) #if !defined(__ARM_ARCH) ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] e7b8d37 - [libunwind] LIBUNWIND_REMEMBER_HEAP_ALLOC to cmake.
Author: Daniel Kiss
Date: 2020-11-11T11:21:17+01:00
New Revision: e7b8d3776f36beb9b73cd0f7c81fdc4b832b6df3
URL:
https://github.com/llvm/llvm-project/commit/e7b8d3776f36beb9b73cd0f7c81fdc4b832b6df3
DIFF:
https://github.com/llvm/llvm-project/commit/e7b8d3776f36beb9b73cd0f7c81fdc4b832b6df3.diff
LOG: [libunwind] LIBUNWIND_REMEMBER_HEAP_ALLOC to cmake.
Missed it originally in https://reviews.llvm.org/D85005.
Reviewed By: gargaroff
Differential Revision: https://reviews.llvm.org/D91182
Added:
Modified:
libunwind/CMakeLists.txt
Removed:
diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt
index d7e13b78a9c9..e344263173b0 100644
--- a/libunwind/CMakeLists.txt
+++ b/libunwind/CMakeLists.txt
@@ -69,6 +69,7 @@ option(LIBUNWIND_USE_COMPILER_RT "Use compiler-rt instead of
libgcc" OFF)
option(LIBUNWIND_INCLUDE_DOCS "Build the libunwind documentation."
${LLVM_INCLUDE_DOCS})
option(LIBUNWIND_IS_BAREMETAL "Build libunwind for baremetal targets." OFF)
option(LIBUNWIND_USE_FRAME_HEADER_CACHE "Cache frame headers for unwinding.
Requires locking dl_iterate_phdr." OFF)
+option(LIBUNWIND_REMEMBER_HEAP_ALLOC "Use heap instead of the stack for
.cfi_remember_state." OFF)
set(LIBUNWIND_LIBDIR_SUFFIX "${LLVM_LIBDIR_SUFFIX}" CACHE STRING
"Define suffix of library directory name (32/64)")
@@ -312,6 +313,10 @@ if(LIBUNWIND_USE_FRAME_HEADER_CACHE)
add_compile_definitions(_LIBUNWIND_USE_FRAME_HEADER_CACHE)
endif()
+if(LIBUNWIND_REMEMBER_HEAP_ALLOC)
+ add_compile_definitions(_LIBUNWIND_REMEMBER_HEAP_ALLOC)
+endif()
+
# This is the _ONLY_ place where add_definitions is called.
if (MSVC)
add_definitions(-D_CRT_SECURE_NO_WARNINGS)
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[libunwind] 05598e3 - [libunwind] Fix linker flag handling in the tests.
Author: Daniel Kiss
Date: 2020-10-29T14:02:44+01:00
New Revision: 05598e3d3047cf028cc3e61f3268ff7d999e5f26
URL:
https://github.com/llvm/llvm-project/commit/05598e3d3047cf028cc3e61f3268ff7d999e5f26
DIFF:
https://github.com/llvm/llvm-project/commit/05598e3d3047cf028cc3e61f3268ff7d999e5f26.diff
LOG: [libunwind] Fix linker flag handling in the tests.
--export-dynamic is not always available on all targets.
-funwind-tables was a duplicate in the lit.site.cfg.in.
Reviewed By: ldionne
Differential Revision: https://reviews.llvm.org/D90202
Added:
Modified:
libunwind/test/libunwind/test/config.py
libunwind/test/lit.site.cfg.in
Removed:
diff --git a/libunwind/test/libunwind/test/config.py
b/libunwind/test/libunwind/test/config.py
index 977f9a0fb3f9..9231860fc622 100644
--- a/libunwind/test/libunwind/test/config.py
+++ b/libunwind/test/libunwind/test/config.py
@@ -43,6 +43,9 @@ def configure_compile_flags(self):
# Stack unwinding tests need unwinding tables and these are not
# generated by default on all Targets.
self.cxx.compile_flags += ['-funwind-tables']
+# Make symbols available in the tests.
+if 'linux' in self.config.target_triple:
+self.cxx.link_flags += ['-Wl,--export-dynamic']
if not self.get_lit_bool('enable_threads', True):
self.cxx.compile_flags += ['-D_LIBUNWIND_HAS_NO_THREADS']
self.config.available_features.add('libunwind-no-threads')
diff --git a/libunwind/test/lit.site.cfg.in b/libunwind/test/lit.site.cfg.in
index 84dae3c2bfb0..8ff770fe29bc 100644
--- a/libunwind/test/lit.site.cfg.in
+++ b/libunwind/test/lit.site.cfg.in
@@ -44,10 +44,6 @@ config.test_source_root =
os.path.join(config.libunwind_src_root, 'test')
# Allow expanding substitutions that are based on other substitutions
config.recursiveExpansionLimit = 10
-# Make symbols available in the tests.
-config.test_compiler_flags += " -funwind-tables "
-config.test_linker_flags += " -Wl,--export-dynamic "
-
# Infer the test_exec_root from the build directory.
config.test_exec_root = os.path.join(config.libunwind_obj_root, 'test')
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[libunwind] 1d7786d - [libunwind] Support DW_CFA_remember/restore_state without heap allocation.
Author: Daniel Kiss
Date: 2020-10-30T17:45:20+01:00
New Revision: 1d7786d45f48b4793baf4e4b903c4476f56ffc94
URL:
https://github.com/llvm/llvm-project/commit/1d7786d45f48b4793baf4e4b903c4476f56ffc94
DIFF:
https://github.com/llvm/llvm-project/commit/1d7786d45f48b4793baf4e4b903c4476f56ffc94.diff
LOG: [libunwind] Support DW_CFA_remember/restore_state without heap allocation.
This patch just reorganises the code to make possible to use alloca
instead of malloc. This makes possible to use
`.cfi_remember_state`/`.cfi_restore_state` on
platforms without heap allocation.
Also it will be safe to backtrace/unwind faults related to the allocator behind
malloc.
`_LIBUNWIND_REMEMBER_HEAP_ALLOC ` option reenables the heap usage for
`.cfi_remember_state`/`.cfi_restore_state`.
Define _LIBUNWIND_REMEMBER_STACK_ALLOC to force stack allocation.
Reviewed By: #libunwind, mstorsjo
Differential Revision: https://reviews.llvm.org/D85005
Added:
Modified:
libunwind/src/DwarfParser.hpp
libunwind/src/config.h
Removed:
diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp
index 86c0522afd3f..4bfd0451ed5a 100644
--- a/libunwind/src/DwarfParser.hpp
+++ b/libunwind/src/DwarfParser.hpp
@@ -135,6 +135,24 @@ class CFI_Parser {
PrologInfo info;
};
+ struct RememberStack {
+PrologInfoStackEntry *entry;
+RememberStack() : entry(nullptr) {}
+~RememberStack() {
+#if defined(_LIBUNWIND_REMEMBER_CLEANUP_NEEDED)
+ // Clean up rememberStack. Even in the case where every
+ // DW_CFA_remember_state is paired with a DW_CFA_restore_state,
+ // parseInstructions can skip restore opcodes if it reaches the target PC
+ // and stops interpreting, so we have to make sure we don't leak memory.
+ while (entry) {
+PrologInfoStackEntry *next = entry->next;
+_LIBUNWIND_REMEMBER_FREE(entry);
+entry = next;
+ }
+#endif
+}
+ };
+
static bool findFDE(A &addressSpace, pint_t pc, pint_t ehSectionStart,
uintptr_t sectionLength, pint_t fdeHint, FDE_Info
*fdeInfo,
CIE_Info *cieInfo);
@@ -145,13 +163,6 @@ class CFI_Parser {
int arch, PrologInfo *results);
static const char *parseCIE(A &addressSpace, pint_t cie, CIE_Info *cieInfo);
-
-private:
- static bool parseInstructions(A &addressSpace, pint_t instructions,
-pint_t instructionsEnd, const CIE_Info
&cieInfo,
-pint_t pcoffset,
-PrologInfoStackEntry *&rememberStack, int arch,
-PrologInfo *results);
};
/// Parse a FDE into a CIE_Info and an FDE_Info
@@ -394,418 +405,415 @@ bool CFI_Parser::parseFDEInstructions(A
&addressSpace,
const FDE_Info &fdeInfo,
const CIE_Info &cieInfo, pint_t
upToPC,
int arch, PrologInfo *results) {
- PrologInfoStackEntry *rememberStack = NULL;
-
- // parse CIE then FDE instructions
- bool returnValue =
- parseInstructions(addressSpace, cieInfo.cieInstructions,
-cieInfo.cieStart + cieInfo.cieLength, cieInfo,
-(pint_t)(-1), rememberStack, arch, results) &&
- parseInstructions(addressSpace, fdeInfo.fdeInstructions,
-fdeInfo.fdeStart + fdeInfo.fdeLength, cieInfo,
-upToPC - fdeInfo.pcStart, rememberStack, arch,
results);
-
-#if !defined(_LIBUNWIND_NO_HEAP)
- // Clean up rememberStack. Even in the case where every DW_CFA_remember_state
- // is paired with a DW_CFA_restore_state, parseInstructions can skip restore
- // opcodes if it reaches the target PC and stops interpreting, so we have to
- // make sure we don't leak memory.
- while (rememberStack) {
-PrologInfoStackEntry *next = rememberStack->next;
-free(rememberStack);
-rememberStack = next;
- }
-#endif
-
- return returnValue;
-}
+ // Alloca is used for the allocation of the rememberStack entries. It removes
+ // the dependency on new/malloc but the below for loop can not be refactored
+ // into functions. Entry could be saved during the processing of a CIE and
+ // restored by an FDE.
+ RememberStack rememberStack;
+
+ struct ParseInfo {
+pint_t instructions;
+pint_t instructionsEnd;
+pint_t pcoffset;
+ };
-/// "run" the DWARF instructions
-template
-bool CFI_Parser::parseInstructions(A &addressSpace, pint_t instructions,
- pint_t instructionsEnd,
- const CIE_Info &cieInfo, pint_t pcoffset,
- PrologInfoStackEntry *&rememberStack,
- int arch, PrologInfo *results) {
- pint_t p = instructions;
-
[clang] 7314aea - [clang] Move branch-protection from CodeGenOptions to LangOptions
Author: Daniel Kiss
Date: 2020-04-02T10:31:52+02:00
New Revision: 7314aea5a42d33f9f5af5d158d8892e88072764e
URL:
https://github.com/llvm/llvm-project/commit/7314aea5a42d33f9f5af5d158d8892e88072764e
DIFF:
https://github.com/llvm/llvm-project/commit/7314aea5a42d33f9f5af5d158d8892e88072764e.diff
LOG: [clang] Move branch-protection from CodeGenOptions to LangOptions
Summary:
Reason: the option has an effect on preprocessing.
Also see thread: http://lists.llvm.org/pipermail/cfe-dev/2020-March/065014.html
Reviewers: chill, efriedma
Reviewed By: efriedma
Subscribers: efriedma, danielkiss, cfe-commits, kristof.beyls
Tags: #clang
Differential Revision: https://reviews.llvm.org/D77131
Added:
Modified:
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Basic/CodeGenOptions.h
clang/include/clang/Basic/LangOptions.def
clang/include/clang/Basic/LangOptions.h
clang/include/clang/Basic/TargetInfo.h
clang/lib/AST/PrintfFormatString.cpp
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/CodeGen/CGDeclCXX.cpp
clang/lib/CodeGen/TargetInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
Removed:
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index a62cf5e729db..0faa013ac497 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -387,10 +387,6 @@ CODEGENOPT(ForceEmitVTables, 1, 0)
/// Whether to emit an address-significance table into the object file.
CODEGENOPT(Addrsig, 1, 0)
-ENUM_CODEGENOPT(SignReturnAddress, SignReturnAddressScope, 2,
SignReturnAddressScope::None)
-ENUM_CODEGENOPT(SignReturnAddressKey, SignReturnAddressKeyValue, 1,
SignReturnAddressKeyValue::AKey)
-CODEGENOPT(BranchTargetEnforcement, 1, 0)
-
/// Whether to emit unused static constants.
CODEGENOPT(KeepStaticConsts, 1, 0)
@@ -400,4 +396,3 @@ CODEGENOPT(ForceAAPCSBitfieldLoad, 1, 0)
#undef CODEGENOPT
#undef ENUM_CODEGENOPT
#undef VALUE_CODEGENOPT
-
diff --git a/clang/include/clang/Basic/CodeGenOptions.h
b/clang/include/clang/Basic/CodeGenOptions.h
index d435bebcdcf9..60d418688710 100644
--- a/clang/include/clang/Basic/CodeGenOptions.h
+++ b/clang/include/clang/Basic/CodeGenOptions.h
@@ -110,14 +110,6 @@ class CodeGenOptions : public CodeGenOptionsBase {
Embed_Marker// Embed a marker as a placeholder for bitcode.
};
- enum class SignReturnAddressScope {
-None,// No signing for any function
-NonLeaf, // Sign the return address of functions that spill LR
-All // Sign the return address of all functions
- };
-
- enum class SignReturnAddressKeyValue { AKey, BKey };
-
enum class FramePointerKind {
None,// Omit all frame pointers.
NonLeaf, // Keep non-leaf frame pointers.
diff --git a/clang/include/clang/Basic/LangOptions.def
b/clang/include/clang/Basic/LangOptions.def
index 6152e227d599..51dc87b0b671 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -353,6 +353,12 @@ LANGOPT(RegisterStaticDestructors, 1, 1, "Register C++
static destructors")
COMPATIBLE_VALUE_LANGOPT(MaxTokens, 32, 0, "Max number of tokens per TU or 0")
+ENUM_LANGOPT(SignReturnAddressScope, SignReturnAddressScopeKind, 2,
SignReturnAddressScopeKind::None,
+ "Scope of return address signing")
+ENUM_LANGOPT(SignReturnAddressKey, SignReturnAddressKeyKind, 1,
SignReturnAddressKeyKind::AKey,
+ "Key used for return address signing")
+LANGOPT(BranchTargetEnforcement, 1, 0, "Branch-target enforcement enabled")
+
#undef LANGOPT
#undef COMPATIBLE_LANGOPT
#undef BENIGN_LANGOPT
diff --git a/clang/include/clang/Basic/LangOptions.h
b/clang/include/clang/Basic/LangOptions.h
index 524ae9a822f4..090263342401 100644
--- a/clang/include/clang/Basic/LangOptions.h
+++ b/clang/include/clang/Basic/LangOptions.h
@@ -229,6 +229,22 @@ class LangOptions : public LangOptionsBase {
All,
};
+ enum class SignReturnAddressScopeKind {
+/// No signing for any function.
+None,
+/// Sign the return address of functions that spill LR.
+NonLeaf,
+/// Sign the return address of all functions,
+All
+ };
+
+ enum class SignReturnAddressKeyKind {
+/// Return address signing uses APIA key.
+AKey,
+/// Return address signing uses APIB key.
+BKey
+ };
+
public:
/// Set of enabled sanitizers.
SanitizerSet Sanitize;
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 5edfa0e4e0c7..ab4795404071 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -16,7 +16,7 @@
#include "clang/Basic/AddressSpaces.h"
#include "clang/Basic/LLVM.h"
-#include "clang/Basic/CodeGenOptions.h"
+#include "clang/Basic/LangOptions.h"
#include "clang/Basic/Specifiers.h"
#in
[clang] 37ced5a - [clang][AARCH64] Add __ARM_FEATURE_{PAC, BTI}_DEFAULT defines
Author: Daniel Kiss
Date: 2020-04-02T12:54:21+02:00
New Revision: 37ced5a571066c11548c672f354c6091f5903991
URL:
https://github.com/llvm/llvm-project/commit/37ced5a571066c11548c672f354c6091f5903991
DIFF:
https://github.com/llvm/llvm-project/commit/37ced5a571066c11548c672f354c6091f5903991.diff
LOG: [clang][AARCH64] Add __ARM_FEATURE_{PAC, BTI}_DEFAULT defines
Summary:
As defined by Arm C Language Extensions (ACLE) these macro defines
should be set to specific values depending on -mbranch-protection.
Reviewers: chill
Reviewed By: chill
Subscribers: danielkiss, cfe-commits, kristof.beyls
Tags: #clang
Differential Revision: https://reviews.llvm.org/D77134
Added:
Modified:
clang/include/clang/Basic/LangOptions.h
clang/lib/Basic/Targets/AArch64.cpp
clang/test/Preprocessor/aarch64-target-features.c
Removed:
diff --git a/clang/include/clang/Basic/LangOptions.h
b/clang/include/clang/Basic/LangOptions.h
index 090263342401..0a0cbaf80ae8 100644
--- a/clang/include/clang/Basic/LangOptions.h
+++ b/clang/include/clang/Basic/LangOptions.h
@@ -367,6 +367,21 @@ class LangOptions : public LangOptionsBase {
/// Return the OpenCL C or C++ version as a VersionTuple.
VersionTuple getOpenCLVersionTuple() const;
+
+ /// Check if return address signing is enabled.
+ bool hasSignReturnAddress() const {
+return getSignReturnAddressScope() != SignReturnAddressScopeKind::None;
+ }
+
+ /// Check if return address signing uses AKey.
+ bool isSignReturnAddressWithAKey() const {
+return getSignReturnAddressKey() == SignReturnAddressKeyKind::AKey;
+ }
+
+ /// Check if leaf functions are also signed.
+ bool isSignReturnAddressScopeAll() const {
+return getSignReturnAddressScope() == SignReturnAddressScopeKind::All;
+ }
};
/// Floating point control options
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index f70a53457613..8ceb7f2b515e 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -283,6 +283,27 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if ((FPU & NeonMode) && HasFP16FML)
Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
+ if (Opts.hasSignReturnAddress()) {
+// Bitmask:
+// 0: Protection using the A key
+// 1: Protection using the B key
+// 2: Protection including leaf functions
+unsigned Value = 0;
+
+if (Opts.isSignReturnAddressWithAKey())
+ Value |= (1 << 0);
+else
+ Value |= (1 << 1);
+
+if (Opts.isSignReturnAddressScopeAll())
+ Value |= (1 << 2);
+
+Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
+ }
+
+ if (Opts.BranchTargetEnforcement)
+Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
+
switch (ArchKind) {
default:
break;
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index c62c82a0c96a..9cb12f8afb32 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -39,6 +39,8 @@
// CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2
// CHECK-NOT: __ARM_FEATURE_SVE
// CHECK-NOT: __ARM_FEATURE_DOTPROD
+// CHECK-NOT: __ARM_FEATURE_PAC_DEFAULT
+// CHECK-NOT: __ARM_FEATURE_BTI_DEFAULT
// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crypto -x c -E
-dM %s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM
%s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
@@ -334,3 +336,33 @@
// == Check Memory Tagging Extensions (MTE).
// RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a+memtag -x c -E
-dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MEMTAG %s
// CHECK-MEMTAG: __ARM_FEATURE_MEMORY_TAGGING 1
+
+// == Check Pointer Authentication Extension (PAuth).
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o -
| FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a -x c -E -dM %s -o
- | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a
-mbranch-protection=none -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a
-mbranch-protection=standard -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck
[clang] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -1398,6 +1400,42 @@ class TargetInfo : public TransferrableTargetInfo,
}
llvm_unreachable("Unexpected SignReturnAddressKeyKind");
}
+
+ public:
+BranchProtectionInfo() = default;
DanielKristofKiss wrote:
We need the default constructor:
e.g
https://github.com/llvm/llvm-project/blob/main/clang/lib/Sema/SemaDeclAttr.cpp#L3481
https://github.com/llvm/llvm-project/blob/main/clang/lib/CodeGen/Targets/ARM.cpp#L144
https://github.com/llvm/llvm-project/pull/82819
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[clang] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
DanielKristofKiss wrote: > This still has "foo"="true" style function attributes, which are problematic. > Is the plan to change that? Can be changed to just "foo" just makes the function/module attribute importer more complicated to handle the old IR. https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss updated https://github.com/llvm/llvm-project/pull/82819 >From 5973486010ffe387789e8129d53a2b9d0cc4ca69 Mon Sep 17 00:00:00 2001 From: Daniel Kiss Date: Mon, 22 Jan 2024 11:33:15 +0100 Subject: [PATCH] Emit attributes for functions always. Branch protection, sign return address, guarded control stack flags are only emitted as module flags if not specified per function. The inliner might inline functions with different set of flags as it doesn't see the flags. In case of LTO build the module flags get merged with the `min` rule which means if one of the modules is not build with PAC/BTI then the features will be turned off on all functions due to the functions takes the branch-protection and sign-return-address features from the module flags. The sign-return-address is function level option therefore it is expected functions from files that are compiled with -mbranch-protection=pac-ret to be protected but in LTO case this might not happen. This patch adds the flags to functions in case of an LTO build therefore they don't need to rely on the module flag. --- clang/include/clang/Basic/TargetInfo.h| 44 +-- clang/lib/CodeGen/Targets/AArch64.cpp | 43 ++ clang/lib/CodeGen/Targets/ARM.cpp | 8 ++-- .../CodeGen/aarch64-branch-protection-attr.c | 26 +-- .../CodeGen/aarch64-sign-return-address.c | 12 +++-- clang/test/CodeGen/aarch64-targetattr.c | 2 +- .../CodeGen/arm-branch-protection-attr-1.c| 12 ++--- .../CodeGen/arm-branch-protection-attr-2.c| 13 -- .../test/Frontend/arm-branch-protection-lto.c | 22 ++ .../SelectionDAG/SelectionDAGBuilder.cpp | 12 + llvm/lib/IR/Verifier.cpp | 21 - llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +-- .../AArch64/AArch64MachineFunctionInfo.cpp| 39 +++- .../lib/Target/ARM/ARMMachineFunctionInfo.cpp | 22 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 6 ++- ...ranch-target-enforcement-indirect-calls.ll | 18 .../CodeGen/AArch64/bti-branch-relaxation.ll | 2 +- llvm/test/CodeGen/AArch64/kcfi-bti.ll | 7 +-- ...machine-outliner-2fixup-blr-terminator.mir | 2 +- .../CodeGen/AArch64/machine-outliner-bti.mir | 2 +- .../AArch64/machine-outliner-outline-bti.ll | 4 +- .../AArch64/note-gnu-property-pac-bti-0.ll| 2 +- .../AArch64/note-gnu-property-pac-bti-4.ll| 4 +- .../AArch64/pacbti-llvm-generated-funcs-1.ll | 4 +- .../AArch64/pacbti-llvm-generated-funcs-2.ll | 4 +- .../CodeGen/AArch64/pacbti-module-attrs.ll| 12 ++--- .../AArch64/patchable-function-entry-bti.ll | 10 ++--- .../CodeGen/AArch64/setjmp-bti-outliner.ll| 15 +++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 6 +-- .../AArch64/sign-return-address-pauth-lr.ll | 36 +++ .../CodeGen/AArch64/sign-return-address.ll| 8 ++-- llvm/test/CodeGen/AArch64/wineh-bti.ll| 7 +-- llvm/test/CodeGen/AArch64/wineh-pac.ll| 7 +-- llvm/test/CodeGen/ARM/setjmp-bti-basic.ll | 5 +-- llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll | 7 +-- llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll | 7 +-- .../CodeGen/Thumb2/bti-indirect-branches.ll | 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-1.ll| 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-2.ll| 12 ++--- .../CodeGen/Thumb2/bti-outliner-cost-2.ll | 6 +-- .../test/CodeGen/Thumb2/bti-pac-replace-1.mir | 8 +--- llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll | 7 +-- llvm/test/CodeGen/Thumb2/jump-table-bti.ll| 10 ++--- llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll| 6 +-- .../Thumb2/pacbti-m-indirect-tail-call.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-3.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 6 +-- .../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-overalign.ll | 2 +- .../test/CodeGen/Thumb2/pacbti-m-stack-arg.ll | 4 +- .../Thumb2/pacbti-m-unsupported-arch.ll | 8 +--- .../test/CodeGen/Thumb2/pacbti-m-varargs-1.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-varargs-2.ll | 4 +- llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 2 +- .../AArch64/link-branch-target-enforcement.ll | 2 +- .../Inline/inline-sign-return-address.ll | 13 +++--- .../LowerTypeTests/function-arm-thumb.ll | 2 +- .../LowerTypeTests/function-thumb-bti.ll | 4 +- .../Transforms/LowerTypeTests/function.ll | 4 +- 60 files changed, 277 insertions(+), 312 deletions(-) create mode 100644 clang/test/Frontend/arm-branch-protection-lto.c diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 374595edd2ce4a..5f6f5bbba8e56a 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -32,7 +32,9 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/St
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
DanielKristofKiss wrote: #83154 merged into this one as no test would pass without that. todo: update #83153 with the new semantic. #84494 and #84804 to be merged into 1 PR and add support this semantic. https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss updated https://github.com/llvm/llvm-project/pull/82819 >From 5973486010ffe387789e8129d53a2b9d0cc4ca69 Mon Sep 17 00:00:00 2001 From: Daniel Kiss Date: Mon, 22 Jan 2024 11:33:15 +0100 Subject: [PATCH 1/2] Emit attributes for functions always. Branch protection, sign return address, guarded control stack flags are only emitted as module flags if not specified per function. The inliner might inline functions with different set of flags as it doesn't see the flags. In case of LTO build the module flags get merged with the `min` rule which means if one of the modules is not build with PAC/BTI then the features will be turned off on all functions due to the functions takes the branch-protection and sign-return-address features from the module flags. The sign-return-address is function level option therefore it is expected functions from files that are compiled with -mbranch-protection=pac-ret to be protected but in LTO case this might not happen. This patch adds the flags to functions in case of an LTO build therefore they don't need to rely on the module flag. --- clang/include/clang/Basic/TargetInfo.h| 44 +-- clang/lib/CodeGen/Targets/AArch64.cpp | 43 ++ clang/lib/CodeGen/Targets/ARM.cpp | 8 ++-- .../CodeGen/aarch64-branch-protection-attr.c | 26 +-- .../CodeGen/aarch64-sign-return-address.c | 12 +++-- clang/test/CodeGen/aarch64-targetattr.c | 2 +- .../CodeGen/arm-branch-protection-attr-1.c| 12 ++--- .../CodeGen/arm-branch-protection-attr-2.c| 13 -- .../test/Frontend/arm-branch-protection-lto.c | 22 ++ .../SelectionDAG/SelectionDAGBuilder.cpp | 12 + llvm/lib/IR/Verifier.cpp | 21 - llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +-- .../AArch64/AArch64MachineFunctionInfo.cpp| 39 +++- .../lib/Target/ARM/ARMMachineFunctionInfo.cpp | 22 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 6 ++- ...ranch-target-enforcement-indirect-calls.ll | 18 .../CodeGen/AArch64/bti-branch-relaxation.ll | 2 +- llvm/test/CodeGen/AArch64/kcfi-bti.ll | 7 +-- ...machine-outliner-2fixup-blr-terminator.mir | 2 +- .../CodeGen/AArch64/machine-outliner-bti.mir | 2 +- .../AArch64/machine-outliner-outline-bti.ll | 4 +- .../AArch64/note-gnu-property-pac-bti-0.ll| 2 +- .../AArch64/note-gnu-property-pac-bti-4.ll| 4 +- .../AArch64/pacbti-llvm-generated-funcs-1.ll | 4 +- .../AArch64/pacbti-llvm-generated-funcs-2.ll | 4 +- .../CodeGen/AArch64/pacbti-module-attrs.ll| 12 ++--- .../AArch64/patchable-function-entry-bti.ll | 10 ++--- .../CodeGen/AArch64/setjmp-bti-outliner.ll| 15 +++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 6 +-- .../AArch64/sign-return-address-pauth-lr.ll | 36 +++ .../CodeGen/AArch64/sign-return-address.ll| 8 ++-- llvm/test/CodeGen/AArch64/wineh-bti.ll| 7 +-- llvm/test/CodeGen/AArch64/wineh-pac.ll| 7 +-- llvm/test/CodeGen/ARM/setjmp-bti-basic.ll | 5 +-- llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll | 7 +-- llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll | 7 +-- .../CodeGen/Thumb2/bti-indirect-branches.ll | 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-1.ll| 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-2.ll| 12 ++--- .../CodeGen/Thumb2/bti-outliner-cost-2.ll | 6 +-- .../test/CodeGen/Thumb2/bti-pac-replace-1.mir | 8 +--- llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll | 7 +-- llvm/test/CodeGen/Thumb2/jump-table-bti.ll| 10 ++--- llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll| 6 +-- .../Thumb2/pacbti-m-indirect-tail-call.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-3.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 6 +-- .../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-overalign.ll | 2 +- .../test/CodeGen/Thumb2/pacbti-m-stack-arg.ll | 4 +- .../Thumb2/pacbti-m-unsupported-arch.ll | 8 +--- .../test/CodeGen/Thumb2/pacbti-m-varargs-1.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-varargs-2.ll | 4 +- llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 2 +- .../AArch64/link-branch-target-enforcement.ll | 2 +- .../Inline/inline-sign-return-address.ll | 13 +++--- .../LowerTypeTests/function-arm-thumb.ll | 2 +- .../LowerTypeTests/function-thumb-bti.ll | 4 +- .../Transforms/LowerTypeTests/function.ll | 4 +- 60 files changed, 277 insertions(+), 312 deletions(-) create mode 100644 clang/test/Frontend/arm-branch-protection-lto.c diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 374595edd2ce4a..5f6f5bbba8e56a 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -32,7 +32,9 @@ #include "llvm/ADT/StringRef.h" #include "llvm/AD
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss edited https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -2314,7 +2314,7 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
if (auto A = Attrs.getFnAttr("sign-return-address"); A.isValid()) {
StringRef S = A.getValueAsString();
-if (S != "none" && S != "all" && S != "non-leaf")
DanielKristofKiss wrote:
This isn't right, to support\import the old format the old values and nothing
need to accepted here.
https://github.com/llvm/llvm-project/pull/82819
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[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss updated https://github.com/llvm/llvm-project/pull/82819 >From 28e7b4e10208991790f0c7b1e225831714a47572 Mon Sep 17 00:00:00 2001 From: Daniel Kiss Date: Mon, 22 Jan 2024 11:33:15 +0100 Subject: [PATCH] Emit attributes for functions always. Branch protection, sign return address, guarded control stack flags are only emitted as module flags if not specified per function. The inliner might inline functions with different set of flags as it doesn't see the flags. In case of LTO build the module flags get merged with the `min` rule which means if one of the modules is not build with PAC/BTI then the features will be turned off on all functions due to the functions takes the branch-protection and sign-return-address features from the module flags. The sign-return-address is function level option therefore it is expected functions from files that are compiled with -mbranch-protection=pac-ret to be protected but in LTO case this might not happen. This patch adds the flags to functions in case of an LTO build therefore they don't need to rely on the module flag. --- clang/include/clang/Basic/TargetInfo.h| 44 +-- clang/lib/CodeGen/Targets/AArch64.cpp | 43 ++ clang/lib/CodeGen/Targets/ARM.cpp | 8 ++-- .../CodeGen/aarch64-branch-protection-attr.c | 26 +-- .../CodeGen/aarch64-sign-return-address.c | 12 +++-- clang/test/CodeGen/aarch64-targetattr.c | 2 +- .../CodeGen/arm-branch-protection-attr-1.c| 12 ++--- .../CodeGen/arm-branch-protection-attr-2.c| 13 -- .../test/Frontend/arm-branch-protection-lto.c | 22 ++ .../SelectionDAG/SelectionDAGBuilder.cpp | 12 + llvm/lib/IR/Verifier.cpp | 20 - llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +-- .../AArch64/AArch64MachineFunctionInfo.cpp| 37 ++-- .../lib/Target/ARM/ARMMachineFunctionInfo.cpp | 22 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 6 ++- ...ranch-target-enforcement-indirect-calls.ll | 18 .../CodeGen/AArch64/bti-branch-relaxation.ll | 2 +- llvm/test/CodeGen/AArch64/kcfi-bti.ll | 7 +-- ...machine-outliner-2fixup-blr-terminator.mir | 2 +- .../CodeGen/AArch64/machine-outliner-bti.mir | 2 +- .../AArch64/machine-outliner-outline-bti.ll | 4 +- .../AArch64/note-gnu-property-pac-bti-0.ll| 2 +- .../AArch64/note-gnu-property-pac-bti-4.ll| 4 +- .../AArch64/pacbti-llvm-generated-funcs-1.ll | 4 +- .../AArch64/pacbti-llvm-generated-funcs-2.ll | 4 +- .../CodeGen/AArch64/pacbti-module-attrs.ll| 12 ++--- .../AArch64/patchable-function-entry-bti.ll | 10 ++--- .../CodeGen/AArch64/setjmp-bti-outliner.ll| 15 +++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 6 +-- .../AArch64/sign-return-address-pauth-lr.ll | 36 +++ .../CodeGen/AArch64/sign-return-address.ll| 8 ++-- llvm/test/CodeGen/AArch64/wineh-bti.ll| 7 +-- llvm/test/CodeGen/AArch64/wineh-pac.ll| 7 +-- llvm/test/CodeGen/ARM/setjmp-bti-basic.ll | 5 +-- llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll | 7 +-- llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll | 7 +-- .../CodeGen/Thumb2/bti-indirect-branches.ll | 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-1.ll| 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-2.ll| 12 ++--- .../CodeGen/Thumb2/bti-outliner-cost-2.ll | 6 +-- .../test/CodeGen/Thumb2/bti-pac-replace-1.mir | 8 +--- llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll | 7 +-- llvm/test/CodeGen/Thumb2/jump-table-bti.ll| 10 ++--- llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll| 6 +-- .../Thumb2/pacbti-m-indirect-tail-call.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-3.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 6 +-- .../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-overalign.ll | 2 +- .../test/CodeGen/Thumb2/pacbti-m-stack-arg.ll | 4 +- .../Thumb2/pacbti-m-unsupported-arch.ll | 8 +--- .../test/CodeGen/Thumb2/pacbti-m-varargs-1.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-varargs-2.ll | 4 +- llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 2 +- .../AArch64/link-branch-target-enforcement.ll | 2 +- .../Inline/inline-sign-return-address.ll | 13 +++--- .../LowerTypeTests/function-arm-thumb.ll | 2 +- .../LowerTypeTests/function-thumb-bti.ll | 4 +- .../Transforms/LowerTypeTests/function.ll | 4 +- llvm/test/Verifier/branch-prot-attrs.ll | 7 ++- 61 files changed, 281 insertions(+), 312 deletions(-) create mode 100644 clang/test/Frontend/arm-branch-protection-lto.c diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 374595edd2ce4a..5f6f5bbba8e56a 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -32,7 +32,9 @@
[clang] [lld] [llvm] [ARM][AArch64] BTI,GCS,PAC Module flag update. (PR #86212)
https://github.com/DanielKristofKiss created
https://github.com/llvm/llvm-project/pull/86212
Module flag is used to indicate the feature to be propagated to the function.
As now the frontend emits all attributes accordingly let's help the auto
upgrade to only do work when old and new bitcodes are merged.
Depends on #82819 and #86031
>From 33d8277d188f82847d914273be2379151dd33d41 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 8 Mar 2024 15:06:28 +0100
Subject: [PATCH] BTI,GCS,PAC Module flag update.
Module flag is used to indicate the feature to be propagated to the
function. As now the frontend emits all attributes accoringly let's
help the automerger to only do work when old and new bitcodes are
merged.
Autoupgrade function attributes from Module attributes when needed.
---
clang/lib/CodeGen/CodeGenModule.cpp | 19 ++--
.../CodeGen/aarch64-sign-return-address.c | 12 +--
.../CodeGen/arm-branch-protection-attr-2.c| 8 +-
.../arm-ignore-branch-protection-option.c | 2 +-
lld/test/ELF/lto/aarch64_inline.ll| 73 +
llvm/include/llvm/IR/AutoUpgrade.h| 3 +
llvm/lib/AsmParser/LLParser.cpp | 1 +
llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +
llvm/lib/IR/AutoUpgrade.cpp | 100 +
llvm/lib/Linker/IRMover.cpp | 10 ++
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 +-
llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 2 +-
.../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 2 +-
llvm/test/LTO/AArch64/Inputs/foo.ll | 16 ---
llvm/test/LTO/AArch64/TestInputs/bar.ll | 35 ++
llvm/test/LTO/AArch64/TestInputs/foo.ll | 38 +++
llvm/test/LTO/AArch64/TestInputs/old.ll | 46
.../AArch64/link-branch-target-enforcement.ll | 5 +-
.../LTO/AArch64/link-sign-return-address.ll | 102 ++
llvm/test/Linker/link-arm-and-thumb.ll| 6 +-
20 files changed, 444 insertions(+), 40 deletions(-)
create mode 100644 lld/test/ELF/lto/aarch64_inline.ll
delete mode 100644 llvm/test/LTO/AArch64/Inputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/bar.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/old.ll
create mode 100644 llvm/test/LTO/AArch64/link-sign-return-address.ll
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index cb153066b28dd1..1acc0510256268 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1173,22 +1173,29 @@ void CodeGenModule::Release() {
"tag-stack-memory-buildattr", 1);
if (T.isARM() || T.isThumb() || T.isAArch64()) {
+// Previously 1 is used and meant for the backed to derive the function
+// attribute form it. 2 now means function attributes already set for all
+// functions in this module, so no need to propagate those from the module
+// flag. Value is only used in case of LTO module merge because the backend
+// will see all required function attribute set already. Value is used
+// before modules got merged. Any posive value means the feature is active
+// and required binary markings need to be emit accordingly.
if (LangOpts.BranchTargetEnforcement)
getModule().addModuleFlag(llvm::Module::Min, "branch-target-enforcement",
-1);
+2);
if (LangOpts.BranchProtectionPAuthLR)
getModule().addModuleFlag(llvm::Module::Min,
"branch-protection-pauth-lr",
-1);
+2);
if (LangOpts.GuardedControlStack)
- getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 2);
if (LangOpts.hasSignReturnAddress())
- getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 2);
if (LangOpts.isSignReturnAddressScopeAll())
getModule().addModuleFlag(llvm::Module::Min, "sign-return-address-all",
-1);
+2);
if (!LangOpts.isSignReturnAddressWithAKey())
getModule().addModuleFlag(llvm::Module::Min,
-"sign-return-address-with-bkey", 1);
+"sign-return-address-with-bkey", 2);
}
if (CodeGenOpts.StackClashProtector)
diff --git a/clang/test/CodeGen/aarch64-sign-return-address.c
b/clang/test/CodeGen/aarch64-sign-return-address.c
index 8bc54b1a56c38c..35c56889e07071 100644
--- a/clang/test/CodeGen/aarch64-sign-return-address.c
+++ b/clang/test/CodeGen/aarch64-sign-return-address.c
@@ -22,17 +22,17 @@
// NONE-NOT: !"branch-target-enforcement"
// ALL-NOT: !"branch-target-enforcement"
// PAR
[clang] [lld] [llvm] [ARM][AArch64] Change module flags values. (PR #84804)
https://github.com/DanielKristofKiss closed https://github.com/llvm/llvm-project/pull/84804 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
DanielKristofKiss wrote: #86212 Deals with the import of the "true"/"false" values in the attributes. https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [ARM][AArch64] Change module flags values. (PR #84804)
DanielKristofKiss wrote: superseded by #86212 https://github.com/llvm/llvm-project/pull/84804 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [ARM][AArch64] BTI,GCS,PAC Module flag update. (PR #86212)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/86212
>From 33d8277d188f82847d914273be2379151dd33d41 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 8 Mar 2024 15:06:28 +0100
Subject: [PATCH 1/2] BTI,GCS,PAC Module flag update.
Module flag is used to indicate the feature to be propagated to the
function. As now the frontend emits all attributes accoringly let's
help the automerger to only do work when old and new bitcodes are
merged.
Autoupgrade function attributes from Module attributes when needed.
---
clang/lib/CodeGen/CodeGenModule.cpp | 19 ++--
.../CodeGen/aarch64-sign-return-address.c | 12 +--
.../CodeGen/arm-branch-protection-attr-2.c| 8 +-
.../arm-ignore-branch-protection-option.c | 2 +-
lld/test/ELF/lto/aarch64_inline.ll| 73 +
llvm/include/llvm/IR/AutoUpgrade.h| 3 +
llvm/lib/AsmParser/LLParser.cpp | 1 +
llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +
llvm/lib/IR/AutoUpgrade.cpp | 100 +
llvm/lib/Linker/IRMover.cpp | 10 ++
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 +-
llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 2 +-
.../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 2 +-
llvm/test/LTO/AArch64/Inputs/foo.ll | 16 ---
llvm/test/LTO/AArch64/TestInputs/bar.ll | 35 ++
llvm/test/LTO/AArch64/TestInputs/foo.ll | 38 +++
llvm/test/LTO/AArch64/TestInputs/old.ll | 46
.../AArch64/link-branch-target-enforcement.ll | 5 +-
.../LTO/AArch64/link-sign-return-address.ll | 102 ++
llvm/test/Linker/link-arm-and-thumb.ll| 6 +-
20 files changed, 444 insertions(+), 40 deletions(-)
create mode 100644 lld/test/ELF/lto/aarch64_inline.ll
delete mode 100644 llvm/test/LTO/AArch64/Inputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/bar.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/old.ll
create mode 100644 llvm/test/LTO/AArch64/link-sign-return-address.ll
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index cb153066b28dd1..1acc0510256268 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1173,22 +1173,29 @@ void CodeGenModule::Release() {
"tag-stack-memory-buildattr", 1);
if (T.isARM() || T.isThumb() || T.isAArch64()) {
+// Previously 1 is used and meant for the backed to derive the function
+// attribute form it. 2 now means function attributes already set for all
+// functions in this module, so no need to propagate those from the module
+// flag. Value is only used in case of LTO module merge because the backend
+// will see all required function attribute set already. Value is used
+// before modules got merged. Any posive value means the feature is active
+// and required binary markings need to be emit accordingly.
if (LangOpts.BranchTargetEnforcement)
getModule().addModuleFlag(llvm::Module::Min, "branch-target-enforcement",
-1);
+2);
if (LangOpts.BranchProtectionPAuthLR)
getModule().addModuleFlag(llvm::Module::Min,
"branch-protection-pauth-lr",
-1);
+2);
if (LangOpts.GuardedControlStack)
- getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 2);
if (LangOpts.hasSignReturnAddress())
- getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 2);
if (LangOpts.isSignReturnAddressScopeAll())
getModule().addModuleFlag(llvm::Module::Min, "sign-return-address-all",
-1);
+2);
if (!LangOpts.isSignReturnAddressWithAKey())
getModule().addModuleFlag(llvm::Module::Min,
-"sign-return-address-with-bkey", 1);
+"sign-return-address-with-bkey", 2);
}
if (CodeGenOpts.StackClashProtector)
diff --git a/clang/test/CodeGen/aarch64-sign-return-address.c
b/clang/test/CodeGen/aarch64-sign-return-address.c
index 8bc54b1a56c38c..35c56889e07071 100644
--- a/clang/test/CodeGen/aarch64-sign-return-address.c
+++ b/clang/test/CodeGen/aarch64-sign-return-address.c
@@ -22,17 +22,17 @@
// NONE-NOT: !"branch-target-enforcement"
// ALL-NOT: !"branch-target-enforcement"
// PART-NOT: !"branch-target-enforcement"
-// BTE: !{i32 8, !"branch-target-enforcement", i32 1}
+// BTE: !{i32 8, !"branch-target-enforcement", i32 2}
// B-KEY-NOT: !"branch-target-enforcement"
// NONE-NOT: !"sign-return-address"
[clang] AArch64: add __builtin_arm_trap (PR #85054)
https://github.com/DanielKristofKiss approved this pull request. Maybe a line or two in the `clang/docs/LanguageExtensions.rst` would be useful. https://github.com/llvm/llvm-project/pull/85054 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV] Emit the resolver along with the default version definition. (PR #84405)
DanielKristofKiss wrote:
I'd like to support FMV in existing codebases as lean as possible, so the
default version attribute would be optional to write as not all
version/toolchain will support it. smallest possible codebase change to
introduce multi versioning:
```c
int foo(void);
+ #ifdef __HAVE_FUNCTION_MULTI_VERSIONING
+ int __attribute__((target_version("feature"))) foo(void);
+ #endif
```
https://github.com/llvm/llvm-project/pull/84405
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[clang] [lld] [llvm] [ARM][AArch64] Change module flags values. (PR #84804)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/84804
>From e0596b2e216c041cfeb63faa8cf6d31a2601934f Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 8 Mar 2024 15:06:28 +0100
Subject: [PATCH 1/2] [LLVM] Autoupgrade function attributes from Module
attributes.
Refactoring #82763 to cache module attributes.
---
lld/test/ELF/lto/aarch64_inline.ll| 51 +++
llvm/include/llvm/IR/AutoUpgrade.h| 3 ++
llvm/lib/IR/AutoUpgrade.cpp | 47 +
llvm/lib/Linker/IRMover.cpp | 10
.../AArch64/link-branch-target-enforcement.ll | 3 ++
.../LTO/AArch64/link-sign-return-address.ll | 43
llvm/test/Linker/link-arm-and-thumb.ll| 6 +--
7 files changed, 160 insertions(+), 3 deletions(-)
create mode 100644 lld/test/ELF/lto/aarch64_inline.ll
create mode 100644 llvm/test/LTO/AArch64/link-sign-return-address.ll
diff --git a/lld/test/ELF/lto/aarch64_inline.ll
b/lld/test/ELF/lto/aarch64_inline.ll
new file mode 100644
index 00..781c283bc56a3e
--- /dev/null
+++ b/lld/test/ELF/lto/aarch64_inline.ll
@@ -0,0 +1,51 @@
+; REQUIRES: aarch64
+;; Test verifies inlining happens cross module when module flags are upgraded
+;; by the thin-lto linker/IRMover.
+;; Regression test for #82763
+
+; RUN: split-file %s %t
+; RUN: opt -thinlto-bc -thinlto-split-lto-unit -unified-lto %t/foo.s -o
%t/foo.o
+; RUN: opt -thinlto-bc -thinlto-split-lto-unit -unified-lto %t/main.s -o
%t/main.o
+; RUN: ld.lld -O2 --lto=thin --entry=main %t/main.o %t/foo.o -o %t/exe
+; RUN: llvm-objdump -d %t/exe | FileCheck %s
+
+
+; CHECK-LABEL: :
+; CHECK-NEXT: pacibsp
+; CHECK-NEXT: mov w0, #0x22
+; CHECK-NEXT: autibsp
+; CHECK-NEXT: ret
+
+;--- foo.s
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define dso_local noundef i32 @foo() local_unnamed_addr #0 {
+entry:
+ ret i32 34
+}
+
+attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn
memory(none) }
+!llvm.module.flags = !{!0, !1, !2, !3 }
+!0 = !{i32 8, !"branch-target-enforcement", i32 1}
+!1 = !{i32 8, !"sign-return-address", i32 1}
+!2 = !{i32 8, !"sign-return-address-all", i32 1}
+!3 = !{i32 8, !"sign-return-address-with-bkey", i32 1}
+
+;--- main.s
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+declare i32 @foo();
+
+define i32 @main() {
+entry:
+ %1 = call i32 @foo()
+ ret i32 %1
+}
+
+!llvm.module.flags = !{!0, !1, !2, !3 }
+!0 = !{i32 8, !"branch-target-enforcement", i32 1}
+!1 = !{i32 8, !"sign-return-address", i32 1}
+!2 = !{i32 8, !"sign-return-address-all", i32 1}
+!3 = !{i32 8, !"sign-return-address-with-bkey", i32 1}
diff --git a/llvm/include/llvm/IR/AutoUpgrade.h
b/llvm/include/llvm/IR/AutoUpgrade.h
index 152f781ffa9b30..1ef32bcb121bec 100644
--- a/llvm/include/llvm/IR/AutoUpgrade.h
+++ b/llvm/include/llvm/IR/AutoUpgrade.h
@@ -88,6 +88,9 @@ namespace llvm {
/// info. Return true if module is modified.
bool UpgradeDebugInfo(Module &M);
+ /// Copies module attributes to the functions in the module.
+ void CopyModuleAttrToFunctions(Module &M);
+
/// Check whether a string looks like an old loop attachment tag.
inline bool mayBeOldLoopAttachmentTag(StringRef Name) {
return Name.starts_with("llvm.vectorizer.");
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index be0abb4b71dae2..ed7699c113584b 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -5178,6 +5178,53 @@ void llvm::UpgradeFunctionAttributes(Function &F) {
Arg.removeAttrs(AttributeFuncs::typeIncompatible(Arg.getType()));
}
+// Check if the module attribute is present and not zero.
+static bool isModuleAttributeSet(Module &M, const StringRef &ModAttr) {
+ const auto *Attr =
+ mdconst::extract_or_null(M.getModuleFlag(ModAttr));
+ return Attr && !Attr->isZero();
+}
+
+// Check if the function attribute is not present and set it.
+static void SetFunctionAttrIfNotSet(Function &F, StringRef FnAttrName,
+StringRef Value) {
+ if (!F.hasFnAttribute(FnAttrName))
+F.addFnAttr(FnAttrName, Value);
+}
+
+void llvm::CopyModuleAttrToFunctions(Module &M) {
+ Triple T(M.getTargetTriple());
+ if (!T.isThumb() && !T.isARM() && !T.isAArch64())
+return;
+
+ StringRef SignTypeValue = "none";
+ if (isModuleAttributeSet(M, "sign-return-address-all"))
+SignTypeValue = "all";
+ else if (isModuleAttributeSet(M, "sign-return-address"))
+SignTypeValue = "non-leaf";
+
+ StringRef BTEValue =
+ isModuleAttributeSet(M, "branch-target-enforcement") ? "true" : "false";
+ StringRef BPPLValue =
+ isModuleAttributeSet(M, "branch-protection-pauth-lr") ? "true" : "false";
+ StringRef GCSValue =
+ isModuleAttributeSet(M, "guarded-control-st
[clang] [FMV][AArch64] Don't optimize backward compatible features in resolver. (PR #90928)
https://github.com/DanielKristofKiss approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90928 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -22,4 +22,9 @@ attributes #1 = {
; CHECK: invalid value for 'sign-return-address-key' attribute: B_Key
"sign-return-address-key"="B_Key"
; CHECK: invalid value for 'branch-target-enforcement' attribute: True
- "branch-target-enforcement"="True" }
+ "branch-target-enforcement"="True"
+; CHECK: invalid value for 'branch-protection-pauth-lr' attribute: Yes
+ "branch-protection-pauth-lr"="Yes"
+; CHECK: invalid value for 'guarded-control-stack' attribute: True
+ "guarded-control-stack"="True"
+ }
DanielKristofKiss wrote:
ack
https://github.com/llvm/llvm-project/pull/82819
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[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -0,0 +1,22 @@
+// REQUIRES: arm-registered-target
+
+// RUN: %clang_cc1 -triple=thumbv7m-unknown-unknown-eabi
-msign-return-address=non-leaf %s -S -emit-llvm -o - 2>&1 | FileCheck %s
--check-prefix=CHECK --check-prefix=SIGN
+// RUN: %clang_cc1 -triple=thumbv7m-unknown-unknown-eabi
-mbranch-target-enforce %s -S -emit-llvm -o - 2>&1 | FileCheck %s
--check-prefix=CHECK --check-prefix=BTE
+// RUN: %clang_cc1 -triple=thumbv7m-unknown-unknown-eabi
-mbranch-target-enforce -msign-return-address=all %s -S -emit-llvm -o - 2>&1 |
FileCheck %s --check-prefix=CHECK --check-prefix=ALL
+
+// RUN: %clang_cc1 -flto -triple=thumbv7m-unknown-unknown-eabi
-msign-return-address=non-leaf %s -S -emit-llvm -o - 2>&1 | FileCheck %s
--check-prefix=CHECK --check-prefix=SIGN
+// RUN: %clang_cc1 -flto -triple=thumbv7m-unknown-unknown-eabi
-mbranch-target-enforce %s -S -emit-llvm -o - 2>&1 | FileCheck %s
--check-prefix=CHECK --check-prefix=BTE
+// RUN: %clang_cc1 -flto -triple=thumbv7m-unknown-unknown-eabi
-mbranch-target-enforce -msign-return-address=all %s -S -emit-llvm -o - 2>&1 |
FileCheck %s --check-prefix=CHECK --check-prefix=ALL
+
+// RUN: %clang_cc1 -flto=thin -triple=thumbv7m-unknown-unknown-eabi
-msign-return-address=non-leaf %s -S -emit-llvm -o - 2>&1 | FileCheck %s
--check-prefix=CHECK --check-prefix=SIGN
+// RUN: %clang_cc1 -flto=thin -triple=thumbv7m-unknown-unknown-eabi
-mbranch-target-enforce %s -S -emit-llvm -o - 2>&1 | FileCheck %s
--check-prefix=CHECK --check-prefix=BTE
+// RUN: %clang_cc1 -flto=thin -triple=thumbv7m-unknown-unknown-eabi
-mbranch-target-enforce -msign-return-address=all %s -S -emit-llvm -o - 2>&1 |
FileCheck %s --check-prefix=CHECK --check-prefix=ALL
+
+void foo() {}
+
+// Check there are branch protection function attributes.
+// CHECK-LABEL: @foo() #[[#ATTR:]]
+
+// SIGN: attributes #[[#ATTR]] = { {{.*}} "sign-return-address"="non-leaf"
+// BTE: attributes #[[#ATTR]] = { {{.*}} "branch-target-enforcement"
+// ALL: attributes #[[#ATTR]] = { {{.*}} "branch-target-enforcement"{{.*}}
"sign-return-address"="all"
DanielKristofKiss wrote:
ack
https://github.com/llvm/llvm-project/pull/82819
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[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -2323,15 +2323,33 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
if (S != "a_key" && S != "b_key")
CheckFailed("invalid value for 'sign-return-address-key' attribute: " +
S,
V);
+if (auto AA = Attrs.getFnAttr("sign-return-address"); !AA.isValid()) {
+ CheckFailed("invalid value for 'sign-return-address-key' present without
"
+ "sign-return-address ");
+}
}
if (auto A = Attrs.getFnAttr("branch-target-enforcement"); A.isValid()) {
StringRef S = A.getValueAsString();
-if (S != "true" && S != "false")
+if (S != "" && S != "true" && S != "false")
DanielKristofKiss wrote:
Unfortunately yes, people mixing up pre_build objects from different versions
of the compiler.
If they IR would contain a toolchain major version that would make life simpler
( note the auto upgrade pass in the IRMover)
https://github.com/llvm/llvm-project/pull/82819
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[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -2323,15 +2323,33 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
if (S != "a_key" && S != "b_key")
CheckFailed("invalid value for 'sign-return-address-key' attribute: " +
S,
V);
+if (auto AA = Attrs.getFnAttr("sign-return-address"); !AA.isValid()) {
+ CheckFailed("invalid value for 'sign-return-address-key' present without
"
+ "sign-return-address ");
DanielKristofKiss wrote:
ack
https://github.com/llvm/llvm-project/pull/82819
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[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -58,8 +58,8 @@ entry:
;; CHECK-NEXT: .cfi_negate_ra_state
attributes #0 = { norecurse nounwind readnone "sign-return-address"="all"
"sign-return-address-key"="b_key" }
-attributes #1 = { noinline }
-attributes #2 = { nofree noinline norecurse nounwind writeonly }
+attributes #1 = { noinline "sign-return-address"="all"
"sign-return-address-key"="b_key" }
+attributes #2 = { nofree noinline norecurse nounwind writeonly
"sign-return-address"="all" "sign-return-address-key"="b_key" }
DanielKristofKiss wrote:
Module flags do nothing from here, I dropped them from the test.
The fronted will append these attributes as the generated functions created
see: #83153
https://github.com/llvm/llvm-project/pull/82819
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[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss updated https://github.com/llvm/llvm-project/pull/82819 >From b6e063f335b41a5fd924d0c630c615cec32bd528 Mon Sep 17 00:00:00 2001 From: Daniel Kiss Date: Mon, 22 Jan 2024 11:33:15 +0100 Subject: [PATCH] Emit attributes for functions always. Branch protection, sign return address, guarded control stack flags are only emitted as module flags if not specified per function. The inliner might inline functions with different set of flags as it doesn't see the flags. In case of LTO build the module flags get merged with the `min` rule which means if one of the modules is not build with PAC/BTI then the features will be turned off on all functions due to the functions takes the branch-protection and sign-return-address features from the module flags. The sign-return-address is function level option therefore it is expected functions from files that are compiled with -mbranch-protection=pac-ret to be protected but in LTO case this might not happen. This patch adds the flags to functions in case of an LTO build therefore they don't need to rely on the module flag. --- clang/include/clang/Basic/TargetInfo.h| 44 +-- clang/lib/CodeGen/Targets/AArch64.cpp | 43 ++ clang/lib/CodeGen/Targets/ARM.cpp | 8 ++-- .../CodeGen/aarch64-branch-protection-attr.c | 26 +-- .../CodeGen/aarch64-sign-return-address.c | 12 +++-- clang/test/CodeGen/aarch64-targetattr.c | 2 +- .../CodeGen/arm-branch-protection-attr-1.c| 12 ++--- .../CodeGen/arm-branch-protection-attr-2.c| 13 -- .../test/Frontend/arm-branch-protection-lto.c | 24 ++ .../SelectionDAG/SelectionDAGBuilder.cpp | 12 + llvm/lib/IR/Verifier.cpp | 19 +++- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +-- .../AArch64/AArch64MachineFunctionInfo.cpp| 37 ++-- .../lib/Target/ARM/ARMMachineFunctionInfo.cpp | 22 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 6 ++- ...ranch-target-enforcement-indirect-calls.ll | 18 .../CodeGen/AArch64/bti-branch-relaxation.ll | 2 +- llvm/test/CodeGen/AArch64/kcfi-bti.ll | 7 +-- ...machine-outliner-2fixup-blr-terminator.mir | 2 +- .../CodeGen/AArch64/machine-outliner-bti.mir | 2 +- .../AArch64/machine-outliner-outline-bti.ll | 4 +- .../AArch64/note-gnu-property-pac-bti-0.ll| 2 +- .../AArch64/note-gnu-property-pac-bti-4.ll| 4 +- .../AArch64/pacbti-llvm-generated-funcs-1.ll | 4 +- .../AArch64/pacbti-llvm-generated-funcs-2.ll | 10 ++--- .../CodeGen/AArch64/pacbti-module-attrs.ll| 12 ++--- .../AArch64/patchable-function-entry-bti.ll | 10 ++--- .../CodeGen/AArch64/setjmp-bti-outliner.ll| 15 +++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 6 +-- .../AArch64/sign-return-address-pauth-lr.ll | 36 +++ .../CodeGen/AArch64/sign-return-address.ll| 8 ++-- llvm/test/CodeGen/AArch64/wineh-bti.ll| 7 +-- llvm/test/CodeGen/AArch64/wineh-pac.ll| 7 +-- llvm/test/CodeGen/ARM/setjmp-bti-basic.ll | 5 +-- llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll | 7 +-- llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll | 7 +-- .../CodeGen/Thumb2/bti-indirect-branches.ll | 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-1.ll| 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-2.ll| 12 ++--- .../CodeGen/Thumb2/bti-outliner-cost-2.ll | 6 +-- .../test/CodeGen/Thumb2/bti-pac-replace-1.mir | 8 +--- llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll | 7 +-- llvm/test/CodeGen/Thumb2/jump-table-bti.ll| 10 ++--- llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll| 6 +-- .../Thumb2/pacbti-m-indirect-tail-call.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-3.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 6 +-- .../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-overalign.ll | 2 +- .../test/CodeGen/Thumb2/pacbti-m-stack-arg.ll | 4 +- .../Thumb2/pacbti-m-unsupported-arch.ll | 8 +--- .../test/CodeGen/Thumb2/pacbti-m-varargs-1.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-varargs-2.ll | 4 +- llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 2 +- .../AArch64/link-branch-target-enforcement.ll | 2 +- .../Inline/inline-sign-return-address.ll | 13 +++--- .../LowerTypeTests/function-arm-thumb.ll | 2 +- .../LowerTypeTests/function-thumb-bti.ll | 4 +- .../Transforms/LowerTypeTests/function.ll | 4 +- llvm/test/Verifier/branch-prot-attrs.ll | 16 ++- 61 files changed, 292 insertions(+), 317 deletions(-) create mode 100644 clang/test/Frontend/arm-branch-protection-lto.c diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 8a6511b9ced83..fde6e6315da5c 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -32,7 +32,
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss edited https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss updated https://github.com/llvm/llvm-project/pull/82819 >From f459bf1714936e008f548b767cf099872a570260 Mon Sep 17 00:00:00 2001 From: Daniel Kiss Date: Mon, 22 Jan 2024 11:33:15 +0100 Subject: [PATCH] Emit attributes for functions always. Branch protection, sign return address, guarded control stack flags are only emitted as module flags if not specified per function. The inliner might inline functions with different set of flags as it doesn't see the flags. In case of LTO build the module flags get merged with the `min` rule which means if one of the modules is not build with PAC/BTI then the features will be turned off on all functions due to the functions takes the branch-protection and sign-return-address features from the module flags. The sign-return-address is function level option therefore it is expected functions from files that are compiled with -mbranch-protection=pac-ret to be protected but in LTO case this might not happen. This patch adds the flags to functions in case of an LTO build therefore they don't need to rely on the module flag. --- clang/include/clang/Basic/TargetInfo.h| 44 +-- clang/lib/CodeGen/Targets/AArch64.cpp | 43 ++ clang/lib/CodeGen/Targets/ARM.cpp | 8 ++-- .../CodeGen/aarch64-branch-protection-attr.c | 26 +-- .../CodeGen/aarch64-sign-return-address.c | 12 +++-- clang/test/CodeGen/aarch64-targetattr.c | 2 +- .../CodeGen/arm-branch-protection-attr-1.c| 12 ++--- .../CodeGen/arm-branch-protection-attr-2.c| 13 -- .../test/Frontend/arm-branch-protection-lto.c | 24 ++ .../SelectionDAG/SelectionDAGBuilder.cpp | 12 + llvm/lib/IR/Verifier.cpp | 20 - llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +-- .../AArch64/AArch64MachineFunctionInfo.cpp| 37 ++-- .../lib/Target/ARM/ARMMachineFunctionInfo.cpp | 22 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 6 ++- ...ranch-target-enforcement-indirect-calls.ll | 18 .../CodeGen/AArch64/bti-branch-relaxation.ll | 2 +- llvm/test/CodeGen/AArch64/kcfi-bti.ll | 7 +-- ...machine-outliner-2fixup-blr-terminator.mir | 2 +- .../CodeGen/AArch64/machine-outliner-bti.mir | 2 +- .../AArch64/machine-outliner-outline-bti.ll | 4 +- .../AArch64/note-gnu-property-pac-bti-0.ll| 2 +- .../AArch64/note-gnu-property-pac-bti-4.ll| 4 +- .../AArch64/pacbti-llvm-generated-funcs-1.ll | 4 +- .../AArch64/pacbti-llvm-generated-funcs-2.ll | 10 ++--- .../CodeGen/AArch64/pacbti-module-attrs.ll| 12 ++--- .../AArch64/patchable-function-entry-bti.ll | 10 ++--- .../CodeGen/AArch64/setjmp-bti-outliner.ll| 15 +++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 6 +-- .../AArch64/sign-return-address-pauth-lr.ll | 36 +++ .../CodeGen/AArch64/sign-return-address.ll| 8 ++-- llvm/test/CodeGen/AArch64/wineh-bti.ll| 7 +-- llvm/test/CodeGen/AArch64/wineh-pac.ll| 7 +-- llvm/test/CodeGen/ARM/setjmp-bti-basic.ll | 5 +-- llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll | 7 +-- llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll | 7 +-- .../CodeGen/Thumb2/bti-indirect-branches.ll | 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-1.ll| 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-2.ll| 12 ++--- .../CodeGen/Thumb2/bti-outliner-cost-2.ll | 6 +-- .../test/CodeGen/Thumb2/bti-pac-replace-1.mir | 8 +--- llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll | 7 +-- llvm/test/CodeGen/Thumb2/jump-table-bti.ll| 10 ++--- llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll| 6 +-- .../Thumb2/pacbti-m-indirect-tail-call.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-3.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 6 +-- .../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-overalign.ll | 2 +- .../test/CodeGen/Thumb2/pacbti-m-stack-arg.ll | 4 +- .../Thumb2/pacbti-m-unsupported-arch.ll | 8 +--- .../test/CodeGen/Thumb2/pacbti-m-varargs-1.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-varargs-2.ll | 4 +- llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 2 +- .../AArch64/link-branch-target-enforcement.ll | 2 +- .../Inline/inline-sign-return-address.ll | 13 +++--- .../LowerTypeTests/function-arm-thumb.ll | 2 +- .../LowerTypeTests/function-thumb-bti.ll | 4 +- .../Transforms/LowerTypeTests/function.ll | 4 +- llvm/test/Verifier/branch-prot-attrs.ll | 16 ++- 61 files changed, 293 insertions(+), 317 deletions(-) create mode 100644 clang/test/Frontend/arm-branch-protection-lto.c diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 8a6511b9ced83..fde6e6315da5c 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -32,7 +32
[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/86212
>From f2f3356da08d68dab4431f49d0921515560e4927 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 8 Mar 2024 15:06:28 +0100
Subject: [PATCH] BTI,GCS,PAC Module flag update.
Module flag is used to indicate the feature to be propagated to the
function. As now the frontend emits all attributes accoringly let's
help the automerger to only do work when old and new bitcodes are
merged.
Autoupgrade function attributes from Module attributes when needed.
---
clang/lib/CodeGen/CodeGenModule.cpp | 19 ++--
.../CodeGen/aarch64-sign-return-address.c | 12 +--
.../CodeGen/arm-branch-protection-attr-2.c| 8 +-
.../arm-ignore-branch-protection-option.c | 2 +-
llvm/include/llvm/IR/AutoUpgrade.h| 3 +
llvm/lib/AsmParser/LLParser.cpp | 1 +
llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +
llvm/lib/IR/AutoUpgrade.cpp | 100 +
llvm/lib/Linker/IRMover.cpp | 10 ++
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 +-
llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 2 +-
.../test/Bitcode/upgrade-branch-protection.ll | 15 +--
.../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 2 +-
llvm/test/LTO/AArch64/Inputs/foo.ll | 16 ---
llvm/test/LTO/AArch64/TestInputs/bar.ll | 35 ++
llvm/test/LTO/AArch64/TestInputs/foo.ll | 38 +++
llvm/test/LTO/AArch64/TestInputs/old.ll | 46
.../AArch64/link-branch-target-enforcement.ll | 5 +-
.../LTO/AArch64/link-sign-return-address.ll | 102 ++
llvm/test/Linker/link-arm-and-thumb.ll| 6 +-
llvm/test/ThinLTO/AArch64/aarch64_inline.ll | 86 +++
llvm/test/ThinLTO/AArch64/lit.local.cfg | 2 +
22 files changed, 468 insertions(+), 46 deletions(-)
delete mode 100644 llvm/test/LTO/AArch64/Inputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/bar.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/old.ll
create mode 100644 llvm/test/LTO/AArch64/link-sign-return-address.ll
create mode 100644 llvm/test/ThinLTO/AArch64/aarch64_inline.ll
create mode 100644 llvm/test/ThinLTO/AArch64/lit.local.cfg
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 227813ad44e8b..6efc2283535f3 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1176,22 +1176,29 @@ void CodeGenModule::Release() {
"tag-stack-memory-buildattr", 1);
if (T.isARM() || T.isThumb() || T.isAArch64()) {
+// Previously 1 is used and meant for the backed to derive the function
+// attribute form it. 2 now means function attributes already set for all
+// functions in this module, so no need to propagate those from the module
+// flag. Value is only used in case of LTO module merge because the backend
+// will see all required function attribute set already. Value is used
+// before modules got merged. Any posive value means the feature is active
+// and required binary markings need to be emit accordingly.
if (LangOpts.BranchTargetEnforcement)
getModule().addModuleFlag(llvm::Module::Min, "branch-target-enforcement",
-1);
+2);
if (LangOpts.BranchProtectionPAuthLR)
getModule().addModuleFlag(llvm::Module::Min,
"branch-protection-pauth-lr",
-1);
+2);
if (LangOpts.GuardedControlStack)
- getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 2);
if (LangOpts.hasSignReturnAddress())
- getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 2);
if (LangOpts.isSignReturnAddressScopeAll())
getModule().addModuleFlag(llvm::Module::Min, "sign-return-address-all",
-1);
+2);
if (!LangOpts.isSignReturnAddressWithAKey())
getModule().addModuleFlag(llvm::Module::Min,
-"sign-return-address-with-bkey", 1);
+"sign-return-address-with-bkey", 2);
if (getTriple().isOSLinux()) {
assert(getTriple().isOSBinFormatELF());
diff --git a/clang/test/CodeGen/aarch64-sign-return-address.c
b/clang/test/CodeGen/aarch64-sign-return-address.c
index 8bc54b1a56c38..35c56889e0707 100644
--- a/clang/test/CodeGen/aarch64-sign-return-address.c
+++ b/clang/test/CodeGen/aarch64-sign-return-address.c
@@ -22,17 +22,17 @@
// NONE-NOT: !"branch-target-enforcement"
// ALL-NOT: !"branch-target-enforcement"
// PART-NOT: !"branch-target-enfor
[clang] 30b67c6 - [AArch64] Make ACLE intrinsics always available part1
Author: Daniel Kiss
Date: 2022-10-14T17:23:11+02:00
New Revision: 30b67c677c6baf0d6ef6c3051cf270133c43e4d2
URL:
https://github.com/llvm/llvm-project/commit/30b67c677c6baf0d6ef6c3051cf270133c43e4d2
DIFF:
https://github.com/llvm/llvm-project/commit/30b67c677c6baf0d6ef6c3051cf270133c43e4d2.diff
LOG: [AArch64] Make ACLE intrinsics always available part1
A given arch feature might enabled by a pragma or a function attribute so in
this cases would be nice to use intrinsics.
Today GCC offers the intrinsics without the march flag[1].
PR[2] for ACLE to clarify the intention and remove the need for -march flag for
a given intrinsics.
This is going to be more useful when D127812 lands.
[1] https://godbolt.org/z/bxcMhav3z
[2] https://github.com/ARM-software/acle/pull/214
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D133359
Added:
Modified:
clang/include/clang/Basic/BuiltinsAArch64.def
clang/lib/Headers/arm_acle.h
clang/test/CodeGen/arm_acle.c
clang/test/CodeGen/builtins-arm64.c
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def
b/clang/include/clang/Basic/BuiltinsAArch64.def
index 036df7435bfb..e6e375bc2b83 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -74,7 +74,7 @@ BUILTIN(__builtin_arm_dmb, "vUi", "nc")
BUILTIN(__builtin_arm_dsb, "vUi", "nc")
BUILTIN(__builtin_arm_isb, "vUi", "nc")
-BUILTIN(__builtin_arm_jcvt, "Zid", "nc")
+TARGET_BUILTIN(__builtin_arm_jcvt, "Zid", "nc", "v8.3a")
// Prefetch
BUILTIN(__builtin_arm_prefetch, "vvC*UiUiUiUi", "nc")
@@ -107,24 +107,24 @@ BUILTIN(__builtin_arm_tcancel, "vWUIi", "n")
BUILTIN(__builtin_arm_ttest, "WUi", "nc")
// Armv8.5-A FP rounding intrinsics
-BUILTIN(__builtin_arm_rint32zf, "ff", "")
-BUILTIN(__builtin_arm_rint32z, "dd", "")
-BUILTIN(__builtin_arm_rint64zf, "ff", "")
-BUILTIN(__builtin_arm_rint64z, "dd", "")
-BUILTIN(__builtin_arm_rint32xf, "ff", "")
-BUILTIN(__builtin_arm_rint32x, "dd", "")
-BUILTIN(__builtin_arm_rint64xf, "ff", "")
-BUILTIN(__builtin_arm_rint64x, "dd", "")
+TARGET_BUILTIN(__builtin_arm_rint32zf, "ff", "", "v8.5a")
+TARGET_BUILTIN(__builtin_arm_rint32z, "dd", "", "v8.5a")
+TARGET_BUILTIN(__builtin_arm_rint64zf, "ff", "", "v8.5a")
+TARGET_BUILTIN(__builtin_arm_rint64z, "dd", "", "v8.5a")
+TARGET_BUILTIN(__builtin_arm_rint32xf, "ff", "", "v8.5a")
+TARGET_BUILTIN(__builtin_arm_rint32x, "dd", "", "v8.5a")
+TARGET_BUILTIN(__builtin_arm_rint64xf, "ff", "", "v8.5a")
+TARGET_BUILTIN(__builtin_arm_rint64x, "dd", "", "v8.5a")
// Armv8.5-A Random number generation intrinsics
-BUILTIN(__builtin_arm_rndr, "iWUi*", "n")
-BUILTIN(__builtin_arm_rndrrs, "iWUi*", "n")
+TARGET_BUILTIN(__builtin_arm_rndr, "iWUi*", "n", "rand")
+TARGET_BUILTIN(__builtin_arm_rndrrs, "iWUi*", "n", "rand")
// Armv8.7-A load/store 64-byte intrinsics
-BUILTIN(__builtin_arm_ld64b, "vvC*WUi*", "n")
-BUILTIN(__builtin_arm_st64b, "vv*WUiC*", "n")
-BUILTIN(__builtin_arm_st64bv, "WUiv*WUiC*", "n")
-BUILTIN(__builtin_arm_st64bv0, "WUiv*WUiC*", "n")
+TARGET_BUILTIN(__builtin_arm_ld64b, "vvC*WUi*", "n", "ls64")
+TARGET_BUILTIN(__builtin_arm_st64b, "vv*WUiC*", "n", "ls64")
+TARGET_BUILTIN(__builtin_arm_st64bv, "WUiv*WUiC*", "n", "ls64")
+TARGET_BUILTIN(__builtin_arm_st64bv0, "WUiv*WUiC*", "n", "ls64")
TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index ed3fc1de1fd4..d73b6bf82d69 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -589,122 +589,123 @@ __smusdx(int16x2_t __a, int16x2_t __b) {
#endif
/* 9.7 CRC32 intrinsics */
-#if defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+#if (defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32) ||
\
+(defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE)
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__,
target("crc")))
__crc32b(uint32_t __a, uint8_t __b) {
return __builtin_arm_crc32b(__a, __b);
}
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__,
target("crc")))
__crc32h(uint32_t __a, uint16_t __b) {
return __builtin_arm_crc32h(__a, __b);
}
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__,
target("crc")))
__crc32w(uint32_t __a, uint32_t __b) {
return __builtin_arm_crc32w(__a, __b);
}
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __n
[clang] 09aaf19 - [AArch64] Make ACLE intrinsics always available part MTE
Author: Daniel Kiss
Date: 2022-10-18T10:35:40+02:00
New Revision: 09aaf190d93393d9e29d29a033cc3979589c5e84
URL:
https://github.com/llvm/llvm-project/commit/09aaf190d93393d9e29d29a033cc3979589c5e84
DIFF:
https://github.com/llvm/llvm-project/commit/09aaf190d93393d9e29d29a033cc3979589c5e84.diff
LOG: [AArch64] Make ACLE intrinsics always available part MTE
Make MTE intrinsics available in function scope too.
Followup from D133359.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136062
Added:
Modified:
clang/include/clang/Basic/BuiltinsAArch64.def
clang/lib/Headers/arm_acle.h
clang/test/CodeGen/arm64-mte.c
clang/test/Sema/builtins-arm64-mte.c
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def
b/clang/include/clang/Basic/BuiltinsAArch64.def
index e6e375bc2b83a..bc8ab4eade91a 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -59,15 +59,15 @@ TARGET_BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc", "crc")
TARGET_BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc", "crc")
// Memory Tagging Extensions (MTE)
-BUILTIN(__builtin_arm_irg, "v*v*Ui", "t")
-BUILTIN(__builtin_arm_addg, "v*v*Ui", "t")
-BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t")
-BUILTIN(__builtin_arm_ldg, "v*v*", "t")
-BUILTIN(__builtin_arm_stg, "vv*", "t")
-BUILTIN(__builtin_arm_subp, "Uiv*v*", "t")
+TARGET_BUILTIN(__builtin_arm_irg, "v*v*Ui", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_addg, "v*v*Ui", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_ldg, "v*v*", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_stg, "vv*", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_subp, "Uiv*v*", "t", "mte")
// Memory Operations
-BUILTIN(__builtin_arm_mops_memset_tag, "v*v*iz", "")
+TARGET_BUILTIN(__builtin_arm_mops_memset_tag, "v*v*iz", "", "mte,mops")
// Memory barrier
BUILTIN(__builtin_arm_dmb, "vUi", "nc")
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index d73b6bf82d699..b30010274392c 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -722,17 +722,15 @@ __arm_st64bv0(void *__addr, data512_t __value) {
#define __arm_wsrf64(sysreg, v) __arm_wsr64(sysreg,
__builtin_bit_cast(uint64_t, v))
/* Memory Tagging Extensions (MTE) Intrinsics */
-#if defined(__ARM_FEATURE_MEMORY_TAGGING) && __ARM_FEATURE_MEMORY_TAGGING
+#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
#define __arm_mte_create_random_tag(__ptr, __mask) __builtin_arm_irg(__ptr,
__mask)
#define __arm_mte_increment_tag(__ptr, __tag_offset)
__builtin_arm_addg(__ptr, __tag_offset)
#define __arm_mte_exclude_tag(__ptr, __excluded) __builtin_arm_gmi(__ptr,
__excluded)
#define __arm_mte_get_tag(__ptr) __builtin_arm_ldg(__ptr)
#define __arm_mte_set_tag(__ptr) __builtin_arm_stg(__ptr)
#define __arm_mte_ptr
diff (__ptra, __ptrb) __builtin_arm_subp(__ptra, __ptrb)
-#endif
/* Memory Operations Intrinsics */
-#if defined(__ARM_FEATURE_MOPS) && __ARM_FEATURE_MOPS &&
defined(__ARM_FEATURE_MEMORY_TAGGING) && __ARM_FEATURE_MEMORY_TAGGING
#define __arm_mops_memset_tag(__tagged_address, __value, __size)\
__builtin_arm_mops_memset_tag(__tagged_address, __value, __size)
#endif
diff --git a/clang/test/CodeGen/arm64-mte.c b/clang/test/CodeGen/arm64-mte.c
index 12b568b2ece76..1c65d6a626dda 100644
--- a/clang/test/CodeGen/arm64-mte.c
+++ b/clang/test/CodeGen/arm64-mte.c
@@ -1,9 +1,17 @@
// Test memory tagging extension intrinsics
// RUN: %clang_cc1 -triple aarch64-none-linux-eabi -target-feature +mte -O3 -S
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-eabi -DMTE -O3 -S -emit-llvm -o
- %s | FileCheck %s
#include
#include
+#ifdef MTE
+#define attribute __attribute__((target("mte")))
+#else
+#define attribute
+#endif
+
// CHECK-LABEL: define{{.*}} ptr @create_tag1
+attribute
int *create_tag1(int *a, unsigned b) {
// CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
// CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -11,6 +19,7 @@ int *create_tag1(int *a, unsigned b) {
}
// CHECK-LABEL: define{{.*}} ptr @create_tag2
+attribute
short *create_tag2(short *a, unsigned b) {
// CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
// CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -18,6 +27,7 @@ short *create_tag2(short *a, unsigned b) {
}
// CHECK-LABEL: define{{.*}} ptr @create_tag3
+attribute
char *create_tag3(char *a, unsigned b) {
// CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
// CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -26,18 +36,21 @@ char *create_tag3(char *a, unsigned b) {
}
// CHECK-LABEL: define{{.*}} ptr @increment_tag1
+attribute
char *increment_tag1(char *a) {
// CHECK: call ptr @llvm.aarch64.addg(ptr %a, i64 3)
return __
[clang] a175d8b - Revert "[AArch64] Make ACLE intrinsics always available part MTE"
Author: Daniel Kiss
Date: 2022-10-18T10:45:32+02:00
New Revision: a175d8b1772f729b2caf95a1b755cb9a59563e21
URL:
https://github.com/llvm/llvm-project/commit/a175d8b1772f729b2caf95a1b755cb9a59563e21
DIFF:
https://github.com/llvm/llvm-project/commit/a175d8b1772f729b2caf95a1b755cb9a59563e21.diff
LOG: Revert "[AArch64] Make ACLE intrinsics always available part MTE"
This reverts commit 09aaf190d93393d9e29d29a033cc3979589c5e84.
Added:
Modified:
clang/include/clang/Basic/BuiltinsAArch64.def
clang/lib/Headers/arm_acle.h
clang/test/CodeGen/arm64-mte.c
clang/test/Sema/builtins-arm64-mte.c
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def
b/clang/include/clang/Basic/BuiltinsAArch64.def
index bc8ab4eade91a..e6e375bc2b83a 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -59,15 +59,15 @@ TARGET_BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc", "crc")
TARGET_BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc", "crc")
// Memory Tagging Extensions (MTE)
-TARGET_BUILTIN(__builtin_arm_irg, "v*v*Ui", "t", "mte")
-TARGET_BUILTIN(__builtin_arm_addg, "v*v*Ui", "t", "mte")
-TARGET_BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t", "mte")
-TARGET_BUILTIN(__builtin_arm_ldg, "v*v*", "t", "mte")
-TARGET_BUILTIN(__builtin_arm_stg, "vv*", "t", "mte")
-TARGET_BUILTIN(__builtin_arm_subp, "Uiv*v*", "t", "mte")
+BUILTIN(__builtin_arm_irg, "v*v*Ui", "t")
+BUILTIN(__builtin_arm_addg, "v*v*Ui", "t")
+BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t")
+BUILTIN(__builtin_arm_ldg, "v*v*", "t")
+BUILTIN(__builtin_arm_stg, "vv*", "t")
+BUILTIN(__builtin_arm_subp, "Uiv*v*", "t")
// Memory Operations
-TARGET_BUILTIN(__builtin_arm_mops_memset_tag, "v*v*iz", "", "mte,mops")
+BUILTIN(__builtin_arm_mops_memset_tag, "v*v*iz", "")
// Memory barrier
BUILTIN(__builtin_arm_dmb, "vUi", "nc")
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index b30010274392c..d73b6bf82d699 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -722,15 +722,17 @@ __arm_st64bv0(void *__addr, data512_t __value) {
#define __arm_wsrf64(sysreg, v) __arm_wsr64(sysreg,
__builtin_bit_cast(uint64_t, v))
/* Memory Tagging Extensions (MTE) Intrinsics */
-#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
+#if defined(__ARM_FEATURE_MEMORY_TAGGING) && __ARM_FEATURE_MEMORY_TAGGING
#define __arm_mte_create_random_tag(__ptr, __mask) __builtin_arm_irg(__ptr,
__mask)
#define __arm_mte_increment_tag(__ptr, __tag_offset)
__builtin_arm_addg(__ptr, __tag_offset)
#define __arm_mte_exclude_tag(__ptr, __excluded) __builtin_arm_gmi(__ptr,
__excluded)
#define __arm_mte_get_tag(__ptr) __builtin_arm_ldg(__ptr)
#define __arm_mte_set_tag(__ptr) __builtin_arm_stg(__ptr)
#define __arm_mte_ptr
diff (__ptra, __ptrb) __builtin_arm_subp(__ptra, __ptrb)
+#endif
/* Memory Operations Intrinsics */
+#if defined(__ARM_FEATURE_MOPS) && __ARM_FEATURE_MOPS &&
defined(__ARM_FEATURE_MEMORY_TAGGING) && __ARM_FEATURE_MEMORY_TAGGING
#define __arm_mops_memset_tag(__tagged_address, __value, __size)\
__builtin_arm_mops_memset_tag(__tagged_address, __value, __size)
#endif
diff --git a/clang/test/CodeGen/arm64-mte.c b/clang/test/CodeGen/arm64-mte.c
index 1c65d6a626dda..12b568b2ece76 100644
--- a/clang/test/CodeGen/arm64-mte.c
+++ b/clang/test/CodeGen/arm64-mte.c
@@ -1,17 +1,9 @@
// Test memory tagging extension intrinsics
// RUN: %clang_cc1 -triple aarch64-none-linux-eabi -target-feature +mte -O3 -S
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-eabi -DMTE -O3 -S -emit-llvm -o
- %s | FileCheck %s
#include
#include
-#ifdef MTE
-#define attribute __attribute__((target("mte")))
-#else
-#define attribute
-#endif
-
// CHECK-LABEL: define{{.*}} ptr @create_tag1
-attribute
int *create_tag1(int *a, unsigned b) {
// CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
// CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -19,7 +11,6 @@ int *create_tag1(int *a, unsigned b) {
}
// CHECK-LABEL: define{{.*}} ptr @create_tag2
-attribute
short *create_tag2(short *a, unsigned b) {
// CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
// CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -27,7 +18,6 @@ short *create_tag2(short *a, unsigned b) {
}
// CHECK-LABEL: define{{.*}} ptr @create_tag3
-attribute
char *create_tag3(char *a, unsigned b) {
// CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
// CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -36,21 +26,18 @@ char *create_tag3(char *a, unsigned b) {
}
// CHECK-LABEL: define{{.*}} ptr @increment_tag1
-attribute
char *increment_tag1(char *a) {
// CHECK: call ptr @llvm.aarch64.addg(ptr %a, i64 3)
return __arm_mte_increment_tag(a,3);
}
// CHECK-LABEL: define{{.*}} ptr @increment_tag2
-
[clang] 0d0ca64 - [AArch64] Make ACLE intrinsics always available part MTE
Author: Daniel Kiss
Date: 2022-10-18T11:03:02+02:00
New Revision: 0d0ca64356ff1a9e3427660732da033a14521e5b
URL:
https://github.com/llvm/llvm-project/commit/0d0ca64356ff1a9e3427660732da033a14521e5b
DIFF:
https://github.com/llvm/llvm-project/commit/0d0ca64356ff1a9e3427660732da033a14521e5b.diff
LOG: [AArch64] Make ACLE intrinsics always available part MTE
Make MTE intrinsics available in function scope too.
Followup from D133359.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136062
Added:
Modified:
clang/include/clang/Basic/BuiltinsAArch64.def
clang/lib/Headers/arm_acle.h
clang/test/CodeGen/aarch64-mops.c
clang/test/CodeGen/arm64-mte.c
clang/test/Sema/builtins-arm64-mte.c
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def
b/clang/include/clang/Basic/BuiltinsAArch64.def
index e6e375bc2b83a..bc8ab4eade91a 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -59,15 +59,15 @@ TARGET_BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc", "crc")
TARGET_BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc", "crc")
// Memory Tagging Extensions (MTE)
-BUILTIN(__builtin_arm_irg, "v*v*Ui", "t")
-BUILTIN(__builtin_arm_addg, "v*v*Ui", "t")
-BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t")
-BUILTIN(__builtin_arm_ldg, "v*v*", "t")
-BUILTIN(__builtin_arm_stg, "vv*", "t")
-BUILTIN(__builtin_arm_subp, "Uiv*v*", "t")
+TARGET_BUILTIN(__builtin_arm_irg, "v*v*Ui", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_addg, "v*v*Ui", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_ldg, "v*v*", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_stg, "vv*", "t", "mte")
+TARGET_BUILTIN(__builtin_arm_subp, "Uiv*v*", "t", "mte")
// Memory Operations
-BUILTIN(__builtin_arm_mops_memset_tag, "v*v*iz", "")
+TARGET_BUILTIN(__builtin_arm_mops_memset_tag, "v*v*iz", "", "mte,mops")
// Memory barrier
BUILTIN(__builtin_arm_dmb, "vUi", "nc")
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index d73b6bf82d699..b30010274392c 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -722,17 +722,15 @@ __arm_st64bv0(void *__addr, data512_t __value) {
#define __arm_wsrf64(sysreg, v) __arm_wsr64(sysreg,
__builtin_bit_cast(uint64_t, v))
/* Memory Tagging Extensions (MTE) Intrinsics */
-#if defined(__ARM_FEATURE_MEMORY_TAGGING) && __ARM_FEATURE_MEMORY_TAGGING
+#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
#define __arm_mte_create_random_tag(__ptr, __mask) __builtin_arm_irg(__ptr,
__mask)
#define __arm_mte_increment_tag(__ptr, __tag_offset)
__builtin_arm_addg(__ptr, __tag_offset)
#define __arm_mte_exclude_tag(__ptr, __excluded) __builtin_arm_gmi(__ptr,
__excluded)
#define __arm_mte_get_tag(__ptr) __builtin_arm_ldg(__ptr)
#define __arm_mte_set_tag(__ptr) __builtin_arm_stg(__ptr)
#define __arm_mte_ptr
diff (__ptra, __ptrb) __builtin_arm_subp(__ptra, __ptrb)
-#endif
/* Memory Operations Intrinsics */
-#if defined(__ARM_FEATURE_MOPS) && __ARM_FEATURE_MOPS &&
defined(__ARM_FEATURE_MEMORY_TAGGING) && __ARM_FEATURE_MEMORY_TAGGING
#define __arm_mops_memset_tag(__tagged_address, __value, __size)\
__builtin_arm_mops_memset_tag(__tagged_address, __value, __size)
#endif
diff --git a/clang/test/CodeGen/aarch64-mops.c
b/clang/test/CodeGen/aarch64-mops.c
index f7efb1635185d..c0f151837c751 100644
--- a/clang/test/CodeGen/aarch64-mops.c
+++ b/clang/test/CodeGen/aarch64-mops.c
@@ -1,77 +1,68 @@
// RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion
-target-feature +mops -target-feature +mte -w -S -emit-llvm -o - %s |
FileCheck --check-prefix=CHECK-MOPS %s
-// RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion
-target-feature +mops -Wno-implicit-function-declaration -w -S -emit-llvm -o -
%s | FileCheck --check-prefix=CHECK-NOMOPS %s
-// RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion
-Wno-implicit-function-declaration -target-feature +mte -w -S -emit-llvm -o -
%s | FileCheck --check-prefix=CHECK-NOMOPS %s
-// RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion
-Wno-implicit-function-declaration -w -S -emit-llvm -o - %s | FileCheck
--check-prefix=CHECK-NOMOPS %s
+// RUN: not %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion
-target-feature +mops -Wno-implicit-function-declaration -w -S -emit-llvm -o -
%s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
+// RUN: not %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion
-Wno-implicit-function-declaration -target-feature +mte -w -S -emit-llvm -o -
%s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
+// RUN: not %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion
-Wno-implicit-function-declaration -w -S -emit-llvm -o - %s 2>&1 | FileCheck
--check-prefix=CHECK-NOMOPS %s
[clang] d75e70d - [AArch64] Add preserve_all calling convention.
Author: Daniel Kiss
Date: 2023-04-28T14:55:38+02:00
New Revision: d75e70d7ae1f84cea71f0be5fbee836bdc22138a
URL:
https://github.com/llvm/llvm-project/commit/d75e70d7ae1f84cea71f0be5fbee836bdc22138a
DIFF:
https://github.com/llvm/llvm-project/commit/d75e70d7ae1f84cea71f0be5fbee836bdc22138a.diff
LOG: [AArch64] Add preserve_all calling convention.
Clang accepts preserve_all for AArch64 while it is missing form the backed.
Fixes #58145
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D135652
Added:
llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
llvm/test/CodeGen/AArch64/preserve.ll
llvm/test/CodeGen/AArch64/tailcall-ccmismatch2.ll
Modified:
clang/docs/ReleaseNotes.rst
clang/include/clang/Basic/AttrDocs.td
llvm/docs/LangRef.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/AArch64/AArch64CallingConvention.td
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a61e6615b9371..87db8cedd6a7b 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -432,6 +432,9 @@ Arm and AArch64 Support
// int a = foo(); int* b = bar();
asm("ands %w[a], %w[a], #3" : [a] "+r"(a), "=@cceq"(*b));
+- Fix a crash when ``preserve_all`` calling convention is used on AArch64.
+ `Issue 58145 `_
+
Windows Support
^^^
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index dae12624a822b..0a0afe619ec2c 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5182,6 +5182,9 @@ apply for values returned in callee-saved registers.
R11. R11 can be used as a scratch register. Floating-point registers
(XMMs/YMMs) are not preserved and need to be saved by the caller.
+- On AArch64 the callee preserve all general purpose registers, except X0-X8
and
+ X16-X18.
+
The idea behind this convention is to support calls to runtime functions
that have a hot path and a cold path. The hot path is usually a small piece
of code that doesn't use many registers. The cold path might need to call out
to
@@ -5222,6 +5225,10 @@ returned in callee-saved registers.
R11. R11 can be used as a scratch register. Furthermore it also preserves
all floating-point registers (XMMs/YMMs).
+- On AArch64 the callee preserve all general purpose registers, except X0-X8
and
+ X16-X18. Furthermore it also preserves lower 128 bits of V8-V31 SIMD -
floating
+ point registers.
+
The idea behind this convention is to support calls to runtime functions
that don't need to call out to any other functions.
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index a0d012d3a14f5..48e658d08e7b3 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -370,6 +370,9 @@ added in the future:
Floating-point registers (XMMs/YMMs) are not preserved and need to be
saved by the caller.
+- On AArch64 the callee preserve all general purpose registers, except
X0-X8
+ and X16-X18.
+
The idea behind this convention is to support calls to runtime functions
that have a hot path and a cold path. The hot path is usually a small piece
of code that doesn't use many registers. The cold path might need to call
out to
@@ -404,6 +407,10 @@ added in the future:
R11. R11 can be used as a scratch register. Furthermore it also preserves
all floating-point registers (XMMs/YMMs).
+- On AArch64 the callee preserve all general purpose registers, except
X0-X8
+ and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31 SIMD
-
+ floating point registers.
+
The idea behind this convention is to support calls to runtime functions
that don't need to call out to any other functions.
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c5bf6cbeb6fde..334365fa0a8a4 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -84,6 +84,7 @@ Changes to the AArch64 Backend
* Added Assembly Support for the 2022 A-profile extensions FEAT_GCS (Guarded
Control Stacks), FEAT_CHK (Check Feature Status), and FEAT_ATS1A.
+* Support for preserve_all calling convention is added.
Changes to the AMDGPU Backend
-
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td
b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
index 853975c6193d9..ce087be79202e 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.td
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
@@ -489,6 +489,9 @@ def CS
[clang] 7e1a873 - [Arm][AArch64] Make getArchFeatures to use TargetParser.def
Author: Daniel Kiss
Date: 2022-09-23T10:25:37+02:00
New Revision: 7e1a87387209252dec5902925a232467db951db6
URL:
https://github.com/llvm/llvm-project/commit/7e1a87387209252dec5902925a232467db951db6
DIFF:
https://github.com/llvm/llvm-project/commit/7e1a87387209252dec5902925a232467db951db6.diff
LOG: [Arm][AArch64] Make getArchFeatures to use TargetParser.def
Prefixing the the SubArch with plus sign makes the ArchFeature name.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D134349
Added:
Modified:
clang/test/Driver/arch.c
clang/test/Driver/arm-cortex-cpus-1.c
clang/test/Driver/arm-cortex-cpus-2.c
clang/test/Driver/arm-features.c
clang/test/Driver/arm-target-as-march-mcpu.s
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/include/llvm/Support/ARMTargetParser.def
llvm/include/llvm/Support/ARMTargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/test/Driver/arch.c b/clang/test/Driver/arch.c
index f113c1dfa5c27..09afc6a6455b7 100644
--- a/clang/test/Driver/arch.c
+++ b/clang/test/Driver/arch.c
@@ -2,4 +2,4 @@
// RUN: %clang -target armv8a-unknown-linux-gnueabi -S -emit-llvm %s -o - |
FileCheck %s --check-prefix=V8
// V7: target triple = "armv7-unknown-linux-gnueabi"
-// V8: target triple = "armv8-unknown-linux-gnueabi"
+// V8: target triple = "armv8a-unknown-linux-gnueabi"
diff --git a/clang/test/Driver/arm-cortex-cpus-1.c
b/clang/test/Driver/arm-cortex-cpus-1.c
index 7b6c203b53b80..bfdf4d1515793 100644
--- a/clang/test/Driver/arm-cortex-cpus-1.c
+++ b/clang/test/Driver/arm-cortex-cpus-1.c
@@ -148,7 +148,7 @@
// RUN: %clang -target armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A %s
// RUN: %clang -target arm -march=armv8a -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A %s
// RUN: %clang -target arm -march=armv8-a -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A %s
-// CHECK-V8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "generic"
+// CHECK-V8A: "-cc1"{{.*}} "-triple" "armv8a-{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target armv8r-linux-gnueabi -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
// RUN: %clang -target arm -march=armv8r -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
@@ -181,7 +181,7 @@
// RUN: %clang -mcpu=generic -target armv8a -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8a -mlittle-endian -### -c
%s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8-a -mlittle-endian -###
-c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
-// CHECK-V8A-GENERIC: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu"
"generic"
+// CHECK-V8A-GENERIC: "-cc1"{{.*}} "-triple" "armv8a-{{.*}}" "-target-cpu"
"generic"
// RUN: %clang -target armebv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V8A %s
// RUN: %clang -target armeb -march=armebv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V8A %s
@@ -193,7 +193,7 @@
// RUN: %clang -target armv8a -mbig-endian -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V8A %s
// RUN: %clang -target arm -march=armebv8a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V8A %s
// RUN: %clang -target arm -march=armebv8-a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V8A %s
-// CHECK-BE-V8A: "-cc1"{{.*}} "-triple" "armebv8-{{.*}}" "-target-cpu"
"generic"
+// CHECK-BE-V8A: "-cc1"{{.*}} "-triple" "armebv8a-{{.*}}" "-target-cpu"
"generic"
// RUN: %clang -target armv8 -mthumb -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-THUMB %s
// RUN: %clang -target arm -march=armv8 -mthumb -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-THUMB %s
@@ -203,7 +203,7 @@
// RUN: %clang -target arm -march=armv8 -mlittle-endian -mthumb -### -c %s
2>&1 | FileCheck -check-prefix=CHECK-V8A-THUMB %s
// RUN: %clang -target armv8a -mlittle-endian -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-THUMB %s
// RUN: %clang -target arm -march=armv8a -mlittle-endian -mthumb -### -c %s
2>&1 | FileCheck -check-prefix=CHECK-V8A-THUMB %s
-// CHECK-V8A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8-{{.*}}" "-target-cpu"
"generic"
+// CHECK-V8A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8a-{{.*}}" "-target-cpu"
"generic"
// RUN: %clang -target armebv8 -mthumb -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V8A-THUMB %s
// RUN: %clang -target armeb -march=armebv8 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V8A-THUMB %s
@@ -213,7 +213,7 @@
// RUN: %clang -target arm -march=armebv8 -mbig-endian -mthumb -### -c %s 2>&1
| FileCheck -check-prefix=CHECK-BE-V8A-THUMB %s
// R
[clang] 712de9d - [AArch64] Add all predecessor archs in target info
Author: Daniel Kiss
Date: 2022-09-27T10:23:21+02:00
New Revision: 712de9d1716c010e895a578ad86cbd47680a4fdd
URL:
https://github.com/llvm/llvm-project/commit/712de9d1716c010e895a578ad86cbd47680a4fdd
DIFF:
https://github.com/llvm/llvm-project/commit/712de9d1716c010e895a578ad86cbd47680a4fdd.diff
LOG: [AArch64] Add all predecessor archs in target info
A given function is compatible with all previous arch versions.
To avoid compering values of the attribute this logic adds all predecessor
architecture values.
Reviewed By: dmgreen, DavidSpickett
Differential Revision: https://reviews.llvm.org/D134353
Added:
clang/test/CodeGen/aarch64-subarch-compatbility.c
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index e8745402b58f..604c7bbb8153 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -529,6 +529,22 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature)
const {
.Default(false);
}
+void AArch64TargetInfo::setFeatureEnabled(llvm::StringMap &Features,
+ StringRef Name, bool Enabled) const {
+ Features[Name] = Enabled;
+ llvm::AArch64::ArchKind AK = llvm::AArch64::getSubArchArchKind(Name);
+ // Add all previous architecture versions.
+ // In case of v9.x the v8.x counterparts are added too.
+ if ("9" == getArchVersionString(AK))
+for (llvm::AArch64::ArchKind I = llvm::AArch64::convertV9toV8(AK);
+ I != llvm::AArch64::ArchKind::INVALID; --I)
+ Features[llvm::AArch64::getSubArch(I)] = Enabled;
+
+ for (llvm::AArch64::ArchKind I = --AK; I != llvm::AArch64::ArchKind::INVALID;
+ --I)
+Features[llvm::AArch64::getSubArch(I)] = Enabled;
+}
+
bool AArch64TargetInfo::handleTargetFeatures(std::vector
&Features,
DiagnosticsEngine &Diags) {
FPU = FPUMode;
@@ -620,31 +636,32 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasSM4 = true;
if (Feature == "+strict-align")
HasUnaligned = false;
-if (Feature == "+v8a")
+// All predecessor archs are added but select the latest one for ArchKind.
+if (Feature == "+v8a" && ArchKind < llvm::AArch64::ArchKind::ARMV8A)
ArchKind = llvm::AArch64::ArchKind::ARMV8A;
-if (Feature == "+v8.1a")
+if (Feature == "+v8.1a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_1A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
-if (Feature == "+v8.2a")
+if (Feature == "+v8.2a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_2A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
-if (Feature == "+v8.3a")
+if (Feature == "+v8.3a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_3A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
-if (Feature == "+v8.4a")
+if (Feature == "+v8.4a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_4A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
-if (Feature == "+v8.5a")
+if (Feature == "+v8.5a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_5A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
-if (Feature == "+v8.6a")
+if (Feature == "+v8.6a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_6A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
-if (Feature == "+v8.7a")
+if (Feature == "+v8.7a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_7A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
-if (Feature == "+v8.8a")
+if (Feature == "+v8.8a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_8A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_8A;
-if (Feature == "+v9a")
+if (Feature == "+v9a" && ArchKind < llvm::AArch64::ArchKind::ARMV9A)
ArchKind = llvm::AArch64::ArchKind::ARMV9A;
-if (Feature == "+v9.1a")
+if (Feature == "+v9.1a" && ArchKind < llvm::AArch64::ArchKind::ARMV9_1A)
ArchKind = llvm::AArch64::ArchKind::ARMV9_1A;
-if (Feature == "+v9.2a")
+if (Feature == "+v9.2a" && ArchKind < llvm::AArch64::ArchKind::ARMV9_2A)
ArchKind = llvm::AArch64::ArchKind::ARMV9_2A;
-if (Feature == "+v9.3a")
+if (Feature == "+v9.3a" && ArchKind < llvm::AArch64::ArchKind::ARMV9_3A)
ArchKind = llvm::AArch64::ArchKind::ARMV9_3A;
if (Feature == "+v8r")
ArchKind = llvm::AArch64::ArchKind::ARMV8R;
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 1930092c248b..302cab409745 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -114,6 +114,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
g
[libunwind] f326df3 - [libunwind][AArch64] Fix _Unwind_ForcedUnwind via sigreturn.
Author: Daniel Kiss
Date: 2022-04-28T18:41:38+02:00
New Revision: f326df34bc179e41ea17d31e1ffba4a479e45589
URL:
https://github.com/llvm/llvm-project/commit/f326df34bc179e41ea17d31e1ffba4a479e45589
DIFF:
https://github.com/llvm/llvm-project/commit/f326df34bc179e41ea17d31e1ffba4a479e45589.diff
LOG: [libunwind][AArch64] Fix _Unwind_ForcedUnwind via sigreturn.
When the sigreturn trampoline is found the unw_proc_info_t.end_ip need to be
set to
indicate a stack frame is found.
Reviewed By: cjdb, #libunwind, MaskRay
Differential Revision: https://reviews.llvm.org/D124522
Added:
libcxxabi/test/forced_unwind4.pass.cpp
Modified:
libunwind/src/UnwindCursor.hpp
Removed:
diff --git a/libcxxabi/test/forced_unwind4.pass.cpp
b/libcxxabi/test/forced_unwind4.pass.cpp
new file mode 100644
index 0..53a0121da92e4
--- /dev/null
+++ b/libcxxabi/test/forced_unwind4.pass.cpp
@@ -0,0 +1,50 @@
+// -*- C++ -*-
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// REQUIRES: linux && target={{aarch64-.+}}
+
+// pthread_cancel in case of glibc calls _Unwind_ForcedUnwind from a signal on
+// the child_thread. This test ensures sigretrun is handled correctly (see:
+// UnwindCursor::setInfoForSigReturn).
+
+#include
+#include
+#include
+#include
+
+using namespace std::chrono_literals;
+
+std::condition_variable cv;
+std::mutex cv_m;
+bool thread_ready = false;
+
+static void* test(void* arg) {
+ (void)arg;
+ thread_ready = true;
+ cv.notify_all();
+
+ // This must be a pthread cancellation point.
+ while (1)
+sleep(100);
+
+ return (void*)1;
+}
+
+int main() {
+ pthread_t child_thread;
+ std::unique_lock lk(cv_m);
+ pthread_create(&child_thread, 0, test, (void*)0);
+
+ if (!cv.wait_for(lk, 100ms, [] { return thread_ready; }))
+return -1;
+
+ pthread_cancel(child_thread);
+ pthread_join(child_thread, NULL);
+ return 0;
+}
diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp
index dd849b781753e..29ded5c4e78ed 100644
--- a/libunwind/src/UnwindCursor.hpp
+++ b/libunwind/src/UnwindCursor.hpp
@@ -2606,6 +2606,8 @@ bool UnwindCursor::setInfoForSigReturn(Registers_arm64 &) {
if (_addressSpace.get32(pc) == 0xd2801168 &&
_addressSpace.get32(pc + 4) == 0xd401) {
_info = {};
+_info.start_ip = pc;
+_info.end_ip = pc + 4;
_isSigReturn = true;
return true;
}
___
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[clang] b0343a3 - Support the min of module flags when linking, use for AArch64 BTI/PAC-RET
Author: Daniel Kiss
Date: 2022-04-13T09:31:51+02:00
New Revision: b0343a38a5910e980bb031e4014655d77cd0c162
URL:
https://github.com/llvm/llvm-project/commit/b0343a38a5910e980bb031e4014655d77cd0c162
DIFF:
https://github.com/llvm/llvm-project/commit/b0343a38a5910e980bb031e4014655d77cd0c162.diff
LOG: Support the min of module flags when linking, use for AArch64 BTI/PAC-RET
LTO objects might compiled with different `mbranch-protection` flags which will
cause an error in the linker.
Such a setup is allowed in the normal build with this change that is possible.
Reviewed By: pcc
Differential Revision: https://reviews.llvm.org/D123493
Added:
llvm/test/Bitcode/upgrade-branch-protection.ll
llvm/test/LTO/AArch64/Inputs/foo.ll
llvm/test/LTO/AArch64/link-branch-target-enforcement.ll
llvm/test/LTO/AArch64/lit.local.cfg
Modified:
clang/lib/CodeGen/CodeGenModule.cpp
clang/test/CodeGen/aarch64-sign-return-address.c
clang/test/CodeGen/arm-branch-protection-attr-2.c
clang/test/Frontend/arm-ignore-branch-protection-option.c
llvm/include/llvm/IR/Module.h
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Linker/IRMover.cpp
llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
llvm/test/CodeGen/AArch64/memsize-remarks.ll
llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll
llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll
llvm/test/CodeGen/AArch64/setjmp-bti.ll
llvm/test/CodeGen/ARM/pacbti-module-attrs.ll
llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
llvm/test/CodeGen/Thumb2/bti-const-island-multiple-jump-tables.mir
llvm/test/CodeGen/Thumb2/bti-const-island.mir
llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll
llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
llvm/test/CodeGen/Thumb2/bti-jump-table.mir
llvm/test/CodeGen/Thumb2/bti-outliner-1.ll
llvm/test/CodeGen/Thumb2/bti-outliner-2.ll
llvm/test/CodeGen/Thumb2/bti-outliner-cost-1.ll
llvm/test/CodeGen/Thumb2/bti-outliner-cost-2.ll
llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir
llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll
llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll
llvm/test/CodeGen/Thumb2/pacbti-m-indirect-tail-call.ll
llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
llvm/test/CodeGen/Thumb2/pacbti-m-outliner-2.ll
llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll
llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
llvm/test/CodeGen/Thumb2/pacbti-m-outliner-5.ll
llvm/test/CodeGen/Thumb2/pacbti-m-overalign.ll
llvm/test/CodeGen/Thumb2/pacbti-m-unsupported-arch.ll
llvm/test/CodeGen/Thumb2/pacbti-m-varargs-1.ll
llvm/test/CodeGen/Thumb2/pacbti-m-varargs-2.ll
llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll
llvm/test/DebugInfo/AArch64/debugline-endsequence.ll
llvm/test/Instrumentation/InstrProfiling/debug-info-correlate-coverage.ll
llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll
llvm/test/Verifier/module-flags-1.ll
Removed:
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 4efcc8447d81b..b251a4a7df3d2 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -729,7 +729,10 @@ void CodeGenModule::Release() {
// attributes, but we use module metadata to emit build attributes. This is
// needed for LTO, where the function attributes are inside bitcode
// serialised into a global variable by the time build attributes are
- // emitted, so we can't access them.
+ // emitted, so we can't access them. LTO objects could be compiled with
+ //
diff erent flags therefore module flags are set to "Min" behavior to achieve
+ // the same end result of the normal build where e.g BTI is off if any object
+ // doesn't support it.
if (Context.getTargetInfo().hasFeature("ptrauth") &&
LangOpts.getSignReturnAddressScope() !=
LangOptions::SignReturnAddressScopeKind::None)
@@ -743,16 +746,16 @@ void CodeGenModule::Release() {
Arch == llvm::Triple::arm || Arch == llvm::Triple::armeb ||
Arch == llvm::Triple::aarch64 || Arch == llvm::Triple::aarch64_32 ||
Arch == llvm::Triple::aarch64_be) {
-getModule().addModuleFlag(llvm::Module::Error, "branch-target-enforcement",
+getModule().addModuleFlag(llvm::Mod
[libunwind] 77aa9ca - [libunwind] Support cfi_undefined and cfi_register for float registers.
Author: Daniel Kiss
Date: 2021-09-27T12:04:02+02:00
New Revision: 77aa9ca92ae4732f5f92e580e14bb4d757f6b364
URL:
https://github.com/llvm/llvm-project/commit/77aa9ca92ae4732f5f92e580e14bb4d757f6b364
DIFF:
https://github.com/llvm/llvm-project/commit/77aa9ca92ae4732f5f92e580e14bb4d757f6b364.diff
LOG: [libunwind] Support cfi_undefined and cfi_register for float registers.
During a backtrace the `.cfi_undefined` for a float register causes an assert
in libunwind.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D110144
Added:
libunwind/test/floatregister.pass.cpp
Modified:
libunwind/src/DwarfInstructions.hpp
Removed:
diff --git a/libunwind/src/DwarfInstructions.hpp
b/libunwind/src/DwarfInstructions.hpp
index 60b242e0c143..53baf6a148f3 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -115,12 +115,13 @@ double DwarfInstructions::getSavedFloatRegister(
return addressSpace.getDouble(
evaluateExpression((pint_t)savedReg.value, addressSpace,
registers, cfa));
-
+ case CFI_Parser::kRegisterInRegister:
+return registers.getFloatRegister((int)savedReg.value);
+ case CFI_Parser::kRegisterUndefined:
+return 0.0;
case CFI_Parser::kRegisterIsExpression:
case CFI_Parser::kRegisterUnused:
- case CFI_Parser::kRegisterUndefined:
case CFI_Parser::kRegisterOffsetFromCFA:
- case CFI_Parser::kRegisterInRegister:
// FIX ME
break;
}
diff --git a/libunwind/test/floatregister.pass.cpp
b/libunwind/test/floatregister.pass.cpp
new file mode 100644
index ..64107e6d490b
--- /dev/null
+++ b/libunwind/test/floatregister.pass.cpp
@@ -0,0 +1,51 @@
+// -*- C++ -*-
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// REQUIRES: linux && target={{aarch64-.+}}
+
+// Basic test for float registers number are accepted.
+
+#include
+#include
+#include
+#include
+
+_Unwind_Reason_Code frame_handler(struct _Unwind_Context *ctx, void *arg) {
+ (void)arg;
+ Dl_info info = {0, 0, 0, 0};
+
+ // Unwind util the main is reached, above frames depend on the platform and
+ // architecture.
+ if (dladdr(reinterpret_cast(_Unwind_GetIP(ctx)), &info) &&
+ info.dli_sname && !strcmp("main", info.dli_sname))
+_Exit(0);
+
+ return _URC_NO_REASON;
+}
+
+__attribute__((noinline)) void foo() {
+ // Provide some CFI directives that instructs the unwinder where given
+ // float register is.
+#if defined(__aarch64__)
+ // DWARF register number for V0-V31 registers are 64-95.
+ // Previous value of V0 is saved at offset 0 from CFA.
+ asm volatile(".cfi_offset 64, 0");
+ // From now on the previous value of register can't be restored anymore.
+ asm volatile(".cfi_undefined 65");
+ asm volatile(".cfi_undefined 95");
+ // Previous value of V2 is in V30.
+ asm volatile(".cfi_register 66, 94");
+#endif
+ _Unwind_Backtrace(frame_handler, NULL);
+}
+
+int main() {
+ foo();
+ return -2;
+}
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[libunwind] 532783f - [libunwind] Fix cfi_register for float registers.
Author: Daniel Kiss Date: 2021-10-01T16:51:51+02:00 New Revision: 532783f9e1e65c7bd48b1592d2376e9dd47c5a73 URL: https://github.com/llvm/llvm-project/commit/532783f9e1e65c7bd48b1592d2376e9dd47c5a73 DIFF: https://github.com/llvm/llvm-project/commit/532783f9e1e65c7bd48b1592d2376e9dd47c5a73.diff LOG: [libunwind] Fix cfi_register for float registers. Fixes D110144. registers.getFloatRegister is not const in ARM therefor can't be called here. Reviewed By: mstorsjo, #libunwind Differential Revision: https://reviews.llvm.org/D110731 Added: Modified: libunwind/src/DwarfInstructions.hpp Removed: diff --git a/libunwind/src/DwarfInstructions.hpp b/libunwind/src/DwarfInstructions.hpp index 53baf6a148f33..b58c51bb7a604 100644 --- a/libunwind/src/DwarfInstructions.hpp +++ b/libunwind/src/DwarfInstructions.hpp @@ -115,10 +115,12 @@ double DwarfInstructions::getSavedFloatRegister( return addressSpace.getDouble( evaluateExpression((pint_t)savedReg.value, addressSpace, registers, cfa)); - case CFI_Parser::kRegisterInRegister: -return registers.getFloatRegister((int)savedReg.value); case CFI_Parser::kRegisterUndefined: return 0.0; + case CFI_Parser::kRegisterInRegister: +#ifndef _LIBUNWIND_TARGET_ARM +return registers.getFloatRegister((int)savedReg.value); +#endif case CFI_Parser::kRegisterIsExpression: case CFI_Parser::kRegisterUnused: case CFI_Parser::kRegisterOffsetFromCFA: ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [libunwind] Fix problems caused by combining BTI and GCS (PR #102322)
https://github.com/DanielKristofKiss edited https://github.com/llvm/llvm-project/pull/102322 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [libunwind] Fix problems caused by combining BTI and GCS (PR #102322)
@@ -82,7 +82,22 @@ #define PPC64_OPD2 #endif -#if defined(__aarch64__) && defined(__ARM_FEATURE_BTI_DEFAULT) +#if defined(__aarch64__) +#if defined(__ARM_FEATURE_GCS_DEFAULT) && defined(__ARM_FEATURE_BTI_DEFAULT) +// Set BTI, PAC, and GCS gnu property bits +#define GNU_PROPERTY 7 +// We indirectly branch to __libunwind_Registers_arm64_jumpto from +// __unw_phase2_resume, so we need to use bti jc. +#define AARCH64_BTI bti jc DanielKristofKiss wrote: `__unw_getcontext` will also get the `bti jc` so slightly weakens the BTI protection but since `paciasp` is also `bti jc` might not be a big problem. https://github.com/llvm/llvm-project/pull/102322 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [libunwind] Fix problems caused by combining BTI and GCS (PR #102322)
https://github.com/DanielKristofKiss approved this pull request. Thanks! LGTM with a NIT. Please wait for someone from the unwind group to ack it too. https://github.com/llvm/llvm-project/pull/102322 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [libunwind] Fix problems caused by combining BTI and GCS (PR #102322)
@@ -680,7 +684,17 @@ DEFINE_LIBUNWIND_FUNCTION(__libunwind_Registers_arm64_jumpto) ldrx16, [x0, #0x0F8] ldpx0, x1, [x0, #0x000] // restore x0,x1 movsp,x16 // restore sp - br x30// jump to pc +#if defined(__ARM_FEATURE_GCS_DEFAULT) + // If GCS is enabled we need to push the address we're returning to onto the + // GCS stack. We can't just return using br, as there won't be a BTI landing + // pad instruction at the destination. + mov x16, #1 + chkfeat x16 + cbnz x16, Lnogcs + gcspushm x30 +Lnogcs: +#endif + ret // jump to pc DanielKristofKiss wrote: I'd keep spelling of x30 for sake of readability. (NFC) ```suggestion retx30// jump to pc ``` https://github.com/llvm/llvm-project/pull/102322 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
@@ -0,0 +1,35 @@
+; This file contains the new semantic of the branch-target-enforcement,
sign-return-address.
+; Used for test mixing a mixed link case and also verify the import too in llc.
+
+; RUN: llc %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define dso_local void @bar() #0 {
+entry:
+ ret void
+}
+; CHECK-LABEL: bar:
+; CHECK-NOT: hint
+; CHECK-NOT: bti
+; CHECK: ret
+
+define dso_local void @baz() #1 {
+entry:
+ ret void
+}
+
+; CHECK-LABEL: baz:
+; CHECK: hint
+; CHECK: ret
+
+attributes #0 = { noinline nounwind optnone uwtable }
+attributes #1 = { noinline nounwind optnone uwtable
"branch-target-enforcement" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+
+!0 = !{i32 8, !"branch-target-enforcement", i32 2}
DanielKristofKiss wrote:
Yes, it is for counter test as `bar` shouldn't get BTI bits.
If something goes wrong and the module flag is treated as `1` then it will get
BTI landing pads.
https://github.com/llvm/llvm-project/pull/86212
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[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
@@ -0,0 +1,35 @@
+; This file contains the new semantic of the branch-target-enforcement,
sign-return-address.
+; Used for test mixing a mixed link case and also verify the import too in llc.
+
+; RUN: llc %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define dso_local void @bar() #0 {
+entry:
+ ret void
+}
+; CHECK-LABEL: bar:
DanielKristofKiss wrote:
`bar` could come from a function that is decorated with
`__attribute__((branch-protection=none))` while the file compiled with
`-mbranch-protection=bti+pac-ret+b_key`.
Frontend already assigns the function attributes so in this case we want bar to
not have any pac instruction.
https://github.com/llvm/llvm-project/pull/86212
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[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
@@ -0,0 +1,35 @@ +; This file contains the new semantic of the branch-target-enforcement, sign-return-address. DanielKristofKiss wrote: done. https://github.com/llvm/llvm-project/pull/86212 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
@@ -0,0 +1,35 @@ +; This file contains the new semantic of the branch-target-enforcement, sign-return-address. +; Used for test mixing a mixed link case and also verify the import too in llc. + +; RUN: llc %s -o - | FileCheck %s DanielKristofKiss wrote: ack. https://github.com/llvm/llvm-project/pull/86212 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
@@ -0,0 +1,86 @@
+;; Test verifies inlining happens cross module when module flags are upgraded.
+;; `foo` and `main` are both old semantic while bar is the new semantic.
+;; Regression test for #82763
+
+; RUN: split-file %s %t
+; RUN: opt -module-summary %t/foo.s -o %t/foo.o
+; RUN: opt -module-summary %t/bar.s -o %t/bar.o
+; RUN: opt -module-summary %t/main.s -o %t/main.o
+; RUN: llvm-lto2 run %t/main.o %t/foo.o %t/bar.o -save-temps \
+; RUN: -o %t/t.exe \
+; RUN: -r=%t/foo.o,foo,plx \
+; RUN: -r=%t/bar.o,bar,plx \
+; RUN: -r=%t/main.o,foo,l \
+; RUN: -r=%t/main.o,bar,l \
+; RUN: -r=%t/main.o,main,plx 2>&1
+; RUN: llvm-dis %t/t.exe.1.4.opt.bc -o - | FileCheck %s
+
+; CHECK: define dso_local noundef i32 @main() local_unnamed_addr #0 {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i32 35
+; CHECK-NEXT: }
+
+; CHECK: attributes #0 = { {{.*}}"branch-target-enforcement"
"sign-return-address"="all" "sign-return-address-key"="b_key" }
+
+; CHECK: !llvm.module.flags = !{!0, !1, !2, !3}
+
+; CHECK: !0 = !{i32 8, !"branch-target-enforcement", i32 2}
+; CHECK: !1 = !{i32 8, !"sign-return-address", i32 2}
+; CHECK: !2 = !{i32 8, !"sign-return-address-all", i32 2}
+; CHECK: !3 = !{i32 8, !"sign-return-address-with-bkey", i32 2}
+
+
+;--- foo.s
DanielKristofKiss wrote:
done
https://github.com/llvm/llvm-project/pull/86212
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[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
@@ -5278,6 +5278,106 @@ void llvm::UpgradeFunctionAttributes(Function &F) {
}
}
+// Check if the module attribute is present and set to one.
+static bool isModuleAttributeOne(Module &M, const StringRef &ModAttr) {
+ const auto *Attr =
+ mdconst::extract_or_null(M.getModuleFlag(ModAttr));
+ return Attr && Attr->isOne();
+}
+
+// Check if the module attribute is present and set to two.
+static bool isModuleAttributeTwo(Module &M, const StringRef &ModAttr) {
+ const auto *Attr =
+ mdconst::extract_or_null(M.getModuleFlag(ModAttr));
+ return Attr && Attr->getZExtValue() == 2;
+}
+
+// Check if the function attribute is not present and set it.
+static void SetFunctionAttrIfNotSet(Function &F, StringRef FnAttrName,
+StringRef Value) {
+ if (!F.hasFnAttribute(FnAttrName))
+F.addFnAttr(FnAttrName, Value);
+}
+
+// Check if the function attribute is not present and set it if needed.
+// If the attribute is "false" then removes it.
+// If the attribute is "true" resets it to a valueless attribute.
+static void ConvertFunctionAttr(Function &F, bool Set, StringRef FnAttrName) {
+ if (!F.hasFnAttribute(FnAttrName)) {
+if (Set)
+ F.addFnAttr(FnAttrName);
+ } else {
+auto A = F.getFnAttribute(FnAttrName);
+if ("false" == A.getValueAsString())
+ F.removeFnAttr(FnAttrName);
+else if ("true" == A.getValueAsString()) {
+ F.removeFnAttr(FnAttrName);
+ F.addFnAttr(FnAttrName);
+}
+ }
+}
+
+void llvm::CopyModuleAttrToFunctions(Module &M) {
+ Triple T(M.getTargetTriple());
+ if (!T.isThumb() && !T.isARM() && !T.isAArch64())
+return;
+
+ if (isModuleAttributeTwo(M, "branch-target-enforcement"))
+return;
+ if (isModuleAttributeTwo(M, "branch-protection-pauth-lr"))
+return;
+ if (isModuleAttributeTwo(M, "guarded-control-stack"))
+return;
+ if (isModuleAttributeTwo(M, "sign-return-address"))
+return;
+
+ bool BTE = isModuleAttributeOne(M, "branch-target-enforcement");
+ bool BPPLR = isModuleAttributeOne(M, "branch-protection-pauth-lr");
+ bool GCS = isModuleAttributeOne(M, "guarded-control-stack");
+ bool SRA = isModuleAttributeOne(M, "sign-return-address");
+
+ StringRef SignTypeValue = "non-leaf";
+ if (SRA && isModuleAttributeOne(M, "sign-return-address-all"))
+SignTypeValue = "all";
+
+ StringRef SignKeyValue = "a_key";
DanielKristofKiss wrote:
added
https://github.com/llvm/llvm-project/pull/86212
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[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/86212
>From f2f3356da08d68dab4431f49d0921515560e4927 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 8 Mar 2024 15:06:28 +0100
Subject: [PATCH 1/2] BTI,GCS,PAC Module flag update.
Module flag is used to indicate the feature to be propagated to the
function. As now the frontend emits all attributes accoringly let's
help the automerger to only do work when old and new bitcodes are
merged.
Autoupgrade function attributes from Module attributes when needed.
---
clang/lib/CodeGen/CodeGenModule.cpp | 19 ++--
.../CodeGen/aarch64-sign-return-address.c | 12 +--
.../CodeGen/arm-branch-protection-attr-2.c| 8 +-
.../arm-ignore-branch-protection-option.c | 2 +-
llvm/include/llvm/IR/AutoUpgrade.h| 3 +
llvm/lib/AsmParser/LLParser.cpp | 1 +
llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +
llvm/lib/IR/AutoUpgrade.cpp | 100 +
llvm/lib/Linker/IRMover.cpp | 10 ++
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 +-
llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 2 +-
.../test/Bitcode/upgrade-branch-protection.ll | 15 +--
.../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 2 +-
llvm/test/LTO/AArch64/Inputs/foo.ll | 16 ---
llvm/test/LTO/AArch64/TestInputs/bar.ll | 35 ++
llvm/test/LTO/AArch64/TestInputs/foo.ll | 38 +++
llvm/test/LTO/AArch64/TestInputs/old.ll | 46
.../AArch64/link-branch-target-enforcement.ll | 5 +-
.../LTO/AArch64/link-sign-return-address.ll | 102 ++
llvm/test/Linker/link-arm-and-thumb.ll| 6 +-
llvm/test/ThinLTO/AArch64/aarch64_inline.ll | 86 +++
llvm/test/ThinLTO/AArch64/lit.local.cfg | 2 +
22 files changed, 468 insertions(+), 46 deletions(-)
delete mode 100644 llvm/test/LTO/AArch64/Inputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/bar.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/old.ll
create mode 100644 llvm/test/LTO/AArch64/link-sign-return-address.ll
create mode 100644 llvm/test/ThinLTO/AArch64/aarch64_inline.ll
create mode 100644 llvm/test/ThinLTO/AArch64/lit.local.cfg
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 227813ad44e8b8..6efc2283535f3a 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1176,22 +1176,29 @@ void CodeGenModule::Release() {
"tag-stack-memory-buildattr", 1);
if (T.isARM() || T.isThumb() || T.isAArch64()) {
+// Previously 1 is used and meant for the backed to derive the function
+// attribute form it. 2 now means function attributes already set for all
+// functions in this module, so no need to propagate those from the module
+// flag. Value is only used in case of LTO module merge because the backend
+// will see all required function attribute set already. Value is used
+// before modules got merged. Any posive value means the feature is active
+// and required binary markings need to be emit accordingly.
if (LangOpts.BranchTargetEnforcement)
getModule().addModuleFlag(llvm::Module::Min, "branch-target-enforcement",
-1);
+2);
if (LangOpts.BranchProtectionPAuthLR)
getModule().addModuleFlag(llvm::Module::Min,
"branch-protection-pauth-lr",
-1);
+2);
if (LangOpts.GuardedControlStack)
- getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 2);
if (LangOpts.hasSignReturnAddress())
- getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 2);
if (LangOpts.isSignReturnAddressScopeAll())
getModule().addModuleFlag(llvm::Module::Min, "sign-return-address-all",
-1);
+2);
if (!LangOpts.isSignReturnAddressWithAKey())
getModule().addModuleFlag(llvm::Module::Min,
-"sign-return-address-with-bkey", 1);
+"sign-return-address-with-bkey", 2);
if (getTriple().isOSLinux()) {
assert(getTriple().isOSBinFormatELF());
diff --git a/clang/test/CodeGen/aarch64-sign-return-address.c
b/clang/test/CodeGen/aarch64-sign-return-address.c
index 8bc54b1a56c38c..35c56889e07071 100644
--- a/clang/test/CodeGen/aarch64-sign-return-address.c
+++ b/clang/test/CodeGen/aarch64-sign-return-address.c
@@ -22,17 +22,17 @@
// NONE-NOT: !"branch-target-enforcement"
// ALL-NOT: !"branch-target-enforcement"
// PART-NOT: !"branch-targ
[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/101978
>From 4afadb9122c982c63f2b067661548a2c063590a5 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Mon, 5 Aug 2024 13:01:06 +0200
Subject: [PATCH 1/2] [Arm][AArch64][Clang] Respect function's branch
protection attributes.
Default attributes assigned to all functions according to the command line
parameters. Some functions might have their own attributes and we need to set
or remove attributes accordingly.
---
clang/lib/CodeGen/TargetInfo.cpp | 25 ---
clang/lib/CodeGen/TargetInfo.h| 3 +++
.../CodeGen/aarch64-branch-protection-attr.c | 13 +-
.../CodeGen/arm-branch-protection-attr-1.c| 6 +
4 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index 38faa50cf19cf2..ec05db0ecfac58 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -209,9 +209,28 @@ llvm::Value *TargetCodeGenInfo::createEnqueuedBlockKernel(
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
const TargetInfo::BranchProtectionInfo &BPI, llvm::Function &F) {
- llvm::AttrBuilder FuncAttrs(F.getContext());
- setBranchProtectionFnAttributes(BPI, FuncAttrs);
- F.addFnAttrs(FuncAttrs);
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+F.addFnAttr("sign-return-address", BPI.getSignReturnAddrStr());
+F.addFnAttr("sign-return-address-key", BPI.getSignKeyStr());
+ } else {
+if (F.hasFnAttribute("sign-return-address"))
+ F.removeFnAttr("sign-return-address");
+if (F.hasFnAttribute("sign-return-address-key"))
+ F.removeFnAttr("sign-return-address-key");
+ }
+
+ auto AddRemoveAttributeAsSet = [&](bool Set, const StringRef &ModAttr) {
+if (Set)
+ F.addFnAttr(ModAttr);
+else if (F.hasFnAttribute(ModAttr))
+ F.removeFnAttr(ModAttr);
+ };
+
+ AddRemoveAttributeAsSet(BPI.BranchTargetEnforcement,
+ "branch-target-enforcement");
+ AddRemoveAttributeAsSet(BPI.BranchProtectionPAuthLR,
+ "branch-protection-pauth-lr");
+ AddRemoveAttributeAsSet(BPI.GuardedControlStack, "guarded-control-stack");
}
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h
index 8f17c053f4783f..639717bd9580d0 100644
--- a/clang/lib/CodeGen/TargetInfo.h
+++ b/clang/lib/CodeGen/TargetInfo.h
@@ -418,10 +418,13 @@ class TargetCodeGenInfo {
return nullptr;
}
+ // Set the Branch Protection Attributes of the Function accordingly to the
+ // BPI. Might remove attributes if contradicts with the pass request.
static void
setBranchProtectionFnAttributes(const TargetInfo::BranchProtectionInfo &BPI,
llvm::Function &F);
+ // Add the Branch Protection Attributes of the FuncAttrs.
static void
setBranchProtectionFnAttributes(const TargetInfo::BranchProtectionInfo &BPI,
llvm::AttrBuilder &FuncAttrs);
diff --git a/clang/test/CodeGen/aarch64-branch-protection-attr.c
b/clang/test/CodeGen/aarch64-branch-protection-attr.c
index e7ae7fb1570c95..c66bce1bee6d36 100644
--- a/clang/test/CodeGen/aarch64-branch-protection-attr.c
+++ b/clang/test/CodeGen/aarch64-branch-protection-attr.c
@@ -1,6 +1,18 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a %s -o - \
// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mbranch-target-enforce %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mguarded-control-stack %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -msign-return-address=non-leaf
-msign-return-address-key=a_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -msign-return-address=all
-msign-return-address-key=b_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mbranch-protection-pauth-lr -msign-return-address=all
-msign-return-address-key=a_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mguarded-control-stack -mbranch-target-enforce
-mbranch-protection-pauth-lr -msign-return-address=
[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
@@ -209,9 +209,28 @@ llvm::Value *TargetCodeGenInfo::createEnqueuedBlockKernel(
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
const TargetInfo::BranchProtectionInfo &BPI, llvm::Function &F) {
- llvm::AttrBuilder FuncAttrs(F.getContext());
- setBranchProtectionFnAttributes(BPI, FuncAttrs);
- F.addFnAttrs(FuncAttrs);
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+F.addFnAttr("sign-return-address", BPI.getSignReturnAddrStr());
+F.addFnAttr("sign-return-address-key", BPI.getSignKeyStr());
+ } else {
+if (F.hasFnAttribute("sign-return-address"))
+ F.removeFnAttr("sign-return-address");
+if (F.hasFnAttribute("sign-return-address-key"))
+ F.removeFnAttr("sign-return-address-key");
+ }
+
+ auto AddRemoveAttributeAsSet = [&](bool Set, const StringRef &ModAttr) {
+if (Set)
+ F.addFnAttr(ModAttr);
+else if (F.hasFnAttribute(ModAttr))
+ F.removeFnAttr(ModAttr);
+ };
+
+ AddRemoveAttributeAsSet(BPI.BranchTargetEnforcement,
+ "branch-target-enforcement");
+ AddRemoveAttributeAsSet(BPI.BranchProtectionPAuthLR,
+ "branch-protection-pauth-lr");
+ AddRemoveAttributeAsSet(BPI.GuardedControlStack, "guarded-control-stack");
}
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
DanielKristofKiss wrote:
Thanks for the concern. I added more comments and renamed the AttrBuilder
version to make it more distinct.
https://github.com/llvm/llvm-project/pull/101978
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[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
https://github.com/DanielKristofKiss closed https://github.com/llvm/llvm-project/pull/101978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
DanielKristofKiss wrote: /cherry-pick 9e9fa00 https://github.com/llvm/llvm-project/pull/101978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][ARM] Make CRC and DSP intrinsics always available. (PR #107417)
https://github.com/DanielKristofKiss created
https://github.com/llvm/llvm-project/pull/107417
Both feature has target feature so can be checked if the usage is valid.
>From 9dadc9bffc40e02dff9ef6a1d79968c8980892f4 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Thu, 5 Sep 2024 16:42:43 +0200
Subject: [PATCH] [Clang][ARM] Make CRC and DSP intrinsics always available.
Both feature has target feature so can be checked if the usage is valid.
---
clang/lib/Headers/arm_acle.h | 39 +-
clang/test/CodeGen/arm_acle.c | 76 +--
2 files changed, 91 insertions(+), 24 deletions(-)
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index 1518b0c4c8428f..b1dc90f84ad36f 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -264,28 +264,28 @@ __rbitl(unsigned long __t) {
}
/* 8.3 16-bit multiplications */
-#if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP
-static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
+#if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE
+static __inline__ int32_t __attribute__((__always_inline__,__nodebug__,
target("dsp")))
__smulbb(int32_t __a, int32_t __b) {
return __builtin_arm_smulbb(__a, __b);
}
-static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__,__nodebug__,
target("dsp")))
__smulbt(int32_t __a, int32_t __b) {
return __builtin_arm_smulbt(__a, __b);
}
-static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__,__nodebug__,
target("dsp")))
__smultb(int32_t __a, int32_t __b) {
return __builtin_arm_smultb(__a, __b);
}
-static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__,__nodebug__,
target("dsp")))
__smultt(int32_t __a, int32_t __b) {
return __builtin_arm_smultt(__a, __b);
}
-static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__,__nodebug__,
target("dsp")))
__smulwb(int32_t __a, int32_t __b) {
return __builtin_arm_smulwb(__a, __b);
}
-static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__,__nodebug__,
target("dsp")))
__smulwt(int32_t __a, int32_t __b) {
return __builtin_arm_smulwt(__a, __b);
}
@@ -304,46 +304,46 @@ __smulwt(int32_t __a, int32_t __b) {
#endif
/* 8.4.2 Saturating addition and subtraction intrinsics */
-#if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+#if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__qadd(int32_t __t, int32_t __v) {
return __builtin_arm_qadd(__t, __v);
}
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__qsub(int32_t __t, int32_t __v) {
return __builtin_arm_qsub(__t, __v);
}
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__qdbl(int32_t __t) {
return __builtin_arm_qadd(__t, __t);
}
#endif
/* 8.4.3 Accumulating multiplications */
-#if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+#if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__smlabb(int32_t __a, int32_t __b, int32_t __c) {
return __builtin_arm_smlabb(__a, __b, __c);
}
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__smlabt(int32_t __a, int32_t __b, int32_t __c) {
return __builtin_arm_smlabt(__a, __b, __c);
}
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__smlatb(int32_t __a, int32_t __b, int32_t __c) {
return __builtin_arm_smlatb(__a, __b, __c);
}
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__smlatt(int32_t __a, int32_t __b, int32_t __c) {
return __builtin_arm_smlatt(__a, __b, __c);
}
-static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ int32_t __attribute__((__always_inline__, __nodebug__,
target("dsp")))
__smlawb(int32_t __a, int32_t __b, int32_t __c) {
return __builtin_arm_smlawb(__a, __b, __c);
}
-static __inline__ int32_t __attribute__((__al
[clang] [Clang][ARM] Make CRC and DSP intrinsics always available. (PR #107417)
DanielKristofKiss wrote: Clang-format failure is expected as I kept intentionally the format to match with the rest of the file. https://github.com/llvm/llvm-project/pull/107417 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss updated https://github.com/llvm/llvm-project/pull/82819 >From df64bb1a12ea2b2a89151fa034a16cd641129347 Mon Sep 17 00:00:00 2001 From: Daniel Kiss Date: Mon, 22 Jan 2024 11:33:15 +0100 Subject: [PATCH] Emit attributes for functions always. Branch protection, sign return address, guarded control stack flags are only emitted as module flags if not specified per function. The inliner might inline functions with different set of flags as it doesn't see the flags. In case of LTO build the module flags get merged with the `min` rule which means if one of the modules is not build with PAC/BTI then the features will be turned off on all functions due to the functions takes the branch-protection and sign-return-address features from the module flags. The sign-return-address is function level option therefore it is expected functions from files that are compiled with -mbranch-protection=pac-ret to be protected but in LTO case this might not happen. This patch adds the flags to functions in case of an LTO build therefore they don't need to rely on the module flag. --- clang/include/clang/Basic/TargetInfo.h| 44 +-- clang/lib/CodeGen/Targets/AArch64.cpp | 43 ++ clang/lib/CodeGen/Targets/ARM.cpp | 8 ++-- .../CodeGen/aarch64-branch-protection-attr.c | 26 +-- .../CodeGen/aarch64-sign-return-address.c | 12 +++-- .../CodeGen/arm-branch-protection-attr-1.c| 12 ++--- .../CodeGen/arm-branch-protection-attr-2.c| 13 -- .../test/Frontend/arm-branch-protection-lto.c | 24 ++ .../SelectionDAG/SelectionDAGBuilder.cpp | 12 + llvm/lib/IR/Verifier.cpp | 20 - llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +-- .../AArch64/AArch64MachineFunctionInfo.cpp| 37 ++-- .../lib/Target/ARM/ARMMachineFunctionInfo.cpp | 22 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 6 ++- ...ranch-target-enforcement-indirect-calls.ll | 18 .../CodeGen/AArch64/bti-branch-relaxation.ll | 2 +- llvm/test/CodeGen/AArch64/kcfi-bti.ll | 7 +-- ...machine-outliner-2fixup-blr-terminator.mir | 2 +- .../CodeGen/AArch64/machine-outliner-bti.mir | 2 +- .../AArch64/machine-outliner-outline-bti.ll | 4 +- .../AArch64/note-gnu-property-pac-bti-0.ll| 2 +- .../AArch64/note-gnu-property-pac-bti-4.ll| 4 +- .../AArch64/pacbti-llvm-generated-funcs-1.ll | 4 +- .../AArch64/pacbti-llvm-generated-funcs-2.ll | 10 ++--- .../CodeGen/AArch64/pacbti-module-attrs.ll| 12 ++--- .../AArch64/patchable-function-entry-bti.ll | 10 ++--- .../CodeGen/AArch64/setjmp-bti-outliner.ll| 15 +++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 6 +-- .../AArch64/sign-return-address-pauth-lr.ll | 36 +++ .../CodeGen/AArch64/sign-return-address.ll| 8 ++-- llvm/test/CodeGen/AArch64/wineh-bti.ll| 7 +-- llvm/test/CodeGen/AArch64/wineh-pac.ll| 7 +-- llvm/test/CodeGen/ARM/setjmp-bti-basic.ll | 5 +-- llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll | 7 +-- llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll | 7 +-- .../CodeGen/Thumb2/bti-indirect-branches.ll | 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-1.ll| 9 ++-- llvm/test/CodeGen/Thumb2/bti-outliner-2.ll| 12 ++--- .../CodeGen/Thumb2/bti-outliner-cost-2.ll | 6 +-- .../test/CodeGen/Thumb2/bti-pac-replace-1.mir | 8 +--- llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll | 7 +-- llvm/test/CodeGen/Thumb2/jump-table-bti.ll| 10 ++--- llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll| 6 +-- .../Thumb2/pacbti-m-indirect-tail-call.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-3.ll | 2 +- .../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 6 +-- .../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-overalign.ll | 2 +- .../test/CodeGen/Thumb2/pacbti-m-stack-arg.ll | 4 +- .../Thumb2/pacbti-m-unsupported-arch.ll | 8 +--- .../test/CodeGen/Thumb2/pacbti-m-varargs-1.ll | 4 +- .../test/CodeGen/Thumb2/pacbti-m-varargs-2.ll | 4 +- llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 2 +- .../AArch64/link-branch-target-enforcement.ll | 2 +- .../Inline/inline-sign-return-address.ll | 13 +++--- .../LowerTypeTests/function-arm-thumb.ll | 2 +- .../LowerTypeTests/function-thumb-bti.ll | 4 +- .../Transforms/LowerTypeTests/function.ll | 4 +- llvm/test/Verifier/branch-prot-attrs.ll | 16 ++- 60 files changed, 292 insertions(+), 316 deletions(-) create mode 100644 clang/test/Frontend/arm-branch-protection-lto.c diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 9b0ae2102e098..1f208b40f92cb 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -32,7 +32,9 @@ #include "llvm/ADT/StringRef.h" #include "llvm/
[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/86212
>From f2f3356da08d68dab4431f49d0921515560e4927 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 8 Mar 2024 15:06:28 +0100
Subject: [PATCH] BTI,GCS,PAC Module flag update.
Module flag is used to indicate the feature to be propagated to the
function. As now the frontend emits all attributes accoringly let's
help the automerger to only do work when old and new bitcodes are
merged.
Autoupgrade function attributes from Module attributes when needed.
---
clang/lib/CodeGen/CodeGenModule.cpp | 19 ++--
.../CodeGen/aarch64-sign-return-address.c | 12 +--
.../CodeGen/arm-branch-protection-attr-2.c| 8 +-
.../arm-ignore-branch-protection-option.c | 2 +-
llvm/include/llvm/IR/AutoUpgrade.h| 3 +
llvm/lib/AsmParser/LLParser.cpp | 1 +
llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +
llvm/lib/IR/AutoUpgrade.cpp | 100 +
llvm/lib/Linker/IRMover.cpp | 10 ++
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 +-
llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 2 +-
.../test/Bitcode/upgrade-branch-protection.ll | 15 +--
.../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 2 +-
llvm/test/LTO/AArch64/Inputs/foo.ll | 16 ---
llvm/test/LTO/AArch64/TestInputs/bar.ll | 35 ++
llvm/test/LTO/AArch64/TestInputs/foo.ll | 38 +++
llvm/test/LTO/AArch64/TestInputs/old.ll | 46
.../AArch64/link-branch-target-enforcement.ll | 5 +-
.../LTO/AArch64/link-sign-return-address.ll | 102 ++
llvm/test/Linker/link-arm-and-thumb.ll| 6 +-
llvm/test/ThinLTO/AArch64/aarch64_inline.ll | 86 +++
llvm/test/ThinLTO/AArch64/lit.local.cfg | 2 +
22 files changed, 468 insertions(+), 46 deletions(-)
delete mode 100644 llvm/test/LTO/AArch64/Inputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/bar.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/foo.ll
create mode 100644 llvm/test/LTO/AArch64/TestInputs/old.ll
create mode 100644 llvm/test/LTO/AArch64/link-sign-return-address.ll
create mode 100644 llvm/test/ThinLTO/AArch64/aarch64_inline.ll
create mode 100644 llvm/test/ThinLTO/AArch64/lit.local.cfg
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 227813ad44e8b..6efc2283535f3 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1176,22 +1176,29 @@ void CodeGenModule::Release() {
"tag-stack-memory-buildattr", 1);
if (T.isARM() || T.isThumb() || T.isAArch64()) {
+// Previously 1 is used and meant for the backed to derive the function
+// attribute form it. 2 now means function attributes already set for all
+// functions in this module, so no need to propagate those from the module
+// flag. Value is only used in case of LTO module merge because the backend
+// will see all required function attribute set already. Value is used
+// before modules got merged. Any posive value means the feature is active
+// and required binary markings need to be emit accordingly.
if (LangOpts.BranchTargetEnforcement)
getModule().addModuleFlag(llvm::Module::Min, "branch-target-enforcement",
-1);
+2);
if (LangOpts.BranchProtectionPAuthLR)
getModule().addModuleFlag(llvm::Module::Min,
"branch-protection-pauth-lr",
-1);
+2);
if (LangOpts.GuardedControlStack)
- getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "guarded-control-stack", 2);
if (LangOpts.hasSignReturnAddress())
- getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 1);
+ getModule().addModuleFlag(llvm::Module::Min, "sign-return-address", 2);
if (LangOpts.isSignReturnAddressScopeAll())
getModule().addModuleFlag(llvm::Module::Min, "sign-return-address-all",
-1);
+2);
if (!LangOpts.isSignReturnAddressWithAKey())
getModule().addModuleFlag(llvm::Module::Min,
-"sign-return-address-with-bkey", 1);
+"sign-return-address-with-bkey", 2);
if (getTriple().isOSLinux()) {
assert(getTriple().isOSBinFormatELF());
diff --git a/clang/test/CodeGen/aarch64-sign-return-address.c
b/clang/test/CodeGen/aarch64-sign-return-address.c
index 8bc54b1a56c38..35c56889e0707 100644
--- a/clang/test/CodeGen/aarch64-sign-return-address.c
+++ b/clang/test/CodeGen/aarch64-sign-return-address.c
@@ -22,17 +22,17 @@
// NONE-NOT: !"branch-target-enforcement"
// ALL-NOT: !"branch-target-enforcement"
// PART-NOT: !"branch-target-enfor
[clang] [NFC][Clang] Move set functions out BranchProtectionInfo. (PR #98451)
https://github.com/DanielKristofKiss closed https://github.com/llvm/llvm-project/pull/98451 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/83277
>From 0c3118713387246dc1c503f3792ba5af82e6b5eb Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 15:18:31 +0100
Subject: [PATCH 1/8] Add branch protection attributes to the defaults.
These attributes are no longer inherited from the module flags,
therefore need to be added for synthetic functions.
---
clang/lib/CodeGen/CGCall.cpp | 16 ++
.../CodeGenCXX/arm64-generated-fn-attr.cpp| 30 +++
2 files changed, 46 insertions(+)
create mode 100644 clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 7e7b2b395f7d6..7b93f6d2dded1 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2030,6 +2030,22 @@ static void getTrivialDefaultFunctionAttributes(
std::tie(Var, Value) = Attr.split('=');
FuncAttrs.addAttribute(Var, Value);
}
+
+ TargetInfo::BranchProtectionInfo BPI(LangOpts);
+
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
+FuncAttrs.addAttribute(
+"sign-return-address-key",
+BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
+ : "b_key");
+ }
+ if (BPI.BranchTargetEnforcement)
+FuncAttrs.addAttribute("branch-target-enforcement", "true");
+ if (BPI.BranchProtectionPAuthLR)
+FuncAttrs.addAttribute("branch-protection-pauth-lr", "true");
+ if (BPI.GuardedControlStack)
+FuncAttrs.addAttribute("guarded-control-stack", "true");
}
/// Merges `target-features` from \TargetOpts and \F, and sets the result in
diff --git a/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
new file mode 100644
index 0..8daf44abd4f91
--- /dev/null
+++ b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -triple aarch64-none-none -mbranch-target-enforce
-msign-return-address=all -fcxx-exceptions -fexceptions -emit-llvm %s -o - |
FileCheck %s --check-prefixes=CHECK
+
+// Check that functions generated by clang have the correct attributes
+
+class Example {
+public:
+ Example();
+ int fn();
+};
+
+// Initialization of var1 causes __cxx_global_var_init and __tls_init to be
generated
+thread_local Example var1;
+extern thread_local Example var2;
+extern void fn();
+
+int testfn() noexcept {
+ // Calling fn in a noexcept function causes __clang_call_terminate to be
generated
+ fn();
+ // Use of var1 and var2 causes TLS wrapper functions to be generated
+ return var1.fn() + var2.fn();
+}
+
+// CHECK: define {{.*}} @__cxx_global_var_init() [[ATTR1:#[0-9]+]]
+// CHECK: define {{.*}} @__clang_call_terminate({{.*}}) [[ATTR2:#[0-9]+]]
+// CHECK: define {{.*}} @_ZTW4var1() [[ATTR1]]
+// CHECK: define {{.*}} @_ZTW4var2() [[ATTR1]]
+// CHECK: define {{.*}} @__tls_init() [[ATTR1]]
+
+// CHECK: attributes [[ATTR1]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
+// CHECK: attributes [[ATTR2]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
>From 0e2a9e129bcb4f569a443494b9266ae482c73c94 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 17:38:49 +0100
Subject: [PATCH 2/8] fixup! [Clang][Arm][AArch64] Add branch protection
attributes to the defaults.
---
clang/lib/CodeGen/CGCall.cpp | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 7b93f6d2dded1..131666d732b3d 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2035,10 +2035,7 @@ static void getTrivialDefaultFunctionAttributes(
if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
-FuncAttrs.addAttribute(
-"sign-return-address-key",
-BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
- : "b_key");
+FuncAttrs.addAttribute("sign-return-address-key", BPI.getSignKeyStr());
}
if (BPI.BranchTargetEnforcement)
FuncAttrs.addAttribute("branch-target-enforcement", "true");
>From 735d24d5fe8bb4f37d87cb2345cbe45d53b1ba42 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Mon, 4 Mar 2024 17:31:31 +0100
Subject: [PATCH 3/8] Move TargetInfo changes over.
Dropping restrictions on the member functions.
---
clang/include/clang/Basic/TargetInfo.h | 15 ---
1 file changed, 15 deletions(-)
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 1f208b40f92cb..d8075ee97972e 1
[libunwind] [libunwind] Undefined behaviour pointer arithmetic with null pointer (PR #98648)
https://github.com/DanielKristofKiss created
https://github.com/llvm/llvm-project/pull/98648
Fixes #91144
>From 240add341b2c0a1be3d1ebf21938e70e51669126 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 12 Jul 2024 15:56:40 +0200
Subject: [PATCH] [libunwind] Fix ubsan issue
---
libunwind/src/UnwindCursor.hpp | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp
index 2ec60e4c123d5..01a61cea53ffa 100644
--- a/libunwind/src/UnwindCursor.hpp
+++ b/libunwind/src/UnwindCursor.hpp
@@ -230,8 +230,13 @@ void DwarfFDECache::iterateCacheEntries(void (*func)(
}
#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-
-#define arrayoffsetof(type, index, field) ((size_t)(&((type *)0)[index].field))
+template
+__attribute__((no_sanitize("undefined"))) static inline size_t
+_arrayoffsetof(int index, FIELD TYPE::*field) {
+ return ((size_t)(&(((TYPE *)0)[index].*field)));
+}
+#define arrayoffsetof(type, index, field)
\
+ _arrayoffsetof(index, &type::field)
#if defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND)
template class UnwindSectionHeader {
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[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/DanielKristofKiss closed https://github.com/llvm/llvm-project/pull/83277 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [libunwind] Undefined behaviour pointer arithmetic with null pointer (PR #98648)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/98648
>From 240add341b2c0a1be3d1ebf21938e70e51669126 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 12 Jul 2024 15:56:40 +0200
Subject: [PATCH 1/2] [libunwind] Fix ubsan issue
---
libunwind/src/UnwindCursor.hpp | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp
index 2ec60e4c123d5..01a61cea53ffa 100644
--- a/libunwind/src/UnwindCursor.hpp
+++ b/libunwind/src/UnwindCursor.hpp
@@ -230,8 +230,13 @@ void DwarfFDECache::iterateCacheEntries(void (*func)(
}
#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-
-#define arrayoffsetof(type, index, field) ((size_t)(&((type *)0)[index].field))
+template
+__attribute__((no_sanitize("undefined"))) static inline size_t
+_arrayoffsetof(int index, FIELD TYPE::*field) {
+ return ((size_t)(&(((TYPE *)0)[index].*field)));
+}
+#define arrayoffsetof(type, index, field)
\
+ _arrayoffsetof(index, &type::field)
#if defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND)
template class UnwindSectionHeader {
>From a9f5774e9847082ce16f2a04e8a4d4ce456dfc62 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 12 Jul 2024 20:59:48 +0200
Subject: [PATCH 2/2] Simplify the code.
---
libunwind/src/UnwindCursor.hpp | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp
index 01a61cea53ffa..1fa95b4ebee19 100644
--- a/libunwind/src/UnwindCursor.hpp
+++ b/libunwind/src/UnwindCursor.hpp
@@ -230,13 +230,8 @@ void DwarfFDECache::iterateCacheEntries(void (*func)(
}
#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-template
-__attribute__((no_sanitize("undefined"))) static inline size_t
-_arrayoffsetof(int index, FIELD TYPE::*field) {
- return ((size_t)(&(((TYPE *)0)[index].*field)));
-}
#define arrayoffsetof(type, index, field)
\
- _arrayoffsetof(index, &type::field)
+ (sizeof(type) * (index) + offsetof(type, field))
#if defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND)
template class UnwindSectionHeader {
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[libunwind] [libunwind] Undefined behaviour pointer arithmetic with null pointer (PR #98648)
@@ -230,8 +230,13 @@ void DwarfFDECache::iterateCacheEntries(void (*func)(
}
#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-
-#define arrayoffsetof(type, index, field) ((size_t)(&((type *)0)[index].field))
+template
+__attribute__((no_sanitize("undefined"))) static inline size_t
+_arrayoffsetof(int index, FIELD TYPE::*field) {
+ return ((size_t)(&(((TYPE *)0)[index].*field)));
+}
+#define arrayoffsetof(type, index, field)
\
+ _arrayoffsetof(index, &type::field)
DanielKristofKiss wrote:
Correct (facepalm) no need for my overcomplicated code... Thanks!
https://github.com/llvm/llvm-project/pull/98648
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[clang] [llvm] [PAC][Driver] Support `pauthtest` ABI for AArch64 Linux triples (PR #97237)
@@ -0,0 +1,4 @@ +// RUN: %clang --target=aarch64-linux-pauthtest --sysroot=%S/Inputs/multilib_aarch64_linux_tree -### -c %s 2>&1 | FileCheck %s DanielKristofKiss wrote: Looks this is not used: "clang/test/Driver/Inputs/multilib_aarch64_linux_tree/usr/include/aarch64-linux-gnu/.keep" BTW we could just add to the test: `rm -rf %t.dir && mkdir -p %t.dir/multilib_aarch64_linux_tree/usr/include/aarch64-linux-gnu/ && mkdir -p %t.dir/multilib_aarch64_linux_tree/usr/include/aarch64-linux-pauthtest/` https://github.com/llvm/llvm-project/pull/97237 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [libunwind] Undefined behaviour pointer arithmetic with null pointer (PR #98648)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/98648
>From 240add341b2c0a1be3d1ebf21938e70e51669126 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 12 Jul 2024 15:56:40 +0200
Subject: [PATCH 1/2] [libunwind] Fix ubsan issue
---
libunwind/src/UnwindCursor.hpp | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp
index 2ec60e4c123d5..01a61cea53ffa 100644
--- a/libunwind/src/UnwindCursor.hpp
+++ b/libunwind/src/UnwindCursor.hpp
@@ -230,8 +230,13 @@ void DwarfFDECache::iterateCacheEntries(void (*func)(
}
#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-
-#define arrayoffsetof(type, index, field) ((size_t)(&((type *)0)[index].field))
+template
+__attribute__((no_sanitize("undefined"))) static inline size_t
+_arrayoffsetof(int index, FIELD TYPE::*field) {
+ return ((size_t)(&(((TYPE *)0)[index].*field)));
+}
+#define arrayoffsetof(type, index, field)
\
+ _arrayoffsetof(index, &type::field)
#if defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND)
template class UnwindSectionHeader {
>From a9f5774e9847082ce16f2a04e8a4d4ce456dfc62 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Fri, 12 Jul 2024 20:59:48 +0200
Subject: [PATCH 2/2] Simplify the code.
---
libunwind/src/UnwindCursor.hpp | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp
index 01a61cea53ffa..1fa95b4ebee19 100644
--- a/libunwind/src/UnwindCursor.hpp
+++ b/libunwind/src/UnwindCursor.hpp
@@ -230,13 +230,8 @@ void DwarfFDECache::iterateCacheEntries(void (*func)(
}
#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-template
-__attribute__((no_sanitize("undefined"))) static inline size_t
-_arrayoffsetof(int index, FIELD TYPE::*field) {
- return ((size_t)(&(((TYPE *)0)[index].*field)));
-}
#define arrayoffsetof(type, index, field)
\
- _arrayoffsetof(index, &type::field)
+ (sizeof(type) * (index) + offsetof(type, field))
#if defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND)
template class UnwindSectionHeader {
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[libunwind] [libunwind] Undefined behaviour pointer arithmetic with null pointer (PR #98648)
https://github.com/DanielKristofKiss ready_for_review https://github.com/llvm/llvm-project/pull/98648 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [libunwind] Undefined behaviour pointer arithmetic with null pointer (PR #98648)
https://github.com/DanielKristofKiss closed https://github.com/llvm/llvm-project/pull/98648 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
https://github.com/DanielKristofKiss created
https://github.com/llvm/llvm-project/pull/101978
Default attributes assigned to all functions according to the command line
parameters. Some functions might have their own attributes and we need to set
or remove attributes accordingly.
Tests are updated to test this scenarios too.
>From 4afadb9122c982c63f2b067661548a2c063590a5 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Mon, 5 Aug 2024 13:01:06 +0200
Subject: [PATCH] [Arm][AArch64][Clang] Respect function's branch protection
attributes.
Default attributes assigned to all functions according to the command line
parameters. Some functions might have their own attributes and we need to set
or remove attributes accordingly.
---
clang/lib/CodeGen/TargetInfo.cpp | 25 ---
clang/lib/CodeGen/TargetInfo.h| 3 +++
.../CodeGen/aarch64-branch-protection-attr.c | 13 +-
.../CodeGen/arm-branch-protection-attr-1.c| 6 +
4 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index 38faa50cf19cf..ec05db0ecfac5 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -209,9 +209,28 @@ llvm::Value *TargetCodeGenInfo::createEnqueuedBlockKernel(
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
const TargetInfo::BranchProtectionInfo &BPI, llvm::Function &F) {
- llvm::AttrBuilder FuncAttrs(F.getContext());
- setBranchProtectionFnAttributes(BPI, FuncAttrs);
- F.addFnAttrs(FuncAttrs);
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+F.addFnAttr("sign-return-address", BPI.getSignReturnAddrStr());
+F.addFnAttr("sign-return-address-key", BPI.getSignKeyStr());
+ } else {
+if (F.hasFnAttribute("sign-return-address"))
+ F.removeFnAttr("sign-return-address");
+if (F.hasFnAttribute("sign-return-address-key"))
+ F.removeFnAttr("sign-return-address-key");
+ }
+
+ auto AddRemoveAttributeAsSet = [&](bool Set, const StringRef &ModAttr) {
+if (Set)
+ F.addFnAttr(ModAttr);
+else if (F.hasFnAttribute(ModAttr))
+ F.removeFnAttr(ModAttr);
+ };
+
+ AddRemoveAttributeAsSet(BPI.BranchTargetEnforcement,
+ "branch-target-enforcement");
+ AddRemoveAttributeAsSet(BPI.BranchProtectionPAuthLR,
+ "branch-protection-pauth-lr");
+ AddRemoveAttributeAsSet(BPI.GuardedControlStack, "guarded-control-stack");
}
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h
index 8f17c053f4783..639717bd9580d 100644
--- a/clang/lib/CodeGen/TargetInfo.h
+++ b/clang/lib/CodeGen/TargetInfo.h
@@ -418,10 +418,13 @@ class TargetCodeGenInfo {
return nullptr;
}
+ // Set the Branch Protection Attributes of the Function accordingly to the
+ // BPI. Might remove attributes if contradicts with the pass request.
static void
setBranchProtectionFnAttributes(const TargetInfo::BranchProtectionInfo &BPI,
llvm::Function &F);
+ // Add the Branch Protection Attributes of the FuncAttrs.
static void
setBranchProtectionFnAttributes(const TargetInfo::BranchProtectionInfo &BPI,
llvm::AttrBuilder &FuncAttrs);
diff --git a/clang/test/CodeGen/aarch64-branch-protection-attr.c
b/clang/test/CodeGen/aarch64-branch-protection-attr.c
index e7ae7fb1570c9..c66bce1bee6d3 100644
--- a/clang/test/CodeGen/aarch64-branch-protection-attr.c
+++ b/clang/test/CodeGen/aarch64-branch-protection-attr.c
@@ -1,6 +1,18 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a %s -o - \
// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mbranch-target-enforce %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mguarded-control-stack %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -msign-return-address=non-leaf
-msign-return-address-key=a_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -msign-return-address=all
-msign-return-address-key=b_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mbranch-protection-pauth-lr -msign-return-address=all
-msign-return-address-key=a_key %s -o - \
+// RUN: |
[libunwind] [libunwind] Add GCS support for AArch64 (PR #99335)
@@ -680,7 +680,7 @@ DEFINE_LIBUNWIND_FUNCTION(__libunwind_Registers_arm64_jumpto) ldrx16, [x0, #0x0F8] ldpx0, x1, [x0, #0x000] // restore x0,x1 movsp,x16 // restore sp - retx30// jump to pc DanielKristofKiss wrote: If the application is compiled with BTI then `br x30` will cause an exception as it jumps to a non landing pad instruction. (We only generate landing pads for `return-twice` locations but a normal `catch` block won't get it) https://github.com/llvm/llvm-project/pull/99335 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [PAC][AArch64] Support init/fini array signing (PR #96478)
https://github.com/DanielKristofKiss approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/96478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/101978
>From 4afadb9122c982c63f2b067661548a2c063590a5 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Mon, 5 Aug 2024 13:01:06 +0200
Subject: [PATCH] [Arm][AArch64][Clang] Respect function's branch protection
attributes.
Default attributes assigned to all functions according to the command line
parameters. Some functions might have their own attributes and we need to set
or remove attributes accordingly.
---
clang/lib/CodeGen/TargetInfo.cpp | 25 ---
clang/lib/CodeGen/TargetInfo.h| 3 +++
.../CodeGen/aarch64-branch-protection-attr.c | 13 +-
.../CodeGen/arm-branch-protection-attr-1.c| 6 +
4 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index 38faa50cf19cf..ec05db0ecfac5 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -209,9 +209,28 @@ llvm::Value *TargetCodeGenInfo::createEnqueuedBlockKernel(
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
const TargetInfo::BranchProtectionInfo &BPI, llvm::Function &F) {
- llvm::AttrBuilder FuncAttrs(F.getContext());
- setBranchProtectionFnAttributes(BPI, FuncAttrs);
- F.addFnAttrs(FuncAttrs);
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+F.addFnAttr("sign-return-address", BPI.getSignReturnAddrStr());
+F.addFnAttr("sign-return-address-key", BPI.getSignKeyStr());
+ } else {
+if (F.hasFnAttribute("sign-return-address"))
+ F.removeFnAttr("sign-return-address");
+if (F.hasFnAttribute("sign-return-address-key"))
+ F.removeFnAttr("sign-return-address-key");
+ }
+
+ auto AddRemoveAttributeAsSet = [&](bool Set, const StringRef &ModAttr) {
+if (Set)
+ F.addFnAttr(ModAttr);
+else if (F.hasFnAttribute(ModAttr))
+ F.removeFnAttr(ModAttr);
+ };
+
+ AddRemoveAttributeAsSet(BPI.BranchTargetEnforcement,
+ "branch-target-enforcement");
+ AddRemoveAttributeAsSet(BPI.BranchProtectionPAuthLR,
+ "branch-protection-pauth-lr");
+ AddRemoveAttributeAsSet(BPI.GuardedControlStack, "guarded-control-stack");
}
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h
index 8f17c053f4783..639717bd9580d 100644
--- a/clang/lib/CodeGen/TargetInfo.h
+++ b/clang/lib/CodeGen/TargetInfo.h
@@ -418,10 +418,13 @@ class TargetCodeGenInfo {
return nullptr;
}
+ // Set the Branch Protection Attributes of the Function accordingly to the
+ // BPI. Might remove attributes if contradicts with the pass request.
static void
setBranchProtectionFnAttributes(const TargetInfo::BranchProtectionInfo &BPI,
llvm::Function &F);
+ // Add the Branch Protection Attributes of the FuncAttrs.
static void
setBranchProtectionFnAttributes(const TargetInfo::BranchProtectionInfo &BPI,
llvm::AttrBuilder &FuncAttrs);
diff --git a/clang/test/CodeGen/aarch64-branch-protection-attr.c
b/clang/test/CodeGen/aarch64-branch-protection-attr.c
index e7ae7fb1570c9..c66bce1bee6d3 100644
--- a/clang/test/CodeGen/aarch64-branch-protection-attr.c
+++ b/clang/test/CodeGen/aarch64-branch-protection-attr.c
@@ -1,6 +1,18 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a %s -o - \
// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mbranch-target-enforce %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mguarded-control-stack %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -msign-return-address=non-leaf
-msign-return-address-key=a_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -msign-return-address=all
-msign-return-address-key=b_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mbranch-protection-pauth-lr -msign-return-address=all
-msign-return-address-key=a_key %s -o - \
+// RUN: | FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -target-cpu generic
-target-feature +v8.5a -mguarded-control-stack -mbranch-target-enforce
-mbranch-protection-pauth-lr -msign-return-address=all
-msig
[clang] [llvm] [PAC][Driver] Implement `-mbranch-protection=pauthabi` option (PR #97237)
@@ -1537,11 +1570,16 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args, if (!isAArch64 && PBP.Key == "b_key") D.Diag(diag::warn_unsupported_branch_protection) << "b-key" << A->getAsString(Args); +if (!isAArch64 && PBP.HasPauthABI) + D.Diag(diag::warn_unsupported_branch_protection) + << "pauthabi" << A->getAsString(Args); Scope = PBP.Scope; Key = PBP.Key; BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR; IndirectBranches = PBP.BranchTargetEnforcement; GuardedControlStack = PBP.GuardedControlStack; +if (isAArch64 && PBP.HasPauthABI) DanielKristofKiss wrote: FYI - I'm going to change the `sign-return-address` and variants to be a function flag. (#82819) `bti` - All `BRA*` and `BLRA*` instructions set the `PSTATE.BTYPE`. I prefer to check the [pseudo code](https://developer.arm.com/documentation/ddi0602/2022-06/Base-Instructions/BLRAA--BLRAAZ--BLRAB--BLRABZ--Branch-with-Link-to-Register--with-pointer-authentication- )for this things (see BTypeNext) IMHO `pauthabi+bti` makes sense as they are complementary while other option are overlapping. We can introduce this combination later. https://github.com/llvm/llvm-project/pull/97237 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
DanielKristofKiss wrote: I'm planning to merge this and subsequent patches this week, please let me know if you any more concerns. Thanks! https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
https://github.com/DanielKristofKiss closed https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/83277
>From c421b6b9c167e82cedc5db2a67f47d3ba12deba9 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 15:18:31 +0100
Subject: [PATCH 1/5] Add branch protection attributes to the defaults.
These attributes are no longer inherited from the module flags,
therefore need to be added for synthetic functions.
---
clang/lib/CodeGen/CGCall.cpp | 16 ++
.../CodeGenCXX/arm64-generated-fn-attr.cpp| 30 +++
2 files changed, 46 insertions(+)
create mode 100644 clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 13f68237b464d..5b59c77353675 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2022,6 +2022,22 @@ static void getTrivialDefaultFunctionAttributes(
std::tie(Var, Value) = Attr.split('=');
FuncAttrs.addAttribute(Var, Value);
}
+
+ TargetInfo::BranchProtectionInfo BPI(LangOpts);
+
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
+FuncAttrs.addAttribute(
+"sign-return-address-key",
+BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
+ : "b_key");
+ }
+ if (BPI.BranchTargetEnforcement)
+FuncAttrs.addAttribute("branch-target-enforcement", "true");
+ if (BPI.BranchProtectionPAuthLR)
+FuncAttrs.addAttribute("branch-protection-pauth-lr", "true");
+ if (BPI.GuardedControlStack)
+FuncAttrs.addAttribute("guarded-control-stack", "true");
}
/// Merges `target-features` from \TargetOpts and \F, and sets the result in
diff --git a/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
new file mode 100644
index 0..8daf44abd4f91
--- /dev/null
+++ b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -triple aarch64-none-none -mbranch-target-enforce
-msign-return-address=all -fcxx-exceptions -fexceptions -emit-llvm %s -o - |
FileCheck %s --check-prefixes=CHECK
+
+// Check that functions generated by clang have the correct attributes
+
+class Example {
+public:
+ Example();
+ int fn();
+};
+
+// Initialization of var1 causes __cxx_global_var_init and __tls_init to be
generated
+thread_local Example var1;
+extern thread_local Example var2;
+extern void fn();
+
+int testfn() noexcept {
+ // Calling fn in a noexcept function causes __clang_call_terminate to be
generated
+ fn();
+ // Use of var1 and var2 causes TLS wrapper functions to be generated
+ return var1.fn() + var2.fn();
+}
+
+// CHECK: define {{.*}} @__cxx_global_var_init() [[ATTR1:#[0-9]+]]
+// CHECK: define {{.*}} @__clang_call_terminate({{.*}}) [[ATTR2:#[0-9]+]]
+// CHECK: define {{.*}} @_ZTW4var1() [[ATTR1]]
+// CHECK: define {{.*}} @_ZTW4var2() [[ATTR1]]
+// CHECK: define {{.*}} @__tls_init() [[ATTR1]]
+
+// CHECK: attributes [[ATTR1]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
+// CHECK: attributes [[ATTR2]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
>From 3e46bfa6bcd8a0cce142a4e1254c89ff68174117 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 17:38:49 +0100
Subject: [PATCH 2/5] fixup! [Clang][Arm][AArch64] Add branch protection
attributes to the defaults.
---
clang/lib/CodeGen/CGCall.cpp | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 5b59c77353675..58ccd3d181ccd 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2027,10 +2027,7 @@ static void getTrivialDefaultFunctionAttributes(
if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
-FuncAttrs.addAttribute(
-"sign-return-address-key",
-BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
- : "b_key");
+FuncAttrs.addAttribute("sign-return-address-key", BPI.getSignKeyStr());
}
if (BPI.BranchTargetEnforcement)
FuncAttrs.addAttribute("branch-target-enforcement", "true");
>From 054515d8b3b50b3efc792db9dfe4c9e61fa2507d Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Mon, 4 Mar 2024 17:31:31 +0100
Subject: [PATCH 3/5] Move TargetInfo changes over.
Dropping restrictions on the member functions.
---
clang/include/clang/Basic/TargetInfo.h | 43 +++---
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 76
[clang] [llvm] Revert "[Clang][ARM][AArch64] Alway emit protection attributes for functions." (PR #98284)
https://github.com/DanielKristofKiss created
https://github.com/llvm/llvm-project/pull/98284
Reverts llvm/llvm-project#82819
>From 74e9e20f0338824eecea0f27d9c1336676a60d3d Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 10 Jul 2024 10:21:36 +0200
Subject: [PATCH] =?UTF-8?q?Revert=20"[Clang][ARM][AArch64]=20Alway=20emit?=
=?UTF-8?q?=20protection=20attributes=20for=20functions.=E2=80=A6"?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This reverts commit e15d67cfc2e5775cc79281aa860f3ad3be628f39.
---
clang/include/clang/Basic/TargetInfo.h| 44 ++-
clang/lib/CodeGen/Targets/AArch64.cpp | 43 --
clang/lib/CodeGen/Targets/ARM.cpp | 8 ++--
.../CodeGen/aarch64-branch-protection-attr.c | 26 +--
.../CodeGen/aarch64-sign-return-address.c | 12 ++---
.../CodeGen/arm-branch-protection-attr-1.c| 12 ++---
.../CodeGen/arm-branch-protection-attr-2.c| 13 ++
.../test/Frontend/arm-branch-protection-lto.c | 24 --
.../SelectionDAG/SelectionDAGBuilder.cpp | 12 -
llvm/lib/IR/Verifier.cpp | 20 +
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +--
.../AArch64/AArch64MachineFunctionInfo.cpp| 37 ++--
.../lib/Target/ARM/ARMMachineFunctionInfo.cpp | 22 +-
llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 6 +--
...ranch-target-enforcement-indirect-calls.ll | 18
.../CodeGen/AArch64/bti-branch-relaxation.ll | 2 +-
llvm/test/CodeGen/AArch64/kcfi-bti.ll | 7 ++-
...machine-outliner-2fixup-blr-terminator.mir | 2 +-
.../CodeGen/AArch64/machine-outliner-bti.mir | 2 +-
.../AArch64/machine-outliner-outline-bti.ll | 4 +-
.../AArch64/note-gnu-property-pac-bti-0.ll| 2 +-
.../AArch64/note-gnu-property-pac-bti-4.ll| 4 +-
.../AArch64/pacbti-llvm-generated-funcs-1.ll | 4 +-
.../AArch64/pacbti-llvm-generated-funcs-2.ll | 10 +++--
.../CodeGen/AArch64/pacbti-module-attrs.ll| 12 ++---
.../AArch64/patchable-function-entry-bti.ll | 10 ++---
.../CodeGen/AArch64/setjmp-bti-outliner.ll| 15 ---
llvm/test/CodeGen/AArch64/setjmp-bti.ll | 6 ++-
.../AArch64/sign-return-address-pauth-lr.ll | 36 ---
.../CodeGen/AArch64/sign-return-address.ll| 8 ++--
llvm/test/CodeGen/AArch64/wineh-bti.ll| 7 ++-
llvm/test/CodeGen/AArch64/wineh-pac.ll| 7 ++-
llvm/test/CodeGen/ARM/setjmp-bti-basic.ll | 5 ++-
llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll | 7 ++-
llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll | 7 ++-
.../CodeGen/Thumb2/bti-indirect-branches.ll | 9 ++--
llvm/test/CodeGen/Thumb2/bti-outliner-1.ll| 9 ++--
llvm/test/CodeGen/Thumb2/bti-outliner-2.ll| 12 +++--
.../CodeGen/Thumb2/bti-outliner-cost-2.ll | 6 ++-
.../test/CodeGen/Thumb2/bti-pac-replace-1.mir | 8 +++-
llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll | 7 ++-
llvm/test/CodeGen/Thumb2/jump-table-bti.ll| 10 ++---
llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll| 6 +--
.../Thumb2/pacbti-m-indirect-tail-call.ll | 2 +-
.../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +-
.../CodeGen/Thumb2/pacbti-m-outliner-3.ll | 2 +-
.../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 6 +--
.../CodeGen/Thumb2/pacbti-m-outliner-5.ll | 4 +-
.../test/CodeGen/Thumb2/pacbti-m-overalign.ll | 2 +-
.../test/CodeGen/Thumb2/pacbti-m-stack-arg.ll | 4 +-
.../Thumb2/pacbti-m-unsupported-arch.ll | 8 +++-
.../test/CodeGen/Thumb2/pacbti-m-varargs-1.ll | 4 +-
.../test/CodeGen/Thumb2/pacbti-m-varargs-2.ll | 4 +-
llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 2 +-
.../AArch64/link-branch-target-enforcement.ll | 2 +-
.../Inline/inline-sign-return-address.ll | 13 +++---
.../LowerTypeTests/function-arm-thumb.ll | 2 +-
.../LowerTypeTests/function-thumb-bti.ll | 4 +-
.../Transforms/LowerTypeTests/function.ll | 4 +-
llvm/test/Verifier/branch-prot-attrs.ll | 16 +--
60 files changed, 316 insertions(+), 292 deletions(-)
delete mode 100644 clang/test/Frontend/arm-branch-protection-lto.c
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 1f208b40f92cb..9b0ae2102e098 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -32,9 +32,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/Frontend/OpenMP/OMPGridValues.h"
-#include "llvm/IR/Attributes.h"
#include "llvm/IR/DerivedTypes.h"
-#include "llvm/IR/Function.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/VersionTuple.h"
@@ -1402,15 +1400,15 @@ class TargetInfo : public TransferrableTargetInfo,
return true;
}
- class BranchProtectionInfo {
- public:
+ struct BranchProtectionInfo {
LangOptions::SignReturnAddressScopeKind SignReturnAddr;
LangOptions::SignReturnAddressKeyKind Si
[clang] [llvm] Revert "[Clang][ARM][AArch64] Alway emit protection attributes for functions." (PR #98284)
https://github.com/DanielKristofKiss closed https://github.com/llvm/llvm-project/pull/98284 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 1782810 - [Clang][ARM][AArch64] Alway emit protection attributes for functions. (#82819)
Author: Daniel Kiss Date: 2024-07-10T11:32:41+02:00 New Revision: 1782810b8440144a0141c24192acbaeb55a1545d URL: https://github.com/llvm/llvm-project/commit/1782810b8440144a0141c24192acbaeb55a1545d DIFF: https://github.com/llvm/llvm-project/commit/1782810b8440144a0141c24192acbaeb55a1545d.diff LOG: [Clang][ARM][AArch64] Alway emit protection attributes for functions. (#82819) So far branch protection, sign return address, guarded control stack attributes are only emitted as module flags to indicate the functions need to be generated with those features. The problem is in case of an LTO build the module flags are merged with the `min` rule which means if one of the module is not build with sign return address then the features will be turned off for all functions. Due to the functions take the branch-protection and sign-return-address features from the module flags. The sign-return-address is function level option therefore it is expected functions from files that is compiled with -mbranch-protection=pac-ret to be protected. The inliner might inline functions with different set of flags as it doesn't consider the module flags. This patch adds the attributes to all functions and drops the checking of the module flags for the code generation. Module flag is still used for generating the ELF markers. Also drops the "true"/"false" values from the branch-protection-enforcement, branch-protection-pauth-lr, guarded-control-stack attributes as presence of the attribute means it is on absence means off and no other option. Releand with test fixes. Added: clang/test/Frontend/arm-branch-protection-lto.c Modified: clang/include/clang/Basic/TargetInfo.h clang/lib/CodeGen/Targets/AArch64.cpp clang/lib/CodeGen/Targets/ARM.cpp clang/test/CodeGen/aarch64-branch-protection-attr.c clang/test/CodeGen/aarch64-sign-return-address.c clang/test/CodeGen/aarch64-targetattr.c clang/test/CodeGen/arm-branch-protection-attr-1.c clang/test/CodeGen/arm-branch-protection-attr-2.c llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/IR/Verifier.cpp llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp llvm/lib/Transforms/IPO/LowerTypeTests.cpp llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll llvm/test/CodeGen/AArch64/kcfi-bti.ll llvm/test/CodeGen/AArch64/machine-outliner-2fixup-blr-terminator.mir llvm/test/CodeGen/AArch64/machine-outliner-bti.mir llvm/test/CodeGen/AArch64/machine-outliner-outline-bti.ll llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-1.ll llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll llvm/test/CodeGen/AArch64/setjmp-bti.ll llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll llvm/test/CodeGen/AArch64/sign-return-address.ll llvm/test/CodeGen/AArch64/wineh-bti.ll llvm/test/CodeGen/AArch64/wineh-pac.ll llvm/test/CodeGen/ARM/setjmp-bti-basic.ll llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll llvm/test/CodeGen/Thumb2/bti-outliner-1.ll llvm/test/CodeGen/Thumb2/bti-outliner-2.ll llvm/test/CodeGen/Thumb2/bti-outliner-cost-2.ll llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll llvm/test/CodeGen/Thumb2/jump-table-bti.ll llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll llvm/test/CodeGen/Thumb2/pacbti-m-indirect-tail-call.ll llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll llvm/test/CodeGen/Thumb2/pacbti-m-outliner-5.ll llvm/test/CodeGen/Thumb2/pacbti-m-overalign.ll llvm/test/CodeGen/Thumb2/pacbti-m-stack-arg.ll llvm/test/CodeGen/Thumb2/pacbti-m-unsupported-arch.ll llvm/test/CodeGen/Thumb2/pacbti-m-varargs-1.ll llvm/test/CodeGen/Thumb2/pacbti-m-varargs-2.ll llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll llvm/test/LTO/AArch64/link-branch-target-enforcement.ll llvm/test/Transforms/Inline/inline-sign-return-address.ll llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll llvm/test/Transforms/LowerTypeTests/function.ll llvm/test/Verifier/branch-prot-attrs.ll Removed: diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index
[clang] [Clang][ARM] Call constructor on BranchTargetInfo. (PR #98307)
https://github.com/DanielKristofKiss created
https://github.com/llvm/llvm-project/pull/98307
Otherwise members will be uninitialised.
>From 4e10c95c390e519853428f424cd655379d99c61c Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 10 Jul 2024 13:58:52 +0200
Subject: [PATCH] [Clang][ARM] Call constructor on BranchTargetInfo.
Otherwise members will be uninitialised.
---
clang/lib/CodeGen/Targets/ARM.cpp | 2 +-
clang/lib/Sema/SemaDeclAttr.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/Targets/ARM.cpp
b/clang/lib/CodeGen/Targets/ARM.cpp
index d449b97cdc685..93fea94a77248 100644
--- a/clang/lib/CodeGen/Targets/ARM.cpp
+++ b/clang/lib/CodeGen/Targets/ARM.cpp
@@ -141,7 +141,7 @@ class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
ParsedTargetAttr Attr =
CGM.getTarget().parseTargetAttr(TA->getFeaturesStr());
if (!Attr.BranchProtection.empty()) {
-TargetInfo::BranchProtectionInfo BPI;
+TargetInfo::BranchProtectionInfo BPI{};
StringRef DiagMsg;
StringRef Arch =
Attr.CPU.empty() ? CGM.getTarget().getTargetOpts().CPU : Attr.CPU;
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 73a85ff39667b..f2cd46d1e7c93 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -2991,7 +2991,7 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc,
StringRef AttrStr) {
<< Unsupported << None << CurFeature << Target;
}
- TargetInfo::BranchProtectionInfo BPI;
+ TargetInfo::BranchProtectionInfo BPI{};
StringRef DiagMsg;
if (ParsedAttrs.BranchProtection.empty())
return false;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][ARM] Call constructor on BranchTargetInfo. (PR #98307)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/98307
>From 4e10c95c390e519853428f424cd655379d99c61c Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 10 Jul 2024 13:58:52 +0200
Subject: [PATCH 1/2] [Clang][ARM] Call constructor on BranchTargetInfo.
Otherwise members will be uninitialised.
---
clang/lib/CodeGen/Targets/ARM.cpp | 2 +-
clang/lib/Sema/SemaDeclAttr.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/Targets/ARM.cpp
b/clang/lib/CodeGen/Targets/ARM.cpp
index d449b97cdc685..93fea94a77248 100644
--- a/clang/lib/CodeGen/Targets/ARM.cpp
+++ b/clang/lib/CodeGen/Targets/ARM.cpp
@@ -141,7 +141,7 @@ class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
ParsedTargetAttr Attr =
CGM.getTarget().parseTargetAttr(TA->getFeaturesStr());
if (!Attr.BranchProtection.empty()) {
-TargetInfo::BranchProtectionInfo BPI;
+TargetInfo::BranchProtectionInfo BPI{};
StringRef DiagMsg;
StringRef Arch =
Attr.CPU.empty() ? CGM.getTarget().getTargetOpts().CPU : Attr.CPU;
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 73a85ff39667b..f2cd46d1e7c93 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -2991,7 +2991,7 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc,
StringRef AttrStr) {
<< Unsupported << None << CurFeature << Target;
}
- TargetInfo::BranchProtectionInfo BPI;
+ TargetInfo::BranchProtectionInfo BPI{};
StringRef DiagMsg;
if (ParsedAttrs.BranchProtection.empty())
return false;
>From 4dfab4b3e6dca97ddc0348bcfbea7609170a3078 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 10 Jul 2024 16:01:47 +0200
Subject: [PATCH 2/2] Initialize members from the constructor.
---
clang/include/clang/Basic/TargetInfo.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 1f208b40f92cb..079c71d10525f 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1434,7 +1434,14 @@ class TargetInfo : public TransferrableTargetInfo,
}
public:
-BranchProtectionInfo() = default;
+BranchProtectionInfo() {
+ SignReturnAddr = LangOptions::SignReturnAddressScopeKind::None;
+ SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
+ BranchTargetEnforcement = false;
+ BranchProtectionPAuthLR = false;
+ GuardedControlStack = false;
+};
+
BranchProtectionInfo(const LangOptions &LangOpts) {
SignReturnAddr =
LangOpts.hasSignReturnAddress()
___
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[clang] [Clang][ARM] Call constructor on BranchTargetInfo. (PR #98307)
DanielKristofKiss wrote: Let's initialise everything from both of the constructors (as it was in an early version of the original patches) https://github.com/llvm/llvm-project/pull/98307 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][ARM][AArch64] Alway emit protection attributes for functions. (PR #82819)
@@ -32,7 +32,9 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSet.h" #include "llvm/Frontend/OpenMP/OMPGridValues.h" +#include "llvm/IR/Attributes.h" #include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Function.h" DanielKristofKiss wrote: Addressed here https://github.com/llvm/llvm-project/pull/98329 https://github.com/llvm/llvm-project/pull/82819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [NFC][Clang] Move functions of BranchProtectionInfo out of line (PR #98329)
https://github.com/DanielKristofKiss created
https://github.com/llvm/llvm-project/pull/98329
Also let's add const to the setFnAttributes.
>From b1e113f76b289aa8a7d4459314a0dbffb313cb51 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 10 Jul 2024 16:23:11 +0200
Subject: [PATCH] [NFC][Clang] Move functions of BranchProtectionInfo out of
line.
Also let's add const to the setFnAttributes.
---
clang/include/clang/Basic/TargetInfo.h | 20 ++--
clang/lib/Basic/TargetInfo.cpp | 20
2 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 1f208b40f92cb..5a6a0cdbd316a 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -34,7 +34,6 @@
#include "llvm/Frontend/OpenMP/OMPGridValues.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DerivedTypes.h"
-#include "llvm/IR/Function.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/VersionTuple.h"
@@ -1450,24 +1449,9 @@ class TargetInfo : public TransferrableTargetInfo,
GuardedControlStack = LangOpts.GuardedControlStack;
}
-void setFnAttributes(llvm::Function &F) {
- llvm::AttrBuilder FuncAttrs(F.getContext());
- setFnAttributes(FuncAttrs);
- F.addFnAttrs(FuncAttrs);
-}
+void setFnAttributes(llvm::Function &F) const;
-void setFnAttributes(llvm::AttrBuilder &FuncAttrs) {
- if (SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
-FuncAttrs.addAttribute("sign-return-address", getSignReturnAddrStr());
-FuncAttrs.addAttribute("sign-return-address-key", getSignKeyStr());
- }
- if (BranchTargetEnforcement)
-FuncAttrs.addAttribute("branch-target-enforcement");
- if (BranchProtectionPAuthLR)
-FuncAttrs.addAttribute("branch-protection-pauth-lr");
- if (GuardedControlStack)
-FuncAttrs.addAttribute("guarded-control-stack");
-}
+void setFnAttributes(llvm::AttrBuilder &FuncAttrs) const;
};
/// Determine if the Architecture in this TargetInfo supports branch
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 29f5cd14e46e1..a99ddd081ae28 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -18,6 +18,7 @@
#include "clang/Basic/LangOptions.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/IR/Function.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1005,3 +1006,22 @@ void TargetInfo::copyAuxTarget(const TargetInfo *Aux) {
auto *Src = static_cast(Aux);
*Target = *Src;
}
+
+void TargetInfo::BranchProtectionInfo::setFnAttributes(llvm::Function &F)
const {
+ llvm::AttrBuilder FuncAttrs(F.getContext());
+ setFnAttributes(FuncAttrs);
+ F.addFnAttrs(FuncAttrs);
+}
+
+void TargetInfo::BranchProtectionInfo::setFnAttributes(llvm::AttrBuilder
&FuncAttrs) const {
+ if (SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+FuncAttrs.addAttribute("sign-return-address", getSignReturnAddrStr());
+FuncAttrs.addAttribute("sign-return-address-key", getSignKeyStr());
+ }
+ if (BranchTargetEnforcement)
+FuncAttrs.addAttribute("branch-target-enforcement");
+ if (BranchProtectionPAuthLR)
+FuncAttrs.addAttribute("branch-protection-pauth-lr");
+ if (GuardedControlStack)
+FuncAttrs.addAttribute("guarded-control-stack");
+}
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[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/83277
>From c421b6b9c167e82cedc5db2a67f47d3ba12deba9 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 15:18:31 +0100
Subject: [PATCH 1/6] Add branch protection attributes to the defaults.
These attributes are no longer inherited from the module flags,
therefore need to be added for synthetic functions.
---
clang/lib/CodeGen/CGCall.cpp | 16 ++
.../CodeGenCXX/arm64-generated-fn-attr.cpp| 30 +++
2 files changed, 46 insertions(+)
create mode 100644 clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 13f68237b464d..5b59c77353675 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2022,6 +2022,22 @@ static void getTrivialDefaultFunctionAttributes(
std::tie(Var, Value) = Attr.split('=');
FuncAttrs.addAttribute(Var, Value);
}
+
+ TargetInfo::BranchProtectionInfo BPI(LangOpts);
+
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
+FuncAttrs.addAttribute(
+"sign-return-address-key",
+BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
+ : "b_key");
+ }
+ if (BPI.BranchTargetEnforcement)
+FuncAttrs.addAttribute("branch-target-enforcement", "true");
+ if (BPI.BranchProtectionPAuthLR)
+FuncAttrs.addAttribute("branch-protection-pauth-lr", "true");
+ if (BPI.GuardedControlStack)
+FuncAttrs.addAttribute("guarded-control-stack", "true");
}
/// Merges `target-features` from \TargetOpts and \F, and sets the result in
diff --git a/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
new file mode 100644
index 0..8daf44abd4f91
--- /dev/null
+++ b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -triple aarch64-none-none -mbranch-target-enforce
-msign-return-address=all -fcxx-exceptions -fexceptions -emit-llvm %s -o - |
FileCheck %s --check-prefixes=CHECK
+
+// Check that functions generated by clang have the correct attributes
+
+class Example {
+public:
+ Example();
+ int fn();
+};
+
+// Initialization of var1 causes __cxx_global_var_init and __tls_init to be
generated
+thread_local Example var1;
+extern thread_local Example var2;
+extern void fn();
+
+int testfn() noexcept {
+ // Calling fn in a noexcept function causes __clang_call_terminate to be
generated
+ fn();
+ // Use of var1 and var2 causes TLS wrapper functions to be generated
+ return var1.fn() + var2.fn();
+}
+
+// CHECK: define {{.*}} @__cxx_global_var_init() [[ATTR1:#[0-9]+]]
+// CHECK: define {{.*}} @__clang_call_terminate({{.*}}) [[ATTR2:#[0-9]+]]
+// CHECK: define {{.*}} @_ZTW4var1() [[ATTR1]]
+// CHECK: define {{.*}} @_ZTW4var2() [[ATTR1]]
+// CHECK: define {{.*}} @__tls_init() [[ATTR1]]
+
+// CHECK: attributes [[ATTR1]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
+// CHECK: attributes [[ATTR2]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
>From 3e46bfa6bcd8a0cce142a4e1254c89ff68174117 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 17:38:49 +0100
Subject: [PATCH 2/6] fixup! [Clang][Arm][AArch64] Add branch protection
attributes to the defaults.
---
clang/lib/CodeGen/CGCall.cpp | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 5b59c77353675..58ccd3d181ccd 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2027,10 +2027,7 @@ static void getTrivialDefaultFunctionAttributes(
if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
-FuncAttrs.addAttribute(
-"sign-return-address-key",
-BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
- : "b_key");
+FuncAttrs.addAttribute("sign-return-address-key", BPI.getSignKeyStr());
}
if (BPI.BranchTargetEnforcement)
FuncAttrs.addAttribute("branch-target-enforcement", "true");
>From 054515d8b3b50b3efc792db9dfe4c9e61fa2507d Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Mon, 4 Mar 2024 17:31:31 +0100
Subject: [PATCH 3/6] Move TargetInfo changes over.
Dropping restrictions on the member functions.
---
clang/include/clang/Basic/TargetInfo.h | 43 +++---
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 76
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/DanielKristofKiss updated
https://github.com/llvm/llvm-project/pull/83277
>From 0c3118713387246dc1c503f3792ba5af82e6b5eb Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 15:18:31 +0100
Subject: [PATCH 1/6] Add branch protection attributes to the defaults.
These attributes are no longer inherited from the module flags,
therefore need to be added for synthetic functions.
---
clang/lib/CodeGen/CGCall.cpp | 16 ++
.../CodeGenCXX/arm64-generated-fn-attr.cpp| 30 +++
2 files changed, 46 insertions(+)
create mode 100644 clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 7e7b2b395f7d6..7b93f6d2dded1 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2030,6 +2030,22 @@ static void getTrivialDefaultFunctionAttributes(
std::tie(Var, Value) = Attr.split('=');
FuncAttrs.addAttribute(Var, Value);
}
+
+ TargetInfo::BranchProtectionInfo BPI(LangOpts);
+
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
+FuncAttrs.addAttribute(
+"sign-return-address-key",
+BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
+ : "b_key");
+ }
+ if (BPI.BranchTargetEnforcement)
+FuncAttrs.addAttribute("branch-target-enforcement", "true");
+ if (BPI.BranchProtectionPAuthLR)
+FuncAttrs.addAttribute("branch-protection-pauth-lr", "true");
+ if (BPI.GuardedControlStack)
+FuncAttrs.addAttribute("guarded-control-stack", "true");
}
/// Merges `target-features` from \TargetOpts and \F, and sets the result in
diff --git a/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
new file mode 100644
index 0..8daf44abd4f91
--- /dev/null
+++ b/clang/test/CodeGenCXX/arm64-generated-fn-attr.cpp
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -triple aarch64-none-none -mbranch-target-enforce
-msign-return-address=all -fcxx-exceptions -fexceptions -emit-llvm %s -o - |
FileCheck %s --check-prefixes=CHECK
+
+// Check that functions generated by clang have the correct attributes
+
+class Example {
+public:
+ Example();
+ int fn();
+};
+
+// Initialization of var1 causes __cxx_global_var_init and __tls_init to be
generated
+thread_local Example var1;
+extern thread_local Example var2;
+extern void fn();
+
+int testfn() noexcept {
+ // Calling fn in a noexcept function causes __clang_call_terminate to be
generated
+ fn();
+ // Use of var1 and var2 causes TLS wrapper functions to be generated
+ return var1.fn() + var2.fn();
+}
+
+// CHECK: define {{.*}} @__cxx_global_var_init() [[ATTR1:#[0-9]+]]
+// CHECK: define {{.*}} @__clang_call_terminate({{.*}}) [[ATTR2:#[0-9]+]]
+// CHECK: define {{.*}} @_ZTW4var1() [[ATTR1]]
+// CHECK: define {{.*}} @_ZTW4var2() [[ATTR1]]
+// CHECK: define {{.*}} @__tls_init() [[ATTR1]]
+
+// CHECK: attributes [[ATTR1]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
+// CHECK: attributes [[ATTR2]] = {
{{.*}}"branch-target-enforcement"="true"{{.*}}"sign-return-address"="all"
"sign-return-address-key"="a_key"
>From 0e2a9e129bcb4f569a443494b9266ae482c73c94 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Wed, 28 Feb 2024 17:38:49 +0100
Subject: [PATCH 2/6] fixup! [Clang][Arm][AArch64] Add branch protection
attributes to the defaults.
---
clang/lib/CodeGen/CGCall.cpp | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 7b93f6d2dded1..131666d732b3d 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2035,10 +2035,7 @@ static void getTrivialDefaultFunctionAttributes(
if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
FuncAttrs.addAttribute("sign-return-address", BPI.getSignReturnAddrStr());
-FuncAttrs.addAttribute(
-"sign-return-address-key",
-BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey ? "a_key"
- : "b_key");
+FuncAttrs.addAttribute("sign-return-address-key", BPI.getSignKeyStr());
}
if (BPI.BranchTargetEnforcement)
FuncAttrs.addAttribute("branch-target-enforcement", "true");
>From 735d24d5fe8bb4f37d87cb2345cbe45d53b1ba42 Mon Sep 17 00:00:00 2001
From: Daniel Kiss
Date: Mon, 4 Mar 2024 17:31:31 +0100
Subject: [PATCH 3/6] Move TargetInfo changes over.
Dropping restrictions on the member functions.
---
clang/include/clang/Basic/TargetInfo.h | 15 ---
1 file changed, 15 deletions(-)
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 1f208b40f92cb..d8075ee97972e 1
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
DanielKristofKiss wrote: Sorry for the force push, need to be rebased. NFC since last review round. https://github.com/llvm/llvm-project/pull/83277 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
