[clang] [clang-tools-extra] [llvm] [AArch64] Implement -fno-plt for SelectionDAG/GlobalISel (PR #78890)
MaskRay wrote: > It looks like some of the tests might be failing? Or does it need a rebase? Sorry about it. The last minute `FastISel` change caused some failures. `Addr.getGlobalValue()` could be null. I have simplified `AArch64FastISel.cpp` to just check `"RtLibUseGOT"` (added by `-fno-plt`) and fixed the failures. https://github.com/llvm/llvm-project/pull/78890 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [llvm] [AArch64] Implement -fno-plt for SelectionDAG/GlobalISel (PR #78890)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/78890
>From 549e4ea5b292e558e085d881abd4c93f29352029 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Sun, 21 Jan 2024 00:25:34 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 13 ++-
llvm/lib/Target/AArch64/AArch64FastISel.cpp | 7 ++
.../Target/AArch64/AArch64ISelLowering.cpp| 9 ++-
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 11 +--
.../AArch64/GISel/AArch64CallLowering.cpp | 13 ++-
.../GISel/AArch64InstructionSelector.cpp | 16 +++-
.../AArch64/GISel/AArch64LegalizerInfo.cpp| 3 +
llvm/test/CodeGen/AArch64/nonlazybind.ll | 81 +--
8 files changed, 93 insertions(+), 60 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index ccd9b13d730b6..d3484e5229e70 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -144,9 +144,16 @@ bool CallLowering::lowerCall(MachineIRBuilder ,
const CallBase ,
// Try looking through a bitcast from one function type to another.
// Commonly happens with calls to objc_msgSend().
const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
- if (const Function *F = dyn_cast(CalleeV))
-Info.Callee = MachineOperand::CreateGA(F, 0);
- else if (isa(CalleeV) || isa(CalleeV)) {
+ if (const Function *F = dyn_cast(CalleeV)) {
+if (F->hasFnAttribute(Attribute::NonLazyBind)) {
+ auto Reg =
+ MRI.createGenericVirtualRegister(getLLTForType(*F->getType(), DL));
+ MIRBuilder.buildGlobalValue(Reg, F);
+ Info.Callee = MachineOperand::CreateReg(Reg, false);
+} else {
+ Info.Callee = MachineOperand::CreateGA(F, 0);
+}
+ } else if (isa(CalleeV) || isa(CalleeV)) {
// IR IFuncs and Aliases can't be forward declared (only defined), so the
// callee must be in the same TU and therefore we can direct-call it
without
// worrying about it being out of range.
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index e98f6c4984a75..93d6024f34c09 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -3202,6 +3202,13 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo
) {
if (Callee && !computeCallAddress(Callee, Addr))
return false;
+ // MO_GOT is not handled. -fno-plt compiled intrinsic calls do not have the
+ // nonlazybind attribute. Check "RtLibUseGOT" instead.
+ if ((Subtarget->classifyGlobalFunctionReference(Addr.getGlobalValue(), TM) !=
+ AArch64II::MO_NO_FLAG) ||
+ MF->getFunction().getParent()->getRtLibUseGOT())
+return false;
+
// The weak function target may be zero; in that case we must use indirect
// addressing via a stub on windows as it may be out of range for a
// PC-relative jump.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 96ea692d03f56..56de890c78dec 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7969,13 +7969,14 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo ,
Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
}
} else if (auto *S = dyn_cast(Callee)) {
-if (getTargetMachine().getCodeModel() == CodeModel::Large &&
-Subtarget->isTargetMachO()) {
- const char *Sym = S->getSymbol();
+bool UseGot = (getTargetMachine().getCodeModel() == CodeModel::Large &&
+ Subtarget->isTargetMachO()) ||
+ MF.getFunction().getParent()->getRtLibUseGOT();
+const char *Sym = S->getSymbol();
+if (UseGot) {
Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
} else {
- const char *Sym = S->getSymbol();
Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index cf57d950ae8d7..c4c6827313b5e 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -43,10 +43,10 @@ static cl::opt
UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
"an address is ignored"), cl::init(false),
cl::Hidden);
-static cl::opt
-UseNonLazyBind("aarch64-enable-nonlazybind",
- cl::desc("Call nonlazybind functions via direct GOT load"),
- cl::init(false), cl::Hidden);
+static cl::opt MachOUseNonLazyBind(
+
[clang] [clang-tools-extra] [llvm] [AArch64] Implement -fno-plt for SelectionDAG/GlobalISel (PR #78890)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/78890 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CMake] Add a linker test for -Bsymbolic-functions to AddLLVM (PR #79539)
MaskRay wrote: > OpenBSD also has a local patch for linking with the old BFD linker on mips64 > and sparc64. What's the issue? GNU ld has had -Bsymbolic-functions since 2007 and for quite a few releases LLVM has been using `-Bsymbolic-functions`. https://github.com/llvm/llvm-project/pull/79539 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix erroneous warning. (PR #79821)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79821 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix erroneous warning. (PR #79821)
@@ -44,3 +47,4 @@ // CHECK-NOT: -complex-range=fortran // WARN1: warning: overriding '-fcx-limited-range' option with '-fcx-fortran-rules' [-Woverriding-option] // WARN2: warning: overriding '-fcx-fortran-rules' option with '-fcx-limited-range' [-Woverriding-option] +// range-no-diagnostics MaskRay wrote: `-verify` does not work for driver errors/warnings. You can add `-Werror`. In case of errors, `clang -###` will exit with code 1. Since lit requires that commands exit with code 0, `-### -Werror` alone serves as a test. ``` % clang -### -c -fcx-fortran-rules a.c -Werror ... clang: error: overriding '' option with '-fcx-fortran-rules' [-Werror,-Woverriding-option] ... ``` https://github.com/llvm/llvm-project/pull/79821 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix erroneous warning. (PR #79821)
https://github.com/MaskRay requested changes to this pull request. . https://github.com/llvm/llvm-project/pull/79821 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix erroneous warning. (PR #79821)
MaskRay wrote: > Fix erroneous warning. I'd suggest a more descriptive title, e.g. `[Driver] Fix erroneous warning for -fcx-limited-range and -fcx-fortran-rules` Please also mention #70244 in the description. I am not familiar with the two options, I'll trust your judgement as the author of #70244 :) https://github.com/llvm/llvm-project/pull/79821 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [lldb] [flang] [clang] [clang-tools-extra] [libc] [llvm] [compiler-rt] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Add option -fstdlib-hardening= (PR #78763)
MaskRay wrote:
As mentioned, libstdc++ has `_GLIBCXX_ASSERTIONS`. The documentation is at
https://gcc.gnu.org/wiki/LibstdcxxDebugMode
https://gcc.gnu.org/onlinedocs/libstdc++/manual/debug_mode.html
> For example, in a next step we should discuss whether it makes sense for
> `-fstdlib-hardening={extensive,debug}` to turn on `_GLIBCXX_ASSERTIONS` on
> GCC.
I am concerned that `-fstdlib-hardening=` may not map to libstdc++ preferred
enabling mechanism cleanly.
There is a non-zero probability that GCC folks would not add an option that
just passes a `-D...` to cc1.
Then this driver option will feel like a libc++ specific feature using a
generic name...
As I mentioned previously, the option is a very shallow layer of extra
abstraction that a curious reader has to look through.
I understand that setting a macro starting with an underscore feels less
elegant, but a driver option requires thoughts
how to handle `-Wunused-command-line-argument` properly. The current patch
emits an error for C input and a warning for assembly input.
There may be other interaction that is worth considering. The complexity all
arises from we introducing a driver option.
https://github.com/llvm/llvm-project/pull/78763
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[lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
@@ -353,71 +331,30 @@ class MCDCRecordProcessor {
}
}
- /// For a given condition and two executed Test Vectors, A and B, see if the
- /// two test vectors match forming an Independence Pair for the condition.
- /// For two test vectors to match, the following must be satisfied:
- /// - The condition's value in each test vector must be opposite.
- /// - The result's value in each test vector must be opposite.
- /// - All other conditions' values must be equal or marked as "don't care".
- bool matchTestVectors(unsigned Aidx, unsigned Bidx, unsigned ConditionIdx) {
-const MCDCRecord::TestVector = ExecVectors[Aidx];
-const MCDCRecord::TestVector = ExecVectors[Bidx];
-
-// If condition values in both A and B aren't opposites, no match.
-// Because a value can be 0 (false), 1 (true), or -1 (DontCare), a check
-// that "XOR != 1" will ensure that the values are opposites and that
-// neither of them is a DontCare.
-// 1 XOR 0 == 1 | 0 XOR 0 == 0 | -1 XOR 0 == -1
-// 1 XOR 1 == 0 | 0 XOR 1 == 1 | -1 XOR 1 == -2
-// 1 XOR -1 == -2 | 0 XOR -1 == -1 | -1 XOR -1 == 0
-if ((A[ConditionIdx] ^ B[ConditionIdx]) != 1)
- return false;
-
-// If the results of both A and B aren't opposites, no match.
-if ((A[NumConditions] ^ B[NumConditions]) != 1)
- return false;
-
-for (unsigned Idx = 0; Idx < NumConditions; ++Idx) {
- // Look for other conditions that don't match. Skip over the given
- // Condition as well as any conditions marked as "don't care".
- const auto ARecordTyForCond = A[Idx];
- const auto BRecordTyForCond = B[Idx];
- if (Idx == ConditionIdx ||
- ARecordTyForCond == MCDCRecord::MCDC_DontCare ||
- BRecordTyForCond == MCDCRecord::MCDC_DontCare)
-continue;
-
- // If there is a condition mismatch with any of the other conditions,
- // there is no match for the test vectors.
- if (ARecordTyForCond != BRecordTyForCond)
-return false;
-}
-
-// Otherwise, match.
-return true;
- }
-
- /// Find all possible Independence Pairs for a boolean expression given its
- /// executed Test Vectors. This process involves looking at each condition
- /// and attempting to find two Test Vectors that "match", giving us a pair.
+ // Find an independence pair for each condition.
void findIndependencePairs() {
unsigned NumTVs = ExecVectors.size();
-
-// For each condition.
-for (unsigned C = 0; C < NumConditions; ++C) {
- bool PairFound = false;
-
- // For each executed test vector.
- for (unsigned I = 0; !PairFound && I < NumTVs; ++I) {
-// Compared to every other executed test vector.
-for (unsigned J = 0; !PairFound && J < NumTVs; ++J) {
- if (I == J)
+for (unsigned I = 1; I < NumTVs; ++I) {
+ const MCDCRecord::TestVector = ExecVectors[I];
+ for (unsigned J = 0; J < I; ++J) {
+const MCDCRecord::TestVector = ExecVectors[J];
+// Enumerate two execution vectors whose outcomes are different.
+if (A[NumConditions] == B[NumConditions])
+ continue;
+unsigned Flip = NumConditions, Idx;
+for (Idx = 0; Idx < NumConditions; ++Idx) {
+ MCDCRecord::CondState ACond = A[Idx], BCond = B[Idx];
+ if (ACond == BCond || ACond == MCDCRecord::MCDC_DontCare ||
+ BCond == MCDCRecord::MCDC_DontCare)
continue;
-
- // If a matching pair of vectors is found, record them.
- if ((PairFound = matchTestVectors(I, J, C)))
-IndependencePairs[C] = std::make_pair(I + 1, J + 1);
+ if (Flip != NumConditions)
+break;
+ Flip = Idx;
}
MaskRay wrote:
I left some notes on
https://maskray.me/blog/2024-01-28-mc-dc-and-compiler-implementations
GCC has a pending patch implementing MC/DC as well and they apply an algorithm
described by _Efficient Test Coverage Measurement for MC/DC_, which is linear
in terms of the number of conditions.
https://github.com/llvm/llvm-project/pull/79727
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[lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
@@ -458,7 +395,7 @@ class MCDCRecordProcessor {
MCDCRecord::TestVector TV(NumConditions, MCDCRecord::MCDC_DontCare);
// Use the base test vector to build the list of all possible test vectors.
-buildTestVector(TV);
+buildTestVector(TV, 1, 0);
MaskRay wrote:
Thanks for the suggestion. Added
https://github.com/llvm/llvm-project/pull/79727
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[lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79727
>From 1d2470c2d67673f9ef9ea504e0abb3e964d43ebb Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Sat, 27 Jan 2024 22:24:39 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
.../ProfileData/Coverage/CoverageMapping.cpp | 133 +-
1 file changed, 35 insertions(+), 98 deletions(-)
diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
index da8e1d87319dded..16a45d1788236a0 100644
--- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
+++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
@@ -286,17 +286,8 @@ class MCDCRecordProcessor {
TestVectors((size_t)1 << NumConditions) {}
private:
- void recordTestVector(MCDCRecord::TestVector ,
+ void recordTestVector(MCDCRecord::TestVector , unsigned Index,
MCDCRecord::CondState Result) {
-// Calculate an index that is used to identify the test vector in a vector
-// of test vectors. This index also corresponds to the index values of an
-// MCDC Region's bitmap (see findExecutedTestVectors()).
-unsigned Index = 0;
-for (auto Cond = std::rbegin(TV); Cond != std::rend(TV); ++Cond) {
- Index <<= 1;
- Index |= (*Cond == MCDCRecord::MCDC_True) ? 0x1 : 0x0;
-}
-
// Copy the completed test vector to the vector of testvectors.
TestVectors[Index] = TV;
@@ -305,38 +296,25 @@ class MCDCRecordProcessor {
TestVectors[Index].push_back(Result);
}
- void shouldCopyOffTestVectorForTruePath(MCDCRecord::TestVector ,
- unsigned ID) {
-// Branch regions are hashed based on an ID.
-const CounterMappingRegion *Branch = Map[ID];
-
-TV[ID - 1] = MCDCRecord::MCDC_True;
-if (Branch->MCDCParams.TrueID > 0)
- buildTestVector(TV, Branch->MCDCParams.TrueID);
-else
- recordTestVector(TV, MCDCRecord::MCDC_True);
- }
-
- void shouldCopyOffTestVectorForFalsePath(MCDCRecord::TestVector ,
- unsigned ID) {
-// Branch regions are hashed based on an ID.
+ // Walk the binary decision tree and try assigning both false and true to
each
+ // node. When a terminal node (ID == 0) is reached, fill in the value in the
+ // truth table.
+ void buildTestVector(MCDCRecord::TestVector , unsigned ID,
+ unsigned Index) {
const CounterMappingRegion *Branch = Map[ID];
TV[ID - 1] = MCDCRecord::MCDC_False;
if (Branch->MCDCParams.FalseID > 0)
- buildTestVector(TV, Branch->MCDCParams.FalseID);
+ buildTestVector(TV, Branch->MCDCParams.FalseID, Index);
else
- recordTestVector(TV, MCDCRecord::MCDC_False);
- }
+ recordTestVector(TV, Index, MCDCRecord::MCDC_False);
- /// Starting with the base test vector, build a comprehensive list of
- /// possible test vectors by recursively walking the branch condition IDs
- /// provided. Once an end node is reached, record the test vector in a vector
- /// of test vectors that can be matched against during MC/DC analysis, and
- /// then reset the positions to 'DontCare'.
- void buildTestVector(MCDCRecord::TestVector , unsigned ID = 1) {
-shouldCopyOffTestVectorForTruePath(TV, ID);
-shouldCopyOffTestVectorForFalsePath(TV, ID);
+Index |= 1 << (ID - 1);
+TV[ID - 1] = MCDCRecord::MCDC_True;
+if (Branch->MCDCParams.TrueID > 0)
+ buildTestVector(TV, Branch->MCDCParams.TrueID, Index);
+else
+ recordTestVector(TV, Index, MCDCRecord::MCDC_True);
// Reset back to DontCare.
TV[ID - 1] = MCDCRecord::MCDC_DontCare;
@@ -353,71 +331,30 @@ class MCDCRecordProcessor {
}
}
- /// For a given condition and two executed Test Vectors, A and B, see if the
- /// two test vectors match forming an Independence Pair for the condition.
- /// For two test vectors to match, the following must be satisfied:
- /// - The condition's value in each test vector must be opposite.
- /// - The result's value in each test vector must be opposite.
- /// - All other conditions' values must be equal or marked as "don't care".
- bool matchTestVectors(unsigned Aidx, unsigned Bidx, unsigned ConditionIdx) {
-const MCDCRecord::TestVector = ExecVectors[Aidx];
-const MCDCRecord::TestVector = ExecVectors[Bidx];
-
-// If condition values in both A and B aren't opposites, no match.
-// Because a value can be 0 (false), 1 (true), or -1 (DontCare), a check
-// that "XOR != 1" will ensure that the values are opposites and that
-// neither of them is a DontCare.
-// 1 XOR 0 == 1 | 0 XOR 0 == 0 | -1 XOR 0 == -1
-// 1 XOR 1 == 0 | 0 XOR 1 == 1 | -1 XOR 1 == -2
-// 1 XOR -1 == -2 | 0 XOR -1 == -1 | -1 XOR -1 ==
[compiler-rt] [flang] [clang] [lldb] [clang-tools-extra] [llvm] [libcxx] [libc] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Add option -fstdlib-hardening= (PR #78763)
MaskRay wrote: I am on the fence whether a driver option is really needed. It is a very shallow layer of extra abstraction that a curious reader has to look through. I guess I'll not object to this, though. https://github.com/llvm/llvm-project/pull/78763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Add option -fstdlib-hardening= (PR #78763)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/78763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Add option -fstdlib-hardening= (PR #78763)
@@ -1256,6 +1256,14 @@ void Clang::AddPreprocessingOptions(Compilation ,
const JobAction ,
if (Arg *A = Args.getLastArg(options::OPT_I_))
D.Diag(diag::err_drv_I_dash_not_supported) << A->getAsString(Args);
+ if (Arg *A = Args.getLastArg(options::OPT_stdlib_hardening_EQ)) {
+if (types::isCXX(Inputs[0].getType()) &&
MaskRay wrote:
If a project mixes C and C++, and I want to use one option,
`-D_LIBCPP_HARDENING_MODE=... a.c` is totally fine while using
`-fstdlib-hardening=` will cause an error. I wonder whether it's the desired
behavior.
https://github.com/llvm/llvm-project/pull/78763
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[compiler-rt] [clang] [llvm] [clang-tools-extra] [flang] [libc] [X86] Do not end 'note.gnu.property' section with -fcf-protection (PR #79360)
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[libc] [compiler-rt] [flang] [clang-tools-extra] [clang] [llvm] [X86] Do not end 'note.gnu.property' section with -fcf-protection (PR #79360)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/79360 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [lldb] [clang] [mlir] [libcxx] [clang-tools-extra] [libc] [lld] [libunwind] [flang] [llvm] [Driver,CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79256 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float (PR #79109)
MaskRay wrote: > cc @MaskRay The change is reasonable. I'd indent continuation lines by 2 spaces, but probably not worth the churn. https://github.com/llvm/llvm-project/pull/79109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [compiler-rt] [clang] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
@@ -750,13 +750,16 @@ unsigned llvm::X86::getFeaturePriority(ProcessorFeatures
Feat) {
#ifndef NDEBUG
// Check that priorities are set properly in the .def file. We expect that
// "compat" features are assigned non-duplicate consecutive priorities
- // starting from zero (0, 1, ..., num_features - 1).
+ // starting from one (1, ..., 37) and multiple zeros.
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
unsigned Priorities[] = {
#include "llvm/TargetParser/X86TargetParser.def"
};
std::array HelperList;
- std::iota(HelperList.begin(), HelperList.end(), 0);
+ const size_t MaxPriority = 37;
+ std::iota(HelperList.begin(), HelperList.begin() + MaxPriority + 1, 0);
+ for (int i = MaxPriority + 1; i != std::size(Priorities); ++i)
MaskRay wrote:
`int`=>`size_t`
https://github.com/llvm/llvm-project/pull/79086
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[clang-tools-extra] [llvm] [libc] [clang] [libcxx] [lldb] [lld] [libunwind] [flang] [mlir] [compiler-rt] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79239 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [libunwind] [libc] [mlir] [compiler-rt] [lld] [clang-tools-extra] [llvm] [lldb] [libcxx] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
MaskRay wrote: """ This branch is out-of-date with the base branch Merge the latest changes from main into this branch. This merge commit will be associated with ... """ Hmm. rebase + `spr diff` cannot fix it. I'll merge this manually. https://github.com/llvm/llvm-project/pull/79239 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [libunwind] [libc] [mlir] [compiler-rt] [lld] [clang-tools-extra] [llvm] [lldb] [libcxx] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+
[clang] [clang-tools-extra] [lldb] [libc] [libcxx] [lld] [llvm] [flang] [compiler-rt] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -276,7 +276,7 @@ class Triple {
Callable,
Mesh,
Amplification,
-
+OpenCL,
MaskRay wrote:
I wonder why we need this addition. This is not mentioned in the description.
https://github.com/llvm/llvm-project/pull/78655
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[libc] [lld] [flang] [libcxx] [clang] [clang-tools-extra] [compiler-rt] [llvm] [lldb] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -255,7 +255,7 @@ class Triple {
Cygnus,
CoreCLR,
Simulator, // Simulator variants of other systems, e.g., Apple's iOS
-MacABI, // Mac Catalyst variant of Apple's iOS deployment target.
+MacABI,// Mac Catalyst variant of Apple's iOS deployment target.
MaskRay wrote:
Revert this difference? You can ignore clang-format reports.
https://github.com/llvm/llvm-project/pull/78655
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[clang] [lld] [llvm] [libc] [flang] [libcxx] [compiler-rt] [clang-tools-extra] [lldb] Make clang report invalid target versions for all environment types. (PR #78655)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/78655 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [libc] [flang] [libcxx] [compiler-rt] [clang-tools-extra] [lldb] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -1443,15 +1443,17 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) {
const ToolChain = getToolChain(
*UArgs, computeTargetTriple(*this, TargetTriple, *UArgs));
- if (TC.getTriple().isAndroid()) {
-llvm::Triple Triple = TC.getTriple();
-StringRef TripleVersionName = Triple.getEnvironmentVersionString();
-
-if (Triple.getEnvironmentVersion().empty() && TripleVersionName != "") {
- Diags.Report(diag::err_drv_triple_version_invalid)
- << TripleVersionName << TC.getTripleString();
- ContainsError = true;
-}
+ // Check if the environment version is valid.
+ llvm::Triple Triple = TC.getTriple();
+ StringRef TripleVersionName = Triple.getEnvironmentVersionString();
+ StringRef TripleObjectFormat =
+ Triple.getObjectFormatTypeName(Triple.getObjectFormat());
+
MaskRay wrote:
(the prevailing code style does not insert a blank line in this case. )
https://github.com/llvm/llvm-project/pull/78655
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[lldb] [mlir] [libcxx] [lld] [flang] [libc] [clang] [llvm] [libunwind] [clang-tools-extra] [compiler-rt] [Driver,CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63df..7c0bfe32849614 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748faca..773bc1dcda01d5 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc17..7877e20d77f772 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine ,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab59..93fd579eb92ba5 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation , const JobAction
,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+if (Unsupported) {
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << TripleStr;
+} else if (!SupportedArgument) {
+ D.Diag(diag::err_drv_unsupported_option_argument_for_target)
+ << A->getSpelling() << V << TripleStr;
+} else if (EnableTLSDESC) {
+ CmdArgs.push_back("-enable-tlsdesc");
+}
+ }
+
// Add the target cpu
std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
if (!CPU.empty()) {
diff --git
[clang] [clang] Add GCC-compatible code model names for sparc64 (PR #79485)
MaskRay wrote: Have you checked whether these code models are actually implemented and how complete they are? For example, if one model is very far from complete, perhaps we should be honest and say it is unsupported. https://github.com/llvm/llvm-project/pull/79485 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e4781497..67d7e2562e9b17 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+
[compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+break;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+break;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+break;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+if (isInt<12>(val))
+ write32le(loc, 0x0013); // nop
+else
+ write32le(loc, utype(LUI, X_A0, hi20(val))); // lui a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (isInt<12>(val))
+ write32le(loc, itype(ADDI, X_A0, 0, val)); // addi a0,zero,
+else
+ write32le(loc, itype(ADDI, X_A0, X_A0, lo12(val))); // addi a0,a0,
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to LE");
+ }
+}
+
void RISCV::relocateAlloc(InputSectionBase , uint8_t *buf) const {
uint64_t secAddr = sec.getOutputSection()->addr;
if (auto *s = dyn_cast())
secAddr += s->outSecOff;
else if (auto *ehIn = dyn_cast())
secAddr += ehIn->getParent()->outSecOff;
- for (size_t i = 0, size = sec.relocs().size(); i != size; ++i) {
-const Relocation = sec.relocs()[i];
+ uint64_t tlsdescVal = 0;
+ bool isToLe = false;
+ const ArrayRef relocs = sec.relocs();
+ for (size_t i = 0, size = relocs.size(); i != size; ++i) {
+const Relocation = relocs[i];
uint8_t *loc = buf + rel.offset;
-const uint64_t val =
+uint64_t val =
sec.getRelocTargetVA(sec.file, rel.type, rel.addend,
secAddr + rel.offset, *rel.sym, rel.expr);
switch (rel.expr) {
case R_RELAX_HINT:
+ continue;
+case R_TLSDESC_PC:
+ // For R_RISCV_TLSDESC_HI20, store (sym)-PC to be used by the
+ // following two instructions L[DW] and ADDI.
+ if (rel.type == R_RISCV_TLSDESC_HI20)
+tlsdescVal = val;
+ else
+val = tlsdescVal;
break;
+case R_RELAX_TLS_GD_TO_IE:
+ // Only R_RISCV_TLSDESC_HI20 reaches here. tlsdescVal will be finalized
+ // after we see R_RISCV_TLSDESC_ADD_LO12 in the R_RELAX_TLS_GD_TO_LE
case.
+ // The net effect is that tlsdescVal will be smaller than `val` to take
+ // into account of NOP instructions (in the absence of R_RISCV_RELAX)
+ // before AUIPC.
+ tlsdescVal = val + rel.offset;
+ isToLe = false;
+ if (!(i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX))
+tlsdescToIe(loc, rel, val);
+ continue;
+case R_RELAX_TLS_GD_TO_LE:
+ // See the comment in handleTlsRelocation. For TLSDESC=>IE,
+ // R_RISCV_TLSDESC_{LOAD_LO12,ADD_LO12,CALL} also reach here. If isToIe
is
+ // true, this is actually TLSDESC=>IE optimization.
+ if (rel.type == R_RISCV_TLSDESC_HI20) {
+tlsdescVal = val;
+isToLe = true;
+ } else {
+if (!isToLe && rel.type == R_RISCV_TLSDESC_ADD_LO12)
+ tlsdescVal -= rel.offset;
+val = tlsdescVal;
+ }
+ // When NOP conversion is eligible and R_RISCV_RELAX is present, don't
+ // write a NOP in case an unrelated instruction follows the current
+ // instruction.
+ if ((rel.type == R_RISCV_TLSDESC_HI20 ||
+ rel.type == R_RISCV_TLSDESC_LOAD_LO12 ||
+ (rel.type == R_RISCV_TLSDESC_ADD_LO12 && isToLe && !hi20(val))) &&
+ i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX)
MaskRay wrote:
> That sounds like a nice approach.
Thanks. Adopted this approach:)
> Noted. Should we bring this up with the psABI?
Filed https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/421
https://github.com/llvm/llvm-project/pull/79239
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+
[compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+
[lld] [clang] [clang-tools-extra] [libunwind] [compiler-rt] [libc] [lldb] [llvm] [libcxx] [mlir] [flang] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lldb] [libunwind] [libcxx] [compiler-rt] [libc] [flang] [lld] [llvm] [clang-tools-extra] [mlir] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+break;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+break;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+break;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+if (isInt<12>(val))
+ write32le(loc, 0x0013); // nop
+else
+ write32le(loc, utype(LUI, X_A0, hi20(val))); // lui a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (isInt<12>(val))
+ write32le(loc, itype(ADDI, X_A0, 0, val)); // addi a0,zero,
+else
+ write32le(loc, itype(ADDI, X_A0, X_A0, lo12(val))); // addi a0,a0,
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to LE");
+ }
+}
+
void RISCV::relocateAlloc(InputSectionBase , uint8_t *buf) const {
uint64_t secAddr = sec.getOutputSection()->addr;
if (auto *s = dyn_cast())
secAddr += s->outSecOff;
else if (auto *ehIn = dyn_cast())
secAddr += ehIn->getParent()->outSecOff;
- for (size_t i = 0, size = sec.relocs().size(); i != size; ++i) {
-const Relocation = sec.relocs()[i];
+ uint64_t tlsdescVal = 0;
+ bool isToLe = false;
+ const ArrayRef relocs = sec.relocs();
+ for (size_t i = 0, size = relocs.size(); i != size; ++i) {
+const Relocation = relocs[i];
uint8_t *loc = buf + rel.offset;
-const uint64_t val =
+uint64_t val =
sec.getRelocTargetVA(sec.file, rel.type, rel.addend,
secAddr + rel.offset, *rel.sym, rel.expr);
switch (rel.expr) {
case R_RELAX_HINT:
+ continue;
+case R_TLSDESC_PC:
+ // For R_RISCV_TLSDESC_HI20, store (sym)-PC to be used by the
+ // following two instructions L[DW] and ADDI.
+ if (rel.type == R_RISCV_TLSDESC_HI20)
+tlsdescVal = val;
+ else
+val = tlsdescVal;
break;
+case R_RELAX_TLS_GD_TO_IE:
+ // Only R_RISCV_TLSDESC_HI20 reaches here. tlsdescVal will be finalized
+ // after we see R_RISCV_TLSDESC_ADD_LO12 in the R_RELAX_TLS_GD_TO_LE
case.
+ // The net effect is that tlsdescVal will be smaller than `val` to take
+ // into account of NOP instructions (in the absence of R_RISCV_RELAX)
+ // before AUIPC.
+ tlsdescVal = val + rel.offset;
+ isToLe = false;
+ if (!(i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX))
+tlsdescToIe(loc, rel, val);
+ continue;
+case R_RELAX_TLS_GD_TO_LE:
+ // See the comment in handleTlsRelocation. For TLSDESC=>IE,
+ // R_RISCV_TLSDESC_{LOAD_LO12,ADD_LO12,CALL} also reach here. If isToIe
is
+ // true, this is actually TLSDESC=>IE optimization.
+ if (rel.type == R_RISCV_TLSDESC_HI20) {
+tlsdescVal = val;
+isToLe = true;
+ } else {
+if (!isToLe && rel.type == R_RISCV_TLSDESC_ADD_LO12)
+ tlsdescVal -= rel.offset;
+val = tlsdescVal;
+ }
+ // When NOP conversion is eligible and R_RISCV_RELAX is present, don't
+ // write a NOP in case an unrelated instruction follows the current
+ // instruction.
+ if ((rel.type == R_RISCV_TLSDESC_HI20 ||
+ rel.type == R_RISCV_TLSDESC_LOAD_LO12 ||
+ (rel.type == R_RISCV_TLSDESC_ADD_LO12 && isToLe && !hi20(val))) &&
+ i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX)
MaskRay wrote:
I am thinking of a simplification where I only check whether
R_RISCV_TLSDESC_HI20 has an associated R_RISCV_RELAX. If yes, apply relaxation
whether or not the following 3 instructions has an associated R_RISCV_RELAX.
Then, I just use another variable to hold "whether there is R_RISCV_RELAX" and
arguably the straight line code will be more readable than introducing a
function call.
On the LLVM side, relaxation can be enabled by adding R_RISCV_RELAX to just the
first instruction, decreasing the size bloat (sizeof(Elf64_Rela) = 24). There
is not what
[clang] [RISCV] Reformat riscv-target-features.c. NFC (PR #79409)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/79409 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[mlir] [libunwind] [lld] [flang] [clang-tools-extra] [libc] [libcxx] [llvm] [clang] [compiler-rt] [lldb] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[mlir] [libunwind] [lld] [flang] [clang-tools-extra] [libc] [libcxx] [llvm] [clang] [compiler-rt] [lldb] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+
[mlir] [libunwind] [lld] [flang] [clang-tools-extra] [libc] [libcxx] [llvm] [clang] [compiler-rt] [lldb] [Driver, CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63df..7c0bfe32849614 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748faca..773bc1dcda01d5 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc17..7877e20d77f772 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine ,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab59..93fd579eb92ba5 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation , const JobAction
,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+if (Unsupported) {
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << TripleStr;
+} else if (!SupportedArgument) {
+ D.Diag(diag::err_drv_unsupported_option_argument_for_target)
+ << A->getSpelling() << V << TripleStr;
+} else if (EnableTLSDESC) {
+ CmdArgs.push_back("-enable-tlsdesc");
+}
+ }
+
// Add the target cpu
std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
if (!CPU.empty()) {
diff --git
[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -269,6 +286,142 @@ // CHECK-M-EXT: __riscv_mul 1 // CHECK-M-EXT: __riscv_muldiv 1 +// RUN: %clang --target=riscv32-unknown-linux-gnu \ MaskRay wrote: (For newer tests, ensure the continuation line is indented by 2 spaces) https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libc] [lldb] [libunwind] [clang] [compiler-rt] [mlir] [llvm] [lld] [flang] [libcxx] [clang-tools-extra] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
MaskRay wrote:
Thanks for catching this. Implemented the short form.
https://github.com/llvm/llvm-project/pull/79239
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libc] [lldb] [libunwind] [clang] [compiler-rt] [mlir] [llvm] [lld] [flang] [libcxx] [clang-tools-extra] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lldb] [flang] [libc] [clang] [lld] [clang-tools-extra] [libcxx] [compiler-rt] [libunwind] [llvm] [mlir] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+
[flang] [libunwind] [llvm] [clang] [lldb] [libc] [clang-tools-extra] [compiler-rt] [libcxx] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [libunwind] [llvm] [clang] [lldb] [libc] [clang-tools-extra] [compiler-rt] [libcxx] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -0,0 +1,125 @@
+# REQUIRES: riscv
+# RUN: rm -rf %t && split-file %s %t && cd %t
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax a.s -o a.64.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax c.s -o c.64.o
+# RUN: ld.lld -shared -soname=c.64.so c.64.o -o c.64.so
+
+# RUN: ld.lld -shared -z now a.64.o c.64.o -o a.64.so -z separate-code
+# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.so | FileCheck
%s --check-prefix=GD64
+
+# RUN: ld.lld -e 0 -z now a.64.o c.64.o -o a.64.le -z separate-code
+# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.le | FileCheck
%s --check-prefix=LE64
+
+# RUN: ld.lld -e 0 -z now a.64.o c.64.so -o a.64.ie -z separate-code
+# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.ie | FileCheck
%s --check-prefix=IE64
+
+# GD64: .got 0018 20c0
+# GD64-LABEL: <_start>:
+# GD64-NEXT: jal {{.*}}
+# GD64-LABEL: :
+## &.got[c]-. = 0x20c0+8 - 0x1004 = 0x10c4
+# GD64:1004: auipc a2, 0x1
+# GD64-NEXT: ld a3, 0xc4(a2)
+# GD64-NEXT: addia0, a2, 0xc4
+# GD64-NEXT: jalrt0, 0x0(a3)
+# GD64-NEXT: c.add a0, tp
+# GD64-NEXT: jal {{.*}}
+# GD64-NEXT: auipc a4, 0x1
+# GD64-NEXT: ld a5, 0xae(a4)
+# GD64-NEXT: addia0, a4, 0xae
+# GD64-NEXT: jalrt0, 0x0(a5)
+# GD64-NEXT: c.add a0, tp
+
+# LE64-LABEL: <_start>:
+# LE64-NEXT: jal {{.*}}
+# LE64-LABEL: :
+# LE64-NEXT: 11004: lui a0, 0x0
+# LE64-NEXT: addia0, zero, 0xc
+# LE64-NEXT: c.add a0, tp
+# LE64-NEXT: jal {{.*}}
+# LE64-NEXT: addizero, zero, 0x0
+# LE64-NEXT: lui a0, 0x0
+# LE64-NEXT: addia0, zero, 0xc
+# LE64-NEXT: c.add a0, tp
+# LE64-NEXT: addizero, zero, 0x0
+# LE64-NEXT: lui a0, 0x0
+# LE64-NEXT: addia0, zero, 0xc
+# LE64-NEXT: c.add a0, tp
+
+# IE64: .got 0010 000120e0
+# IE64-LABEL: <_start>:
+# IE64-NEXT: jal {{.*}}
+# IE64-LABEL: :
+## &.got[c]-. = 0x120e0+8 - 0x11004 = 0x10e4
+# IE64-NEXT: 11004: auipc a0, 0x1
+# IE64-NEXT: ld a0, 0xe4(a0)
+# IE64-NEXT: c.add a0, tp
+# IE64-NEXT: jal {{.*}}
+# IE64-NEXT: addizero, zero, 0x0
+## &.got[c]-. = 0x120e0+8 - 0x11016 = 0x10d2
+# IE64-NEXT: 11016: auipc a0, 0x1
+# IE64-NEXT: ld a0, 0xd2(a0)
+# IE64-NEXT: c.add a0, tp
+# IE64-NEXT: addizero, zero, 0x0
+## &.got[c]-. = 0x120e0+8 - 0x11024 = 0x10c4
+# IE64-NEXT: 11024: auipc a0, 0x1
+# IE64-NEXT: ld a0, 0xc4(a0)
+# IE64-NEXT: c.add a0, tp
+
+#--- a.s
+.globl _start
+_start:
+.balign 16
+ call foo
+
+foo:
+.Ltlsdesc_hi0:
+.option norelax
+## All 4 instructions have an R_RISCV_RELAX.
+ auipc a2, %tlsdesc_hi(c)
+ .reloc .-4, R_RISCV_RELAX, 0
+ lda3, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a2)
+ .reloc .-4, R_RISCV_RELAX, 0
+ addi a0, a2, %tlsdesc_add_lo(.Ltlsdesc_hi0)
+ .reloc .-4, R_RISCV_RELAX, 0
+ jalr t0, 0(a3), %tlsdesc_call(.Ltlsdesc_hi0)
+ .reloc .-4, R_RISCV_RELAX, 0
+ add a0, a0, tp
MaskRay wrote:
Thanks for noticing this. `i386-tlsdesc-gd.s` has `movl %edx, %ebx # GCC -O0
may add an extra insn in between.` that I forgot to copy here. Done.
This requires the following code to handle it.
```
+ // For HI20/LOAD_LO12, disable NOP conversion in the presence of
+ // R_RISCV_RELAX, in case an unrelated instruction follows the current
+ // instruction.
+ if ((rel.type == R_RISCV_TLSDESC_HI20 ||
+ rel.type == R_RISCV_TLSDESC_LOAD_LO12) &&
+ i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX)
+continue;
```
https://github.com/llvm/llvm-project/pull/79239
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lldb] [llvm] [compiler-rt] [flang] [clang] [clang-tools-extra] [libunwind] [lld] [libc] [libcxx] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e4781497..67d7e2562e9b17 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation ,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation , uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+
[flang] [libunwind] [llvm] [clang] [lldb] [libc] [clang-tools-extra] [compiler-rt] [libcxx] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [clang-tools-extra] [flang] [libc] [llvm] [lld] [compiler-rt] [lldb] [clang] [libunwind] [Driver,CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79256 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [compiler-rt] [lld] [clang-tools-extra] [clang] [lldb] [libcxx] [flang] [llvm] [libc] [Driver,CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63dfa..7c0bfe328496147 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748facaf..773bc1dcda01d5c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc173..7877e20d77f7724 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine ,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab599..93fd579eb92ba50 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation , const JobAction
,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+if (Unsupported) {
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << TripleStr;
+} else if (!SupportedArgument) {
+ D.Diag(diag::err_drv_unsupported_option_argument_for_target)
+ << A->getSpelling() << V << TripleStr;
+} else if (EnableTLSDESC) {
+ CmdArgs.push_back("-enable-tlsdesc");
+}
+ }
+
// Add the target cpu
std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
if (!CPU.empty()) {
diff --git
[clang] [Driver,CodeGen] Support -mtls-dialect= (PR #79256)
MaskRay wrote: > What's the expected interaction here with LTO? Modifying TargetOptions has no > effect if we're generating a bitcode file. Thanks for reminding me this. There seems no motivation to mix trad/desc, so I think we can do it the `-ffunction-sections`/`-femulated-tls` way by passing an option to the linker... https://github.com/llvm/llvm-project/pull/79256 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][Driver][RISCV] Honor -m[no-]global-merge for RISC-V (PR #79372)
@@ -2129,6 +2129,16 @@ void Clang::AddRISCVTargetArgs(const ArgList ,
<< A->getSpelling() << Val;
}
}
+
+ // Forward the -mglobal-merge option for explicit control over the pass.
+ if (Arg *A = Args.getLastArg(options::OPT_mglobal_merge,
+ options::OPT_mno_global_merge)) {
+CmdArgs.push_back("-mllvm");
MaskRay wrote:
I know that you are copying arm/aarch64, but for new code for a boolean option
(sometimes called flag), we use a convention to only pass a non-default option
to cc1.
Since `-riscv-enable-global-merge` defaults to 0, we only pass `-mllvm
-riscv-enable-global-merge` to cc1 (remove `=true`).
https://github.com/llvm/llvm-project/pull/79372
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[clang] 48570a6 - [Driver, test] Add --target= to unsupported-option-gpu.c
Author: Fangrui Song
Date: 2024-01-24T12:32:10-08:00
New Revision: 48570a6feb62c897dc4cdcd1dab3e99a0aa46d48
URL:
https://github.com/llvm/llvm-project/commit/48570a6feb62c897dc4cdcd1dab3e99a0aa46d48
DIFF:
https://github.com/llvm/llvm-project/commit/48570a6feb62c897dc4cdcd1dab3e99a0aa46d48.diff
LOG: [Driver,test] Add --target= to unsupported-option-gpu.c
Added:
Modified:
clang/test/Driver/unsupported-option-gpu.c
Removed:
diff --git a/clang/test/Driver/unsupported-option-gpu.c
b/clang/test/Driver/unsupported-option-gpu.c
index 225f3be7c76242c..f23cb71ebfb08ef 100644
--- a/clang/test/Driver/unsupported-option-gpu.c
+++ b/clang/test/Driver/unsupported-option-gpu.c
@@ -1,5 +1,5 @@
/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
-// DEFINE: %{check} = %clang -### -c -mcmodel=medium
+// DEFINE: %{check} = %clang -### --target=x86_64-linux-gnu -c -mcmodel=medium
// RUN: %{check} -x cuda %s --cuda-path=%S/Inputs/CUDA/usr/local/cuda
--offload-arch=sm_60 --no-cuda-version-check -fbasic-block-sections=all
// RUN: %{check} -x hip %s --rocm-path=%S/Inputs/rocm -nogpulib -nogpuinc
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[lld] [libc] [openmp] [lldb] [compiler-rt] [clang] [libcxx] [llvm] [clang-tools-extra] [mlir] [pstl] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79222 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lld] [libc] [openmp] [lldb] [compiler-rt] [clang] [libcxx] [llvm] [clang-tools-extra] [mlir] [pstl] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,5 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{check} = %clang -### -c -mcmodel=medium
MaskRay wrote:
In general the error reporting is done in the driver and cc1 allows and ignores
options that may be specific to other targets.
> That said, we do have other options that we do need to suppress/ignore and
> some of that does happen on cc1 level.
Perhaps we should figure out them and check whether they should be moved to the
driver
https://github.com/llvm/llvm-project/pull/79222
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[libc] [lld] [clang] [libunwind] [compiler-rt] [flang] [lldb] [openmp] [libcxx] [mlir] [llvm] [pstl] [clang-tools-extra] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALL
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79238 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libc] [lld] [clang] [libunwind] [compiler-rt] [flang] [lldb] [openmp] [libcxx] [mlir] [llvm] [pstl] [clang-tools-extra] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALL
MaskRay wrote:
Fixed a typo and added an example
> ```
> // clang -g
> __attribute__((weak)) int symbol;
> int *foo() { return }
>
> 0x0023: DW_TAG_variable [2] (0x000c)
> ...
> DW_AT_location [DW_FORM_exprloc](DW_OP_addrx 0x0)
> ```
>
>
> .debug_addr references `symbol`, which can be redefined by a symbol
> assignment or --defsym to become a SHN_ABS symbol.
https://github.com/llvm/llvm-project/pull/79238
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[libc] [lld] [clang] [libunwind] [compiler-rt] [flang] [lldb] [openmp] [libcxx] [mlir] [llvm] [pstl] [clang-tools-extra] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALL
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79238
>From 97b500a7061041b5478b6b1b1094e76140e3d9c3 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:53:31 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/InputSection.cpp | 13 ++---
lld/test/ELF/dead-reloc-in-nonalloc.s | 2 +-
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index c728dd6c6306aa0..0e0b9783bd88a0f 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -961,12 +961,11 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
// vector. The computed value is st_value plus a non-negative offset.
// Negative values are invalid, so -1 can be used as the tombstone value.
//
- // If the referenced symbol is discarded (made Undefined), or the
- // section defining the referenced symbol is garbage collected,
- // sym.getOutputSection() is nullptr. `ds->folded` catches the ICF folded
- // case. However, resolving a relocation in .debug_line to -1 would stop
- // debugger users from setting breakpoints on the folded-in function, so
- // exclude .debug_line.
+ // If the referenced symbol is relative to a discarded section (due to
+ // --gc-sections, COMDAT, etc), it has been converted to a Undefined.
+ // `ds->folded` catches the ICF folded case. However, resolving a
+ // relocation in .debug_line to -1 would stop debugger users from setting
+ // breakpoints on the folded-in function, so exclude .debug_line.
//
// For pre-DWARF-v5 .debug_loc and .debug_ranges, -1 is a reserved value
// (base address selection entry), use 1 (which is used by GNU ld for
@@ -974,7 +973,7 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
//
// TODO To reduce disruption, we use 0 instead of -1 as the tombstone
// value. Enable -1 in a future release.
- if (!sym.getOutputSection() || (ds && ds->folded && !isDebugLine)) {
+ if (!ds || (ds->folded && !isDebugLine)) {
// If -z dead-reloc-in-nonalloc= is specified, respect it.
uint64_t value = SignExtend64(*tombstone);
// For a 32-bit local TU reference in .debug_names, X86_64::relocate
diff --git a/lld/test/ELF/dead-reloc-in-nonalloc.s
b/lld/test/ELF/dead-reloc-in-nonalloc.s
index 145604eb883a9af..b675fc50fc2ea2f 100644
--- a/lld/test/ELF/dead-reloc-in-nonalloc.s
+++ b/lld/test/ELF/dead-reloc-in-nonalloc.s
@@ -17,7 +17,7 @@
# AA: Contents of section .debug_info:
# AA-NEXT: [[ADDR]]
# AA: Contents of section .not_debug:
-# AA-NEXT: .
+# AA-NEXT: 2a00 .
## Specifying zero can get a behavior similar to GNU ld.
# RUN: ld.lld --icf=all -z dead-reloc-in-nonalloc=.debug_info=0 %t.o %tabs.o
-o %tzero
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[pstl] [libcxx] [lldb] [llvm] [compiler-rt] [libunwind] [mlir] [clang-tools-extra] [libc] [flang] [clang] [lld] [openmp] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALL
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79238 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lld] [clang] [llvm] [mlir] [pstl] [libcxx] [openmp] [lldb] [clang-tools-extra] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALLOC sections (PR #79238)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79238
>From 97b500a7061041b5478b6b1b1094e76140e3d9c3 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:53:31 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/InputSection.cpp | 13 ++---
lld/test/ELF/dead-reloc-in-nonalloc.s | 2 +-
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index c728dd6c6306aa..0e0b9783bd88a0 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -961,12 +961,11 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
// vector. The computed value is st_value plus a non-negative offset.
// Negative values are invalid, so -1 can be used as the tombstone value.
//
- // If the referenced symbol is discarded (made Undefined), or the
- // section defining the referenced symbol is garbage collected,
- // sym.getOutputSection() is nullptr. `ds->folded` catches the ICF folded
- // case. However, resolving a relocation in .debug_line to -1 would stop
- // debugger users from setting breakpoints on the folded-in function, so
- // exclude .debug_line.
+ // If the referenced symbol is relative to a discarded section (due to
+ // --gc-sections, COMDAT, etc), it has been converted to a Undefined.
+ // `ds->folded` catches the ICF folded case. However, resolving a
+ // relocation in .debug_line to -1 would stop debugger users from setting
+ // breakpoints on the folded-in function, so exclude .debug_line.
//
// For pre-DWARF-v5 .debug_loc and .debug_ranges, -1 is a reserved value
// (base address selection entry), use 1 (which is used by GNU ld for
@@ -974,7 +973,7 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
//
// TODO To reduce disruption, we use 0 instead of -1 as the tombstone
// value. Enable -1 in a future release.
- if (!sym.getOutputSection() || (ds && ds->folded && !isDebugLine)) {
+ if (!ds || (ds->folded && !isDebugLine)) {
// If -z dead-reloc-in-nonalloc= is specified, respect it.
uint64_t value = SignExtend64(*tombstone);
// For a 32-bit local TU reference in .debug_names, X86_64::relocate
diff --git a/lld/test/ELF/dead-reloc-in-nonalloc.s
b/lld/test/ELF/dead-reloc-in-nonalloc.s
index 145604eb883a9a..b675fc50fc2ea2 100644
--- a/lld/test/ELF/dead-reloc-in-nonalloc.s
+++ b/lld/test/ELF/dead-reloc-in-nonalloc.s
@@ -17,7 +17,7 @@
# AA: Contents of section .debug_info:
# AA-NEXT: [[ADDR]]
# AA: Contents of section .not_debug:
-# AA-NEXT: .
+# AA-NEXT: 2a00 .
## Specifying zero can get a behavior similar to GNU ld.
# RUN: ld.lld --icf=all -z dead-reloc-in-nonalloc=.debug_info=0 %t.o %tabs.o
-o %tzero
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[pstl] [lldb] [llvm] [openmp] [clang-tools-extra] [libcxx] [lld] [mlir] [clang] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALLOC sections (PR #79238)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79238 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [KMSAN] Enable on PowerPC64 (PR #73611)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/73611 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver,CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63dfa..7c0bfe328496147 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748facaf..773bc1dcda01d5c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc173..7877e20d77f7724 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine ,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab599..93fd579eb92ba50 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation , const JobAction
,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+if (Unsupported) {
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << TripleStr;
+} else if (!SupportedArgument) {
+ D.Diag(diag::err_drv_unsupported_option_argument_for_target)
+ << A->getSpelling() << V << TripleStr;
+} else if (EnableTLSDESC) {
+ CmdArgs.push_back("-enable-tlsdesc");
+}
+ }
+
// Add the target cpu
std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
if (!CPU.empty()) {
diff --git
[clang] [clang][driver] Add -mtls-dialect option (PR #79031)
MaskRay wrote: Since TLSDialect only has 2 values and it's unlikely a future change will add new, I think sticking with a boolean codegenopt suffices. For x86, we can probably support "gnu" as "gnu2" (TLSDESC) is a desired feature. (I added lld support, but I did not know codegen well enough to add LLVM part...) I think #79256 is a more complete patch, with these ideas taken into account.. It may be a good candidate for the `release/18.x` branch. https://github.com/llvm/llvm-project/pull/79031 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver,CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay created
https://github.com/llvm/llvm-project/pull/79256
GCC supports -mtls-dialect= for several architectures to select TLSDESC.
This patch supports the following values
* x86: "gnu". "gnu2" (TLSDESC) is not supported yet.
* RISC-V: "trad" (general dynamic), "desc" (TLSDESC, see #66915)
AArch64 toolchains seem to support TLSDESC from the beginning, and the
general dynamic model has poor support. Nobody seems to use the option
-mtls-dialect= at all, so we don't bother with it.
There also seems very little interest in AArch32's TLSDESC support.
Co-authored-by: Paul Kirth
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63dfa..7c0bfe328496147 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748facaf..773bc1dcda01d5c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc173..7877e20d77f7724 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine ,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab599..93fd579eb92ba50 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation , const JobAction
,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+
[lldb] [clang] [clang-tools-extra] [openmp] [lld] [libc] [libcxx] [mlir] [pstl] [compiler-rt] [llvm] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
+
+// REDEFINE: %{gpu_opts} = -x hip --rocm-path=%S/Inputs/rocm -nogpulib
MaskRay wrote:
Added!
https://github.com/llvm/llvm-project/pull/79222
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[libcxx] [clang] [openmp] [lldb] [lld] [compiler-rt] [clang-tools-extra] [pstl] [mlir] [llvm] [libc] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79222
>From 3a2b2a1110e7b3348a12a6476ab014a469891062 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 15:13:49 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/test/Driver/unsupported-option-gpu.c | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 clang/test/Driver/unsupported-option-gpu.c
diff --git a/clang/test/Driver/unsupported-option-gpu.c
b/clang/test/Driver/unsupported-option-gpu.c
new file mode 100644
index 00..5713dbbfc7ae4d
--- /dev/null
+++ b/clang/test/Driver/unsupported-option-gpu.c
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
+
+// REDEFINE: %{gpu_opts} = -x hip --rocm-path=%S/Inputs/rocm -nogpulib
+// RUN: %{check}
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[clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
MaskRay wrote:
Thanks for the suggestion. Edited
https://github.com/llvm/llvm-project/pull/79222
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[clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79222 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79222 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79222 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
MaskRay wrote:
Added `-x cuda`. The test is to show we don't get an error
(`err_drv_unsupported_opt_for_target`) when compiling for x86_64 using a device
(AMDGPU/NVPTX) when certain target-specified options are specified.
I am not familiar with offloading but specifying `--cuda-host-only` would
defeat the purpose.
https://github.com/llvm/llvm-project/pull/79222
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[clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79222
>From 3a2b2a1110e7b3348a12a6476ab014a469891062 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 15:13:49 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/test/Driver/unsupported-option-gpu.c | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 clang/test/Driver/unsupported-option-gpu.c
diff --git a/clang/test/Driver/unsupported-option-gpu.c
b/clang/test/Driver/unsupported-option-gpu.c
new file mode 100644
index 00..5713dbbfc7ae4d
--- /dev/null
+++ b/clang/test/Driver/unsupported-option-gpu.c
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
+
+// REDEFINE: %{gpu_opts} = -x hip --rocm-path=%S/Inputs/rocm -nogpulib
+// RUN: %{check}
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[clang] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
MaskRay wrote:
I think `gpu_opts` can be merged into `%{check}`. `%{check}` should be kept as
it will become longer soon.
https://github.com/llvm/llvm-project/pull/79222
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[clang] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay created
https://github.com/llvm/llvm-project/pull/79222
Fix missing test coverage after #70740 #70760
>From 3a2b2a1110e7b3348a12a6476ab014a469891062 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 15:13:49 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/test/Driver/unsupported-option-gpu.c | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 clang/test/Driver/unsupported-option-gpu.c
diff --git a/clang/test/Driver/unsupported-option-gpu.c
b/clang/test/Driver/unsupported-option-gpu.c
new file mode 100644
index 00..5713dbbfc7ae4d
--- /dev/null
+++ b/clang/test/Driver/unsupported-option-gpu.c
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
+
+// REDEFINE: %{gpu_opts} = -x hip --rocm-path=%S/Inputs/rocm -nogpulib
+// RUN: %{check}
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[lldb] [libclc] [libc] [clang] [compiler-rt] [mlir] [flang] [clang-tools-extra] [libcxx] [lld] [llvm] [libcxxabi] [ELF] Add internal InputFile (PR #78944)
MaskRay wrote: Hi, do you have more information (like a reproduce tarball) about a `file` that references a file of `InternalKind`? Could it be a patch in your downstream? If `file` references a file of `InternalKind`, we probably should make it `nullptr` instead. But I don't know a code path where it is the case for the upstream lld. https://github.com/llvm/llvm-project/pull/78944 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [compiler-rt] [llvm] [libcxx] [openmp] [mlir] [libc] [clang-tools-extra] [lld] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
MaskRay wrote: > We're seeing a test failure on our buildbot after this patch landed. Could > you take a look? > > [lab.llvm.org/buildbot/#/builders/216/builds/33382/steps/7/logs/FAIL__lld__defsym_ll](https://lab.llvm.org/buildbot/#/builders/216/builds/33382/steps/7/logs/FAIL__lld__defsym_ll) > > ``` > # RUN: at line 4 > z:\b\llvm-clang-x86_64-sie-win\build\bin\llvm-as.exe > Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto/Inputs/defsym-bar.ll > -o > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o > # executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\llvm-as.exe' > 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto/Inputs/defsym-bar.ll' > -o > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o' > # RUN: at line 5 > z:\b\llvm-clang-x86_64-sie-win\build\bin\ld.lld.exe > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.o > > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o > -shared -o > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.so > -defsym=bar2=bar3 -save-temps > # executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\ld.lld.exe' > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.o' > > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o' > -shared -o > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.so' > -defsym=bar2=bar3 -save-temps > # RUN: at line 6 > z:\b\llvm-clang-x86_64-sie-win\build\bin\llvm-readelf.exe --symbols > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.so.lto.o > | z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe --check-prefix=OBJ > Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto\defsym.ll > # executed command: > 'z:\b\llvm-clang-x86_64-sie-win\build\bin\llvm-readelf.exe' --symbols > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.so.lto.o' > # executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe' > --check-prefix=OBJ > 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto\defsym.ll' > # RUN: at line 7 > z:\b\llvm-clang-x86_64-sie-win\build\bin\llvm-objdump.exe -d > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.so > | z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe > Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto\defsym.ll > # executed command: > 'z:\b\llvm-clang-x86_64-sie-win\build\bin\llvm-objdump.exe' -d > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.so' > # executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe' > 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto\defsym.ll' > # RUN: at line 10 > z:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe -module-summary > Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto\defsym.ll -o > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.o > # executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe' > -module-summary > 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto\defsym.ll' -o > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.o' > # RUN: at line 11 > z:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe -module-summary > Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto/Inputs/defsym-bar.ll > -o > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o > # executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe' > -module-summary > 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\lld\test\ELF\lto/Inputs/defsym-bar.ll' > -o > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o' > # RUN: at line 12 > z:\b\llvm-clang-x86_64-sie-win\build\bin\ld.lld.exe > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.o > > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o > -shared -o > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp2.so > -defsym=bar2=bar3 -save-temps > # executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\ld.lld.exe' > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp.o' > > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp1.o' > -shared -o > 'Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp2.so' > -defsym=bar2=bar3 -save-temps > # RUN: at line 13 > z:\b\llvm-clang-x86_64-sie-win\build\bin\llvm-readelf.exe --symbols > Z:\b\llvm-clang-x86_64-sie-win\build\tools\lld\test\ELF\lto\Output\defsym.ll.tmp2.so1.lto.o > |
[compiler-rt] [openmp] [libc] [libcxx] [flang] [mlir] [llvm] [clang] [clang-tools-extra] [lld] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/78835 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [libcxx] [flang] [lld] [clang-tools-extra] [mlir] [openmp] [compiler-rt] [llvm] [libc] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/78835
>From 37b3ff263f2b46bd4541157bee5b5e1bf2639604 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Sat, 20 Jan 2024 00:40:53 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/LTO.cpp| 70 ++
lld/ELF/LTO.h | 3 +-
lld/test/ELF/common-archive-lookup.s | 7 ++-
lld/test/ELF/lto/comdat-mixed-archive.test | 4 +-
lld/test/ELF/lto/emit-asm.ll | 13 ++--
lld/test/ELF/lto/exclude-libs-libcall.ll | 2 +-
lld/test/ELF/lto/obj-path.ll | 4 +-
lld/test/ELF/lto/parallel-internalize.ll | 2 +-
lld/test/ELF/lto/parallel.ll | 2 +-
lld/test/ELF/lto/pseudo-probe-lto.ll | 3 +-
lld/test/ELF/lto/save-temps-eq.ll | 10 ++--
lld/test/ELF/lto/thinlto.ll| 48 +++
12 files changed, 97 insertions(+), 71 deletions(-)
diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp
index 504c12aac6c569..843ee59479eae9 100644
--- a/lld/ELF/LTO.cpp
+++ b/lld/ELF/LTO.cpp
@@ -12,6 +12,7 @@
#include "SymbolTable.h"
#include "Symbols.h"
#include "lld/Common/Args.h"
+#include "lld/Common/CommonLinkerContext.h"
#include "lld/Common/ErrorHandler.h"
#include "lld/Common/Filesystem.h"
#include "lld/Common/Strings.h"
@@ -26,6 +27,7 @@
#include "llvm/Support/Caching.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Error.h"
+#include "llvm/Support/Path.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/MemoryBuffer.h"
#include
@@ -303,6 +305,7 @@ std::vector BitcodeCompiler::compile() {
unsigned maxTasks = ltoObj->getMaxTasks();
buf.resize(maxTasks);
files.resize(maxTasks);
+ filenames.resize(maxTasks);
// The --thinlto-cache-dir option specifies the path to a directory in which
// to cache native object files for ThinLTO incremental builds. If a path was
@@ -313,13 +316,15 @@ std::vector BitcodeCompiler::compile() {
[&](size_t task, const Twine ,
std::unique_ptr mb) {
files[task] = std::move(mb);
+ filenames[task] = moduleName.str();
}));
if (!ctx.bitcodeFiles.empty())
checkError(ltoObj->run(
[&](size_t task, const Twine ) {
+ buf[task].first = moduleName.str();
return std::make_unique(
- std::make_unique(buf[task]));
+ std::make_unique(buf[task].second));
},
cache));
@@ -338,7 +343,7 @@ std::vector BitcodeCompiler::compile() {
if (config->thinLTOIndexOnly) {
if (!config->ltoObjPath.empty())
- saveBuffer(buf[0], config->ltoObjPath);
+ saveBuffer(buf[0].second, config->ltoObjPath);
// ThinLTO with index only option is required to generate only the index
// files. After that, we exit from linker and ThinLTO backend runs in a
@@ -352,32 +357,49 @@ std::vector BitcodeCompiler::compile() {
pruneCache(config->thinLTOCacheDir, config->thinLTOCachePolicy, files);
if (!config->ltoObjPath.empty()) {
-saveBuffer(buf[0], config->ltoObjPath);
+saveBuffer(buf[0].second, config->ltoObjPath);
for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->ltoObjPath + Twine(i));
- }
-
- if (config->saveTempsArgs.contains("prelink")) {
-if (!buf[0].empty())
- saveBuffer(buf[0], config->outputFile + ".lto.o");
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i) + ".lto.o");
- }
-
- if (config->ltoEmitAsm) {
-saveBuffer(buf[0], config->outputFile);
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i));
-return {};
+ saveBuffer(buf[i].second, config->ltoObjPath + Twine(i));
}
+ bool savePrelink = config->saveTempsArgs.contains("prelink");
std::vector ret;
- for (unsigned i = 0; i != maxTasks; ++i)
-if (!buf[i].empty())
- ret.push_back(createObjFile(MemoryBufferRef(buf[i], "lto.tmp")));
+ const char *ext = config->ltoEmitAsm ? ".s" : ".o";
+ for (unsigned i = 0; i != maxTasks; ++i) {
+StringRef bitcodeFilePath;
+StringRef objBuf;
+if (files[i]) {
+ objBuf = files[i]->getBuffer();
+ bitcodeFilePath = filenames[i];
+} else {
+ objBuf = buf[i].second;
+ bitcodeFilePath = buf[i].first;
+}
+if (objBuf.empty())
+ continue;
- for (std::unique_ptr : files)
-if (file)
- ret.push_back(createObjFile(*file));
+// If the input bitcode file is path/to/a.o and -o specifies a.out, then
the
+// corresponding lto object file name will look something like:
+// path/to/a.out.lto.a.o.
+
[clang-tools-extra] [libcxx] [llvm] [openmp] [mlir] [compiler-rt] [flang] [clang] [libc] [lld] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/78835 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [libc] [clang] [lld] [clang-tools-extra] [flang] [compiler-rt] [llvm] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
@@ -46,8 +46,9 @@ class BitcodeCompiler {
private:
std::unique_ptr ltoObj;
- std::vector> buf;
+ SmallVector>, 0> buf;
MaskRay wrote:
Added a comment
https://github.com/llvm/llvm-project/pull/78835
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[compiler-rt] [clang] [libc] [libcxx] [lld] [clang-tools-extra] [llvm] [flang] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
@@ -352,32 +357,49 @@ std::vector BitcodeCompiler::compile() {
pruneCache(config->thinLTOCacheDir, config->thinLTOCachePolicy, files);
if (!config->ltoObjPath.empty()) {
-saveBuffer(buf[0], config->ltoObjPath);
+saveBuffer(buf[0].second, config->ltoObjPath);
for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->ltoObjPath + Twine(i));
- }
-
- if (config->saveTempsArgs.contains("prelink")) {
-if (!buf[0].empty())
- saveBuffer(buf[0], config->outputFile + ".lto.o");
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i) + ".lto.o");
- }
-
- if (config->ltoEmitAsm) {
-saveBuffer(buf[0], config->outputFile);
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i));
-return {};
+ saveBuffer(buf[i].second, config->ltoObjPath + Twine(i));
}
+ bool savePrelink = config->saveTempsArgs.contains("prelink");
std::vector ret;
- for (unsigned i = 0; i != maxTasks; ++i)
-if (!buf[i].empty())
- ret.push_back(createObjFile(MemoryBufferRef(buf[i], "lto.tmp")));
+ const char *ext = config->ltoEmitAsm ? ".s" : ".o";
+ for (unsigned i = 0; i != maxTasks; ++i) {
+StringRef bitcodeFilePath;
+StringRef objBuf;
+if (files[i]) {
MaskRay wrote:
Clarified the comment a bit
https://github.com/llvm/llvm-project/pull/78835
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[compiler-rt] [clang] [libc] [libcxx] [lld] [clang-tools-extra] [llvm] [flang] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/78835
>From 37b3ff263f2b46bd4541157bee5b5e1bf2639604 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Sat, 20 Jan 2024 00:40:53 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/LTO.cpp| 70 ++
lld/ELF/LTO.h | 3 +-
lld/test/ELF/common-archive-lookup.s | 7 ++-
lld/test/ELF/lto/comdat-mixed-archive.test | 4 +-
lld/test/ELF/lto/emit-asm.ll | 13 ++--
lld/test/ELF/lto/exclude-libs-libcall.ll | 2 +-
lld/test/ELF/lto/obj-path.ll | 4 +-
lld/test/ELF/lto/parallel-internalize.ll | 2 +-
lld/test/ELF/lto/parallel.ll | 2 +-
lld/test/ELF/lto/pseudo-probe-lto.ll | 3 +-
lld/test/ELF/lto/save-temps-eq.ll | 10 ++--
lld/test/ELF/lto/thinlto.ll| 48 +++
12 files changed, 97 insertions(+), 71 deletions(-)
diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp
index 504c12aac6c5696..843ee59479eae92 100644
--- a/lld/ELF/LTO.cpp
+++ b/lld/ELF/LTO.cpp
@@ -12,6 +12,7 @@
#include "SymbolTable.h"
#include "Symbols.h"
#include "lld/Common/Args.h"
+#include "lld/Common/CommonLinkerContext.h"
#include "lld/Common/ErrorHandler.h"
#include "lld/Common/Filesystem.h"
#include "lld/Common/Strings.h"
@@ -26,6 +27,7 @@
#include "llvm/Support/Caching.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Error.h"
+#include "llvm/Support/Path.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/MemoryBuffer.h"
#include
@@ -303,6 +305,7 @@ std::vector BitcodeCompiler::compile() {
unsigned maxTasks = ltoObj->getMaxTasks();
buf.resize(maxTasks);
files.resize(maxTasks);
+ filenames.resize(maxTasks);
// The --thinlto-cache-dir option specifies the path to a directory in which
// to cache native object files for ThinLTO incremental builds. If a path was
@@ -313,13 +316,15 @@ std::vector BitcodeCompiler::compile() {
[&](size_t task, const Twine ,
std::unique_ptr mb) {
files[task] = std::move(mb);
+ filenames[task] = moduleName.str();
}));
if (!ctx.bitcodeFiles.empty())
checkError(ltoObj->run(
[&](size_t task, const Twine ) {
+ buf[task].first = moduleName.str();
return std::make_unique(
- std::make_unique(buf[task]));
+ std::make_unique(buf[task].second));
},
cache));
@@ -338,7 +343,7 @@ std::vector BitcodeCompiler::compile() {
if (config->thinLTOIndexOnly) {
if (!config->ltoObjPath.empty())
- saveBuffer(buf[0], config->ltoObjPath);
+ saveBuffer(buf[0].second, config->ltoObjPath);
// ThinLTO with index only option is required to generate only the index
// files. After that, we exit from linker and ThinLTO backend runs in a
@@ -352,32 +357,49 @@ std::vector BitcodeCompiler::compile() {
pruneCache(config->thinLTOCacheDir, config->thinLTOCachePolicy, files);
if (!config->ltoObjPath.empty()) {
-saveBuffer(buf[0], config->ltoObjPath);
+saveBuffer(buf[0].second, config->ltoObjPath);
for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->ltoObjPath + Twine(i));
- }
-
- if (config->saveTempsArgs.contains("prelink")) {
-if (!buf[0].empty())
- saveBuffer(buf[0], config->outputFile + ".lto.o");
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i) + ".lto.o");
- }
-
- if (config->ltoEmitAsm) {
-saveBuffer(buf[0], config->outputFile);
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i));
-return {};
+ saveBuffer(buf[i].second, config->ltoObjPath + Twine(i));
}
+ bool savePrelink = config->saveTempsArgs.contains("prelink");
std::vector ret;
- for (unsigned i = 0; i != maxTasks; ++i)
-if (!buf[i].empty())
- ret.push_back(createObjFile(MemoryBufferRef(buf[i], "lto.tmp")));
+ const char *ext = config->ltoEmitAsm ? ".s" : ".o";
+ for (unsigned i = 0; i != maxTasks; ++i) {
+StringRef bitcodeFilePath;
+StringRef objBuf;
+if (files[i]) {
+ objBuf = files[i]->getBuffer();
+ bitcodeFilePath = filenames[i];
+} else {
+ objBuf = buf[i].second;
+ bitcodeFilePath = buf[i].first;
+}
+if (objBuf.empty())
+ continue;
- for (std::unique_ptr : files)
-if (file)
- ret.push_back(createObjFile(*file));
+// If the input bitcode file is path/to/a.o and -o specifies a.out, then
the
+// corresponding lto object file name will look something like:
+// path/to/a.out.lto.a.o.
+
[lld] [clang-tools-extra] [llvm] [clang] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
@@ -53,10 +53,10 @@
; RUN: rm -fr cache && mkdir cache
; RUN: ld.lld --thinlto-cache-dir=cache --save-temps -o out b.bc a.bc -M |
FileCheck %s --check-prefix=MAP
-; RUN: ls out1.lto.o a.bc.0.preopt.bc b.bc.0.preopt.bc
+; RUN: ls out.lto.a.o a.bc.0.preopt.bc b.bc.0.preopt.bc
-; MAP: llvmcache-{{.*}}:(.text)
-; MAP: llvmcache-{{.*}}:(.text)
+; MAP: out.lto.b.o:(.text)
MaskRay wrote:
This is a new test. I noticed the `-Map` difference, so I pre-committed a test
and changed this PR to demonstrate the difference.
https://github.com/llvm/llvm-project/pull/78835
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[clang] [llvm] [lld] [clang-tools-extra] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
@@ -352,32 +357,49 @@ std::vector BitcodeCompiler::compile() {
pruneCache(config->thinLTOCacheDir, config->thinLTOCachePolicy, files);
if (!config->ltoObjPath.empty()) {
-saveBuffer(buf[0], config->ltoObjPath);
+saveBuffer(buf[0].second, config->ltoObjPath);
for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->ltoObjPath + Twine(i));
- }
-
- if (config->saveTempsArgs.contains("prelink")) {
-if (!buf[0].empty())
- saveBuffer(buf[0], config->outputFile + ".lto.o");
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i) + ".lto.o");
- }
-
- if (config->ltoEmitAsm) {
-saveBuffer(buf[0], config->outputFile);
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i));
-return {};
+ saveBuffer(buf[i].second, config->ltoObjPath + Twine(i));
}
+ bool savePrelink = config->saveTempsArgs.contains("prelink");
std::vector ret;
- for (unsigned i = 0; i != maxTasks; ++i)
-if (!buf[i].empty())
- ret.push_back(createObjFile(MemoryBufferRef(buf[i], "lto.tmp")));
+ const char *ext = config->ltoEmitAsm ? ".s" : ".o";
+ for (unsigned i = 0; i != maxTasks; ++i) {
+StringRef bitcodeFilePath;
+StringRef objBuf;
+if (files[i]) {
MaskRay wrote:
Done!
https://github.com/llvm/llvm-project/pull/78835
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[clang-tools-extra] [llvm] [lld] [clang] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/78835
>From 37b3ff263f2b46bd4541157bee5b5e1bf2639604 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Sat, 20 Jan 2024 00:40:53 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/LTO.cpp| 70 ++
lld/ELF/LTO.h | 3 +-
lld/test/ELF/common-archive-lookup.s | 7 ++-
lld/test/ELF/lto/comdat-mixed-archive.test | 4 +-
lld/test/ELF/lto/emit-asm.ll | 13 ++--
lld/test/ELF/lto/exclude-libs-libcall.ll | 2 +-
lld/test/ELF/lto/obj-path.ll | 4 +-
lld/test/ELF/lto/parallel-internalize.ll | 2 +-
lld/test/ELF/lto/parallel.ll | 2 +-
lld/test/ELF/lto/pseudo-probe-lto.ll | 3 +-
lld/test/ELF/lto/save-temps-eq.ll | 10 ++--
lld/test/ELF/lto/thinlto.ll| 48 +++
12 files changed, 97 insertions(+), 71 deletions(-)
diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp
index 504c12aac6c5696..843ee59479eae92 100644
--- a/lld/ELF/LTO.cpp
+++ b/lld/ELF/LTO.cpp
@@ -12,6 +12,7 @@
#include "SymbolTable.h"
#include "Symbols.h"
#include "lld/Common/Args.h"
+#include "lld/Common/CommonLinkerContext.h"
#include "lld/Common/ErrorHandler.h"
#include "lld/Common/Filesystem.h"
#include "lld/Common/Strings.h"
@@ -26,6 +27,7 @@
#include "llvm/Support/Caching.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Error.h"
+#include "llvm/Support/Path.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/MemoryBuffer.h"
#include
@@ -303,6 +305,7 @@ std::vector BitcodeCompiler::compile() {
unsigned maxTasks = ltoObj->getMaxTasks();
buf.resize(maxTasks);
files.resize(maxTasks);
+ filenames.resize(maxTasks);
// The --thinlto-cache-dir option specifies the path to a directory in which
// to cache native object files for ThinLTO incremental builds. If a path was
@@ -313,13 +316,15 @@ std::vector BitcodeCompiler::compile() {
[&](size_t task, const Twine ,
std::unique_ptr mb) {
files[task] = std::move(mb);
+ filenames[task] = moduleName.str();
}));
if (!ctx.bitcodeFiles.empty())
checkError(ltoObj->run(
[&](size_t task, const Twine ) {
+ buf[task].first = moduleName.str();
return std::make_unique(
- std::make_unique(buf[task]));
+ std::make_unique(buf[task].second));
},
cache));
@@ -338,7 +343,7 @@ std::vector BitcodeCompiler::compile() {
if (config->thinLTOIndexOnly) {
if (!config->ltoObjPath.empty())
- saveBuffer(buf[0], config->ltoObjPath);
+ saveBuffer(buf[0].second, config->ltoObjPath);
// ThinLTO with index only option is required to generate only the index
// files. After that, we exit from linker and ThinLTO backend runs in a
@@ -352,32 +357,49 @@ std::vector BitcodeCompiler::compile() {
pruneCache(config->thinLTOCacheDir, config->thinLTOCachePolicy, files);
if (!config->ltoObjPath.empty()) {
-saveBuffer(buf[0], config->ltoObjPath);
+saveBuffer(buf[0].second, config->ltoObjPath);
for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->ltoObjPath + Twine(i));
- }
-
- if (config->saveTempsArgs.contains("prelink")) {
-if (!buf[0].empty())
- saveBuffer(buf[0], config->outputFile + ".lto.o");
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i) + ".lto.o");
- }
-
- if (config->ltoEmitAsm) {
-saveBuffer(buf[0], config->outputFile);
-for (unsigned i = 1; i != maxTasks; ++i)
- saveBuffer(buf[i], config->outputFile + Twine(i));
-return {};
+ saveBuffer(buf[i].second, config->ltoObjPath + Twine(i));
}
+ bool savePrelink = config->saveTempsArgs.contains("prelink");
std::vector ret;
- for (unsigned i = 0; i != maxTasks; ++i)
-if (!buf[i].empty())
- ret.push_back(createObjFile(MemoryBufferRef(buf[i], "lto.tmp")));
+ const char *ext = config->ltoEmitAsm ? ".s" : ".o";
+ for (unsigned i = 0; i != maxTasks; ++i) {
+StringRef bitcodeFilePath;
+StringRef objBuf;
+if (files[i]) {
+ objBuf = files[i]->getBuffer();
+ bitcodeFilePath = filenames[i];
+} else {
+ objBuf = buf[i].second;
+ bitcodeFilePath = buf[i].first;
+}
+if (objBuf.empty())
+ continue;
- for (std::unique_ptr : files)
-if (file)
- ret.push_back(createObjFile(*file));
+// If the input bitcode file is path/to/a.o and -o specifies a.out, then
the
+// corresponding lto object file name will look something like:
+// path/to/a.out.lto.a.o.
+
[clang] [clang-tools-extra] [llvm] [lld] [ELF] --save-temps --lto-emit-asm: derive ELF/asm file names from bitcode file names (PR #78835)
@@ -61,10 +61,11 @@ # RUN: ld.lld --no-fortran-common -o 11 main.o --start-lib 1.o strong_data_only.o --end-lib # RUN: llvm-readobj --syms 11 | FileCheck --check-prefix=NFC %s -# RUN: ld.lld -o - main.o 4.a --fortran-common --lto-emit-asm | FileCheck --check-prefix=ASM %s +# RUN: ld.lld -o out main.o 4.a --fortran-common --lto-emit-asm +# RUN: FileCheck --check-prefix=ASM %s < out.lto.s -# RUN: ld.lld -o - main.o --start-lib 1.bc 2.bc --end-lib --fortran-common --lto-emit-asm | \ -# RUN: FileCheck --check-prefix=ASM %s +# RUN: ld.lld -o out main.o --start-lib 1.bc 2.bc --end-lib --fortran-common --lto-emit-asm +# RUN: FileCheck --check-prefix=ASM %s < out.lto.s MaskRay wrote: Thanks for the suggestion. Removed. https://github.com/llvm/llvm-project/pull/78835 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [libunwind] [compiler-rt] [libc] [flang] [lld] [libcxx] [lldb] [libclc] [clang-tools-extra] [libcxxabi] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)
MaskRay wrote: This PR needs a rebase.. There are quite a few merge commits. Hmm, I don't know how to squash the changes to rebase them to latest main branch. `git rebase --keep-base -i main` has quite a few merge conflicts. (My lld change (https://github.com/maskray/llvm-project/tree/rv-tlsdesc) is almost complete. I want to rebase it onto the latest revision of this LLVM PR.) https://github.com/llvm/llvm-project/pull/66915 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [libclc] [compiler-rt] [lldb] [libcxxabi] [libunwind] [llvm] [libcxx] [lld] [flang] [libc] [clang] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)
@@ -89,8 +89,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine
,
if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
!Subtarget.hasStdExtF()) {
errs() << "Hard-float 'f' ABI can't be used for a target that "
-"doesn't support the F instruction set extension (ignoring "
- "target-abi)\n";
+ "doesn't support the F instruction set extension (ignoring "
MaskRay wrote:
Ah, I only use `git diff -U0 --no-color --relative main... -- |
path/to/clang/tools/clang-format/clang-format-diff.py -p1 -i` :)
https://github.com/llvm/llvm-project/pull/66915
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[clang] [libunwind] [libc] [libcxx] [clang-tools-extra] [lld] [lldb] [libclc] [flang] [llvm] [libcxxabi] [compiler-rt] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/66915 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FatLTO] output of -ffat-lto-objects -S should be assembly. (PR #79041)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/79041 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang-tools-extra] [libc] [compiler-rt] [lldb] [libcxx] [libcxxabi] [lld] [clang] [libclc] [llvm] [Thumb,ELF] Fix access to dso_preemptable __stack_chk_guard with static relocation model (PR
MaskRay wrote: > (the commit message seems odd; intentional?) Hopefully clarified:) https://github.com/llvm/llvm-project/pull/78950 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang-tools-extra] [libc] [compiler-rt] [lldb] [libcxx] [libcxxabi] [lld] [clang] [libclc] [llvm] [Thumb,ELF] Fix access to dso_preemptable __stack_chk_guard with static relocation model (PR
@@ -135,14 +135,15 @@ void
Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock ,
void Thumb1InstrInfo::expandLoadStackGuard(
MachineBasicBlock::iterator MI) const {
MachineFunction = *MI->getParent()->getParent();
- const TargetMachine = MF.getTarget();
const ARMSubtarget = MF.getSubtarget();
+ const GlobalValue *GV =
+ cast((*MI->memoperands_begin())->getValue());
MaskRay wrote:
Thanks for the suggestion. Done
https://github.com/llvm/llvm-project/pull/78950
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[flang] [clang-tools-extra] [libc] [compiler-rt] [lldb] [libcxx] [libcxxabi] [lld] [clang] [libclc] [llvm] [Thumb,ELF] Fix access to dso_preemptable __stack_chk_guard with static relocation model (PR
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/78950
>From 2ce57488682873d2dc005144db57fbb555f29d8a Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Mon, 22 Jan 2024 00:29:09 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp | 5 ++--
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 2 +-
llvm/test/CodeGen/ARM/stack-guard-elf.ll | 30 +++-
3 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index e2f3fad2007904..e3104e8ee765f9 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -135,14 +135,15 @@ void
Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock ,
void Thumb1InstrInfo::expandLoadStackGuard(
MachineBasicBlock::iterator MI) const {
MachineFunction = *MI->getParent()->getParent();
- const TargetMachine = MF.getTarget();
const ARMSubtarget = MF.getSubtarget();
+ const GlobalValue *GV =
+ cast((*MI->memoperands_begin())->getValue());
assert(MF.getFunction().getParent()->getStackProtectorGuard() != "tls" &&
"TLS stack protector not supported for Thumb1 targets");
unsigned Instr;
- if (TM.isPositionIndependent())
+ if (!GV->isDSOLocal())
Instr = ARM::tLDRLIT_ga_pcrel;
else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps())
Instr = ARM::t2MOVi32imm;
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 2ea0eaa0aad8f5..9e4b51616b56ec 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -264,7 +264,7 @@ void Thumb2InstrInfo::expandLoadStackGuard(
const GlobalValue *GV =
cast((*MI->memoperands_begin())->getValue());
- if (MF.getSubtarget().isGVInGOT(GV))
+ if (!GV->isDSOLocal())
expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12);
else if (MF.getTarget().isPositionIndependent())
expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
diff --git a/llvm/test/CodeGen/ARM/stack-guard-elf.ll
b/llvm/test/CodeGen/ARM/stack-guard-elf.ll
index 250f2ad9ed1093..d0e5db7e5711b0 100644
--- a/llvm/test/CodeGen/ARM/stack-guard-elf.ll
+++ b/llvm/test/CodeGen/ARM/stack-guard-elf.ll
@@ -59,6 +59,8 @@ define i32 @test1() #0 {
; THUMB1-NEXT:.pad #16
; THUMB1-NEXT:sub sp, #16
; THUMB1-NEXT:ldr r0, .LCPI0_0
+; THUMB1-NEXT: .LPC0_0:
+; THUMB1-NEXT:add r0, pc
; THUMB1-NEXT:ldr r0, [r0]
; THUMB1-NEXT:ldr r0, [r0]
; THUMB1-NEXT:add r1, sp, #904
@@ -67,7 +69,9 @@ define i32 @test1() #0 {
; THUMB1-NEXT:bl foo
; THUMB1-NEXT:add r0, sp, #904
; THUMB1-NEXT:ldr r0, [r0, #124]
-; THUMB1-NEXT:ldr r1, .LCPI0_0
+; THUMB1-NEXT:ldr r1, .LCPI0_1
+; THUMB1-NEXT: .LPC0_1:
+; THUMB1-NEXT:add r1, pc
; THUMB1-NEXT:ldr r1, [r1]
; THUMB1-NEXT:ldr r1, [r1]
; THUMB1-NEXT:cmp r1, r0
@@ -83,7 +87,11 @@ define i32 @test1() #0 {
; THUMB1-NEXT:.p2align 2
; THUMB1-NEXT: @ %bb.3:
; THUMB1-NEXT: .LCPI0_0:
-; THUMB1-NEXT:.long __stack_chk_guard
+; THUMB1-NEXT: .Ltmp0:
+; THUMB1-NEXT:.long __stack_chk_guard(GOT_PREL)-((.LPC0_0+4)-.Ltmp0)
+; THUMB1-NEXT: .LCPI0_1:
+; THUMB1-NEXT: .Ltmp1:
+; THUMB1-NEXT:.long __stack_chk_guard(GOT_PREL)-((.LPC0_1+4)-.Ltmp1)
;
; THUMB1-PIC-LABEL: test1:
; THUMB1-PIC: @ %bb.0:
@@ -136,16 +144,18 @@ define i32 @test1() #0 {
; THUMB2-NEXT:push {r7, lr}
; THUMB2-NEXT:.pad #1032
; THUMB2-NEXT:sub.w sp, sp, #1032
-; THUMB2-NEXT:movw r0, :lower16:__stack_chk_guard
-; THUMB2-NEXT:movt r0, :upper16:__stack_chk_guard
+; THUMB2-NEXT:ldr r0, .LCPI0_0
+; THUMB2-NEXT: .LPC0_0:
+; THUMB2-NEXT:add r0, pc
; THUMB2-NEXT:ldr r0, [r0]
; THUMB2-NEXT:ldr r0, [r0]
; THUMB2-NEXT:str.w r0, [sp, #1028]
; THUMB2-NEXT:add r0, sp, #4
; THUMB2-NEXT:bl foo
-; THUMB2-NEXT:movw r1, :lower16:__stack_chk_guard
; THUMB2-NEXT:ldr.w r0, [sp, #1028]
-; THUMB2-NEXT:movt r1, :upper16:__stack_chk_guard
+; THUMB2-NEXT:ldr r1, .LCPI0_1
+; THUMB2-NEXT: .LPC0_1:
+; THUMB2-NEXT:add r1, pc
; THUMB2-NEXT:ldr r1, [r1]
; THUMB2-NEXT:ldr r1, [r1]
; THUMB2-NEXT:cmp r1, r0
@@ -155,6 +165,14 @@ define i32 @test1() #0 {
; THUMB2-NEXT:popeq {r7, pc}
; THUMB2-NEXT: .LBB0_1:
; THUMB2-NEXT:bl __stack_chk_fail
+; THUMB2-NEXT:.p2align 2
+; THUMB2-NEXT: @ %bb.2:
+; THUMB2-NEXT: .LCPI0_0:
+; THUMB2-NEXT: .Ltmp0:
+; THUMB2-NEXT:.long __stack_chk_guard(GOT_PREL)-((.LPC0_0+4)-.Ltmp0)
+; THUMB2-NEXT: .LCPI0_1:
+; THUMB2-NEXT: .Ltmp1:
+; THUMB2-NEXT:.long __stack_chk_guard(GOT_PREL)-((.LPC0_1+4)-.Ltmp1)
;
; THUMB2-PIC-LABEL: test1:
; THUMB2-PIC: @
[libc] [libcxxabi] [libcxx] [lld] [flang] [libclc] [clang] [compiler-rt] [clang-tools-extra] [lldb] [llvm] [Thumb,ELF] Fix access to dso_preemptable __stack_chk_guard with static relocation model (PR
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/78950 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][driver] Add -mtls-dialect option (PR #79031)
@@ -401,6 +401,8 @@ static bool initTargetOptions(DiagnosticsEngine , Options.UniqueBasicBlockSectionNames = CodeGenOpts.UniqueBasicBlockSectionNames; Options.TLSSize = CodeGenOpts.TLSSize; + // TODO: Add correct codegen options in LLVM + // Options.TLSDesc = CodeGenOpts.getDefaultTLSDialect(); MaskRay wrote: This should be supported in this patch, otherwise there is no point in ignoring a rarely-used GCC option. https://github.com/llvm/llvm-project/pull/79031 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
