[clang] [llvm] [AArch64] Introduce the Armv9.5-A architecture version (PR #72392)
https://github.com/pratlucas created
https://github.com/llvm/llvm-project/pull/72392
This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.
Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Patch by Oliver Stannard.
>From 98ac417eff3ba114cc56241635917190930df266 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Tue, 14 Nov 2023 11:26:25 +
Subject: [PATCH] [AArch64] Introduce the Armv9.5-A architecture version
This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.
Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Patch by Oliver Stannard.
---
clang/lib/Basic/Targets/AArch64.cpp | 11 +++
clang/lib/Basic/Targets/AArch64.h | 2 ++
clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 1 +
clang/test/Driver/aarch64-v95a.c | 15 +++
clang/test/Preprocessor/aarch64-target-features.c | 2 ++
.../llvm/TargetParser/AArch64TargetParser.h | 5 +++--
llvm/include/llvm/TargetParser/Triple.h | 1 +
llvm/lib/Target/AArch64/AArch64.td| 4
.../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 2 ++
llvm/lib/TargetParser/ARMTargetParserCommon.cpp | 1 +
llvm/unittests/TargetParser/TargetParserTest.cpp | 7 ++-
11 files changed, 48 insertions(+), 3 deletions(-)
create mode 100644 clang/test/Driver/aarch64-v95a.c
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c71af71eba60ce2..fde220163805554 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -333,6 +333,12 @@ void AArch64TargetInfo::getTargetDefinesARMV94A(const
LangOptions &Opts,
getTargetDefinesARMV89A(Opts, Builder);
}
+void AArch64TargetInfo::getTargetDefinesARMV95A(const LangOptions &Opts,
+MacroBuilder &Builder) const {
+ // Armv9.5-A does not have a v8.* equivalent, but is a superset of v9.4-A.
+ getTargetDefinesARMV94A(Opts, Builder);
+}
+
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
@@ -565,6 +571,8 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
getTargetDefinesARMV93A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_4A)
getTargetDefinesARMV94A(Opts, Builder);
+ else if (*ArchInfo == llvm::AArch64::ARMV9_5A)
+getTargetDefinesARMV95A(Opts, Builder);
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
@@ -899,6 +907,9 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
if (Feature == "+v9.4a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_4A.Version)
ArchInfo = &llvm::AArch64::ARMV9_4A;
+if (Feature == "+v9.5a" &&
+ArchInfo->Version < llvm::AArch64::ARMV9_5A.Version)
+ ArchInfo = &llvm::AArch64::ARMV9_5A;
if (Feature == "+v8r")
ArchInfo = &llvm::AArch64::ARMV8R;
if (Feature == "+fullfp16") {
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 4304693e473dee3..9ccc637f5494784 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -143,6 +143,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
MacroBuilder &Builder) const;
void getTargetDefinesARMV94A(const LangOptions &Opts,
MacroBuilder &Builder) const;
+ void getTargetDefinesARMV95A(const LangOptions &Opts,
+ MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 276984f96d57a51..1f77c987051749c 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -411,6 +411,7 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
else if (*I == "+v9.2a") V9Version = 2;
else if (*I == "+v9.3a") V9Version = 3;
else if (*I == "+v9.4a") V9Version = 4;
+else if (*I == "+v9.5a") V9Version = 5;
else if (*I == "+sm4") HasSM4 = true;
else if (*I == "+sha3") HasSHA3 = true;
else if (*I == "+sha2") HasSHA2 = true;
diff --git a
[llvm] [clang] [AArch64] Introduce the Armv9.5-A architecture version (PR #72392)
https://github.com/pratlucas updated
https://github.com/llvm/llvm-project/pull/72392
>From 98ac417eff3ba114cc56241635917190930df266 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Tue, 14 Nov 2023 11:26:25 +
Subject: [PATCH 1/2] [AArch64] Introduce the Armv9.5-A architecture version
This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.
Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Patch by Oliver Stannard.
---
clang/lib/Basic/Targets/AArch64.cpp | 11 +++
clang/lib/Basic/Targets/AArch64.h | 2 ++
clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 1 +
clang/test/Driver/aarch64-v95a.c | 15 +++
clang/test/Preprocessor/aarch64-target-features.c | 2 ++
.../llvm/TargetParser/AArch64TargetParser.h | 5 +++--
llvm/include/llvm/TargetParser/Triple.h | 1 +
llvm/lib/Target/AArch64/AArch64.td| 4
.../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 2 ++
llvm/lib/TargetParser/ARMTargetParserCommon.cpp | 1 +
llvm/unittests/TargetParser/TargetParserTest.cpp | 7 ++-
11 files changed, 48 insertions(+), 3 deletions(-)
create mode 100644 clang/test/Driver/aarch64-v95a.c
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c71af71eba60ce2..fde220163805554 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -333,6 +333,12 @@ void AArch64TargetInfo::getTargetDefinesARMV94A(const
LangOptions &Opts,
getTargetDefinesARMV89A(Opts, Builder);
}
+void AArch64TargetInfo::getTargetDefinesARMV95A(const LangOptions &Opts,
+MacroBuilder &Builder) const {
+ // Armv9.5-A does not have a v8.* equivalent, but is a superset of v9.4-A.
+ getTargetDefinesARMV94A(Opts, Builder);
+}
+
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
@@ -565,6 +571,8 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
getTargetDefinesARMV93A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_4A)
getTargetDefinesARMV94A(Opts, Builder);
+ else if (*ArchInfo == llvm::AArch64::ARMV9_5A)
+getTargetDefinesARMV95A(Opts, Builder);
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
@@ -899,6 +907,9 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
if (Feature == "+v9.4a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_4A.Version)
ArchInfo = &llvm::AArch64::ARMV9_4A;
+if (Feature == "+v9.5a" &&
+ArchInfo->Version < llvm::AArch64::ARMV9_5A.Version)
+ ArchInfo = &llvm::AArch64::ARMV9_5A;
if (Feature == "+v8r")
ArchInfo = &llvm::AArch64::ARMV8R;
if (Feature == "+fullfp16") {
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 4304693e473dee3..9ccc637f5494784 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -143,6 +143,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
MacroBuilder &Builder) const;
void getTargetDefinesARMV94A(const LangOptions &Opts,
MacroBuilder &Builder) const;
+ void getTargetDefinesARMV95A(const LangOptions &Opts,
+ MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 276984f96d57a51..1f77c987051749c 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -411,6 +411,7 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
else if (*I == "+v9.2a") V9Version = 2;
else if (*I == "+v9.3a") V9Version = 3;
else if (*I == "+v9.4a") V9Version = 4;
+else if (*I == "+v9.5a") V9Version = 5;
else if (*I == "+sm4") HasSM4 = true;
else if (*I == "+sha3") HasSHA3 = true;
else if (*I == "+sha2") HasSHA2 = true;
diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c
new file mode 100644
index 000..6044a4f155db02c
--- /dev/null
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -0,0 +1,15 @@
+// RUN: %clang -target aarch64 -march=armv9.5a -### -c %s 2>&1 | FileCheck
-check-prefix=GENERICV95A %s
+// RUN: %clang -target aarch64 -march=armv9.5-a -### -c %s 2>&1 | FileCheck
-check-prefix=GE
[llvm] [clang] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)
@@ -1372,6 +1408,11 @@ def ProcessorFeatures {
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
FeatureMTE, FeatureSVE2BitPerm,
FeatureFullFP16,
FeatureFP16FML];
+ list X4 = [HasV9_2aOps, FeatureSVE, FeatureNEON,
pratlucas wrote:
`FeatureSVE`, `FeatureFullFP16`, `FeatureNeon`, `FeatureBF16` and
`FeatureMatMulInt8` are already enabled by default on Armv9.2-A. Can they be
removed from this list to avoid the redundancy?
https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)
@@ -1351,6 +1382,11 @@ def ProcessorFeatures {
FeatureFP16FML, FeatureSVE, FeatureTRBE,
FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
FeaturePerfMon, FeatureMatMulInt8,
FeatureSPE];
+ list A720 = [HasV9_2aOps, FeatureNEON, FeatureMTE,
pratlucas wrote:
Also, it looks like the TRM states that FEAT_TME (`FeatureTME`) is not enabled
on Cortex-A720.
https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)
@@ -1372,6 +1408,11 @@ def ProcessorFeatures {
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
FeatureMTE, FeatureSVE2BitPerm,
FeatureFullFP16,
FeatureFP16FML];
+ list X4 = [HasV9_2aOps, FeatureSVE, FeatureNEON,
pratlucas wrote:
Also FEAT_SPEv1p2 (`FeatureSPE_EEF`) is mentioned as supported in the TRM but
is missing from this list.
https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)
@@ -1351,6 +1382,11 @@ def ProcessorFeatures {
FeatureFP16FML, FeatureSVE, FeatureTRBE,
FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
FeaturePerfMon, FeatureMatMulInt8,
FeatureSPE];
+ list A720 = [HasV9_2aOps, FeatureNEON, FeatureMTE,
pratlucas wrote:
`FeatureNeon`, `FeatureSVE`, `FeatureBF16` and `FeatureMatMulInt8` are already
enabled by default on Armv9.2-A. Can they be removed from this list to avoid
the redundancy?
https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)
@@ -1325,6 +1352,10 @@ def ProcessorFeatures {
FeatureMatMulInt8, FeatureBF16, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML];
+ list A520 = [HasV9_2aOps, FeatureNEON, FeaturePerfMon,
pratlucas wrote:
`FeatureNeon`, `FeatureMatMulInt8`, `FeatureBF16` and `FeatureFineGrainedTraps`
are already enabled by default on Armv9.2-A. Can they be removed from this list
to avoid the redundancy?
https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Introduce the Armv9.5-A architecture version (PR #72392)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/72392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)
https://github.com/pratlucas approved this pull request. Thanks for the updates! LGTM. https://github.com/llvm/llvm-project/pull/72395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] Replace usage of StringRef::find_last_of with a string literal of size one by the equivalent char literal (PR #73776)
https://github.com/pratlucas created
https://github.com/llvm/llvm-project/pull/73776
None
>From bff5119a857124f113d9dc499701ad87941fe1c3 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Wed, 15 Nov 2023 10:33:42 +
Subject: [PATCH] [AArch64] Assembly support for the Checked Pointer Arithmetic
Extension
This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture
version.
The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register
Mode details about the extension can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Co-authored-by: Rodolfo Wottrich
---
clang/test/Driver/aarch64-v95a.c | 5 ++
.../llvm/TargetParser/AArch64TargetParser.h | 5 +-
llvm/lib/Target/AArch64/AArch64.td| 5 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 52 ++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 19 +
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 21 ++
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV1.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 18 +
llvm/lib/Target/AArch64/SVEInstrFormats.td| 31 +
llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s | 69 +++
llvm/test/MC/AArch64/armv9.5a-cpa.s | 50 ++
llvm/test/MC/AArch64/basic-a64-diagnostics.s | 8 +++
llvm/test/MC/AArch64/basic-a64-instructions.s | 4 ++
.../MC/Disassembler/AArch64/armv9.5a-cpa.txt | 42 +++
.../AArch64/basic-a64-instructions.txt| 2 +
.../TargetParser/TargetParserTest.cpp | 4 +-
19 files changed, 336 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-cpa.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt
diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c
index 6044a4f155db02c..366cade86a9fb71 100644
--- a/clang/test/Driver/aarch64-v95a.c
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -13,3 +13,8 @@
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s
2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu"
"generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
+// = Features supported on aarch64 =
+
+// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck
-check-prefix=V95A-CPA %s
+// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-CPA %s
+// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
"-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 38ccca56336abb9..90fd666da8d13b5 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -173,6 +173,7 @@ enum ArchExtKind : unsigned {
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
AEK_SMEFA64 = 71, // FEAT_SME_FA64
+ AEK_CPA = 72, // FEAT_CPA
AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset;
@@ -295,6 +296,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16",
FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32",
FEAT_INIT, "+sme2,+fp8", 0},
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT,
"", 0},
+{"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
// Special cases
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "",
ExtensionInfo::MaxFMVPriority},
};
@@ -378,7 +380,8 @@ inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3},
AProfile, "armv9.3-a
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile,
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC,
AArch64::AEK_RASv2}))};
-inline constexpr ArchInfo ARMV9_5A = { Ver
[clang] [llvm] Replace usage of StringRef::find_last_of with a string literal of size one by the equivalent char literal (PR #73776)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/73776 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (PR #73777)
https://github.com/pratlucas created
https://github.com/llvm/llvm-project/pull/73777
This introduces assembly support for the Checked Pointer Arithmetic Extension
(FEAT_CPA), annouced as part of the Armv9.5-A architecture version.
The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register
Mode details about the extension can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Changes by me and @rgwott .
>From bff5119a857124f113d9dc499701ad87941fe1c3 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Wed, 15 Nov 2023 10:33:42 +
Subject: [PATCH] [AArch64] Assembly support for the Checked Pointer Arithmetic
Extension
This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture
version.
The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register
Mode details about the extension can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Co-authored-by: Rodolfo Wottrich
---
clang/test/Driver/aarch64-v95a.c | 5 ++
.../llvm/TargetParser/AArch64TargetParser.h | 5 +-
llvm/lib/Target/AArch64/AArch64.td| 5 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 52 ++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 19 +
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 21 ++
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV1.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 18 +
llvm/lib/Target/AArch64/SVEInstrFormats.td| 31 +
llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s | 69 +++
llvm/test/MC/AArch64/armv9.5a-cpa.s | 50 ++
llvm/test/MC/AArch64/basic-a64-diagnostics.s | 8 +++
llvm/test/MC/AArch64/basic-a64-instructions.s | 4 ++
.../MC/Disassembler/AArch64/armv9.5a-cpa.txt | 42 +++
.../AArch64/basic-a64-instructions.txt| 2 +
.../TargetParser/TargetParserTest.cpp | 4 +-
19 files changed, 336 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-cpa.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt
diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c
index 6044a4f155db02c..366cade86a9fb71 100644
--- a/clang/test/Driver/aarch64-v95a.c
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -13,3 +13,8 @@
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s
2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu"
"generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
+// = Features supported on aarch64 =
+
+// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck
-check-prefix=V95A-CPA %s
+// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-CPA %s
+// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
"-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 38ccca56336abb9..90fd666da8d13b5 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -173,6 +173,7 @@ enum ArchExtKind : unsigned {
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
AEK_SMEFA64 = 71, // FEAT_SME_FA64
+ AEK_CPA = 72, // FEAT_CPA
AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset;
@@ -295,6 +296,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16",
FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32",
FEAT_INIT, "+sme
[llvm] [clang] [Abandoned][AArch64] Assembly support for the Checked Pointer Arithmetic Extension (PR #73776)
https://github.com/pratlucas edited https://github.com/llvm/llvm-project/pull/73776 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (PR #73777)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/73777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (PR #73777)
@@ -4163,3 +4163,24 @@ let Predicates = [HasSVE2orSME2, HasLUT] in {
// LUTI4 (two contiguous registers)
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
} // End HasSVE2orSME2, HasLUT
+
+//===--===//
+// Checked Pointer Arithmetic (FEAT_CPA)
+//===--===//
+let Predicates = [HasSVEorSME, HasCPA] in {
pratlucas wrote:
Good catch! Thanks @CarolineConcatto
I'll upload a fix for this soon
https://github.com/llvm/llvm-project/pull/73777
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[libcxx] [flang] [llvm] [mlir] [clang] [AsmWriter] Ensure getMnemonic doesn't return invalid pointers (PR #75783)
https://github.com/pratlucas updated
https://github.com/llvm/llvm-project/pull/75783
>From 62f4b5daeca0be5b463c5c42271a4b997f084523 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Mon, 18 Dec 2023 10:49:25 +
Subject: [PATCH] [AsmWriter] Ensure getMnemonic doesn't return invalid
pointers
For instructions that don't map to a mnemonic string, the implementation
of MCInstPrinter::getMnemonic would return an invalid pointer due to the
result of the calculation of the instruction's position in the `AsmStrs`
table. This patch fixes the issue by ensuring those cases return a
`nullptr` value instead.
Fixes #74177.
---
llvm/lib/MC/MCAsmStreamer.cpp| 5 -
llvm/utils/TableGen/AsmWriterEmitter.cpp | 4
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 9e1d108ac14dc5..532ac89bf9ff76 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -154,7 +154,10 @@ class MCAsmStreamer final : public MCStreamer {
void emitGNUAttribute(unsigned Tag, unsigned Value) override;
StringRef getMnemonic(MCInst &MI) override {
-return InstPrinter->getMnemonic(&MI).first;
+std::pair M = InstPrinter->getMnemonic(&MI);
+assert((M.second != 0 || M.first == nullptr) &&
+ "Invalid char pointer for instruction with no mnemonic");
+return M.first;
}
void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override;
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp
b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 0220927295cf78..e0cd5fad3254de 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -438,6 +438,10 @@ void AsmWriterEmitter::EmitGetMnemonic(
O << " // Emit the opcode for the instruction.\n";
O << BitsString;
+ // Make sure we don't return an invalid pointer if bits is 0
+ O << " if (Bits == 0)\n"
+ "return {nullptr, Bits};\n";
+
// Return mnemonic string and bits.
O << " return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1
<< ")-1, Bits};\n\n";
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[libcxx] [flang] [llvm] [mlir] [clang] [AsmWriter] Ensure getMnemonic doesn't return invalid pointers (PR #75783)
https://github.com/pratlucas updated
https://github.com/llvm/llvm-project/pull/75783
>From 62f4b5daeca0be5b463c5c42271a4b997f084523 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Mon, 18 Dec 2023 10:49:25 +
Subject: [PATCH 1/2] [AsmWriter] Ensure getMnemonic doesn't return invalid
pointers
For instructions that don't map to a mnemonic string, the implementation
of MCInstPrinter::getMnemonic would return an invalid pointer due to the
result of the calculation of the instruction's position in the `AsmStrs`
table. This patch fixes the issue by ensuring those cases return a
`nullptr` value instead.
Fixes #74177.
---
llvm/lib/MC/MCAsmStreamer.cpp| 5 -
llvm/utils/TableGen/AsmWriterEmitter.cpp | 4
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 9e1d108ac14dc5..532ac89bf9ff76 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -154,7 +154,10 @@ class MCAsmStreamer final : public MCStreamer {
void emitGNUAttribute(unsigned Tag, unsigned Value) override;
StringRef getMnemonic(MCInst &MI) override {
-return InstPrinter->getMnemonic(&MI).first;
+std::pair M = InstPrinter->getMnemonic(&MI);
+assert((M.second != 0 || M.first == nullptr) &&
+ "Invalid char pointer for instruction with no mnemonic");
+return M.first;
}
void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override;
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp
b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 0220927295cf78..e0cd5fad3254de 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -438,6 +438,10 @@ void AsmWriterEmitter::EmitGetMnemonic(
O << " // Emit the opcode for the instruction.\n";
O << BitsString;
+ // Make sure we don't return an invalid pointer if bits is 0
+ O << " if (Bits == 0)\n"
+ "return {nullptr, Bits};\n";
+
// Return mnemonic string and bits.
O << " return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1
<< ")-1, Bits};\n\n";
>From 1326609f665f6f202301bc6f7945d49e3cd1b72c Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Mon, 18 Dec 2023 11:59:26 +
Subject: [PATCH 2/2] fixup! [AsmWriter] Ensure getMnemonic doesn't return
invalid pointers
---
llvm/lib/MC/MCAsmStreamer.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 532ac89bf9ff76..49668de27d67e7 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -154,10 +154,10 @@ class MCAsmStreamer final : public MCStreamer {
void emitGNUAttribute(unsigned Tag, unsigned Value) override;
StringRef getMnemonic(MCInst &MI) override {
-std::pair M = InstPrinter->getMnemonic(&MI);
-assert((M.second != 0 || M.first == nullptr) &&
+auto [Ptr, Bits] = InstPrinter->getMnemonic(&MI);
+assert((Bits != 0 || Ptr == nullptr) &&
"Invalid char pointer for instruction with no mnemonic");
-return M.first;
+return Ptr;
}
void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override;
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[flang] [clang] [mlir] [clang-tools-extra] [libcxx] [libc] [compiler-rt] [llvm] [AsmWriter] Ensure getMnemonic doesn't return invalid pointers (PR #75783)
https://github.com/pratlucas updated
https://github.com/llvm/llvm-project/pull/75783
>From 62f4b5daeca0be5b463c5c42271a4b997f084523 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Mon, 18 Dec 2023 10:49:25 +
Subject: [PATCH 1/2] [AsmWriter] Ensure getMnemonic doesn't return invalid
pointers
For instructions that don't map to a mnemonic string, the implementation
of MCInstPrinter::getMnemonic would return an invalid pointer due to the
result of the calculation of the instruction's position in the `AsmStrs`
table. This patch fixes the issue by ensuring those cases return a
`nullptr` value instead.
Fixes #74177.
---
llvm/lib/MC/MCAsmStreamer.cpp| 5 -
llvm/utils/TableGen/AsmWriterEmitter.cpp | 4
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 9e1d108ac14dc5..532ac89bf9ff76 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -154,7 +154,10 @@ class MCAsmStreamer final : public MCStreamer {
void emitGNUAttribute(unsigned Tag, unsigned Value) override;
StringRef getMnemonic(MCInst &MI) override {
-return InstPrinter->getMnemonic(&MI).first;
+std::pair M = InstPrinter->getMnemonic(&MI);
+assert((M.second != 0 || M.first == nullptr) &&
+ "Invalid char pointer for instruction with no mnemonic");
+return M.first;
}
void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override;
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp
b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 0220927295cf78..e0cd5fad3254de 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -438,6 +438,10 @@ void AsmWriterEmitter::EmitGetMnemonic(
O << " // Emit the opcode for the instruction.\n";
O << BitsString;
+ // Make sure we don't return an invalid pointer if bits is 0
+ O << " if (Bits == 0)\n"
+ "return {nullptr, Bits};\n";
+
// Return mnemonic string and bits.
O << " return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1
<< ")-1, Bits};\n\n";
>From 1326609f665f6f202301bc6f7945d49e3cd1b72c Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Mon, 18 Dec 2023 11:59:26 +
Subject: [PATCH 2/2] fixup! [AsmWriter] Ensure getMnemonic doesn't return
invalid pointers
---
llvm/lib/MC/MCAsmStreamer.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 532ac89bf9ff76..49668de27d67e7 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -154,10 +154,10 @@ class MCAsmStreamer final : public MCStreamer {
void emitGNUAttribute(unsigned Tag, unsigned Value) override;
StringRef getMnemonic(MCInst &MI) override {
-std::pair M = InstPrinter->getMnemonic(&MI);
-assert((M.second != 0 || M.first == nullptr) &&
+auto [Ptr, Bits] = InstPrinter->getMnemonic(&MI);
+assert((Bits != 0 || Ptr == nullptr) &&
"Invalid char pointer for instruction with no mnemonic");
-return M.first;
+return Ptr;
}
void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override;
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[llvm] [libc] [clang] [clang-tools-extra] [libcxx] [compiler-rt] [mlir] [flang] [AsmWriter] Ensure getMnemonic doesn't return invalid pointers (PR #75783)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/75783 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/pratlucas approved this pull request. https://github.com/llvm/llvm-project/pull/75947 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Assembly support for the Armv9.5-A Memory System Extensions (PR #76237)
https://github.com/pratlucas created
https://github.com/llvm/llvm-project/pull/76237
This implements assembly support for the Memory Systems Extensions
introduced as part of the Armv9.5-A architecture version.
The changes include:
* New subtarget feature for FEAT_TLBIW.
* New system registers for FEAT_HDBSS:
* HDBSSBR_EL2 and HDBSSPROD_EL2.
* New system registers for FEAT_HACDBS:
* HACDBSBR_EL2 and HACDBSCONS_EL2.
* New TLBI instructions for FEAT_TLBIW:
* VMALLWS2E1(nXS), VMALLWS2E1IS(nXS) and VMALLWS2E1OS(nXS).
* New system register for FEAT_FGWTE3:
* FGWTE3_EL3.
>From 4f2834cd78430ac69418f307cb54e9e583c7c7fd Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Fri, 22 Dec 2023 12:05:26 +
Subject: [PATCH] [AArch64] Assembly support for the Armv9.5-A Memory System
Extensions
This implements assembly support for the Memory Systems Extensions
introduced as part of the Armv9.5-A architecture version.
The changes include:
* New subtarget feature for FEAT_TLBIW.
* New system registers for FEAT_HDBSS:
* HDBSSBR_EL2 and HDBSSPROD_EL2.
* New system registers for FEAT_HACDBS:
* HACDBSBR_EL2 and HACDBSCONS_EL2.
* New TLBI instructions for FEAT_TLBIW:
* VMALLWS2E1(nXS), VMALLWS2E1IS(nXS) and VMALLWS2E1OS(nXS).
* New system register for FEAT_FGWTE3:
* FGWTE3_EL3.
---
clang/test/Driver/aarch64-v95a.c | 4 +++
.../llvm/TargetParser/AArch64TargetParser.h | 2 ++
llvm/lib/Target/AArch64/AArch64.td| 3 +++
.../Target/AArch64/AArch64SystemOperands.td | 22 +++
.../AArch64/AsmParser/AArch64AsmParser.cpp| 1 +
llvm/test/MC/AArch64/armv9.5a-fgwte3.s| 6 +
llvm/test/MC/AArch64/armv9.5a-hacdbs.s| 12 +
llvm/test/MC/AArch64/armv9.5a-hdbss.s | 12 +
llvm/test/MC/AArch64/armv9.5a-tlbiw.s | 27 +++
.../Disassembler/AArch64/armv9.5a-fgwte3.txt | 7 +
.../Disassembler/AArch64/armv9.5a-hacdbs.txt | 14 ++
.../Disassembler/AArch64/armv9.5a-hdbss.txt | 14 ++
.../Disassembler/AArch64/armv9.5a-tlbiw.txt | 27 +++
.../TargetParser/TargetParserTest.cpp | 2 ++
14 files changed, 153 insertions(+)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-fgwte3.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-hacdbs.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-hdbss.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-tlbiw.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-fgwte3.txt
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-hacdbs.txt
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-hdbss.txt
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-tlbiw.txt
diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c
index 6fac62e8b389a6..13069c04c8d1c8 100644
--- a/clang/test/Driver/aarch64-v95a.c
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -25,3 +25,7 @@
// RUN: %clang -target aarch64 -march=armv9.5a+pauth-lr -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-PAUTHLR %s
// RUN: %clang -target aarch64 -march=armv9.5-a+pauth-lr -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-PAUTHLR %s
// V95A-PAUTHLR: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
"-target-feature" "+pauth-lr"
+
+// RUN: %clang -target aarch64 -march=armv9.5a+tlbiw -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-TLBIW %s
+// RUN: %clang -target aarch64 -march=armv9.5-a+tlbiw -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-TLBIW %s
+// V95A-TLBIW: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
"-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+tlbiw"
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 6c7410a8b8f792..53dc2be825f28e 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -175,6 +175,7 @@ enum ArchExtKind : unsigned {
AEK_SMEFA64 = 71, // FEAT_SME_FA64
AEK_CPA = 72, // FEAT_CPA
AEK_PAUTHLR = 73, // FEAT_PAuth_LR
+ AEK_TLBIW = 74, // FEAT_TLBIW
AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset;
@@ -299,6 +300,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT,
"", 0},
{"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
{"pauth-lr", AArch64::AEK_PAUTHLR, "+pauth-lr", "-pauth-lr", FEAT_INIT,
"", 0},
+{"tlbiw", AArch64::AEK_TLBIW, "+tlbiw", "-tlbiw", FEAT_INIT, "", 0},
// Special cases
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "",
ExtensionInfo::MaxFMVPriority},
};
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 97e92a57a7ff4b..68f452039c9b68 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@
[clang] [llvm] [AArch64] Assembly support for the Armv9.5-A Memory System Extensions (PR #76237)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/76237 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][AArch64] Add ACLE macros for FEAT_PAuth_LR (PR #80163)
https://github.com/pratlucas created
https://github.com/llvm/llvm-project/pull/80163
This updates clang's target defines to include the ACLE changes covering
the FEAT_PAuth_LR architecture extension.
The changes include:
* The new `__ARM_FEATURE_PAUTH_LR` feature macro, which is set to 1 when
FEAT_PAuth_LR is available in the target.
* A new bit field for the existing `__ARM_FEATURE_PAC_DEFAULT` macro,
indicating the use of PC as a diversifier for Pointer Authentication
(from -mbranch-protection=pac-ret+pc).
The approved changes to the ACLE spec can be found here:
https://github.com/ARM-software/acle/pull/292
>From 885e82fe163246f154058b01f58acadb4a477df8 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Wed, 31 Jan 2024 15:00:42 +
Subject: [PATCH] [Clang][AArch64] Add ACLE macros for FEAT_PAuth_LR
This updates clang's target defines to include the ACLE changes covering
the FEAT_PAuth_LR architecture extension.
The changes include:
* The new `__ARM_FEATURE_PAUTH_LR` feature macro, which is set to 1 when
FEAT_PAuth_LR is available in the target.
* A new bit field for the existing `__ARM_FEATURE_PAC_DEFAULT` macro,
indicating the use of PC as a diversifier for Pointer Authentication
(from -mbranch-protection=pac-ret+pc).
The approved changes to the ACLE spec can be found here:
https://github.com/ARM-software/acle/pull/292
---
clang/lib/Basic/Targets/AArch64.cpp | 11 +++
clang/lib/Basic/Targets/AArch64.h | 1 +
.../Preprocessor/aarch64-target-features.c| 31 +++
3 files changed, 43 insertions(+)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c89e16677e974..46f14b47261ae 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -466,6 +466,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasPAuth)
Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
+ if (HasPAuthLR)
+Builder.defineMacro("__ARM_FEATURE_PAUTH_LR", "1");
+
if (HasUnaligned)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
@@ -517,6 +520,7 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
// 0: Protection using the A key
// 1: Protection using the B key
// 2: Protection including leaf functions
+// 3: Protection using PC as a diversifier
unsigned Value = 0;
if (Opts.isSignReturnAddressWithAKey())
@@ -527,6 +531,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (Opts.isSignReturnAddressScopeAll())
Value |= (1 << 2);
+if (Opts.BranchProtectionPAuthLR)
+ Value |= (1 << 3);
+
Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
}
@@ -966,6 +973,10 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasGCS = true;
if (Feature == "+rcpc3")
HasRCPC3 = true;
+if (Feature == "+pauth-lr") {
+ HasPAuthLR = true;
+ HasPAuth = true;
+}
}
// Check features that are manually disabled by command line options.
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 9f5e88a6ddd99..7761812295ffa 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -84,6 +84,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
bool HasGCS = false;
bool HasRCPC3 = false;
bool HasSMEFA64 = false;
+ bool HasPAuthLR = false;
const llvm::AArch64::ArchInfo *ArchInfo = &llvm::AArch64::ARMV8A;
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index 15879da04fcf0..062b802909f16 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -602,6 +602,37 @@
// CHECK-GCS-DEFAULT: __ARM_FEATURE_GCS_DEFAULT 1
// CHECK-NOGCS-DEFAULT-NOT: __ARM_FEATURE_GCS_DEFAULT 1
+// == Check Armv9.5-A Pointer Authentication
Enhancements(PAuth_LR).
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o -
| FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a -x c -E -dM %s -o
- | FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth
-mbranch-protection=none -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH-LR-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr
-mbranch-protection=none -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH-LR %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH-LR %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a
-mbranch-protection=standard -x c -E -dM %s -o - | FileCheck
-check-prefix=CHECK-PAUTH-LR-OFF %s
+// RUN: %clang -target arm64-no
[clang] [Clang][AArch64] Add ACLE macros for FEAT_PAuth_LR (PR #80163)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/80163 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM] Introduce the v9.5-A architecture version to Arm targets (PR #78994)
https://github.com/pratlucas created
https://github.com/llvm/llvm-project/pull/78994
This introduces the Armv9.5-A architecture version to the Arm backend,
following on from the existing implementation for AArch64 targets.
Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
>From b3f8e9d1ce4f9a88dc6b57f2862e928a465aecf8 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Mon, 22 Jan 2024 15:13:45 +
Subject: [PATCH] [ARM] Introduce the v9.5-A architecture version to Arm
targets
This introduces the Armv9.5-A architecture version to the Arm backend,
following on from the existing implementation for AArch64 targets.
Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
---
clang/lib/Basic/Targets/ARM.cpp | 4
clang/test/CodeGen/arm-acle-coproc.c| 2 ++
clang/test/Driver/arm-cortex-cpus-1.c | 17 +
clang/test/Preprocessor/arm-target-features.c | 5 +
.../llvm/TargetParser/ARMTargetParser.def | 5 +
llvm/lib/Target/ARM/ARM.td | 16
llvm/lib/Target/ARM/ARMSubtarget.h | 1 +
.../Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 1 +
llvm/lib/TargetParser/ARMTargetParser.cpp | 2 ++
llvm/lib/TargetParser/Triple.cpp| 2 ++
.../unittests/TargetParser/TargetParserTest.cpp | 6 +-
11 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index a72bd42bad41579..55b71557452fa04 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -227,6 +227,8 @@ StringRef ARMTargetInfo::getCPUAttr() const {
return "9_3A";
case llvm::ARM::ArchKind::ARMV9_4A:
return "9_4A";
+ case llvm::ARM::ArchKind::ARMV9_5A:
+return "9_5A";
case llvm::ARM::ArchKind::ARMV8MBaseline:
return "8M_BASE";
case llvm::ARM::ArchKind::ARMV8MMainline:
@@ -889,6 +891,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::ARM::ArchKind::ARMV9_2A:
case llvm::ARM::ArchKind::ARMV9_3A:
case llvm::ARM::ArchKind::ARMV9_4A:
+ case llvm::ARM::ArchKind::ARMV9_5A:
// Filter __arm_cdp, __arm_ldcl, __arm_stcl in arm_acle.h
FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B3;
break;
@@ -1057,6 +1060,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::ARM::ArchKind::ARMV9_2A:
case llvm::ARM::ArchKind::ARMV9_3A:
case llvm::ARM::ArchKind::ARMV9_4A:
+ case llvm::ARM::ArchKind::ARMV9_5A:
getTargetDefinesARMV83A(Opts, Builder);
break;
}
diff --git a/clang/test/CodeGen/arm-acle-coproc.c
b/clang/test/CodeGen/arm-acle-coproc.c
index cf87130932edfe9..0354d1297ece182 100644
--- a/clang/test/CodeGen/arm-acle-coproc.c
+++ b/clang/test/CodeGen/arm-acle-coproc.c
@@ -24,6 +24,7 @@
// RUN: %clang_cc1 -triple armv9.2a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple armv9.3a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple armv9.4a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv9.5a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv4 %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V4-THUMB %s
// RUN: %clang_cc1 -triple thumbv4t %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V4-THUMB %s
// RUN: %clang_cc1 -triple thumbv5 %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V5-THUMB %s
@@ -52,6 +53,7 @@
// RUN: %clang_cc1 -triple thumbv9.2a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv9.3a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv9.4a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv9.5a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv8m.base %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8-BASE %s
// RUN: %clang_cc1 -triple thumbv8m.main %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8-MAIN %s
// RUN: %clang_cc1 -triple thumbv8.1m.main %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8-MAIN %s
diff --git a/clang/test/Driver/arm-cortex-cpus-1.c
b/clang/test/Driver/arm-cortex-cpus-1.c
index 2f300efee75ed4c..25abbe1e3a8ad7a 100644
--- a/clang/test/Driver/arm-cortex-cpus-1.c
+++ b/clang/test/Driver/arm-cortex-cpus-1.c
@@ -478,3 +478,20 @@
// RUN: %clang -target arm -march=armebv9.4a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V94A %s
[llvm] [clang] [ARM] Introduce the v9.5-A architecture version to Arm targets (PR #78994)
pratlucas wrote: No, V9.5-A is v9-only. The v9.4-A version was the last one to have a matching v8.x. https://github.com/llvm/llvm-project/pull/78994 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [ARM] Introduce the v9.5-A architecture version to Arm targets (PR #78994)
https://github.com/pratlucas updated
https://github.com/llvm/llvm-project/pull/78994
>From b3f8e9d1ce4f9a88dc6b57f2862e928a465aecf8 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Mon, 22 Jan 2024 15:13:45 +
Subject: [PATCH 1/2] [ARM] Introduce the v9.5-A architecture version to Arm
targets
This introduces the Armv9.5-A architecture version to the Arm backend,
following on from the existing implementation for AArch64 targets.
Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
---
clang/lib/Basic/Targets/ARM.cpp | 4
clang/test/CodeGen/arm-acle-coproc.c| 2 ++
clang/test/Driver/arm-cortex-cpus-1.c | 17 +
clang/test/Preprocessor/arm-target-features.c | 5 +
.../llvm/TargetParser/ARMTargetParser.def | 5 +
llvm/lib/Target/ARM/ARM.td | 16
llvm/lib/Target/ARM/ARMSubtarget.h | 1 +
.../Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 1 +
llvm/lib/TargetParser/ARMTargetParser.cpp | 2 ++
llvm/lib/TargetParser/Triple.cpp| 2 ++
.../unittests/TargetParser/TargetParserTest.cpp | 6 +-
11 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index a72bd42bad41579..55b71557452fa04 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -227,6 +227,8 @@ StringRef ARMTargetInfo::getCPUAttr() const {
return "9_3A";
case llvm::ARM::ArchKind::ARMV9_4A:
return "9_4A";
+ case llvm::ARM::ArchKind::ARMV9_5A:
+return "9_5A";
case llvm::ARM::ArchKind::ARMV8MBaseline:
return "8M_BASE";
case llvm::ARM::ArchKind::ARMV8MMainline:
@@ -889,6 +891,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::ARM::ArchKind::ARMV9_2A:
case llvm::ARM::ArchKind::ARMV9_3A:
case llvm::ARM::ArchKind::ARMV9_4A:
+ case llvm::ARM::ArchKind::ARMV9_5A:
// Filter __arm_cdp, __arm_ldcl, __arm_stcl in arm_acle.h
FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B3;
break;
@@ -1057,6 +1060,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::ARM::ArchKind::ARMV9_2A:
case llvm::ARM::ArchKind::ARMV9_3A:
case llvm::ARM::ArchKind::ARMV9_4A:
+ case llvm::ARM::ArchKind::ARMV9_5A:
getTargetDefinesARMV83A(Opts, Builder);
break;
}
diff --git a/clang/test/CodeGen/arm-acle-coproc.c
b/clang/test/CodeGen/arm-acle-coproc.c
index cf87130932edfe9..0354d1297ece182 100644
--- a/clang/test/CodeGen/arm-acle-coproc.c
+++ b/clang/test/CodeGen/arm-acle-coproc.c
@@ -24,6 +24,7 @@
// RUN: %clang_cc1 -triple armv9.2a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple armv9.3a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple armv9.4a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv9.5a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv4 %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V4-THUMB %s
// RUN: %clang_cc1 -triple thumbv4t %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V4-THUMB %s
// RUN: %clang_cc1 -triple thumbv5 %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V5-THUMB %s
@@ -52,6 +53,7 @@
// RUN: %clang_cc1 -triple thumbv9.2a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv9.3a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv9.4a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv9.5a %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv8m.base %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8-BASE %s
// RUN: %clang_cc1 -triple thumbv8m.main %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8-MAIN %s
// RUN: %clang_cc1 -triple thumbv8.1m.main %s -E -dD -o - | FileCheck
--check-prefix=CHECK-V8-MAIN %s
diff --git a/clang/test/Driver/arm-cortex-cpus-1.c
b/clang/test/Driver/arm-cortex-cpus-1.c
index 2f300efee75ed4c..25abbe1e3a8ad7a 100644
--- a/clang/test/Driver/arm-cortex-cpus-1.c
+++ b/clang/test/Driver/arm-cortex-cpus-1.c
@@ -478,3 +478,20 @@
// RUN: %clang -target arm -march=armebv9.4a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V94A %s
// RUN: %clang -target arm -march=armebv9.4-a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V94A %s
// CHECK-BE-V94A: "-cc1"{{.*}} "-triple" "armebv9.4{{.*}}" "-target-cpu"
"generic"
+
+// RUN: %clang -target armv9.5a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V95A %s
+// RUN: %clang -target arm -march=armv9.5a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V95A %s
+// R
[llvm] [clang] [ARM] Introduce the v9.5-A architecture version to Arm targets (PR #78994)
pratlucas wrote: The ARM Target Parser is behind the AArch64 one in terms of design and refactoring. For the ARM case that relationship is not explicitly encoded in a single place, there are multiple switch-cases covering specific scenarios instead (e.g. the ones updated by this patch in clang/lib/Basic/Targets/ARM.cpp). I've added a comment only to the TableGen file for now, at least until we get the ARM target parser to the same standards as the AArch64 one. https://github.com/llvm/llvm-project/pull/78994 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM] Introduce the v9.5-A architecture version to Arm targets (PR #78994)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/78994 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] Re-land: "[AArch64] Add ability to list extensions enabled for a target" (#95805) (PR #96795)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/96795 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][TargetParser] move CPUInfo into tablegen [NFC] (PR #92145)
https://github.com/pratlucas approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/92145 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
https://github.com/pratlucas edited https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// = Architecture extensions =
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions
2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
pratlucas wrote:
The output for `--print-enbled-extensions` was implemented using the following
format:
```
Extensions enabled for the given AArch64 target
Architecture Feature(s)Description
FEAT_ETE Enable Embedded
Trace Extension
```
I chose not to include the `+foo` values in the output mostly because not all
of the extensions are exposed via `-march`/`-mcpu` and the implications between
them are not very clear. I'm happy to add these on a extra column, though, if
you think there's value to it.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// = Architecture extensions =
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions
2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
pratlucas wrote:
Also, yes, I believe it should be possible to use something like `clang
--print-enabled-extensions | tail | cut ... | sort | uniq`.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -161,6 +162,39 @@ static int PrintSupportedExtensions(std::string TargetStr)
{
return 0;
}
+static int PrintEnabledExtensions(const TargetOptions& TargetOpts) {
pratlucas wrote:
It's just following the local code style. I'm happy to update all of the
`static int PrintSomething(...)` functions in the file on a separate commit, to
keep things consistent.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -204,6 +238,10 @@ int cc1_main(ArrayRef Argv, const char
*Argv0, void *MainAddr) {
if (Clang->getFrontendOpts().PrintSupportedExtensions)
return PrintSupportedExtensions(Clang->getTargetOpts().Triple);
+ // --print-enabled-extensions takes priority over the actual compilation.
pratlucas wrote:
Only one of them wins and is executed, depending on the order of their
implementation in `cc1_main.cpp`. The same applies when using the two existing
`--print-supported-extensions` and `--print-supported-cpus` together.
Ideally, we should make these three options mutually exclusive in the future.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -5703,6 +5703,11 @@ def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions"> Visibility<[ClangOption, CC1Option, CLOption]>, HelpText<"Print supported -march extensions (RISC-V, AArch64 and ARM only)">, MarshallingInfoFlag>; +def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">, + Visibility<[ClangOption, CC1Option, CLOption]>, + HelpText<"Print the -march/-mcpu extensions enabled for the given target" pratlucas wrote: Done. https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -134,17 +136,39 @@ std::optional
AArch64::parseCpu(StringRef Name) {
return {};
}
-void AArch64::PrintSupportedExtensions(StringMap DescMap) {
+void AArch64::PrintSupportedExtensions() {
outs() << "All available -march extensions for AArch64\n\n"
<< "" << left_justify("Name", 20)
- << (DescMap.empty() ? "\n" : "Description\n");
+ << left_justify("Architecture Feature(s)", 55)
+ << "Description\n";
for (const auto &Ext : Extensions) {
// Extensions without a feature cannot be used with -march.
-if (!Ext.Feature.empty()) {
- std::string Description = DescMap[Ext.Name].str();
+if (!Ext.UserVisibleName.empty() && !Ext.TargetFeature.empty()) {
pratlucas wrote:
I've added a new unit test to cover the formatting in `TargetParserTest.cpp`.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisibleName; // Human readable name used in -march/-cpu,
e.g. "profile"
pratlucas wrote:
I've updated the comment accordingly.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisibleName; // Human readable name used in -march/-cpu,
e.g. "profile"
std::optional Alias; // An alias for this extension, if one
exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
- StringRef Feature; // -mattr enable string, e.g. "+spe"
- StringRef NegFeature; // -mattr disable string, e.g. "-spe"
+ StringRef ArchFeatureName; // The feature name defined by the
Architecture
pratlucas wrote:
Done.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisibleName; // Human readable name used in -march/-cpu,
e.g. "profile"
std::optional Alias; // An alias for this extension, if one
exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
- StringRef Feature; // -mattr enable string, e.g. "+spe"
- StringRef NegFeature; // -mattr disable string, e.g. "-spe"
+ StringRef ArchFeatureName; // The feature name defined by the
Architecture
+ StringRef Description; // The textual description of the extension
+ StringRef TargetFeature;// -target-feature/-mattr enable string,
e.g. "+spe"
pratlucas wrote:
Done.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -116,7 +116,9 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch)
{
std::optional
AArch64::parseArchExtension(StringRef ArchExt) {
for (const auto &A : Extensions) {
-if (ArchExt == A.Name || ArchExt == A.Alias)
+if (A.UserVisibleName.empty() && !A.Alias)
+ continue;
pratlucas wrote:
Done.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -140,89 +152,480 @@ def FeatureAES : Extension< // compatibility, and now imply features SHA2 and AES, which was the // "traditional" meaning of Crypto. let FMVDependencies = "+aes,+sha2" in -def FeatureCrypto : Extension<"crypto", "Crypto", +def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto", "FEAT_Crypto", "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; -def FeatureCRC : Extension<"crc", "CRC", - "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [], +def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32", + "Enable ARMv8 CRC-32 checksum instructions", [], "FEAT_CRC", "+crc", 110>; -def FeatureRAS : Extension<"ras", "RAS", - "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; - -def FeatureRASv2 : Extension<"rasv2", "RASv2", - "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", - [FeatureRAS]>; - -def FeatureLSE : Extension<"lse", "LSE", - "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", [], - "FEAT_LSE", "+lse", 80>; +// This SubtargetFeature is special. It controls only whether codegen will turn +// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The +// `FEAT_PMUv3*` system registers are always available for assembly/disassembly. +let MArchName = "pmuv3" in +def FeaturePerfMon : ExtensionWithMArch<"perfmon", "PerfMon", "FEAT_PMUv3", + "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension">; -def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", - "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; +def FeatureSpecRestrict : Extension<"specrestrict", "SpecRestrict", "FEAT_CSV2_2", + "Enable architectural speculation restriction">; -def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", - "Enable out of line atomics to support LSE instructions">; +//===--===// +// Armv8.1 Architecture Extensions +//===--===// -def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", - "Enable Function Multi Versioning support.">; +def FeatureLSE : ExtensionWithMArch<"lse", "LSE", "FEAT_LSE", + "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", [], + "FEAT_LSE", "+lse", 80>; let MArchAlias = "rdma" in -def FeatureRDM : Extension<"rdm", "RDM", - "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)", +def FeatureRDM : ExtensionWithMArch<"rdm", "RDM", "FEAT_RDM", + "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions", [FeatureNEON], "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>; -def FeaturePAN : SubtargetFeature< -"pan", "HasPAN", "true", -"Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">; +def FeaturePAN : Extension<"pan", "PAN", "FEAT_PAN", + "Enables ARM v8.1 Privileged Access-Never extension">; -def FeatureLOR : SubtargetFeature< -"lor", "HasLOR", "true", -"Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">; +def FeatureLOR : Extension<"lor", "LOR", "FEAT_LOR", + "Enables ARM v8.1 Limited Ordering Regions extension">; def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", "true", "Enable RW operand CONTEXTIDR_EL2" >; -def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", -"Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >; +def FeatureVH : Extension<"vh", "VH", "FEAT_VHE", + "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >; -// This SubtargetFeature is special. It controls only whether codegen will turn -// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The -// `FEAT_PMUv3*` system registers are always available for assembly/disassembly. -let MArchName = "pmuv3" in -def FeaturePerfMon : Extension<"perfmon", "PerfMon", - "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; +//===--===// +// Armv8.2 Architecture Extensions +//===--===// + +def FeatureSM4 : ExtensionWithMArch<"sm4", "SM4", "FEAT_SM4, FEAT_SM3", + "Enable SM3 and SM4 support", [FeatureNEON], + "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>; + +def FeatureSHA3 : ExtensionWithMArch<"sha3", "SHA3", "FEAT_SHA3, FEAT_SHA512", + "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2], + "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>; + +def FeatureRAS : ExtensionWithMArch<"ras", "RAS", "FEAT_RAS, FEAT_RASv1p1", + "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in -def FeatureFullFP16 : Extension<"fullfp16", "FullF
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// = Architecture extensions =
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions
2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
pratlucas wrote:
When adding those tests, I've noticed a few inconsistencies in the list of
extensions enabled per architecture version. Usually, for arch versions, we
only enable mandatory extensions by default, but these don't follow that
approach.
We've seen a few issues recently when adding new CPUs, where it can be tricky
to get a match between the llvm and the TRMs due to this.
I mostly wanted to double-check if this is something we want to
re-visit/discuss.
Do you have any thoughts on this? I'm happy to remove the FIXME lines otherwise.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// = Architecture extensions =
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions
2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
pratlucas wrote:
I wanted to keep these tests focused on the `FEAT_*` identifiers and to remove
the need of dealing with the less strict "description" content, which makes it
tricky to autogenerate the check lines. The set of extensions for each
architecture version is also stable, which reduces the value of going for
autogenerated tests in this case.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
https://github.com/pratlucas edited https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Remove SME/SVE uses of FMVDependencies (PR #93695)
https://github.com/pratlucas approved this pull request. The changes look good to me. Good catch spotting the inconsistency in the dependency expansion after the extension set is flattened. https://github.com/llvm/llvm-project/pull/93695 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Remove SME/SVE uses of FMVDependencies (PR #93695)
https://github.com/pratlucas approved this pull request. https://github.com/llvm/llvm-project/pull/93695 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// = Architecture extensions =
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions
2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
pratlucas wrote:
Agreed. I'll remove these comments and these can be discussed case-by-case in
the future.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -161,6 +162,39 @@ static int PrintSupportedExtensions(std::string TargetStr)
{
return 0;
}
+static int PrintEnabledExtensions(const TargetOptions& TargetOpts) {
+ std::string Error;
+ const llvm::Target *TheTarget =
+ llvm::TargetRegistry::lookupTarget(TargetOpts.Triple, Error);
+ if (!TheTarget) {
+llvm::errs() << Error;
+return 1;
+ }
+
+ llvm::TargetOptions BackendOptions;
+ std::string FeaturesStr = llvm::join(TargetOpts.FeaturesAsWritten, ",");
+ std::unique_ptr TheTargetMachine(
+ TheTarget->createTargetMachine(TargetOpts.Triple, TargetOpts.CPU,
FeaturesStr, BackendOptions, std::nullopt));
+ const llvm::Triple &MachineTriple = TheTargetMachine->getTargetTriple();
+ const llvm::MCSubtargetInfo *MCInfo = TheTargetMachine->getMCSubtargetInfo();
+ const std::vector Features =
+MCInfo->getEnabledProcessorFeatures();
+
+ std::vector EnabledFeatureNames;
+ for (const llvm::SubtargetFeatureKV &feature : Features)
+EnabledFeatureNames.push_back(feature.Key);
pratlucas wrote:
Unfortunately `llvm::SubtargetFeatureKV` doesn't hold a lot of information and
semantics of its contents is even less clear the what's capture here. I'll add
a comment to this block clarifying what's being captured.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -161,6 +162,39 @@ static int PrintSupportedExtensions(std::string TargetStr)
{
return 0;
}
+static int PrintEnabledExtensions(const TargetOptions& TargetOpts) {
+ std::string Error;
+ const llvm::Target *TheTarget =
+ llvm::TargetRegistry::lookupTarget(TargetOpts.Triple, Error);
+ if (!TheTarget) {
+llvm::errs() << Error;
+return 1;
+ }
+
+ llvm::TargetOptions BackendOptions;
pratlucas wrote:
`TargetOpts` captures the frontend options as a `clang::TargetOptions`
instance. The target machine takes an instance of `llvm::TargetOptions`
instead. It's confusing that the same class name was chosen for both.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -1841,7 +1868,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, + AArch64::AEK_CCDP}), pratlucas wrote: I don't see an advantage to not having AEK entries for all extensions. Having this correspondence not only increases testability, as shown by the changes in `TargetParserTest.cpp`, but also makes them consistently visible to the wider codebase via the Target Parser interface. https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -154,17 +156,39 @@ std::optional
AArch64::parseCpu(StringRef Name) {
return {};
}
-void AArch64::PrintSupportedExtensions(StringMap DescMap) {
+void AArch64::PrintSupportedExtensions() {
outs() << "All available -march extensions for AArch64\n\n"
<< "" << left_justify("Name", 20)
- << (DescMap.empty() ? "\n" : "Description\n");
+ << left_justify("Architecture Feature(s)", 55)
+ << "Description\n";
for (const auto &Ext : Extensions) {
// Extensions without a feature cannot be used with -march.
-if (!Ext.Feature.empty()) {
- std::string Description = DescMap[Ext.Name].str();
+if (!Ext.UserVisibleName.empty() && !Ext.PosTargetFeature.empty()) {
+ outs() << ""
+ << format(Ext.Description.empty() ? "%-20s%s\n" :
"%-20s%-55s%s\n",
+ Ext.UserVisibleName.str().c_str(),
+ Ext.ArchFeatureName.str().c_str(),
+ Ext.Description.str().c_str());
+}
+ }
+}
+
+void
+AArch64::printEnabledExtensions(std::vector EnabledFeatureNames) {
+ outs() << "Extensions enabled for the given AArch64 target\n\n"
+ << "" << left_justify("Architecture Feature(s)", 55)
+ << "Description\n";
+ auto IsEnabled = [&](const ExtensionInfo &Ext) {
+StringRef FeatureName = Ext.PosTargetFeature.drop_front(); // drop '+'
before comparing
pratlucas wrote:
No, the only `PosTargetFeature` was chosen as a reference here.
`EnabledFeatureNames` captures the list of plain names - i.e. without the `+`
or `-` prefixes, so we just need a fixed reference to compare them to.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [flang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -1130,7 +1130,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_MTE, AArch64::AEK_SSBS, AArch64::AEK_FP16,AArch64::AEK_FP16FML, AArch64::AEK_SB, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA,AArch64::AEK_PERFMON}), + AArch64::AEK_FCMA,AArch64::AEK_PERFMON, + AArch64::AEK_ETE, AArch64::AEK_AM}), pratlucas wrote: Yes, that's a very good idea! I'll work on migrating those tests in a follow up PR. https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] Revert "[AArch64] Add ability to list extensions enabled for a target" (PR #96768)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/96768 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
pratlucas wrote: > Looks like the new tests in `Driver` are missing `// REQUIRES: > aarch64-registered-target` Yes, I'm adding those now. There was also an odd ThreadSanitizer failure in clangd (https://lab.llvm.org/buildbot/#/builders/134/builds/680), which I'm investigating to check if is indeed related to this change. https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
pratlucas wrote: Good catch. I also wasn't able to reproduce it locally. I've created #96795 to re-land the changes with the updated tests. https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] Re-land: "[AArch64] Add ability to list extensions enabled for a target" (#95805) (PR #96795)
@@ -343,7 +350,9 @@ bool isX18ReservedByDefault(const Triple &TT); // themselves, they are sequential (0, 1, 2, 3, ...). uint64_t getCpuSupportsMask(ArrayRef FeatureStrs); -void PrintSupportedExtensions(StringMap DescMap); +void PrintSupportedExtensions(); + +void printEnabledExtensions(std::set EnabledFeatureNames); pratlucas wrote: Thanks for catching this! Not sure how I missed it 🤦 https://github.com/llvm/llvm-project/pull/96795 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] Re-land: "[AArch64] Add ability to list extensions enabled for a target" (#95805) (PR #96795)
@@ -21,7 +21,7 @@ // RUN: %clang --target=aarch64 -march=armv8a+fp16fml -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A-FP16FML %s pratlucas wrote: The check for target validity doesn't run when using `-###` in the command line. E.g.: ``` $ ../build/bin/clang -target foo -c test.c -### clang version 19.0.0git Target: foo Thread model: posix InstalledDir: /Users/lucpra01/Workspace/opensource/build/bin Build config: +tsan (in-process) "/Users/lucpra01/Workspace/opensource/build/bin/clang-19" "-cc1" "-triple" "foo" "-emit-obj" "-disable-free" "-clear-ast-before-backend" "-disable-llvm-verifier" "-discard-value-names" "-main-file-name" "test.c" "-mrelocation-model" "static" "-mframe-pointer=all" "-fmath-errno" "-ffp-contract=on" "-fno-rounding-math" "-mconstructor-aliases" "-debugger-tuning=gdb" "-fdebug-compilation-dir=/Users/lucpra01/Workspace/opensource/test" "-target-linker-version" "1053.12" "-fcoverage-compilation-dir=/Users/lucpra01/Workspace/opensource/test" "-resource-dir" "/Users/lucpra01/Workspace/opensource/build/lib/clang/19" "-ferror-limit" "19" "-fgnuc-version=4.2.1" "-fskip-odr-check-in-gmf" "-fcolor-diagnostics" "-faddrsig" "-o" "test.o" "-x" "c" "test.c" $ echo $? 0 ``` As adding the `// REQUIRES:` directive would reduced our current test coverage, I chose to add an `%if aarch64-registered-target` condition only to the relevant `// RUN:` lines instead. https://github.com/llvm/llvm-project/pull/96795 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] Re-land: "[AArch64] Add ability to list extensions enabled for a target" (#95805) (PR #96795)
@@ -315,37 +315,37 @@
// RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
// RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-MCPU-A64FX %s
// RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a"
"-target-feature" "+aes"{{.*}} "-target-feature" "+fp-armv8" "-target-feature"
"+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon"
pratlucas wrote:
Ditto.
https://github.com/llvm/llvm-project/pull/96795
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[clang] [AArch64]: Refactor target parser to use BitVector. (PR #65423)
@@ -315,23 +317,23 @@ struct ArchInfo {
};
// clang-format off
-inline constexpr ArchInfo ARMV8A= { VersionTuple{8, 0}, AProfile,
"armv8-a", "+v8a", (AArch64::AEK_FP | AArch64::AEK_SIMD), };
-inline constexpr ArchInfo ARMV8_1A = { VersionTuple{8, 1}, AProfile,
"armv8.1-a", "+v8.1a", (ARMV8A.DefaultExts | AArch64::AEK_CRC |
AArch64::AEK_LSE | AArch64::AEK_RDM)};
-inline constexpr ArchInfo ARMV8_2A = { VersionTuple{8, 2}, AProfile,
"armv8.2-a", "+v8.2a", (ARMV8_1A.DefaultExts | AArch64::AEK_RAS)};
-inline constexpr ArchInfo ARMV8_3A = { VersionTuple{8, 3}, AProfile,
"armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts | AArch64::AEK_RCPC)};
-inline constexpr ArchInfo ARMV8_4A = { VersionTuple{8, 4}, AProfile,
"armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts | AArch64::AEK_DOTPROD)};
-inline constexpr ArchInfo ARMV8_5A = { VersionTuple{8, 5}, AProfile,
"armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)};
-inline constexpr ArchInfo ARMV8_6A = { VersionTuple{8, 6}, AProfile,
"armv8.6-a", "+v8.6a", (ARMV8_5A.DefaultExts | AArch64::AEK_BF16 |
AArch64::AEK_I8MM)};
-inline constexpr ArchInfo ARMV8_7A = { VersionTuple{8, 7}, AProfile,
"armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
-inline constexpr ArchInfo ARMV8_8A = { VersionTuple{8, 8}, AProfile,
"armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | AArch64::AEK_MOPS |
AArch64::AEK_HBC)};
-inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile,
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts | AArch64::AEK_SPECRES2 |
AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
-inline constexpr ArchInfo ARMV9A= { VersionTuple{9, 0}, AProfile,
"armv9-a", "+v9a", (ARMV8_5A.DefaultExts | AArch64::AEK_FP16 | AArch64::AEK_SVE
| AArch64::AEK_SVE2)};
-inline constexpr ArchInfo ARMV9_1A = { VersionTuple{9, 1}, AProfile,
"armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts | AArch64::AEK_BF16 |
AArch64::AEK_I8MM)};
-inline constexpr ArchInfo ARMV9_2A = { VersionTuple{9, 2}, AProfile,
"armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)};
-inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile,
"armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts | AArch64::AEK_MOPS |
AArch64::AEK_HBC)};
-inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile,
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts | AArch64::AEK_SPECRES2 |
AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
+inline ArchInfo ARMV8A= { VersionTuple{8, 0}, AProfile, "armv8-a", "+v8a",
(BitVector(AEK_EXTENTIONS_NUM).set(AArch64::AEK_FP).set(AArch64::AEK_SIMD)), };
pratlucas wrote:
Could we have a constructor for `ArchInfo` that takes a list of `ArchExtKind`s
as an argument (e.g. an initialiser_list)? This would make these lines less
verbose and a bit more readable.
https://github.com/llvm/llvm-project/pull/65423
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[clang] [AArch64]: Refactor target parser to use BitVector. (PR #65423)
@@ -96,64 +97,65 @@ static_assert(FEAT_MAX <= 64,
// Arch extension modifiers for CPUs. These are labelled with their Arm ARM
// feature name (though the canonical reference for those is AArch64.td)
// clang-format off
-enum ArchExtKind : uint64_t {
- AEK_NONE =1,
- AEK_CRC = 1 << 1, // FEAT_CRC32
- AEK_CRYPTO = 1 << 2,
- AEK_FP = 1 << 3, // FEAT_FP
- AEK_SIMD =1 << 4, // FEAT_AdvSIMD
- AEK_FP16 =1 << 5, // FEAT_FP16
- AEK_PROFILE = 1 << 6, // FEAT_SPE
- AEK_RAS = 1 << 7, // FEAT_RAS, FEAT_RASv1p1
- AEK_LSE = 1 << 8, // FEAT_LSE
- AEK_SVE = 1 << 9, // FEAT_SVE
- AEK_DOTPROD = 1 << 10, // FEAT_DotProd
- AEK_RCPC =1 << 11, // FEAT_LRCPC
- AEK_RDM = 1 << 12, // FEAT_RDM
- AEK_SM4 = 1 << 13, // FEAT_SM4, FEAT_SM3
- AEK_SHA3 =1 << 14, // FEAT_SHA3, FEAT_SHA512
- AEK_SHA2 =1 << 15, // FEAT_SHA1, FEAT_SHA256
- AEK_AES = 1 << 16, // FEAT_AES, FEAT_PMULL
- AEK_FP16FML = 1 << 17, // FEAT_FHM
- AEK_RAND =1 << 18, // FEAT_RNG
- AEK_MTE = 1 << 19, // FEAT_MTE, FEAT_MTE2
- AEK_SSBS =1 << 20, // FEAT_SSBS, FEAT_SSBS2
- AEK_SB = 1 << 21, // FEAT_SB
- AEK_PREDRES = 1 << 22, // FEAT_SPECRES
- AEK_SVE2 =1 << 23, // FEAT_SVE2
- AEK_SVE2AES = 1 << 24, // FEAT_SVE_AES, FEAT_SVE_PMULL128
- AEK_SVE2SM4 = 1 << 25, // FEAT_SVE_SM4
- AEK_SVE2SHA3 =1 << 26, // FEAT_SVE_SHA3
- AEK_SVE2BITPERM = 1 << 27, // FEAT_SVE_BitPerm
- AEK_TME = 1 << 28, // FEAT_TME
- AEK_BF16 =1 << 29, // FEAT_BF16
- AEK_I8MM =1 << 30, // FEAT_I8MM
- AEK_F32MM = 1ULL << 31, // FEAT_F32MM
- AEK_F64MM = 1ULL << 32, // FEAT_F64MM
- AEK_LS64 =1ULL << 33, // FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA
- AEK_BRBE =1ULL << 34, // FEAT_BRBE
- AEK_PAUTH = 1ULL << 35, // FEAT_PAuth
- AEK_FLAGM = 1ULL << 36, // FEAT_FlagM
- AEK_SME = 1ULL << 37, // FEAT_SME
- AEK_SMEF64F64 = 1ULL << 38, // FEAT_SME_F64F64
- AEK_SMEI16I64 = 1ULL << 39, // FEAT_SME_I16I64
- AEK_HBC = 1ULL << 40, // FEAT_HBC
- AEK_MOPS =1ULL << 41, // FEAT_MOPS
- AEK_PERFMON = 1ULL << 42, // FEAT_PMUv3
- AEK_SME2 =1ULL << 43, // FEAT_SME2
- AEK_SVE2p1 = 1ULL << 44, // FEAT_SVE2p1
- AEK_SME2p1 = 1ULL << 45, // FEAT_SME2p1
- AEK_B16B16 = 1ULL << 46, // FEAT_B16B16
- AEK_SMEF16F16 = 1ULL << 47, // FEAT_SMEF16F16
- AEK_CSSC =1ULL << 48, // FEAT_CSSC
- AEK_RCPC3 = 1ULL << 49, // FEAT_LRCPC3
- AEK_THE = 1ULL << 50, // FEAT_THE
- AEK_D128 =1ULL << 51, // FEAT_D128
- AEK_LSE128 = 1ULL << 52, // FEAT_LSE128
- AEK_SPECRES2 =1ULL << 53, // FEAT_SPECRES2
- AEK_RASv2 = 1ULL << 54, // FEAT_RASv2
- AEK_ITE = 1ULL << 55, // FEAT_ITE
- AEK_GCS = 1ULL << 56, // FEAT_GCS
+enum ArchExtKind : int {
pratlucas wrote:
Since the enum will no longer represent a bit map, can it be made an `enum
class`?
https://github.com/llvm/llvm-project/pull/65423
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[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
@@ -19,10 +19,38 @@
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include
+#include
#include
using namespace llvm;
+/// Collect the full set of implied features for a SubtargetFeature.
+static void CollectImpliedFeatures(std::set &SeenFeats, Record *Rec)
{
+ assert(Rec->isSubClassOf("SubtargetFeature") &&
+ "Rec is not a SubtargetFeature");
+
+ SeenFeats.insert(Rec);
+ for (Record *Implied : Rec->getValueAsListOfDefs("Implies"))
+CollectImpliedFeatures(SeenFeats, Implied);
+}
+
+static void CheckFeatureTree(Record *Root) {
+ std::set SeenFeats;
+ CollectImpliedFeatures(SeenFeats, Root);
+
+ // For processors, check that each of the mandatory (implied) features which
pratlucas wrote:
Nit: this seems to be covering architecture versions rather than processors.
https://github.com/llvm/llvm-project/pull/104435
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[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/pratlucas approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][test] Split invalid-cpu-note tests (PR #104601)
https://github.com/pratlucas approved this pull request. LGTM. Thanks for splitting these! https://github.com/llvm/llvm-project/pull/104601 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Add -mbranch-protection to ARM and AArch64 multilib flags (PR #106391)
https://github.com/pratlucas updated
https://github.com/llvm/llvm-project/pull/106391
>From b3d7b528a422f7c44b535c480acbd74f03555b4d Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Wed, 28 Aug 2024 13:58:57 +0100
Subject: [PATCH 1/2] [Driver] Add -mbranch-protection to ARM and AArch64
multilib flags
This adds the `-mbranch-protection` command line option to the set of
flags used by the multilib selection for ARM and AArch64 targets.
---
clang/lib/Driver/ToolChain.cpp | 10 ++
clang/test/Driver/print-multi-selection-flags.c | 4
2 files changed, 14 insertions(+)
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index c93c97146b6104..442512366c9114 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -221,6 +221,11 @@ static void getAArch64MultilibFlags(const Driver &D,
assert(!ArchName.empty() && "at least one architecture should be found");
MArch.insert(MArch.begin(), ("-march=" + ArchName).str());
Result.push_back(llvm::join(MArch, "+"));
+
+ const Arg *BranchProtectionArg =
Args.getLastArgNoClaim(options::OPT_mbranch_protection_EQ);
+ if (BranchProtectionArg) {
+Result.push_back(BranchProtectionArg->getAsString(Args));
+ }
}
static void getARMMultilibFlags(const Driver &D,
@@ -268,6 +273,11 @@ static void getARMMultilibFlags(const Driver &D,
case arm::FloatABI::Invalid:
llvm_unreachable("Invalid float ABI");
}
+
+ const Arg *BranchProtectionArg =
Args.getLastArgNoClaim(options::OPT_mbranch_protection_EQ);
+ if (BranchProtectionArg) {
+Result.push_back(BranchProtectionArg->getAsString(Args));
+ }
}
static void getRISCVMultilibFlags(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/test/Driver/print-multi-selection-flags.c
b/clang/test/Driver/print-multi-selection-flags.c
index 2770a3ad5eaa1d..0116c7f5a03b9a 100644
--- a/clang/test/Driver/print-multi-selection-flags.c
+++ b/clang/test/Driver/print-multi-selection-flags.c
@@ -59,6 +59,10 @@
// CHECK-SVE2: --target=aarch64-unknown-none-elf
// CHECK-SVE2: -march=armv{{.*}}-a{{.*}}+simd{{.*}}+sve{{.*}}+sve2{{.*}}
+// RUN: %clang -print-multi-flags-experimental --target=arm-none-eabi
-mbranch-protection=standard| FileCheck
--check-prefix=CHECK-BRANCH-PROTECTION %s
+// RUN: %clang -print-multi-flags-experimental --target=aarch64-none-elf
-mbranch-protection=standard | FileCheck --check-prefix=CHECK-BRANCH-PROTECTION
%s
+// CHECK-BRANCH-PROTECTION: -mbranch-protection=standard
+
// RUN: %clang -print-multi-flags-experimental --target=riscv32-none-elf
-march=rv32g | FileCheck --check-prefix=CHECK-RV32 %s
// CHECK-RV32: --target=riscv32-unknown-none-elf
// CHECK-RV32: -mabi=ilp32d
>From 5187e069c0f3da4f5dbbfd064c7ceb8e383a2371 Mon Sep 17 00:00:00 2001
From: Lucas Prates
Date: Wed, 28 Aug 2024 14:50:53 +0100
Subject: [PATCH 2/2] fixup! [Driver] Add -mbranch-protection to ARM and
AArch64 multilib flags
---
clang/lib/Driver/ToolChain.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 442512366c9114..76901875c66959 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -222,7 +222,8 @@ static void getAArch64MultilibFlags(const Driver &D,
MArch.insert(MArch.begin(), ("-march=" + ArchName).str());
Result.push_back(llvm::join(MArch, "+"));
- const Arg *BranchProtectionArg =
Args.getLastArgNoClaim(options::OPT_mbranch_protection_EQ);
+ const Arg *BranchProtectionArg =
+ Args.getLastArgNoClaim(options::OPT_mbranch_protection_EQ);
if (BranchProtectionArg) {
Result.push_back(BranchProtectionArg->getAsString(Args));
}
@@ -274,7 +275,8 @@ static void getARMMultilibFlags(const Driver &D,
llvm_unreachable("Invalid float ABI");
}
- const Arg *BranchProtectionArg =
Args.getLastArgNoClaim(options::OPT_mbranch_protection_EQ);
+ const Arg *BranchProtectionArg =
+ Args.getLastArgNoClaim(options::OPT_mbranch_protection_EQ);
if (BranchProtectionArg) {
Result.push_back(BranchProtectionArg->getAsString(Args));
}
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[clang] [Driver] Add -mbranch-protection to ARM and AArch64 multilib flags (PR #106391)
https://github.com/pratlucas closed https://github.com/llvm/llvm-project/pull/106391 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
