from:"Tom Stellard via llvm\-branch\-commits"

[llvm-branch-commits] [mlir] release/18.x: [mlir][NFC] Apply rule of five to *Pass classes (#80998) (PR #83971)

2024-03-13 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

I think it's an ABI change (but I could be wrong), because some of the implicit 
constructors are being deleted.  What happens if a user of the library was 
using these deleted constructors?

https://github.com/llvm/llvm-project/pull/83971
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[llvm-branch-commits] [llvm] 7b61dde - [ArgPromotion] Remove incorrect TranspBlocks set for loads. (#84835)

2024-03-13 Thread Tom Stellard via llvm-branch-commits


Author: Florian Hahn
Date: 2024-03-13T11:01:14-07:00
New Revision: 7b61ddefc28a2c88be3a754ceee7bace98e3b187

URL: 
https://github.com/llvm/llvm-project/commit/7b61ddefc28a2c88be3a754ceee7bace98e3b187
DIFF: 
https://github.com/llvm/llvm-project/commit/7b61ddefc28a2c88be3a754ceee7bace98e3b187.diff

LOG: [ArgPromotion] Remove incorrect TranspBlocks set for loads. (#84835)

The TranspBlocks set was used to cache aliasing decision for all
processed loads in the parent loop. This is incorrect, because each load
can access a different location, which means one load not being modified
in a block doesn't translate to another load not being modified in the
same block.

All loads access the same underlying object, so we could perhaps use a
location without size for all loads and retain the cache, but that would
mean we loose precision.

For now, just drop the cache.

Fixes https://github.com/llvm/llvm-project/issues/84807

PR: https://github.com/llvm/llvm-project/pull/84835
(cherry picked from commit bba4a1daff6ee09941f1369a4e56b4af95efdc5c)

Added: 


Modified: 
llvm/lib/Transforms/IPO/ArgumentPromotion.cpp

llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll

Removed: 




diff  --git a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp 
b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
index 8058282c422503..062a3d341007ce 100644
--- a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
+++ b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
@@ -652,10 +652,6 @@ static bool findArgParts(Argument *Arg, const DataLayout 
, AAResults ,
   // check to see if the pointer is guaranteed to not be modified from entry of
   // the function to each of the load instructions.
 
-  // Because there could be several/many load instructions, remember which
-  // blocks we know to be transparent to the load.
-  df_iterator_default_set TranspBlocks;
-
   for (LoadInst *Load : Loads) {
 // Check to see if the load is invalidated from the start of the block to
 // the load itself.
@@ -669,7 +665,7 @@ static bool findArgParts(Argument *Arg, const DataLayout 
, AAResults ,
 // To do this, we perform a depth first search on the inverse CFG from the
 // loading block.
 for (BasicBlock *P : predecessors(BB)) {
-  for (BasicBlock *TranspBB : inverse_depth_first_ext(P, TranspBlocks))
+  for (BasicBlock *TranspBB : inverse_depth_first(P))
 if (AAR.canBasicBlockModify(*TranspBB, Loc))
   return false;
 }

diff  --git 
a/llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll
 
b/llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll
index 69385a7ea51a74..1e1669b29b0db6 100644
--- 
a/llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll
+++ 
b/llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll
@@ -7,17 +7,14 @@ target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:
 
 ; Test case for https://github.com/llvm/llvm-project/issues/84807.
 
-; FIXME: Currently the loads from @callee are moved to @caller, even though
-;the store in %then may aliases to load from %q.
+; Make sure the loads from @callee are not moved to @caller, as the store
+; in %then may aliases to load from %q.
 
 define i32 @caller1(i1 %c) {
 ; CHECK-LABEL: define i32 @caller1(
 ; CHECK-SAME: i1 [[C:%.*]]) {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:[[F_VAL:%.*]] = load i16, ptr @f, align 8
-; CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr @f, i64 8
-; CHECK-NEXT:[[F_VAL1:%.*]] = load i64, ptr [[TMP0]], align 8
-; CHECK-NEXT:call void @callee1(i16 [[F_VAL]], i64 [[F_VAL1]], i1 [[C]])
+; CHECK-NEXT:call void @callee1(ptr noundef nonnull @f, i1 [[C]])
 ; CHECK-NEXT:ret i32 0
 ;
 entry:
@@ -27,13 +24,16 @@ entry:
 
 define internal void @callee1(ptr nocapture noundef readonly %q, i1 %c) {
 ; CHECK-LABEL: define internal void @callee1(
-; CHECK-SAME: i16 [[Q_0_VAL:%.*]], i64 [[Q_8_VAL:%.*]], i1 [[C:%.*]]) {
+; CHECK-SAME: ptr nocapture noundef readonly [[Q:%.*]], i1 [[C:%.*]]) {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:br i1 [[C]], label [[THEN:%.*]], label [[EXIT:%.*]]
 ; CHECK:   then:
 ; CHECK-NEXT:store i16 123, ptr @f, align 8
 ; CHECK-NEXT:br label [[EXIT]]
 ; CHECK:   exit:
+; CHECK-NEXT:[[Q_0_VAL:%.*]] = load i16, ptr [[Q]], align 8
+; CHECK-NEXT:[[GEP_8:%.*]] = getelementptr inbounds i8, ptr [[Q]], i64 8
+; CHECK-NEXT:[[Q_8_VAL:%.*]] = load i64, ptr [[GEP_8]], align 8
 ; CHECK-NEXT:call void @use(i16 [[Q_0_VAL]], i64 [[Q_8_VAL]])
 ; CHECK-NEXT:ret void
 ;



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[llvm-branch-commits] [llvm] 25a989c - [ArgPromotion] Add test case for #84807.

2024-03-13 Thread Tom Stellard via llvm-branch-commits


Author: Florian Hahn
Date: 2024-03-13T11:01:14-07:00
New Revision: 25a989ce8bf35ccda064d956305f920bf711a7de

URL: 
https://github.com/llvm/llvm-project/commit/25a989ce8bf35ccda064d956305f920bf711a7de
DIFF: 
https://github.com/llvm/llvm-project/commit/25a989ce8bf35ccda064d956305f920bf711a7de.diff

LOG: [ArgPromotion] Add test case for #84807.

Test case for https://github.com/llvm/llvm-project/issues/84807,
showing a mis-compile in ArgPromotion.

(cherry picked from commit 31ffdb56b4df9b772d763dccabbfde542545d695)

Added: 

llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll

Modified: 


Removed: 




diff  --git 
a/llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll
 
b/llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll
new file mode 100644
index 00..69385a7ea51a74
--- /dev/null
+++ 
b/llvm/test/Transforms/ArgumentPromotion/aliasing-and-non-aliasing-loads-with-clobber.ll
@@ -0,0 +1,100 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt -p argpromotion -S %s | FileCheck %s
+
+target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+
+@f = dso_local global { i16, i64 } { i16 1, i64 0 }, align 8
+
+; Test case for https://github.com/llvm/llvm-project/issues/84807.
+
+; FIXME: Currently the loads from @callee are moved to @caller, even though
+;the store in %then may aliases to load from %q.
+
+define i32 @caller1(i1 %c) {
+; CHECK-LABEL: define i32 @caller1(
+; CHECK-SAME: i1 [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[F_VAL:%.*]] = load i16, ptr @f, align 8
+; CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr @f, i64 8
+; CHECK-NEXT:[[F_VAL1:%.*]] = load i64, ptr [[TMP0]], align 8
+; CHECK-NEXT:call void @callee1(i16 [[F_VAL]], i64 [[F_VAL1]], i1 [[C]])
+; CHECK-NEXT:ret i32 0
+;
+entry:
+  call void @callee1(ptr noundef nonnull @f, i1 %c)
+  ret i32 0
+}
+
+define internal void @callee1(ptr nocapture noundef readonly %q, i1 %c) {
+; CHECK-LABEL: define internal void @callee1(
+; CHECK-SAME: i16 [[Q_0_VAL:%.*]], i64 [[Q_8_VAL:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:br i1 [[C]], label [[THEN:%.*]], label [[EXIT:%.*]]
+; CHECK:   then:
+; CHECK-NEXT:store i16 123, ptr @f, align 8
+; CHECK-NEXT:br label [[EXIT]]
+; CHECK:   exit:
+; CHECK-NEXT:call void @use(i16 [[Q_0_VAL]], i64 [[Q_8_VAL]])
+; CHECK-NEXT:ret void
+;
+entry:
+  br i1 %c, label %then, label %exit
+
+then:
+  store i16 123, ptr @f, align 8
+  br label %exit
+
+exit:
+  %l.0 = load i16, ptr %q, align 8
+  %gep.8  = getelementptr inbounds i8, ptr %q, i64 8
+  %l.1 = load i64, ptr %gep.8, align 8
+  call void @use(i16 %l.0, i64 %l.1)
+  ret void
+
+  uselistorder ptr %q, { 1, 0 }
+}
+
+; Same as @caller1/callee2, but with default uselist order.
+define i32 @caller2(i1 %c) {
+; CHECK-LABEL: define i32 @caller2(
+; CHECK-SAME: i1 [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:call void @callee2(ptr noundef nonnull @f, i1 [[C]])
+; CHECK-NEXT:ret i32 0
+;
+entry:
+  call void @callee2(ptr noundef nonnull @f, i1 %c)
+  ret i32 0
+}
+
+define internal void @callee2(ptr nocapture noundef readonly %q, i1 %c) {
+; CHECK-LABEL: define internal void @callee2(
+; CHECK-SAME: ptr nocapture noundef readonly [[Q:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:br i1 [[C]], label [[THEN:%.*]], label [[EXIT:%.*]]
+; CHECK:   then:
+; CHECK-NEXT:store i16 123, ptr @f, align 8
+; CHECK-NEXT:br label [[EXIT]]
+; CHECK:   exit:
+; CHECK-NEXT:[[Q_0_VAL:%.*]] = load i16, ptr [[Q]], align 8
+; CHECK-NEXT:[[GEP_8:%.*]] = getelementptr inbounds i8, ptr [[Q]], i64 8
+; CHECK-NEXT:[[Q_8_VAL:%.*]] = load i64, ptr [[GEP_8]], align 8
+; CHECK-NEXT:call void @use(i16 [[Q_0_VAL]], i64 [[Q_8_VAL]])
+; CHECK-NEXT:ret void
+;
+entry:
+  br i1 %c, label %then, label %exit
+
+then:
+  store i16 123, ptr @f, align 8
+  br label %exit
+
+exit:
+  %l.0 = load i16, ptr %q, align 8
+  %gep.8  = getelementptr inbounds i8, ptr %q, i64 8
+  %l.1 = load i64, ptr %gep.8, align 8
+  call void @use(i16 %l.0, i64 %l.1)
+  ret void
+}
+
+declare void @use(i16, i64)



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[llvm-branch-commits] [llvm] release/18.x: [ArgPromotion] Remove incorrect TranspBlocks set for loads. (#84835) (PR #84945)

2024-03-13 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84945
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[llvm-branch-commits] [lld] release/18.x: [LLD] [COFF] Set the right alignment for DelayDirectoryChunk (#84697) (PR #84844)

2024-03-13 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84844
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[llvm-branch-commits] [lld] 2fc8bea - [LLD] [COFF] Set the right alignment for DelayDirectoryChunk (#84697)

2024-03-13 Thread Tom Stellard via llvm-branch-commits


Author: Martin Storsjö
Date: 2024-03-13T10:58:58-07:00
New Revision: 2fc8bea42f992901cf4dbbe8b62c3383b2eb0288

URL: 
https://github.com/llvm/llvm-project/commit/2fc8bea42f992901cf4dbbe8b62c3383b2eb0288
DIFF: 
https://github.com/llvm/llvm-project/commit/2fc8bea42f992901cf4dbbe8b62c3383b2eb0288.diff

LOG: [LLD] [COFF] Set the right alignment for DelayDirectoryChunk (#84697)

This makes a difference when linking executables with delay loaded
libraries for arm32; the delay loader implementation can load data from
the registry with instructions that assume alignment.

This issue does not show up when linking in MinGW mode, because a
PseudoRelocTableChunk gets injected, which also sets alignment, even if
the chunk itself is empty.

(cherry picked from commit c93c76b562784926b22a69d3f82a5032dcb4a274)

Added: 


Modified: 
lld/COFF/DLL.cpp
lld/test/COFF/delayimports-armnt.yaml

Removed: 




diff  --git a/lld/COFF/DLL.cpp b/lld/COFF/DLL.cpp
index 6b516d8c6d5ef8..c4388ba9e40d0b 100644
--- a/lld/COFF/DLL.cpp
+++ b/lld/COFF/DLL.cpp
@@ -172,7 +172,7 @@ binImports(COFFLinkerContext ,
 // A chunk for the delay import descriptor table etnry.
 class DelayDirectoryChunk : public NonSectionChunk {
 public:
-  explicit DelayDirectoryChunk(Chunk *n) : dllName(n) {}
+  explicit DelayDirectoryChunk(Chunk *n) : dllName(n) { setAlignment(4); }
 
   size_t getSize() const override {
 return sizeof(delay_import_directory_table_entry);

diff  --git a/lld/test/COFF/delayimports-armnt.yaml 
b/lld/test/COFF/delayimports-armnt.yaml
index 7d9bc38c5c3606..ea96d864ef53d5 100644
--- a/lld/test/COFF/delayimports-armnt.yaml
+++ b/lld/test/COFF/delayimports-armnt.yaml
@@ -6,6 +6,7 @@
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s
 # RUN: llvm-readobj --coff-basereloc %t.exe | FileCheck -check-prefix=BASEREL 
%s
 # RUN: llvm-objdump --no-print-imm-hex -d %t.exe | FileCheck 
--check-prefix=DISASM %s
+# RUN: llvm-readobj --file-headers %t.exe | FileCheck -check-prefix=DIR %s
 
 # IMPORT:  Format: COFF-ARM
 # IMPORT-NEXT: Arch: thumb
@@ -13,9 +14,9 @@
 # IMPORT-NEXT: DelayImport {
 # IMPORT-NEXT:   Name: library.dll
 # IMPORT-NEXT:   Attributes: 0x1
-# IMPORT-NEXT:   ModuleHandle: 0x3000
-# IMPORT-NEXT:   ImportAddressTable: 0x3008
-# IMPORT-NEXT:   ImportNameTable: 0x2040
+# IMPORT-NEXT:   ModuleHandle: 0x3008
+# IMPORT-NEXT:   ImportAddressTable: 0x3010
+# IMPORT-NEXT:   ImportNameTable: 0x2044
 # IMPORT-NEXT:   BoundDelayImportTable: 0x0
 # IMPORT-NEXT:   UnloadDelayImportTable: 0x0
 # IMPORT-NEXT:   Import {
@@ -43,7 +44,7 @@
 # BASEREL-NEXT:   }
 # BASEREL-NEXT:   Entry {
 # BASEREL-NEXT: Type: HIGHLOW
-# BASEREL-NEXT: Address: 0x3008
+# BASEREL-NEXT: Address: 0x3010
 # BASEREL-NEXT:   }
 # BASEREL-NEXT:   Entry {
 # BASEREL-NEXT: Type: ABSOLUTE
@@ -52,20 +53,24 @@
 # BASEREL-NEXT: ]
 #
 # DISASM:00401000 <.text>:
-# DISASM:  40100c:   f243 0c08   movw r12, #12296
+# DISASM:  40100c:   f243 0c10   movw r12, #12304
 # DISASM-NEXT:   f2c0 0c40   movtr12, #64
 # DISASM-NEXT:   f000 b800   b.w {{.+}} @ imm = #0
 # DISASM-NEXT:   e92d 480f   push.w  {r0, r1, r2, r3, r11, lr}
 # DISASM-NEXT:   f20d 0b10   addwr11, sp, #16
 # DISASM-NEXT:   ed2d 0b10   vpush   {d0, d1, d2, d3, d4, d5, 
d6, d7}
 # DISASM-NEXT:   4661mov r1, r12
-# DISASM-NEXT:   f242    movw r0, #8192
+# DISASM-NEXT:   f242 0004   movw r0, #8196
 # DISASM-NEXT:   f2c0 0040   movtr0, #64
 # DISASM-NEXT:   f7ff ffe7   bl  0x401000 <.text>
 # DISASM-NEXT:   4684mov r12, r0
 # DISASM-NEXT:   ecbd 0b10   vpop{d0, d1, d2, d3, d4, d5, 
d6, d7}
 # DISASM-NEXT:   e8bd 480f   pop.w   {r0, r1, r2, r3, r11, lr}
 # DISASM-NEXT:   4760bx  r12
+#
+# DIR: DelayImportDescriptorRVA: 0x2004
+# DIR-NEXT:DelayImportDescriptorSize: 0x40
+
 
 --- !COFF
 header:
@@ -80,6 +85,14 @@ sections:
   - VirtualAddress:  0
 SymbolName:  __imp_function
 Type:IMAGE_REL_ARM_MOV32T
+  - Name:.rdata
+Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ ]
+Alignment:   1
+SectionData: 01
+  - Name:.data
+Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, 
IMAGE_SCN_MEM_WRITE ]
+Alignment:   1
+SectionData: 02
 symbols:
   - Name:.text
 Value:   0



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[llvm-branch-commits] [llvm] workflows: Add workaround for lld failures on MacOS (#85021) (PR #85110)

2024-03-13 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar created 
https://github.com/llvm/llvm-project/pull/85110

See #81967

(cherry picked from commit 175b533720956017bb18d1280362f6890ee15b05)

>From b1461c4b8b30a0086bca54e987580c63ae8174b4 Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Wed, 13 Mar 2024 10:44:12 -0700
Subject: [PATCH] workflows: Add workaround for lld failures on MacOS (#85021)

See #81967

(cherry picked from commit 175b533720956017bb18d1280362f6890ee15b05)
---
 .github/workflows/llvm-project-tests.yml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/.github/workflows/llvm-project-tests.yml 
b/.github/workflows/llvm-project-tests.yml
index 43b90193406fc9..a52dd2db8035dd 100644
--- a/.github/workflows/llvm-project-tests.yml
+++ b/.github/workflows/llvm-project-tests.yml
@@ -118,6 +118,11 @@ jobs:
   else
 builddir="$(pwd)"/build
   fi
+  if [ "${{ runner.os }}" == "macOS" ]; then
+# Workaround test failure on some lld tests on MacOS
+# https://github.com/llvm/llvm-project/issues/81967
+extra_cmake_args="-DLLVM_DISABLE_ASSEMBLY_FILES=ON"
+  fi
   echo "llvm-builddir=$builddir" >> "$GITHUB_OUTPUT"
   cmake -G Ninja \
 -B "$builddir" \

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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Add test for aliasing miscompile fixed by #83017. NFC (PR #83856)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

There is a problem with the ABI check CI test, but I believe this patch will 
change the C++ ABI, because it changes the signature of `computeAliasing`  Is 
it possible to add a function with the old signature that wraps and calls the 
new signature?

https://github.com/llvm/llvm-project/pull/83856
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[llvm-branch-commits] [llvm] fcc33dc - [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Simon Pilgrim
Date: 2024-03-12T22:30:11-07:00
New Revision: fcc33dca02d1f22d3dad5c4558ddff4926aef9d9

URL: 
https://github.com/llvm/llvm-project/commit/fcc33dca02d1f22d3dad5c4558ddff4926aef9d9
DIFF: 
https://github.com/llvm/llvm-project/commit/fcc33dca02d1f22d3dad5c4558ddff4926aef9d9.diff

LOG: [X86] combineAndShuffleNot - ensure the type is legal before create 
X86ISD::ANDNP target nodes

Fixes #84660

(cherry picked from commit 862c7e0218f27b55a5b75ae59a4f73cd4610448d)

Added: 


Modified: 
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/combine-and.ll

Removed: 




diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a071c5a3ca0326..9e64726fb6fff7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47878,6 +47878,7 @@ static SDValue combineAndShuffleNot(SDNode *N, 
SelectionDAG ,
   SDValue X, Y;
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  const TargetLowering  = DAG.getTargetLoweringInfo();
 
   if (SDValue Not = GetNot(N0)) {
 X = Not;
@@ -47891,9 +47892,11 @@ static SDValue combineAndShuffleNot(SDNode *N, 
SelectionDAG ,
   X = DAG.getBitcast(VT, X);
   Y = DAG.getBitcast(VT, Y);
   SDLoc DL(N);
+
   // We do not split for SSE at all, but we need to split vectors for AVX1 and
   // AVX2.
-  if (!Subtarget.useAVX512Regs() && VT.is512BitVector()) {
+  if (!Subtarget.useAVX512Regs() && VT.is512BitVector() && 
+  TLI.isTypeLegal(VT.getHalfNumVectorElementsVT(*DAG.getContext( {
 SDValue LoX, HiX;
 std::tie(LoX, HiX) = splitVector(X, DAG, DL);
 SDValue LoY, HiY;
@@ -47903,7 +47906,11 @@ static SDValue combineAndShuffleNot(SDNode *N, 
SelectionDAG ,
 SDValue HiV = DAG.getNode(X86ISD::ANDNP, DL, SplitVT, {HiX, HiY});
 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, {LoV, HiV});
   }
-  return DAG.getNode(X86ISD::ANDNP, DL, VT, {X, Y});
+
+  if (TLI.isTypeLegal(VT))
+return DAG.getNode(X86ISD::ANDNP, DL, VT, {X, Y});
+
+  return SDValue();
 }
 
 // Try to widen AND, OR and XOR nodes to VT in order to remove casts around

diff  --git a/llvm/test/CodeGen/X86/combine-and.ll 
b/llvm/test/CodeGen/X86/combine-and.ll
index d223b75419ac47..294fcd6a9563eb 100644
--- a/llvm/test/CodeGen/X86/combine-and.ll
+++ b/llvm/test/CodeGen/X86/combine-and.ll
@@ -1171,6 +1171,25 @@ define <4 x i32> @neg_scalar_broadcast_two_uses(i32 %a0, 
<4 x i32> %a1, ptr %a2)
   ret <4 x i32> %4
 }
 
+; PR84660 - check for illegal types
+define <2 x i128> @neg_scalar_broadcast_illegaltype(i128 %arg) {
+; CHECK-LABEL: neg_scalar_broadcast_illegaltype:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:movq %rdi, %rax
+; CHECK-NEXT:notl %esi
+; CHECK-NEXT:andl $1, %esi
+; CHECK-NEXT:movq %rsi, 16(%rdi)
+; CHECK-NEXT:movq %rsi, (%rdi)
+; CHECK-NEXT:movq $0, 24(%rdi)
+; CHECK-NEXT:movq $0, 8(%rdi)
+; CHECK-NEXT:retq
+  %i = xor i128 %arg, 1
+  %i1 = insertelement <2 x i128> zeroinitializer, i128 %i, i64 0
+  %i2 = shufflevector <2 x i128> %i1, <2 x i128> zeroinitializer, <2 x i32> 
zeroinitializer
+  %i3 = and <2 x i128> , %i2
+  ret <2 x i128> %i3
+}
+
 define <2 x i64> @andnp_xx(<2 x i64> %v0) nounwind {
 ; SSE-LABEL: andnp_xx:
 ; SSE:   # %bb.0:



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[llvm-branch-commits] [llvm] release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes (PR #84698)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84698
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[llvm-branch-commits] [llvm] release/18.x: [DSE] Remove malloc from EarliestEscapeInfo before removing. (#84157) (PR #84946)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84946
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[llvm-branch-commits] [llvm] 39e3ba8 - [DSE] Remove malloc from EarliestEscapeInfo before removing. (#84157)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Florian Hahn
Date: 2024-03-12T22:28:32-07:00
New Revision: 39e3ba8a383e05af376d613594373c482f72bb3e

URL: 
https://github.com/llvm/llvm-project/commit/39e3ba8a383e05af376d613594373c482f72bb3e
DIFF: 
https://github.com/llvm/llvm-project/commit/39e3ba8a383e05af376d613594373c482f72bb3e.diff

LOG: [DSE] Remove malloc from EarliestEscapeInfo before removing. (#84157)

Not removing the malloc from earliest escape info leaves stale entries
in the cache.

Fixes https://github.com/llvm/llvm-project/issues/84051.

PR: https://github.com/llvm/llvm-project/pull/84157
(cherry picked from commit eb8f379567e8d014194faefe02ce92813e237afc)

Added: 

llvm/test/Transforms/DeadStoreElimination/malloc-earliest-escape-info-invalidation.ll

Modified: 
llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp 
b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
index 340fba4fb9c5a2..380d6583655367 100644
--- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
@@ -1907,15 +1907,15 @@ struct DSEState {
   Malloc->getArgOperand(0), IRB, TLI);
 if (!Calloc)
   return false;
+
 MemorySSAUpdater Updater();
 auto *NewAccess =
   Updater.createMemoryAccessAfter(cast(Calloc), nullptr,
   MallocDef);
 auto *NewAccessMD = cast(NewAccess);
 Updater.insertDef(NewAccessMD, /*RenameUses=*/true);
-Updater.removeMemoryAccess(Malloc);
 Malloc->replaceAllUsesWith(Calloc);
-Malloc->eraseFromParent();
+deleteDeadInstruction(Malloc);
 return true;
   }
 

diff  --git 
a/llvm/test/Transforms/DeadStoreElimination/malloc-earliest-escape-info-invalidation.ll
 
b/llvm/test/Transforms/DeadStoreElimination/malloc-earliest-escape-info-invalidation.ll
new file mode 100644
index 00..60a010cd49ceda
--- /dev/null
+++ 
b/llvm/test/Transforms/DeadStoreElimination/malloc-earliest-escape-info-invalidation.ll
@@ -0,0 +1,302 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt -p dse -S %s | FileCheck %s
+
+target datalayout = 
"E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
+
+define void @widget(ptr %a) {
+; CHECK-LABEL: define void @widget(
+; CHECK-SAME: ptr [[A:%.*]]) {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:[[CALL1:%.*]] = tail call noalias ptr @malloc(i64 0)
+; CHECK-NEXT:store ptr [[CALL1]], ptr [[A]], align 8
+; CHECK-NEXT:[[LOAD:%.*]] = load ptr, ptr [[A]], align 8
+; CHECK-NEXT:[[LOAD2:%.*]] = load i32, ptr [[LOAD]], align 8
+; CHECK-NEXT:[[GETELEMENTPTR:%.*]] = getelementptr i8, ptr [[CALL1]], i64 0
+; CHECK-NEXT:[[GETELEMENTPTR3:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR]], i64 1
+; CHECK-NEXT:[[GETELEMENTPTR4:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR]], i64 8
+; CHECK-NEXT:store i16 0, ptr [[GETELEMENTPTR4]], align 4
+; CHECK-NEXT:[[GETELEMENTPTR5:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR]], i64 12
+; CHECK-NEXT:store i32 0, ptr [[CALL1]], align 4
+; CHECK-NEXT:[[LOAD6:%.*]] = load i32, ptr inttoptr (i64 4 to ptr), align 4
+; CHECK-NEXT:br label [[BB48:%.*]]
+; CHECK:   bb7:
+; CHECK-NEXT:br label [[BB9:%.*]]
+; CHECK:   bb8:
+; CHECK-NEXT:br label [[BB53:%.*]]
+; CHECK:   bb9:
+; CHECK-NEXT:[[PHI:%.*]] = phi ptr [ [[CALL1]], [[BB7:%.*]] ], [ [[A]], 
[[BB43:%.*]] ]
+; CHECK-NEXT:[[GETELEMENTPTR10:%.*]] = getelementptr i8, ptr [[PHI]], i64 0
+; CHECK-NEXT:[[GETELEMENTPTR11:%.*]] = getelementptr i8, ptr [[PHI]], i64 0
+; CHECK-NEXT:[[GETELEMENTPTR12:%.*]] = getelementptr i8, ptr [[PHI]], i64 0
+; CHECK-NEXT:[[GETELEMENTPTR13:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR12]], i64 1
+; CHECK-NEXT:store i8 0, ptr [[CALL1]], align 1
+; CHECK-NEXT:br label [[BB29:%.*]]
+; CHECK:   bb14:
+; CHECK-NEXT:[[GETELEMENTPTR15:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR10]], i64 8
+; CHECK-NEXT:[[LOAD16:%.*]] = load i16, ptr [[CALL1]], align 4
+; CHECK-NEXT:br i1 false, label [[BB22:%.*]], label [[BB17:%.*]]
+; CHECK:   bb17:
+; CHECK-NEXT:[[GETELEMENTPTR18:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR11]], i64 8
+; CHECK-NEXT:[[LOAD19:%.*]] = load i16, ptr [[CALL1]], align 4
+; CHECK-NEXT:[[GETELEMENTPTR20:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR12]], i64 8
+; CHECK-NEXT:store i16 0, ptr [[CALL1]], align 4
+; CHECK-NEXT:[[GETELEMENTPTR21:%.*]] = getelementptr i8, ptr [[PHI]], i64 0
+; CHECK-NEXT:br label [[BB25:%.*]]
+; CHECK:   bb22:
+; CHECK-NEXT:[[GETELEMENTPTR23:%.*]] = getelementptr i8, ptr [[PHI]], i64 0
+; CHECK-NEXT:[[GETELEMENTPTR24:%.*]] = getelementptr i8, ptr 
[[GETELEMENTPTR23]], i64 12
+; CHECK-NEXT:br label [[BB25]]
+; CHECK:   bb25:
+; CHECK-NEXT:

[llvm-branch-commits] [llvm] Backport PR83993 to 18.x (PR #84298)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84298
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[llvm-branch-commits] [llvm] 3f8711f - [InstCombine] Fix miscompilation in PR83947 (#83993)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Yingwei Zheng
Date: 2024-03-12T22:05:53-07:00
New Revision: 3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d

URL: 
https://github.com/llvm/llvm-project/commit/3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d
DIFF: 
https://github.com/llvm/llvm-project/commit/3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d.diff

LOG: [InstCombine] Fix miscompilation in PR83947 (#83993)

https://github.com/llvm/llvm-project/blob/762f762504967efbe159db5c737154b989afc9bb/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp#L394-L407

Comment from @topperc:
> This transforms assumes the mask is a non-zero splat. We only know its
a splat and not provably all 0s. The mask is a constexpr that includes
the address of the global variable. We can't resolve the constant
expression to an exact value.

Fixes #83947.

Added: 
llvm/test/Transforms/InstCombine/pr83947.ll

Modified: 
llvm/include/llvm/Analysis/VectorUtils.h
llvm/lib/Analysis/VectorUtils.cpp
llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
llvm/test/Transforms/InstCombine/masked_intrinsics.ll

Removed: 




diff  --git a/llvm/include/llvm/Analysis/VectorUtils.h 
b/llvm/include/llvm/Analysis/VectorUtils.h
index 7a92e62b53c53d..c6eb66cc9660ca 100644
--- a/llvm/include/llvm/Analysis/VectorUtils.h
+++ b/llvm/include/llvm/Analysis/VectorUtils.h
@@ -406,6 +406,11 @@ bool maskIsAllZeroOrUndef(Value *Mask);
 /// lanes can be assumed active.
 bool maskIsAllOneOrUndef(Value *Mask);
 
+/// Given a mask vector of i1, Return true if any of the elements of this
+/// predicate mask are known to be true or undef.  That is, return true if at
+/// least one lane can be assumed active.
+bool maskContainsAllOneOrUndef(Value *Mask);
+
 /// Given a mask vector of the form , return an APInt (of bitwidth Y)
 /// for each lane which may be active.
 APInt possiblyDemandedEltsInMask(Value *Mask);

diff  --git a/llvm/lib/Analysis/VectorUtils.cpp 
b/llvm/lib/Analysis/VectorUtils.cpp
index 73facc76a92b2c..bf7bc0ba84a033 100644
--- a/llvm/lib/Analysis/VectorUtils.cpp
+++ b/llvm/lib/Analysis/VectorUtils.cpp
@@ -1012,6 +1012,31 @@ bool llvm::maskIsAllOneOrUndef(Value *Mask) {
   return true;
 }
 
+bool llvm::maskContainsAllOneOrUndef(Value *Mask) {
+  assert(isa(Mask->getType()) &&
+ isa(Mask->getType()->getScalarType()) &&
+ cast(Mask->getType()->getScalarType())->getBitWidth() ==
+ 1 &&
+ "Mask must be a vector of i1");
+
+  auto *ConstMask = dyn_cast(Mask);
+  if (!ConstMask)
+return false;
+  if (ConstMask->isAllOnesValue() || isa(ConstMask))
+return true;
+  if (isa(ConstMask->getType()))
+return false;
+  for (unsigned
+   I = 0,
+   E = cast(ConstMask->getType())->getNumElements();
+   I != E; ++I) {
+if (auto *MaskElt = ConstMask->getAggregateElement(I))
+  if (MaskElt->isAllOnesValue() || isa(MaskElt))
+return true;
+  }
+  return false;
+}
+
 /// TODO: This is a lot like known bits, but for
 /// vectors.  Is there something we can common this with?
 APInt llvm::possiblyDemandedEltsInMask(Value *Mask) {

diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index a647be2d26c761..bc43edb5e62065 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -412,11 +412,14 @@ Instruction 
*InstCombinerImpl::simplifyMaskedScatter(IntrinsicInst ) {
   if (auto *SplatPtr = getSplatValue(II.getArgOperand(1))) {
 // scatter(splat(value), splat(ptr), non-zero-mask) -> store value, ptr
 if (auto *SplatValue = getSplatValue(II.getArgOperand(0))) {
-  Align Alignment = 
cast(II.getArgOperand(2))->getAlignValue();
-  StoreInst *S =
-  new StoreInst(SplatValue, SplatPtr, /*IsVolatile=*/false, Alignment);
-  S->copyMetadata(II);
-  return S;
+  if (maskContainsAllOneOrUndef(ConstMask)) {
+Align Alignment =
+cast(II.getArgOperand(2))->getAlignValue();
+StoreInst *S = new StoreInst(SplatValue, SplatPtr, 
/*IsVolatile=*/false,
+ Alignment);
+S->copyMetadata(II);
+return S;
+  }
 }
 // scatter(vector, splat(ptr), splat(true)) -> store extract(vector,
 // lastlane), ptr

diff  --git a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll 
b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
index 2704905f7a358d..c87c1199f727ea 100644
--- a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
@@ -292,7 +292,11 @@ entry:
 define void @scatter_nxv4i16_uniform_vals_uniform_ptrs_all_active_mask(ptr 
%dst, i16 %val) {
 ; CHECK-LABEL: @scatter_nxv4i16_uniform_vals_uniform_ptrs_all_active_mask(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:store i16 [[VAL:%.*]], ptr [[DST:%.*]], align 2
+; CHECK-NEXT:

[llvm-branch-commits] [llvm] Backport PR83993 to 18.x (PR #84298)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/84298

>From 3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng 
Date: Tue, 5 Mar 2024 22:34:04 +0800
Subject: [PATCH] [InstCombine] Fix miscompilation in PR83947 (#83993)

https://github.com/llvm/llvm-project/blob/762f762504967efbe159db5c737154b989afc9bb/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp#L394-L407

Comment from @topperc:
> This transforms assumes the mask is a non-zero splat. We only know its
a splat and not provably all 0s. The mask is a constexpr that includes
the address of the global variable. We can't resolve the constant
expression to an exact value.

Fixes #83947.
---
 llvm/include/llvm/Analysis/VectorUtils.h  |  5 ++
 llvm/lib/Analysis/VectorUtils.cpp | 25 +++
 .../InstCombine/InstCombineCalls.cpp  | 13 ++--
 .../InstCombine/masked_intrinsics.ll  |  6 +-
 llvm/test/Transforms/InstCombine/pr83947.ll   | 67 +++
 5 files changed, 110 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/Transforms/InstCombine/pr83947.ll

diff --git a/llvm/include/llvm/Analysis/VectorUtils.h 
b/llvm/include/llvm/Analysis/VectorUtils.h
index 7a92e62b53c53d..c6eb66cc9660ca 100644
--- a/llvm/include/llvm/Analysis/VectorUtils.h
+++ b/llvm/include/llvm/Analysis/VectorUtils.h
@@ -406,6 +406,11 @@ bool maskIsAllZeroOrUndef(Value *Mask);
 /// lanes can be assumed active.
 bool maskIsAllOneOrUndef(Value *Mask);
 
+/// Given a mask vector of i1, Return true if any of the elements of this
+/// predicate mask are known to be true or undef.  That is, return true if at
+/// least one lane can be assumed active.
+bool maskContainsAllOneOrUndef(Value *Mask);
+
 /// Given a mask vector of the form , return an APInt (of bitwidth Y)
 /// for each lane which may be active.
 APInt possiblyDemandedEltsInMask(Value *Mask);
diff --git a/llvm/lib/Analysis/VectorUtils.cpp 
b/llvm/lib/Analysis/VectorUtils.cpp
index 73facc76a92b2c..bf7bc0ba84a033 100644
--- a/llvm/lib/Analysis/VectorUtils.cpp
+++ b/llvm/lib/Analysis/VectorUtils.cpp
@@ -1012,6 +1012,31 @@ bool llvm::maskIsAllOneOrUndef(Value *Mask) {
   return true;
 }
 
+bool llvm::maskContainsAllOneOrUndef(Value *Mask) {
+  assert(isa(Mask->getType()) &&
+ isa(Mask->getType()->getScalarType()) &&
+ cast(Mask->getType()->getScalarType())->getBitWidth() ==
+ 1 &&
+ "Mask must be a vector of i1");
+
+  auto *ConstMask = dyn_cast(Mask);
+  if (!ConstMask)
+return false;
+  if (ConstMask->isAllOnesValue() || isa(ConstMask))
+return true;
+  if (isa(ConstMask->getType()))
+return false;
+  for (unsigned
+   I = 0,
+   E = cast(ConstMask->getType())->getNumElements();
+   I != E; ++I) {
+if (auto *MaskElt = ConstMask->getAggregateElement(I))
+  if (MaskElt->isAllOnesValue() || isa(MaskElt))
+return true;
+  }
+  return false;
+}
+
 /// TODO: This is a lot like known bits, but for
 /// vectors.  Is there something we can common this with?
 APInt llvm::possiblyDemandedEltsInMask(Value *Mask) {
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index a647be2d26c761..bc43edb5e62065 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -412,11 +412,14 @@ Instruction 
*InstCombinerImpl::simplifyMaskedScatter(IntrinsicInst ) {
   if (auto *SplatPtr = getSplatValue(II.getArgOperand(1))) {
 // scatter(splat(value), splat(ptr), non-zero-mask) -> store value, ptr
 if (auto *SplatValue = getSplatValue(II.getArgOperand(0))) {
-  Align Alignment = 
cast(II.getArgOperand(2))->getAlignValue();
-  StoreInst *S =
-  new StoreInst(SplatValue, SplatPtr, /*IsVolatile=*/false, Alignment);
-  S->copyMetadata(II);
-  return S;
+  if (maskContainsAllOneOrUndef(ConstMask)) {
+Align Alignment =
+cast(II.getArgOperand(2))->getAlignValue();
+StoreInst *S = new StoreInst(SplatValue, SplatPtr, 
/*IsVolatile=*/false,
+ Alignment);
+S->copyMetadata(II);
+return S;
+  }
 }
 // scatter(vector, splat(ptr), splat(true)) -> store extract(vector,
 // lastlane), ptr
diff --git a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll 
b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
index 2704905f7a358d..c87c1199f727ea 100644
--- a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
@@ -292,7 +292,11 @@ entry:
 define void @scatter_nxv4i16_uniform_vals_uniform_ptrs_all_active_mask(ptr 
%dst, i16 %val) {
 ; CHECK-LABEL: @scatter_nxv4i16_uniform_vals_uniform_ptrs_all_active_mask(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:store i16 [[VAL:%.*]], ptr [[DST:%.*]], align 2
+; CHECK-NEXT:[[BROADCAST_SPLATINSERT:%.*]] = insertelement

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84715
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[llvm-branch-commits] [clang] a9ba36c - [Clang][LoongArch] Precommit test for fix wrong return value type of __iocsrrd_h. NFC

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: wanglei
Date: 2024-03-12T22:01:13-07:00
New Revision: a9ba36c7e7d7fa076f201843e3b826b6c6d7f5ef

URL: 
https://github.com/llvm/llvm-project/commit/a9ba36c7e7d7fa076f201843e3b826b6c6d7f5ef
DIFF: 
https://github.com/llvm/llvm-project/commit/a9ba36c7e7d7fa076f201843e3b826b6c6d7f5ef.diff

LOG: [Clang][LoongArch] Precommit test for fix wrong return value type of 
__iocsrrd_h. NFC

(cherry picked from commit aeda1a6e800e0dd6c91c0332b4db95094ad5b301)

Added: 


Modified: 
clang/test/CodeGen/LoongArch/intrinsic-la32.c
clang/test/CodeGen/LoongArch/intrinsic-la64.c

Removed: 




diff  --git a/clang/test/CodeGen/LoongArch/intrinsic-la32.c 
b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
index 93d54f511a9cd2..6a8d99880be399 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -169,8 +169,8 @@ unsigned int cpucfg(unsigned int a) {
 
 // LA32-LABEL: @rdtime(
 // LA32-NEXT:  entry:
-// LA32-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimeh.w $0, $1\0A\09", "=,="() #[[ATTR1:[0-9]+]], !srcloc !2
-// LA32-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimel.w $0, $1\0A\09", "=,="() #[[ATTR1]], !srcloc !3
+// LA32-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimeh.w $0, $1\0A\09", "=,="() #[[ATTR1:[0-9]+]], !srcloc 
[[META2:![0-9]+]]
+// LA32-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimel.w $0, $1\0A\09", "=,="() #[[ATTR1]], !srcloc [[META3:![0-9]+]]
 // LA32-NEXT:ret void
 //
 void rdtime() {
@@ -201,13 +201,28 @@ void loongarch_movgr2fcsr(int a) {
   __builtin_loongarch_movgr2fcsr(1, a);
 }
 
-// CHECK-LABEL: @cacop_w(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A:%.*]], 
i32 1024)
-// CHECK-NEXT:tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A]], i32 
1024)
-// CHECK-NEXT:ret void
+// LA32-LABEL: @cacop_w(
+// LA32-NEXT:  entry:
+// LA32-NEXT:tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A:%.*]], 
i32 1024)
+// LA32-NEXT:tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A]], i32 
1024)
+// LA32-NEXT:ret void
 //
 void cacop_w(unsigned long int a) {
   __cacop_w(1, a, 1024);
   __builtin_loongarch_cacop_w(1, a, 1024);
 }
+
+// LA32-LABEL: @iocsrrd_h_result(
+// LA32-NEXT:  entry:
+// LA32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A:%.*]])
+// LA32-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A]])
+// LA32-NEXT:[[CONV2:%.*]] = and i32 [[TMP0]], 255
+// LA32-NEXT:[[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
+// LA32-NEXT:[[CONV4:%.*]] = trunc i32 [[ADD]] to i16
+// LA32-NEXT:ret i16 [[CONV4]]
+//
+unsigned short iocsrrd_h_result(unsigned int a) {
+  unsigned short b = __iocsrrd_h(a);
+  unsigned short c = __builtin_loongarch_iocsrrd_h(a);
+  return b+c;
+}

diff  --git a/clang/test/CodeGen/LoongArch/intrinsic-la64.c 
b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
index a740882eef5411..48b6a7a3d22704 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -387,7 +387,7 @@ unsigned int cpucfg(unsigned int a) {
 
 // CHECK-LABEL: @rdtime_d(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect 
"rdtime.d $0, $1\0A\09", "=,="() #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect 
"rdtime.d $0, $1\0A\09", "=,="() #[[ATTR1:[0-9]+]], !srcloc 
[[META2:![0-9]+]]
 // CHECK-NEXT:ret void
 //
 void rdtime_d() {
@@ -396,8 +396,8 @@ void rdtime_d() {
 
 // CHECK-LABEL: @rdtime(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimeh.w $0, $1\0A\09", "=,="() #[[ATTR1]], !srcloc !3
-// CHECK-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimel.w $0, $1\0A\09", "=,="() #[[ATTR1]], !srcloc !4
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimeh.w $0, $1\0A\09", "=,="() #[[ATTR1]], !srcloc [[META3:![0-9]+]]
+// CHECK-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect 
"rdtimel.w $0, $1\0A\09", "=,="() #[[ATTR1]], !srcloc [[META4:![0-9]+]]
 // CHECK-NEXT:ret void
 //
 void rdtime() {
@@ -427,3 +427,18 @@ void loongarch_movgr2fcsr(int a) {
   __movgr2fcsr(1, a);
   __builtin_loongarch_movgr2fcsr(1, a);
 }
+
+// CHECK-LABEL: @iocsrrd_h_result(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A]])
+// CHECK-NEXT:[[CONV2:%.*]] = and i32 [[TMP0]], 255
+// CHECK-NEXT:[[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
+// CHECK-NEXT:[[CONV4:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK-NEXT:ret i16 [[CONV4]]
+//
+unsigned short

[llvm-branch-commits] [clang] 9b9aee1 - [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: wanglei
Date: 2024-03-12T22:01:13-07:00
New Revision: 9b9aee16d4dcf1b4af49988ebd7918fa4ce77e44

URL: 
https://github.com/llvm/llvm-project/commit/9b9aee16d4dcf1b4af49988ebd7918fa4ce77e44
DIFF: 
https://github.com/llvm/llvm-project/commit/9b9aee16d4dcf1b4af49988ebd7918fa4ce77e44.diff

LOG: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100)

relate:
https://gcc.gnu.org/pipermail/gcc-patches/2024-February/645016.html
(cherry picked from commit 2f479b811274fede36535e34ecb545ac22e399c3)

Added: 


Modified: 
clang/lib/Headers/larchintrin.h
clang/test/CodeGen/LoongArch/intrinsic-la32.c
clang/test/CodeGen/LoongArch/intrinsic-la64.c

Removed: 




diff  --git a/clang/lib/Headers/larchintrin.h b/clang/lib/Headers/larchintrin.h
index a613e5ca0e5ecd..f4218295919a0d 100644
--- a/clang/lib/Headers/larchintrin.h
+++ b/clang/lib/Headers/larchintrin.h
@@ -156,7 +156,7 @@ extern __inline unsigned char
   return (unsigned char)__builtin_loongarch_iocsrrd_b((unsigned int)_1);
 }
 
-extern __inline unsigned char
+extern __inline unsigned short
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 __iocsrrd_h(unsigned int _1) {
   return (unsigned short)__builtin_loongarch_iocsrrd_h((unsigned int)_1);

diff  --git a/clang/test/CodeGen/LoongArch/intrinsic-la32.c 
b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
index 6a8d99880be399..eb3f8cbe7ac4cc 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -215,11 +215,11 @@ void cacop_w(unsigned long int a) {
 // LA32-LABEL: @iocsrrd_h_result(
 // LA32-NEXT:  entry:
 // LA32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A:%.*]])
+// LA32-NEXT:[[CONV_I:%.*]] = trunc i32 [[TMP0]] to i16
 // LA32-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A]])
-// LA32-NEXT:[[CONV2:%.*]] = and i32 [[TMP0]], 255
-// LA32-NEXT:[[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
-// LA32-NEXT:[[CONV4:%.*]] = trunc i32 [[ADD]] to i16
-// LA32-NEXT:ret i16 [[CONV4]]
+// LA32-NEXT:[[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
+// LA32-NEXT:[[CONV3:%.*]] = add i16 [[TMP2]], [[CONV_I]]
+// LA32-NEXT:ret i16 [[CONV3]]
 //
 unsigned short iocsrrd_h_result(unsigned int a) {
   unsigned short b = __iocsrrd_h(a);

diff  --git a/clang/test/CodeGen/LoongArch/intrinsic-la64.c 
b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
index 48b6a7a3d22704..50ec358f546ec0 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -431,11 +431,11 @@ void loongarch_movgr2fcsr(int a) {
 // CHECK-LABEL: @iocsrrd_h_result(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A:%.*]])
+// CHECK-NEXT:[[CONV_I:%.*]] = trunc i32 [[TMP0]] to i16
 // CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 
[[A]])
-// CHECK-NEXT:[[CONV2:%.*]] = and i32 [[TMP0]], 255
-// CHECK-NEXT:[[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
-// CHECK-NEXT:[[CONV4:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK-NEXT:ret i16 [[CONV4]]
+// CHECK-NEXT:[[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
+// CHECK-NEXT:[[CONV3:%.*]] = add i16 [[TMP2]], [[CONV_I]]
+// CHECK-NEXT:ret i16 [[CONV3]]
 //
 unsigned short iocsrrd_h_result(unsigned int a) {
   unsigned short b = __iocsrrd_h(a);



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[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84716
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[llvm-branch-commits] [llvm] d77c5c3 - [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: wanglei
Date: 2024-03-12T21:55:37-07:00
New Revision: d77c5c3830d925b3795e2f1535a6568399fe6626

URL: 
https://github.com/llvm/llvm-project/commit/d77c5c3830d925b3795e2f1535a6568399fe6626
DIFF: 
https://github.com/llvm/llvm-project/commit/d77c5c3830d925b3795e2f1535a6568399fe6626.diff

LOG: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct 
`MSB` value (#84454)

The `MSB` must not be greater than `GRLen`. Without this patch, newly
added test cases will crash with LoongArch32, resulting in a 'cannot
select' error.

(cherry picked from commit edd4c6c6dca4c556de22b2ab73d5bfc02d28e59b)

Added: 


Modified: 
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/test/CodeGen/LoongArch/bstrins_w.ll

Removed: 




diff  --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index b161c5434ca13e..907aae13d6de0c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2343,7 +2343,9 @@ static SDValue performORCombine(SDNode *N, SelectionDAG 
,
 return DAG.getNode(
 LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
 DAG.getConstant(CN1->getSExtValue() >> MaskIdx0, DL, ValTy),
-DAG.getConstant((MaskIdx0 + MaskLen0 - 1), DL, GRLenVT),
+DAG.getConstant(ValBits == 32 ? (MaskIdx0 + (MaskLen0 & 31) - 1)
+  : (MaskIdx0 + MaskLen0 - 1),
+DL, GRLenVT),
 DAG.getConstant(MaskIdx0, DL, GRLenVT));
   }
 

diff  --git a/llvm/test/CodeGen/LoongArch/bstrins_w.ll 
b/llvm/test/CodeGen/LoongArch/bstrins_w.ll
index dfbe000841cdcb..e008caacad2a17 100644
--- a/llvm/test/CodeGen/LoongArch/bstrins_w.ll
+++ b/llvm/test/CodeGen/LoongArch/bstrins_w.ll
@@ -145,6 +145,19 @@ define i32 @pat5(i32 %a) nounwind {
   ret i32 %or
 }
 
+;; The high bits of `const` are zero.
+define i32 @pat5_high_zeros(i32 %a) nounwind {
+; CHECK-LABEL: pat5_high_zeros:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:lu12i.w $a1, 1
+; CHECK-NEXT:ori $a1, $a1, 564
+; CHECK-NEXT:bstrins.w $a0, $a1, 31, 16
+; CHECK-NEXT:ret
+  %and = and i32 %a, 65535  ; 0x
+  %or = or i32 %and, 305397760  ; 0x1234
+  ret i32 %or
+}
+
 ;; Pattern 6: a = b | ((c & mask) << shamt)
 ;; In this testcase b is 0x1002, but in fact we do not require b being a
 ;; constant. As long as all positions in b to be overwritten by the incoming



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[llvm-branch-commits] [clang] [analyzer] Backport deducing "this" crash fix (PR #84194)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84194
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[llvm-branch-commits] [clang] 1de8ea7 - [analyzer] Fix crash on dereference invalid return value of getAdjustedParameterIndex() (#83585)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Exile
Date: 2024-03-12T21:53:55-07:00
New Revision: 1de8ea75d9b309fd14e9f1be86ea5079d9a53d69

URL: 
https://github.com/llvm/llvm-project/commit/1de8ea75d9b309fd14e9f1be86ea5079d9a53d69
DIFF: 
https://github.com/llvm/llvm-project/commit/1de8ea75d9b309fd14e9f1be86ea5079d9a53d69.diff

LOG: [analyzer] Fix crash on dereference invalid return value of 
getAdjustedParameterIndex() (#83585)

Fixes #78810
Thanks for Snape3058 's comment

-

Co-authored-by: miaozhiyuan 
(cherry picked from commit d4687fe7d1639ea5d16190c89a54de1f2c6e2a9a)

Added: 


Modified: 
clang/lib/StaticAnalyzer/Core/CallEvent.cpp
clang/test/Analysis/cxx2b-deducing-this.cpp

Removed: 




diff  --git a/clang/lib/StaticAnalyzer/Core/CallEvent.cpp 
b/clang/lib/StaticAnalyzer/Core/CallEvent.cpp
index 0ac1d91b79beb5..bc14aea27f6736 100644
--- a/clang/lib/StaticAnalyzer/Core/CallEvent.cpp
+++ b/clang/lib/StaticAnalyzer/Core/CallEvent.cpp
@@ -1409,7 +1409,7 @@ CallEventManager::getSimpleCall(const CallExpr *CE, 
ProgramStateRef State,
   if (const auto *OpCE = dyn_cast(CE)) {
 const FunctionDecl *DirectCallee = OpCE->getDirectCallee();
 if (const auto *MD = dyn_cast(DirectCallee))
-  if (MD->isInstance())
+  if (MD->isImplicitObjectMemberFunction())
 return create(OpCE, State, LCtx, ElemRef);
 
   } else if (CE->getCallee()->getType()->isBlockPointerType()) {

diff  --git a/clang/test/Analysis/cxx2b-deducing-this.cpp 
b/clang/test/Analysis/cxx2b-deducing-this.cpp
index d22a897097bec0..2ec9e96bf0f84f 100644
--- a/clang/test/Analysis/cxx2b-deducing-this.cpp
+++ b/clang/test/Analysis/cxx2b-deducing-this.cpp
@@ -60,3 +60,14 @@ void top() {
   s.c();
   s.c(11);
 }
+
+
+struct S2 {
+  bool operator==(this auto, S2) {
+return true;
+  }
+};
+void use_deducing_this() {
+  int result = S2{} == S2{}; // no-crash
+  clang_analyzer_dump(result); // expected-warning {{1 S32b}}
+}



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[llvm-branch-commits] [clang] [analyzer] Backport deducing "this" crash fix (PR #84194)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/84194

>From 1de8ea75d9b309fd14e9f1be86ea5079d9a53d69 Mon Sep 17 00:00:00 2001
From: Exile <2094247...@qq.com>
Date: Thu, 7 Mar 2024 00:01:30 +0800
Subject: [PATCH] [analyzer] Fix crash on dereference invalid return value of
 getAdjustedParameterIndex() (#83585)

Fixes #78810
Thanks for Snape3058 's comment

-

Co-authored-by: miaozhiyuan 
(cherry picked from commit d4687fe7d1639ea5d16190c89a54de1f2c6e2a9a)
---
 clang/lib/StaticAnalyzer/Core/CallEvent.cpp |  2 +-
 clang/test/Analysis/cxx2b-deducing-this.cpp | 11 +++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/clang/lib/StaticAnalyzer/Core/CallEvent.cpp 
b/clang/lib/StaticAnalyzer/Core/CallEvent.cpp
index 0ac1d91b79beb5..bc14aea27f6736 100644
--- a/clang/lib/StaticAnalyzer/Core/CallEvent.cpp
+++ b/clang/lib/StaticAnalyzer/Core/CallEvent.cpp
@@ -1409,7 +1409,7 @@ CallEventManager::getSimpleCall(const CallExpr *CE, 
ProgramStateRef State,
   if (const auto *OpCE = dyn_cast(CE)) {
 const FunctionDecl *DirectCallee = OpCE->getDirectCallee();
 if (const auto *MD = dyn_cast(DirectCallee))
-  if (MD->isInstance())
+  if (MD->isImplicitObjectMemberFunction())
 return create(OpCE, State, LCtx, ElemRef);
 
   } else if (CE->getCallee()->getType()->isBlockPointerType()) {
diff --git a/clang/test/Analysis/cxx2b-deducing-this.cpp 
b/clang/test/Analysis/cxx2b-deducing-this.cpp
index d22a897097bec0..2ec9e96bf0f84f 100644
--- a/clang/test/Analysis/cxx2b-deducing-this.cpp
+++ b/clang/test/Analysis/cxx2b-deducing-this.cpp
@@ -60,3 +60,14 @@ void top() {
   s.c();
   s.c(11);
 }
+
+
+struct S2 {
+  bool operator==(this auto, S2) {
+return true;
+  }
+};
+void use_deducing_this() {
+  int result = S2{} == S2{}; // no-crash
+  clang_analyzer_dump(result); // expected-warning {{1 S32b}}
+}

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[llvm-branch-commits] [mlir] release/18.x: [mlir][NFC] Apply rule of five to *Pass classes (#80998) (PR #83971)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

> Do we have any ABI stability guarantees for LLVM C++ APIs? I would think that 
> a lot of back ports can break the C++ ABI of LLVM in general?

Yes, we always try to keep the C++ API stable in point releases.

https://github.com/llvm/llvm-project/pull/83971
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Enable availability based on the compiler instead of __has_extension (#84065) (PR #84374)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84374
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[llvm-branch-commits] [libcxx] c14bf0a - [libc++] Enable availability based on the compiler instead of __has_extension (#84065)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Louis Dionne
Date: 2024-03-12T18:38:24-07:00
New Revision: c14bf0a13d426b0b8fc2bc395bf450d9a6982fe3

URL: 
https://github.com/llvm/llvm-project/commit/c14bf0a13d426b0b8fc2bc395bf450d9a6982fe3
DIFF: 
https://github.com/llvm/llvm-project/commit/c14bf0a13d426b0b8fc2bc395bf450d9a6982fe3.diff

LOG: [libc++] Enable availability based on the compiler instead of 
__has_extension (#84065)

__has_extension(...) doesn't work as intended when -pedantic-errors is
used with Clang. With that flag, __has_extension(...) is equivalent to
__has_feature(...), which means that checks like

__has_extension(pragma_clang_attribute_external_declaration)

will return 0. In turn, this has the effect of disabling availability
markup in libc++, which is undesirable.

rdar://124078119
(cherry picked from commit 292a28df6c55679fad0589dea35278a8c66b2ae1)

Added: 

libcxx/test/libcxx/vendor/apple/availability-with-pedantic-errors.compile.pass.cpp

Modified: 
libcxx/include/__availability

Removed: 




diff  --git a/libcxx/include/__availability b/libcxx/include/__availability
index c5069a027750ec..b8b2da9bb12265 100644
--- a/libcxx/include/__availability
+++ b/libcxx/include/__availability
@@ -72,11 +72,10 @@
 #  endif
 #endif
 
-// Availability markup is disabled when building the library, or when the 
compiler
+// Availability markup is disabled when building the library, or when a 
non-Clang
+// compiler is used because only Clang supports the necessary attributes.
 // doesn't support the proper attributes.
-#if defined(_LIBCPP_BUILDING_LIBRARY) || defined(_LIBCXXABI_BUILDING_LIBRARY) 
||   \
-!__has_feature(attribute_availability_with_strict) || 
!__has_feature(attribute_availability_in_templates) ||   \
-!__has_extension(pragma_clang_attribute_external_declaration)
+#if defined(_LIBCPP_BUILDING_LIBRARY) || defined(_LIBCXXABI_BUILDING_LIBRARY) 
|| !defined(_LIBCPP_COMPILER_CLANG_BASED)
 #  if !defined(_LIBCPP_HAS_NO_VENDOR_AVAILABILITY_ANNOTATIONS)
 #define _LIBCPP_HAS_NO_VENDOR_AVAILABILITY_ANNOTATIONS
 #  endif

diff  --git 
a/libcxx/test/libcxx/vendor/apple/availability-with-pedantic-errors.compile.pass.cpp
 
b/libcxx/test/libcxx/vendor/apple/availability-with-pedantic-errors.compile.pass.cpp
new file mode 100644
index 00..c55a0a4d6e5d1b
--- /dev/null
+++ 
b/libcxx/test/libcxx/vendor/apple/availability-with-pedantic-errors.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// REQUIRES: stdlib=apple-libc++
+
+// Test that using -pedantic-errors doesn't turn off availability annotations.
+// This used to be the case because we used __has_extension(...) to enable the
+// availability annotations, and -pedantic-errors changes the behavior of
+// __has_extension(...) in an incompatible way.
+
+// ADDITIONAL_COMPILE_FLAGS: -pedantic-errors
+
+#include <__availability>
+
+#if defined(_LIBCPP_HAS_NO_VENDOR_AVAILABILITY_ANNOTATIONS)
+#  error Availability annotations should be enabled on Apple platforms in the 
system configuration!
+#endif



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[llvm-branch-commits] [llvm] Backport #83980 to 18.x (PR #84023)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

Merged: 55193c2ba53f4156481b63b5956eaadd8edb0877

https://github.com/llvm/llvm-project/pull/84023
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[llvm-branch-commits] [llvm] Backport #83980 to 18.x (PR #84023)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84023
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[llvm-branch-commits] [llvm] 55193c2 - [InstCombine] Handle scalable splat in `getFlippedStrictnessPredicateAndConstant`

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Yingwei Zheng
Date: 2024-03-12T18:19:15-07:00
New Revision: 55193c2ba53f4156481b63b5956eaadd8edb0877

URL: 
https://github.com/llvm/llvm-project/commit/55193c2ba53f4156481b63b5956eaadd8edb0877
DIFF: 
https://github.com/llvm/llvm-project/commit/55193c2ba53f4156481b63b5956eaadd8edb0877.diff

LOG: [InstCombine] Handle scalable splat in 
`getFlippedStrictnessPredicateAndConstant`

(cherry picked from commit d51fcd4ed86ac6075c8a25b053c2b66051feaf62)

Added: 
llvm/test/Transforms/InstCombine/pr83931.ll

Modified: 
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/test/Transforms/InstCombine/select.ll
llvm/test/Transforms/InstCombine/vscale_cmp.ll

Removed: 




diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 8c0fd662255130..9973a80a7db946 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -6491,6 +6491,13 @@ 
InstCombiner::getFlippedStrictnessPredicateAndConstant(CmpInst::Predicate Pred,
   if (!SafeReplacementConstant)
 SafeReplacementConstant = CI;
 }
+  } else if (isa(C->getType())) {
+// Handle scalable splat
+Value *SplatC = C->getSplatValue();
+auto *CI = dyn_cast_or_null(SplatC);
+// Bail out if the constant can't be safely incremented/decremented.
+if (!CI || !ConstantIsOk(CI))
+  return std::nullopt;
   } else {
 // ConstantExpr?
 return std::nullopt;

diff  --git a/llvm/test/Transforms/InstCombine/pr83931.ll 
b/llvm/test/Transforms/InstCombine/pr83931.ll
new file mode 100644
index 00..d36ac8d91abd30
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/pr83931.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+define  @dont_crash( %x) {
+; CHECK-LABEL: define  @dont_crash(
+; CHECK-SAME:  [[X:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[RET:%.*]] = icmp sgt  [[X]], 
shufflevector ( insertelement ( poison, i64 
-309383, i64 0),  poison,  zeroinitializer)
+; CHECK-NEXT:ret  [[RET]]
+;
+entry:
+  %div = sdiv  %x, splat (i64 309383)
+  %ret = icmp sge  %div, zeroinitializer
+  ret  %ret
+}

diff  --git a/llvm/test/Transforms/InstCombine/select.ll 
b/llvm/test/Transforms/InstCombine/select.ll
index b7e743c14a52ca..888e7d28f78afb 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -3459,7 +3459,7 @@ define  @scalable_sign_bits( %x) {
 define  @scalable_non_zero( %x) {
 ; CHECK-LABEL: @scalable_non_zero(
 ; CHECK-NEXT:[[A:%.*]] = or  [[X:%.*]], shufflevector 
( insertelement ( poison, i32 1, i32 0), 
 poison,  zeroinitializer)
-; CHECK-NEXT:[[CMP:%.*]] = icmp ule  [[A]], 
shufflevector ( insertelement ( poison, i32 
56, i64 0),  poison,  zeroinitializer)
+; CHECK-NEXT:[[CMP:%.*]] = icmp ult  [[A]], 
shufflevector ( insertelement ( poison, i32 
57, i64 0),  poison,  zeroinitializer)
 ; CHECK-NEXT:ret  [[CMP]]
 ;
   %a = or  %x, shufflevector ( 
insertelement ( poison, i32 1, i32 0),  
poison,  zeroinitializer)

diff  --git a/llvm/test/Transforms/InstCombine/vscale_cmp.ll 
b/llvm/test/Transforms/InstCombine/vscale_cmp.ll
index a7f8368c5d62c8..b2bfc93da089fc 100644
--- a/llvm/test/Transforms/InstCombine/vscale_cmp.ll
+++ b/llvm/test/Transforms/InstCombine/vscale_cmp.ll
@@ -3,7 +3,7 @@
 
 define  @sge( %x) {
 ; CHECK-LABEL: @sge(
-; CHECK-NEXT:[[CMP:%.*]] = icmp sge  [[X:%.*]], 
zeroinitializer
+; CHECK-NEXT:[[CMP:%.*]] = icmp sgt  [[X:%.*]], 
shufflevector ( insertelement ( poison, i8 
-1, i64 0),  poison,  zeroinitializer)
 ; CHECK-NEXT:ret  [[CMP]]
 ;
   %cmp = icmp sge  %x, zeroinitializer



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[llvm-branch-commits] [llvm] Lld mac fix (PR #84764)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/84764

>From 2ddb32b50752ca91ca9946cb9c9ea3d92c8616d0 Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Sat, 9 Mar 2024 14:26:47 -0800
Subject: [PATCH 1/3] Bump version to 18.1.2

---
 llvm/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index ddf95cbc6c5175..c5fa66390bba8d 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 1)
+  set(LLVM_VERSION_PATCH 2)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX)

>From 9edcbcbb219c221521894b04e668b6f9f450497f Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Mon, 11 Mar 2024 07:28:58 -0700
Subject: [PATCH 2/3] workflows: Add workaround for lld failures on MacOS

See #81967
---
 .github/workflows/llvm-project-tests.yml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/.github/workflows/llvm-project-tests.yml 
b/.github/workflows/llvm-project-tests.yml
index 43b90193406fc9..64788457fb6d60 100644
--- a/.github/workflows/llvm-project-tests.yml
+++ b/.github/workflows/llvm-project-tests.yml
@@ -118,6 +118,11 @@ jobs:
   else
 builddir="$(pwd)"/build
   fi
+  if [ "${{ runner.os }}" == "MacOS" ]; then
+# Workaround test failure on some lld tests on MacOS
+# https://github.com/llvm/llvm-project/issues/81967
+extra_cmake_args="-DLLVM_DISABLE_ASSEMBLY_FILES=ON"
+  fi
   echo "llvm-builddir=$builddir" >> "$GITHUB_OUTPUT"
   cmake -G Ninja \
 -B "$builddir" \

>From 7039f4f84d8046f6148247c3d11c9b4fee0fd813 Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Tue, 12 Mar 2024 17:50:11 -0700
Subject: [PATCH 3/3] Fix os name

---
 .github/workflows/llvm-project-tests.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/llvm-project-tests.yml 
b/.github/workflows/llvm-project-tests.yml
index 64788457fb6d60..a52dd2db8035dd 100644
--- a/.github/workflows/llvm-project-tests.yml
+++ b/.github/workflows/llvm-project-tests.yml
@@ -118,7 +118,7 @@ jobs:
   else
 builddir="$(pwd)"/build
   fi
-  if [ "${{ runner.os }}" == "MacOS" ]; then
+  if [ "${{ runner.os }}" == "macOS" ]; then
 # Workaround test failure on some lld tests on MacOS
 # https://github.com/llvm/llvm-project/issues/81967
 extra_cmake_args="-DLLVM_DISABLE_ASSEMBLY_FILES=ON"

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[llvm-branch-commits] [lld] 78859f1 - [lld][LoongArch] Support the R_LARCH_{ADD, SUB}_ULEB128 relocation types (#81133)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Jinyang He
Date: 2024-03-12T17:44:48-07:00
New Revision: 78859f118a6b4c7b06c543c7794c59befdc78924

URL: 
https://github.com/llvm/llvm-project/commit/78859f118a6b4c7b06c543c7794c59befdc78924
DIFF: 
https://github.com/llvm/llvm-project/commit/78859f118a6b4c7b06c543c7794c59befdc78924.diff

LOG: [lld][LoongArch] Support the R_LARCH_{ADD,SUB}_ULEB128 relocation types 
(#81133)

For a label difference like `.uleb128 A-B`, MC generates a pair of
R_LARCH_{ADD,SUB}_ULEB128 if A-B cannot be folded as a constant. GNU
assembler generates a pair of relocations in more cases (when A or B is
in a code section with linker relaxation). It is similar to RISCV.

R_LARCH_{ADD,SUB}_ULEB128 relocations are created by Clang and GCC in
`.gcc_except_table` and other debug sections with linker relaxation
enabled. On LoongArch, first read the buf and count the available space.
Then add or sub the value. Finally truncate the expected value and fill
it into the available space.

(cherry picked from commit eaa9ef678c63bf392ec2d5b736605db7ea7e7338)

Added: 
lld/test/ELF/loongarch-reloc-leb128.s

Modified: 
lld/ELF/Arch/LoongArch.cpp

Removed: 




diff  --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index 1dab98115d9dea..8a6f6db68f2909 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -11,6 +11,7 @@
 #include "Symbols.h"
 #include "SyntheticSections.h"
 #include "Target.h"
+#include "llvm/Support/LEB128.h"
 
 using namespace llvm;
 using namespace llvm::object;
@@ -155,6 +156,16 @@ static bool isJirl(uint32_t insn) {
   return (insn & 0xfc00) == JIRL;
 }
 
+static void handleUleb128(uint8_t *loc, uint64_t val) {
+  const uint32_t maxcount = 1 + 64 / 7;
+  uint32_t count;
+  uint64_t orig = decodeULEB128(loc, );
+  if (count > maxcount)
+errorOrWarn(getErrorLocation(loc) + "extra space for uleb128");
+  uint64_t mask = count < maxcount ? (1ULL << 7 * count) - 1 : -1ULL;
+  encodeULEB128((orig + val) & mask, loc, count);
+}
+
 LoongArch::LoongArch() {
   // The LoongArch ISA itself does not have a limit on page sizes. According to
   // the ISA manual, the PS (page size) field in MTLB entries and CSR.STLBPS is
@@ -396,11 +407,13 @@ RelExpr LoongArch::getRelExpr(const RelType type, const 
Symbol ,
   case R_LARCH_ADD16:
   case R_LARCH_ADD32:
   case R_LARCH_ADD64:
+  case R_LARCH_ADD_ULEB128:
   case R_LARCH_SUB6:
   case R_LARCH_SUB8:
   case R_LARCH_SUB16:
   case R_LARCH_SUB32:
   case R_LARCH_SUB64:
+  case R_LARCH_SUB_ULEB128:
 // The LoongArch add/sub relocs behave like the RISCV counterparts; reuse
 // the RelExpr to avoid code duplication.
 return R_RISCV_ADD;
@@ -635,6 +648,9 @@ void LoongArch::relocate(uint8_t *loc, const Relocation 
,
   case R_LARCH_ADD64:
 write64le(loc, read64le(loc) + val);
 return;
+  case R_LARCH_ADD_ULEB128:
+handleUleb128(loc, val);
+return;
   case R_LARCH_SUB6:
 *loc = (*loc & 0xc0) | ((*loc - val) & 0x3f);
 return;
@@ -650,6 +666,9 @@ void LoongArch::relocate(uint8_t *loc, const Relocation 
,
   case R_LARCH_SUB64:
 write64le(loc, read64le(loc) - val);
 return;
+  case R_LARCH_SUB_ULEB128:
+handleUleb128(loc, -val);
+return;
 
   case R_LARCH_MARK_LA:
   case R_LARCH_MARK_PCREL:

diff  --git a/lld/test/ELF/loongarch-reloc-leb128.s 
b/lld/test/ELF/loongarch-reloc-leb128.s
new file mode 100644
index 00..9e6f221e62b639
--- /dev/null
+++ b/lld/test/ELF/loongarch-reloc-leb128.s
@@ -0,0 +1,102 @@
+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t && cd %t
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax a.s -o a.o
+# RUN: llvm-readobj -r -x .gcc_except_table -x .debug_rnglists -x 
.debug_loclists a.o | FileCheck %s --check-prefix=REL
+# RUN: ld.lld -shared --gc-sections a.o -o a.so
+# RUN: llvm-readelf -x .gcc_except_table -x .debug_rnglists -x .debug_loclists 
a.so | FileCheck %s
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32 --mattr=+relax a.s -o a32.o
+# RUN: llvm-readobj -r -x .gcc_except_table -x .debug_rnglists -x 
.debug_loclists a32.o | FileCheck %s --check-prefix=REL
+# RUN: ld.lld -shared --gc-sections a32.o -o a32.so
+# RUN: llvm-readelf -x .gcc_except_table -x .debug_rnglists -x .debug_loclists 
a32.so | FileCheck %s
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32 --mattr=+relax extraspace.s 
-o extraspace32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax extraspace.s 
-o extraspace64.o
+# RUN: not ld.lld -shared extraspace32.o 2>&1 | FileCheck %s 
--check-prefix=ERROR
+# RUN: not ld.lld -shared extraspace64.o 2>&1 | FileCheck %s 
--check-prefix=ERROR
+# ERROR: error: extraspace{{.*}}.o:(.rodata+0x0): extra space for uleb128
+
+#--- a.s
+.cfi_startproc
+.cfi_lsda 0x1b,.LLSDA0
+.cfi_endproc
+
+.section .text.w,"axR"
+break 0; break 0; break 0; w1:
+  .p2align 4# 4 bytes after relaxation
+w2: break 0
+
+.section

[llvm-branch-commits] [mlir] release/18.x: [mlir][NFC] Apply rule of five to *Pass classes (#80998) (PR #83971)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

I don't think we have tracked MLIR library ABI for previous releases, but I 
think this will change the ABI.  Do we have a policy on this for MLIR?

https://github.com/llvm/llvm-project/pull/83971
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[llvm-branch-commits] [clang] Backport d23ef9e to release/18.x (PR #83911)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83911
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[llvm-branch-commits] [clang] Backport d23ef9e to release/18.x (PR #83911)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

Merged: d8352e93c1c8042d9166eab3d76d6c07ef585b6d

https://github.com/llvm/llvm-project/pull/83911
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[llvm-branch-commits] [clang] Backport d23ef9e to release/18.x (PR #83911)

2024-03-12 Thread Tom Stellard via llvm-branch-commits

https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/83911

>From 74fa05dead4d52eef3c33406d05dd1bbaf10d546 Mon Sep 17 00:00:00 2001
From: Sirraide 
Date: Tue, 27 Feb 2024 20:19:44 +0100
Subject: [PATCH] [Clang] [Sema] Handle placeholders in '.*' expressions
 (#83103)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When analysing whether we should handle a binary expression as an
overloaded operator call or a builtin operator, we were calling
`checkPlaceholderForOverload()`, which takes care of any placeholders
that are not overload sets—which would usually make sense since those
need to be handled as part of overload resolution.

Unfortunately, we were also doing that for `.*`, which is not
overloadable, and then proceeding to create a builtin operator anyway,
which would crash if the RHS happened to be an unresolved overload set
(due hitting an assertion in `CreateBuiltinBinOp()`—specifically, in one
of its callees—in the `.*` case that makes sure its arguments aren’t
placeholders).

This pr instead makes it so we check for *all* placeholders early if the
operator is `.*`.

It’s worth noting that,
1. In the `.*` case, we now additionally also check for *any*
placeholders (not just non-overload-sets) in the LHS; this shouldn’t
make a difference, however—at least I couldn’t think of a way to trigger
the assertion with an overload set as the LHS of `.*`; it is worth
noting that the assertion in question would also complain if the LHS
happened to be of placeholder type, though.
2. There is another case in which we also don’t perform overload
resolution—namely `=` if the LHS is not of class or enumeration type
after handling non-overload-set placeholders—as in the `.*` case, but
similarly to 1., I first couldn’t think of a way of getting this case to
crash, and secondly, `CreateBuiltinBinOp()` doesn’t seem to care about
placeholders in the LHS or RHS in the `=` case (from what I can tell,
it, or rather one of its callees, only checks that the LHS is not a
pseudo-object type, but those will have already been handled by the call
to `checkPlaceholderForOverload()` by the time we get to this function),
so I don’t think this case suffers from the same problem.

This fixes #53815.

-

Co-authored-by: Aaron Ballman 
---
 clang/docs/ReleaseNotes.rst |  2 ++
 clang/lib/Sema/SemaOverload.cpp | 22 +-
 clang/test/SemaCXX/gh53815.cpp  | 21 +
 3 files changed, 40 insertions(+), 5 deletions(-)
 create mode 100644 clang/test/SemaCXX/gh53815.cpp

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..101b3a54b9af24 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1103,6 +1103,8 @@ Bug Fixes to C++ Support
   (`#82258 `_)
 - Correctly immediate-escalate lambda conversion functions.
   (`#82258 `_)
+- Fix a crash when an unresolved overload set is encountered on the RHS of a 
``.*`` operator.
+  (`#53815 `_)

 Bug Fixes to AST Handling
 ^
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 940bcccb9e261b..b708272ebe7d87 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -14470,6 +14470,23 @@ ExprResult Sema::CreateOverloadedBinOp(SourceLocation 
OpLoc,
CurFPFeatureOverrides());
   }

+  // If this is the .* operator, which is not overloadable, just
+  // create a built-in binary operator.
+  if (Opc == BO_PtrMemD) {
+auto CheckPlaceholder = [&](Expr *) {
+  ExprResult Res = CheckPlaceholderExpr(Arg);
+  if (Res.isUsable())
+Arg = Res.get();
+  return !Res.isUsable();
+};
+
+// CreateBuiltinBinOp() doesn't like it if we tell it to create a '.*'
+// expression that contains placeholders (in either the LHS or RHS).
+if (CheckPlaceholder(Args[0]) || CheckPlaceholder(Args[1]))
+  return ExprError();
+return CreateBuiltinBinOp(OpLoc, Opc, Args[0], Args[1]);
+  }
+
   // Always do placeholder-like conversions on the RHS.
   if (checkPlaceholderForOverload(*this, Args[1]))
 return ExprError();
@@ -14489,11 +14506,6 @@ ExprResult Sema::CreateOverloadedBinOp(SourceLocation 
OpLoc,
   if (Opc == BO_Assign && !Args[0]->getType()->isOverloadableType())
 return CreateBuiltinBinOp(OpLoc, Opc, Args[0], Args[1]);

-  // If this is the .* operator, which is not overloadable, just
-  // create a built-in binary operator.
-  if (Opc == BO_PtrMemD)
-return CreateBuiltinBinOp(OpLoc, Opc, Args[0], Args[1]);
-
   // Build the overload set.
   OverloadCandidateSet CandidateSet(OpLoc, OverloadCandidateSet::CSK_Operator,
 OverloadCandidateSet::OperatorRewriteInfo(
diff --git

[llvm-branch-commits] [clang] d8352e9 - [Clang] [Sema] Handle placeholders in '.*' expressions (#83103)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Sirraide
Date: 2024-03-12T17:38:40-07:00
New Revision: d8352e93c1c8042d9166eab3d76d6c07ef585b6d

URL: 
https://github.com/llvm/llvm-project/commit/d8352e93c1c8042d9166eab3d76d6c07ef585b6d
DIFF: 
https://github.com/llvm/llvm-project/commit/d8352e93c1c8042d9166eab3d76d6c07ef585b6d.diff

LOG: [Clang] [Sema] Handle placeholders in '.*' expressions (#83103)

When analysing whether we should handle a binary expression as an
overloaded operator call or a builtin operator, we were calling
`checkPlaceholderForOverload()`, which takes care of any placeholders
that are not overload sets—which would usually make sense since those
need to be handled as part of overload resolution.

Unfortunately, we were also doing that for `.*`, which is not
overloadable, and then proceeding to create a builtin operator anyway,
which would crash if the RHS happened to be an unresolved overload set
(due hitting an assertion in `CreateBuiltinBinOp()`—specifically, in one
of its callees—in the `.*` case that makes sure its arguments aren’t
placeholders).

This pr instead makes it so we check for *all* placeholders early if the
operator is `.*`.

It’s worth noting that,
1. In the `.*` case, we now additionally also check for *any*
placeholders (not just non-overload-sets) in the LHS; this shouldn’t
make a difference, however—at least I couldn’t think of a way to trigger
the assertion with an overload set as the LHS of `.*`; it is worth
noting that the assertion in question would also complain if the LHS
happened to be of placeholder type, though.
2. There is another case in which we also don’t perform overload
resolution—namely `=` if the LHS is not of class or enumeration type
after handling non-overload-set placeholders—as in the `.*` case, but
similarly to 1., I first couldn’t think of a way of getting this case to
crash, and secondly, `CreateBuiltinBinOp()` doesn’t seem to care about
placeholders in the LHS or RHS in the `=` case (from what I can tell,
it, or rather one of its callees, only checks that the LHS is not a
pseudo-object type, but those will have already been handled by the call
to `checkPlaceholderForOverload()` by the time we get to this function),
so I don’t think this case suffers from the same problem.

This fixes #53815.

-

Co-authored-by: Aaron Ballman 

Added: 
clang/test/SemaCXX/gh53815.cpp

Modified: 
clang/docs/ReleaseNotes.rst
clang/lib/Sema/SemaOverload.cpp

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..101b3a54b9af24 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1103,6 +1103,8 @@ Bug Fixes to C++ Support
   (`#82258 `_)
 - Correctly immediate-escalate lambda conversion functions.
   (`#82258 `_)
+- Fix a crash when an unresolved overload set is encountered on the RHS of a 
``.*`` operator.
+  (`#53815 `_)
 
 Bug Fixes to AST Handling
 ^

diff  --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 940bcccb9e261b..b708272ebe7d87 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -14470,6 +14470,23 @@ ExprResult Sema::CreateOverloadedBinOp(SourceLocation 
OpLoc,
CurFPFeatureOverrides());
   }
 
+  // If this is the .* operator, which is not overloadable, just
+  // create a built-in binary operator.
+  if (Opc == BO_PtrMemD) {
+auto CheckPlaceholder = [&](Expr *) {
+  ExprResult Res = CheckPlaceholderExpr(Arg);
+  if (Res.isUsable())
+Arg = Res.get();
+  return !Res.isUsable();
+};
+
+// CreateBuiltinBinOp() doesn't like it if we tell it to create a '.*'
+// expression that contains placeholders (in either the LHS or RHS).
+if (CheckPlaceholder(Args[0]) || CheckPlaceholder(Args[1]))
+  return ExprError();
+return CreateBuiltinBinOp(OpLoc, Opc, Args[0], Args[1]);
+  }
+
   // Always do placeholder-like conversions on the RHS.
   if (checkPlaceholderForOverload(*this, Args[1]))
 return ExprError();
@@ -14489,11 +14506,6 @@ ExprResult Sema::CreateOverloadedBinOp(SourceLocation 
OpLoc,
   if (Opc == BO_Assign && !Args[0]->getType()->isOverloadableType())
 return CreateBuiltinBinOp(OpLoc, Opc, Args[0], Args[1]);
 
-  // If this is the .* operator, which is not overloadable, just
-  // create a built-in binary operator.
-  if (Opc == BO_PtrMemD)
-return CreateBuiltinBinOp(OpLoc, Opc, Args[0], Args[1]);
-
   // Build the overload set.
   OverloadCandidateSet CandidateSet(OpLoc, OverloadCandidateSet::CSK_Operator,
 OverloadCandidateSet::OperatorRewriteInfo(

diff  --git a/clang/test/SemaCXX/gh53815.cpp b/clang/test/SemaCXX/gh53815.cpp
new file

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Fix crash when unrolling loop containing vector instructions (#83384) (PR #83744)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83744
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[llvm-branch-commits] [llvm] eb9bc02 - [RISCV] Fix crash when unrolling loop containing vector instructions (#83384)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Shih-Po Hung
Date: 2024-03-12T17:28:17-07:00
New Revision: eb9bc02b06cb07ffdd4c5ee55d6b6b591d78656f

URL: 
https://github.com/llvm/llvm-project/commit/eb9bc02b06cb07ffdd4c5ee55d6b6b591d78656f
DIFF: 
https://github.com/llvm/llvm-project/commit/eb9bc02b06cb07ffdd4c5ee55d6b6b591d78656f.diff

LOG: [RISCV] Fix crash when unrolling loop containing vector instructions 
(#83384)

When MVT is not a vector type, TCK_CodeSize should return an invalid
cost. This patch adds a check in the beginning to make sure all cost
kinds return invalid costs consistently.

Before this patch, TCK_CodeSize returns a valid cost on scalar MVT but
other cost kinds doesn't.

This fixes the issue #83294 where a loop contains vector instructions
and MVT is scalar after type legalization when the vector extension is
not enabled,

(cherry picked from commit fb67dce1cb87e279593c27bd4122fe63bad75f04)

Added: 
llvm/test/Analysis/CostModel/RISCV/vector-cost-without-v.ll

Modified: 
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 866d5cf340e68b..66dab70d455ff4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -37,6 +37,9 @@ static cl::opt SLPMaxVF(
 InstructionCost
 RISCVTTIImpl::getRISCVInstructionCost(ArrayRef OpCodes, MVT VT,
   TTI::TargetCostKind CostKind) {
+  // Check if the type is valid for all CostKind
+  if (!VT.isVector())
+return InstructionCost::getInvalid();
   size_t NumInstr = OpCodes.size();
   if (CostKind == TTI::TCK_CodeSize)
 return NumInstr;

diff  --git a/llvm/test/Analysis/CostModel/RISCV/vector-cost-without-v.ll 
b/llvm/test/Analysis/CostModel/RISCV/vector-cost-without-v.ll
new file mode 100644
index 00..cd99065f0285cd
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/RISCV/vector-cost-without-v.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt < %s -mtriple=riscv64 -mattr=+f,+d --passes=loop-unroll-full -S | 
FileCheck %s
+
+; Check it doesn't crash when the vector extension is not enabled.
+define void @foo() {
+; CHECK-LABEL: define void @foo(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:br label [[FOR_BODY:%.*]]
+; CHECK:   for.body:
+; CHECK-NEXT:[[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], 
[[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:[[TMP0:%.*]] = load float, ptr null, align 4
+; CHECK-NEXT:[[SPLAT_SPLAT_I_I_I:%.*]] = shufflevector <2 x float> 
zeroinitializer, <2 x float> zeroinitializer, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[CMP1_I_I_I:%.*]] = fcmp ogt <2 x float> zeroinitializer, 
zeroinitializer
+; CHECK-NEXT:[[SPLAT_SPLAT3_I_I_I:%.*]] = shufflevector <2 x i32> 
zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[XOR3_I_I_I_I_I:%.*]] = select <2 x i1> zeroinitializer, <2 
x i32> zeroinitializer, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[TMP1:%.*]] = load float, ptr null, align 4
+; CHECK-NEXT:[[SPLAT_SPLAT8_I_I_I:%.*]] = shufflevector <2 x float> 
zeroinitializer, <2 x float> zeroinitializer, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[SUB_I_I_I:%.*]] = fsub <2 x float> zeroinitializer, 
zeroinitializer
+; CHECK-NEXT:[[MUL_I_I_I:%.*]] = shl i64 0, 0
+; CHECK-NEXT:[[TMP2:%.*]] = load float, ptr null, align 4
+; CHECK-NEXT:[[SPLAT_SPLAT_I_I_I_I:%.*]] = shufflevector <2 x float> 
zeroinitializer, <2 x float> zeroinitializer, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[XOR3_I_I_I_V_I_I:%.*]] = select <2 x i1> zeroinitializer, 
<2 x float> zeroinitializer, <2 x float> zeroinitializer
+; CHECK-NEXT:[[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV1]], 1
+; CHECK-NEXT:[[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV1]], 8
+; CHECK-NEXT:br i1 [[EXITCOND]], label [[FOR_BODY]], label [[EXIT:%.*]]
+; CHECK:   exit:
+; CHECK-NEXT:ret void
+;
+entry:
+  br label %for.body
+
+for.body: ; preds = %for.body, %entry
+  %indvars.iv1 = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %0 = load float, ptr null, align 4
+  %splat.splat.i.i.i = shufflevector <2 x float> zeroinitializer, <2 x float> 
zeroinitializer, <2 x i32> zeroinitializer
+  %cmp1.i.i.i = fcmp ogt <2 x float> zeroinitializer, zeroinitializer
+  %splat.splat3.i.i.i = shufflevector <2 x i32> zeroinitializer, <2 x i32> 
zeroinitializer, <2 x i32> zeroinitializer
+  %xor3.i.i.i.i.i = select <2 x i1> zeroinitializer, <2 x i32> 
zeroinitializer, <2 x i32> zeroinitializer
+  %1 = load float, ptr null, align 4
+  %splat.splat8.i.i.i = shufflevector <2 x float> zeroinitializer, <2 x float> 
zeroinitializer, <2 x i32>

[llvm-branch-commits] [lld] release/18.x: [ELF] Internalize enum (PR #83613)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83613
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[llvm-branch-commits] [lld] c3721c1 - [ELF] Internalize enum

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Fangrui Song
Date: 2024-03-12T17:19:50-07:00
New Revision: c3721c1dcff5c2fa5e3b6916e369f5a499383c5a

URL: 
https://github.com/llvm/llvm-project/commit/c3721c1dcff5c2fa5e3b6916e369f5a499383c5a
DIFF: 
https://github.com/llvm/llvm-project/commit/c3721c1dcff5c2fa5e3b6916e369f5a499383c5a.diff

LOG: [ELF] Internalize enum

g++ -flto has a diagnostic `-Wodr` about mismatched redeclarations,
which even apply to `enum`.

Fix #83529

Reviewers: thesamesam

Reviewed By: thesamesam

Pull Request: https://github.com/llvm/llvm-project/pull/83604

(cherry picked from commit 4a3f7e798a31072a80a0731b8fb1da21b9c626ed)

Added: 


Modified: 
lld/ELF/Arch/LoongArch.cpp
lld/ELF/Arch/PPC64.cpp
lld/ELF/Arch/RISCV.cpp

Removed: 




diff  --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index 05fd38fb753fda..1dab98115d9dea 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -41,6 +41,7 @@ class LoongArch final : public TargetInfo {
 };
 } // end anonymous namespace
 
+namespace {
 enum Op {
   SUB_W = 0x0011,
   SUB_D = 0x00118000,
@@ -65,6 +66,7 @@ enum Reg {
   R_T2 = 14,
   R_T3 = 15,
 };
+} // namespace
 
 // Mask out the input's lowest 12 bits for use with `pcalau12i`, in sequences
 // like `pcalau12i + addi.[wd]` or `pcalau12i + {ld,st}.*` where the 
`pcalau12i`

diff  --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp
index de52f6a79a40b9..019c073bd541b6 100644
--- a/lld/ELF/Arch/PPC64.cpp
+++ b/lld/ELF/Arch/PPC64.cpp
@@ -26,6 +26,7 @@ using namespace lld::elf;
 constexpr uint64_t ppc64TocOffset = 0x8000;
 constexpr uint64_t dynamicThreadPointerOffset = 0x8000;
 
+namespace {
 // The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
 // instructions that can be used as part of the initial exec TLS sequence.
 enum XFormOpcd {
@@ -139,6 +140,7 @@ enum class PPCPrefixedInsn : uint64_t {
   PSTXV = PREFIX_8LS | 0xd800,
   PSTXVP = PREFIX_8LS | 0xf800
 };
+
 static bool checkPPCLegacyInsn(uint32_t encoding) {
   PPCLegacyInsn insn = static_cast(encoding);
   if (insn == PPCLegacyInsn::NOINSN)
@@ -164,7 +166,6 @@ enum class LegacyToPrefixMask : uint64_t {
   0x83e0, // S/T (6-10) - The [S/T]X bit moves from 28 to 5.
 };
 
-namespace {
 class PPC64 final : public TargetInfo {
 public:
   PPC64();

diff  --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 5fcab4d39d43a8..4798c86f7d1b61 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -57,6 +57,7 @@ class RISCV final : public TargetInfo {
 
 const uint64_t dtpOffset = 0x800;
 
+namespace {
 enum Op {
   ADDI = 0x13,
   AUIPC = 0x17,
@@ -78,6 +79,7 @@ enum Reg {
   X_A0 = 10,
   X_T3 = 28,
 };
+} // namespace
 
 static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
 static uint32_t lo12(uint32_t val) { return val & 4095; }



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[llvm-branch-commits] [compiler-rt] release/18.x: Unbreak *tf builtins for hexfloat (#82208) (PR #82904)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/82904
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[llvm-branch-commits] [compiler-rt] c148795 - Unbreak *tf builtins for hexfloat (#82208)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


Author: Alexander Richardson
Date: 2024-03-12T17:13:57-07:00
New Revision: c14879562f46c9a5b24af8e21e8df0eef3079d4a

URL: 
https://github.com/llvm/llvm-project/commit/c14879562f46c9a5b24af8e21e8df0eef3079d4a
DIFF: 
https://github.com/llvm/llvm-project/commit/c14879562f46c9a5b24af8e21e8df0eef3079d4a.diff

LOG: Unbreak *tf builtins for hexfloat (#82208)

This re-lands cc0065a7d082f0bd322a538cf62cfaef1c8f89f8 in a way that
keeps existing targets working.

-

Original commit message:
#68132 ended up removing
__multc3 & __divtc3 from compiler-rt library builds that have
QUAD_PRECISION but not TF_MODE due to missing int128 support.
I added support for QUAD_PRECISION to use the native hex float long double 
representation.

-

Co-authored-by: Sean Perry 
(cherry picked from commit 99c457dc2ef395872d7448c85609f6cb73a7f89b)

Added: 


Modified: 
compiler-rt/lib/builtins/divtc3.c
compiler-rt/lib/builtins/fp_lib.h
compiler-rt/lib/builtins/int_types.h
compiler-rt/lib/builtins/multc3.c

Removed: 




diff  --git a/compiler-rt/lib/builtins/divtc3.c 
b/compiler-rt/lib/builtins/divtc3.c
index e970cef574b21d..099de5802daf0e 100644
--- a/compiler-rt/lib/builtins/divtc3.c
+++ b/compiler-rt/lib/builtins/divtc3.c
@@ -13,7 +13,7 @@
 #define QUAD_PRECISION
 #include "fp_lib.h"
 
-#if defined(CRT_HAS_TF_MODE)
+#if defined(CRT_HAS_F128)
 
 // Returns: the quotient of (a + ib) / (c + id)
 

diff  --git a/compiler-rt/lib/builtins/fp_lib.h 
b/compiler-rt/lib/builtins/fp_lib.h
index af406e760497a4..c4f0a5b9587f77 100644
--- a/compiler-rt/lib/builtins/fp_lib.h
+++ b/compiler-rt/lib/builtins/fp_lib.h
@@ -22,6 +22,7 @@
 
 #include "int_lib.h"
 #include "int_math.h"
+#include "int_types.h"
 #include 
 #include 
 #include 
@@ -93,13 +94,14 @@ static __inline void wideMultiply(rep_t a, rep_t b, rep_t 
*hi, rep_t *lo) {
 COMPILER_RT_ABI fp_t __adddf3(fp_t a, fp_t b);
 
 #elif defined QUAD_PRECISION
-#if defined(CRT_HAS_TF_MODE)
+#if defined(CRT_HAS_F128) && defined(CRT_HAS_128BIT)
 typedef uint64_t half_rep_t;
 typedef __uint128_t rep_t;
 typedef __int128_t srep_t;
 typedef tf_float fp_t;
 #define HALF_REP_C UINT64_C
 #define REP_C (__uint128_t)
+#if defined(CRT_HAS_IEEE_TF)
 // Note: Since there is no explicit way to tell compiler the constant is a
 // 128-bit integer, we let the constant be casted to 128-bit integer
 #define significandBits 112
@@ -188,7 +190,10 @@ static __inline void wideMultiply(rep_t a, rep_t b, rep_t 
*hi, rep_t *lo) {
 #undef Word_HiMask
 #undef Word_LoMask
 #undef Word_FullMask
-#endif // defined(CRT_HAS_TF_MODE)
+#endif // defined(CRT_HAS_IEEE_TF)
+#else
+typedef long double fp_t;
+#endif // defined(CRT_HAS_F128) && defined(CRT_HAS_128BIT)
 #else
 #error SINGLE_PRECISION, DOUBLE_PRECISION or QUAD_PRECISION must be defined.
 #endif
@@ -196,19 +201,6 @@ static __inline void wideMultiply(rep_t a, rep_t b, rep_t 
*hi, rep_t *lo) {
 #if defined(SINGLE_PRECISION) || defined(DOUBLE_PRECISION) ||  
\
 (defined(QUAD_PRECISION) && defined(CRT_HAS_TF_MODE))
 #define typeWidth (sizeof(rep_t) * CHAR_BIT)
-#define exponentBits (typeWidth - significandBits - 1)
-#define maxExponent ((1 << exponentBits) - 1)
-#define exponentBias (maxExponent >> 1)
-
-#define implicitBit (REP_C(1) << significandBits)
-#define significandMask (implicitBit - 1U)
-#define signBit (REP_C(1) << (significandBits + exponentBits))
-#define absMask (signBit - 1U)
-#define exponentMask (absMask ^ significandMask)
-#define oneRep ((rep_t)exponentBias << significandBits)
-#define infRep exponentMask
-#define quietBit (implicitBit >> 1)
-#define qnanRep (exponentMask | quietBit)
 
 static __inline rep_t toRep(fp_t x) {
   const union {
@@ -226,6 +218,21 @@ static __inline fp_t fromRep(rep_t x) {
   return rep.f;
 }
 
+#if !defined(QUAD_PRECISION) || defined(CRT_HAS_IEEE_TF)
+#define exponentBits (typeWidth - significandBits - 1)
+#define maxExponent ((1 << exponentBits) - 1)
+#define exponentBias (maxExponent >> 1)
+
+#define implicitBit (REP_C(1) << significandBits)
+#define significandMask (implicitBit - 1U)
+#define signBit (REP_C(1) << (significandBits + exponentBits))
+#define absMask (signBit - 1U)
+#define exponentMask (absMask ^ significandMask)
+#define oneRep ((rep_t)exponentBias << significandBits)
+#define infRep exponentMask
+#define quietBit (implicitBit >> 1)
+#define qnanRep (exponentMask | quietBit)
+
 static __inline int normalize(rep_t *significand) {
   const int shift = rep_clz(*significand) - rep_clz(implicitBit);
   *significand <<= shift;
@@ -328,6 +335,8 @@ static __inline fp_t __compiler_rt_scalbnX(fp_t x, int y) {
 return fromRep(sign | ((rep_t)exp << significandBits) | sig);
 }
 
+#endif // !defined(QUAD_PRECISION) || defined(CRT_HAS_IEEE_TF)
+
 // Avoid using fmax from libm.
 static __inline fp_t __compiler_rt_fmaxX(fp_t x, fp_t y) {
   // If either argument is NaN, return the other

[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

2024-03-12 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81800
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[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Override LoongArchTargetLowering::getExtendForAtomicCmpSwapArg (#83656) (PR #83750)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
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[llvm-branch-commits] [llvm] ea6c457 - [LoongArch] Override LoongArchTargetLowering::getExtendForAtomicCmpSwapArg (#83656)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Lu Weining
Date: 2024-03-11T14:19:24-07:00
New Revision: ea6c457b8dd2d0e6a7f05b4a5bdd2686085e1ec0

URL: 
https://github.com/llvm/llvm-project/commit/ea6c457b8dd2d0e6a7f05b4a5bdd2686085e1ec0
DIFF: 
https://github.com/llvm/llvm-project/commit/ea6c457b8dd2d0e6a7f05b4a5bdd2686085e1ec0.diff

LOG: [LoongArch] Override LoongArchTargetLowering::getExtendForAtomicCmpSwapArg 
(#83656)

This patch aims to solve Firefox issue:
https://bugzilla.mozilla.org/show_bug.cgi?id=1882301

Similar to 616289ed2922. Currently LoongArch uses an ll.[wd]/sc.[wd]
loop for ATOMIC_CMP_XCHG. Because the comparison in the loop is
full-width (i.e. the `bne` instruction), we must sign extend the input
comparsion argument.

Note that LoongArch ISA manual V1.1 has introduced compare-and-swap
instructions. We would change the implementation (return `ANY_EXTEND`)
when we support them.

(cherry picked from commit 5f058aa211995d2f0df2a0e063532832569cb7a8)

Added: 


Modified: 
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/lib/Target/LoongArch/LoongArchISelLowering.h
llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll

Removed: 




diff  --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 76c1a14fe0156c..b161c5434ca13e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -4940,3 +4940,8 @@ bool LoongArchTargetLowering::hasAndNotCompare(SDValue Y) 
const {
 
   return !isa(Y);
 }
+
+ISD::NodeType LoongArchTargetLowering::getExtendForAtomicCmpSwapArg() const {
+  // TODO: LAMCAS will use amcas{_DB,}.[bhwd] which does not require extension.
+  return ISD::SIGN_EXTEND;
+}

diff  --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 72182623b2c3dd..9e9ac0b8269291 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -206,6 +206,8 @@ class LoongArchTargetLowering : public TargetLowering {
 return ISD::SIGN_EXTEND;
   }
 
+  ISD::NodeType getExtendForAtomicCmpSwapArg() const override;
+
   Register getRegisterByName(const char *RegName, LLT VT,
  const MachineFunction ) const override;
   bool mayBeEmittedAsTailCall(const CallInst *CI) const override;

diff  --git a/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll 
b/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
index b0f29ee790885d..b84c1093eb75f2 100644
--- a/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
+++ b/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
@@ -25,15 +25,16 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
 ; LA64-NEXT:andi $a5, $a5, 255
 ; LA64-NEXT:sll.w $a5, $a5, $a3
 ; LA64-NEXT:and $a6, $a2, $a4
-; LA64-NEXT:or $a6, $a6, $a5
+; LA64-NEXT:or $a5, $a6, $a5
+; LA64-NEXT:addi.w $a6, $a2, 0
 ; LA64-NEXT:  .LBB0_3: # %atomicrmw.start
 ; LA64-NEXT:# Parent Loop BB0_1 Depth=1
 ; LA64-NEXT:# => This Inner Loop Header: Depth=2
-; LA64-NEXT:ll.w $a5, $a0, 0
-; LA64-NEXT:bne $a5, $a2, .LBB0_5
+; LA64-NEXT:ll.w $a2, $a0, 0
+; LA64-NEXT:bne $a2, $a6, .LBB0_5
 ; LA64-NEXT:  # %bb.4: # %atomicrmw.start
 ; LA64-NEXT:# in Loop: Header=BB0_3 Depth=2
-; LA64-NEXT:move $a7, $a6
+; LA64-NEXT:move $a7, $a5
 ; LA64-NEXT:sc.w $a7, $a0, 0
 ; LA64-NEXT:beqz $a7, .LBB0_3
 ; LA64-NEXT:b .LBB0_6
@@ -42,11 +43,9 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
 ; LA64-NEXT:dbar 20
 ; LA64-NEXT:  .LBB0_6: # %atomicrmw.start
 ; LA64-NEXT:# in Loop: Header=BB0_1 Depth=1
-; LA64-NEXT:addi.w $a6, $a2, 0
-; LA64-NEXT:move $a2, $a5
-; LA64-NEXT:bne $a5, $a6, .LBB0_1
+; LA64-NEXT:bne $a2, $a6, .LBB0_1
 ; LA64-NEXT:  # %bb.2: # %atomicrmw.end
-; LA64-NEXT:srl.w $a0, $a5, $a3
+; LA64-NEXT:srl.w $a0, $a2, $a3
 ; LA64-NEXT:ret
   %result = atomicrmw uinc_wrap ptr %ptr, i8 %val seq_cst
   ret i8 %result
@@ -77,15 +76,16 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
 ; LA64-NEXT:bstrpick.d $a5, $a5, 15, 0
 ; LA64-NEXT:sll.w $a5, $a5, $a3
 ; LA64-NEXT:and $a6, $a2, $a4
-; LA64-NEXT:or $a6, $a6, $a5
+; LA64-NEXT:or $a5, $a6, $a5
+; LA64-NEXT:addi.w $a6, $a2, 0
 ; LA64-NEXT:  .LBB1_3: # %atomicrmw.start
 ; LA64-NEXT:# Parent Loop BB1_1 Depth=1
 ; LA64-NEXT:# => This Inner Loop Header: Depth=2
-; LA64-NEXT:ll.w $a5, $a0, 0
-; LA64-NEXT:bne $a5, $a2, .LBB1_5
+; LA64-NEXT:ll.w $a2, $a0, 0
+; LA64-NEXT:bne $a2, $a6, .LBB1_5
 ; LA64-NEXT:  # %bb.4: # %atomicrmw.start
 ; LA64-NEXT:# in Loop: Header=BB1_3 Depth=2
-; LA64-NEXT:move $a7, $a6
+; LA64-NEXT:

[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Fix miscompilation in PR83947 (#83993) (PR #84021)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

This is fixed in #84298.

https://github.com/llvm/llvm-project/pull/84021
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[llvm-branch-commits] [llvm] release/18.x: [TableGen] Fix wrong codegen of BothFusionPredicateWithMCInstPredicate (#83990) (PR #83999)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83999
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[llvm-branch-commits] [llvm] 69d9b15 - [TableGen] Fix wrong codegen of BothFusionPredicateWithMCInstPredicate (#83990)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Wang Pengcheng
Date: 2024-03-11T13:57:41-07:00
New Revision: 69d9b15fe872bb188474b0ad9e36c8506bdf9cc3

URL: 
https://github.com/llvm/llvm-project/commit/69d9b15fe872bb188474b0ad9e36c8506bdf9cc3
DIFF: 
https://github.com/llvm/llvm-project/commit/69d9b15fe872bb188474b0ad9e36c8506bdf9cc3.diff

LOG: [TableGen] Fix wrong codegen of BothFusionPredicateWithMCInstPredicate 
(#83990)

We should generate the `MCInstPredicate` twice, one with `FirstMI`
and another with `SecondMI`.

(cherry picked from commit de1f33873beff93063577195e1214a9509e229e0)

Added: 


Modified: 
llvm/include/llvm/Target/TargetSchedule.td
llvm/test/TableGen/MacroFusion.td
llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp

Removed: 




diff  --git a/llvm/include/llvm/Target/TargetSchedule.td 
b/llvm/include/llvm/Target/TargetSchedule.td
index 032de728517827..40c2cce8c6effe 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -620,7 +620,7 @@ class 
SecondFusionPredicateWithMCInstPredicate
   : FusionPredicateWithMCInstPredicate;
 // The pred will be applied on both firstMI and secondMI.
 class BothFusionPredicateWithMCInstPredicate
-  : FusionPredicateWithMCInstPredicate;
+  : FusionPredicateWithMCInstPredicate;
 
 // Tie firstOpIdx and secondOpIdx. The operand of `FirstMI` at position
 // `firstOpIdx` should be the same as the operand of `SecondMI` at position

diff  --git a/llvm/test/TableGen/MacroFusion.td 
b/llvm/test/TableGen/MacroFusion.td
index 4aa6c8d9acb273..ce76e7f0f7fa64 100644
--- a/llvm/test/TableGen/MacroFusion.td
+++ b/llvm/test/TableGen/MacroFusion.td
@@ -34,6 +34,11 @@ let Namespace = "Test" in {
 def Inst0 : TestInst<0>;
 def Inst1 : TestInst<1>;
 
+def BothFusionPredicate: 
BothFusionPredicateWithMCInstPredicate>;
+def TestBothFusionPredicate: Fusion<"test-both-fusion-predicate", 
"HasBothFusionPredicate",
+"Test BothFusionPredicate",
+[BothFusionPredicate]>;
+
 def TestFusion: SimpleFusion<"test-fusion", "HasTestFusion", "Test Fusion",
  CheckOpcode<[Inst0]>,
  CheckAll<[
@@ -45,6 +50,7 @@ def TestFusion: SimpleFusion<"test-fusion", "HasTestFusion", 
"Test Fusion",
 // CHECK-PREDICATOR-NEXT:  #undef GET_Test_MACRO_FUSION_PRED_DECL
 // CHECK-PREDICATOR-EMPTY:
 // CHECK-PREDICATOR-NEXT:  namespace llvm {
+// CHECK-PREDICATOR-NEXT:  bool isTestBothFusionPredicate(const 
TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const 
MachineInstr &);
 // CHECK-PREDICATOR-NEXT:  bool isTestFusion(const TargetInstrInfo &, const 
TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
 // CHECK-PREDICATOR-NEXT:  } // end namespace llvm
 // CHECK-PREDICATOR-EMPTY:
@@ -54,6 +60,24 @@ def TestFusion: SimpleFusion<"test-fusion", "HasTestFusion", 
"Test Fusion",
 // CHECK-PREDICATOR-NEXT:  #undef GET_Test_MACRO_FUSION_PRED_IMPL
 // CHECK-PREDICATOR-EMPTY:
 // CHECK-PREDICATOR-NEXT:  namespace llvm {
+// CHECK-PREDICATOR-NEXT:  bool isTestBothFusionPredicate(
+// CHECK-PREDICATOR-NEXT:  const TargetInstrInfo ,
+// CHECK-PREDICATOR-NEXT:  const TargetSubtargetInfo ,
+// CHECK-PREDICATOR-NEXT:  const MachineInstr *FirstMI,
+// CHECK-PREDICATOR-NEXT:  const MachineInstr ) {
+// CHECK-PREDICATOR-NEXT:auto  = SecondMI.getMF()->getRegInfo();
+// CHECK-PREDICATOR-NEXT:{
+// CHECK-PREDICATOR-NEXT:  const MachineInstr *MI = FirstMI;
+// CHECK-PREDICATOR-NEXT:  if (MI->getOperand(0).getReg() != Test::X0)
+// CHECK-PREDICATOR-NEXT:return false;
+// CHECK-PREDICATOR-NEXT:}
+// CHECK-PREDICATOR-NEXT:{
+// CHECK-PREDICATOR-NEXT:  const MachineInstr *MI = 
+// CHECK-PREDICATOR-NEXT:  if (MI->getOperand(0).getReg() != Test::X0)
+// CHECK-PREDICATOR-NEXT:return false;
+// CHECK-PREDICATOR-NEXT:}
+// CHECK-PREDICATOR-NEXT:return true;
+// CHECK-PREDICATOR-NEXT:  }
 // CHECK-PREDICATOR-NEXT:  bool isTestFusion(
 // CHECK-PREDICATOR-NEXT:  const TargetInstrInfo ,
 // CHECK-PREDICATOR-NEXT:  const TargetSubtargetInfo ,
@@ -106,6 +130,7 @@ def TestFusion: SimpleFusion<"test-fusion", 
"HasTestFusion", "Test Fusion",
 
 // CHECK-SUBTARGET:  std::vector 
TestGenSubtargetInfo::getMacroFusions() const {
 // CHECK-SUBTARGET-NEXT:   std::vector Fusions;
+// CHECK-SUBTARGET-NEXT:   if (hasFeature(Test::TestBothFusionPredicate)) 
Fusions.push_back(llvm::isTestBothFusionPredicate); 
 // CHECK-SUBTARGET-NEXT:   if (hasFeature(Test::TestFusion)) 
Fusions.push_back(llvm::isTestFusion);
 // CHECK-SUBTARGET-NEXT:   return Fusions;
 // CHECK-SUBTARGET-NEXT: }

diff  --git a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp 
b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
index 78dcd4471ae747..7f494e532b1f44 100644
---

[llvm-branch-commits] [openmp] release/18.x: [OpenMP] fix endianness dependent definitions in OMP headers for MSVC (#84540) (PR #84668)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84668
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[llvm-branch-commits] [openmp] a91b9bd - [OpenMP] fix endianness dependent definitions in OMP headers for MSVC (#84540)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Vadim Paretsky
Date: 2024-03-11T13:42:47-07:00
New Revision: a91b9bd9c7507b378a7f318db52484c8bacc12eb

URL: 
https://github.com/llvm/llvm-project/commit/a91b9bd9c7507b378a7f318db52484c8bacc12eb
DIFF: 
https://github.com/llvm/llvm-project/commit/a91b9bd9c7507b378a7f318db52484c8bacc12eb.diff

LOG: [OpenMP] fix endianness dependent definitions in OMP headers for MSVC 
(#84540)

MSVC does not define __BYTE_ORDER__ making the check for BigEndian
erroneously evaluate to true and breaking the struct definitions in MSVC
compiled builds correspondingly. The fix adds an additional check for
whether __BYTE_ORDER__ is defined by the compiler to fix these.

-

Co-authored-by: Vadim Paretsky 
(cherry picked from commit 110141b37813dc48af33de5e1407231e56acdfc5)

Added: 


Modified: 
openmp/runtime/src/kmp.h
openmp/runtime/src/kmp_lock.h
openmp/runtime/test/tasking/bug_nested_proxy_task.c
openmp/runtime/test/tasking/bug_proxy_task_dep_waiting.c
openmp/runtime/test/tasking/hidden_helper_task/common.h

Removed: 




diff  --git a/openmp/runtime/src/kmp.h b/openmp/runtime/src/kmp.h
index 259c57b5afbca5..e3a1e20731bbe0 100644
--- a/openmp/runtime/src/kmp.h
+++ b/openmp/runtime/src/kmp.h
@@ -2506,7 +2506,7 @@ typedef struct kmp_depend_info {
   union {
 kmp_uint8 flag; // flag as an unsigned char
 struct { // flag as a set of 8 bits
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
   /* Same fields as in the #else branch, but in reverse order */
   unsigned all : 1;
   unsigned unused : 3;
@@ -2671,7 +2671,7 @@ typedef struct kmp_task_stack {
 #endif // BUILD_TIED_TASK_STACK
 
 typedef struct kmp_tasking_flags { /* Total struct must be exactly 32 bits */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
   /* Same fields as in the #else branch, but in reverse order */
 #if OMPX_TASKGRAPH
   unsigned reserved31 : 6;

diff  --git a/openmp/runtime/src/kmp_lock.h b/openmp/runtime/src/kmp_lock.h
index e2a0cda01a9718..6202f3d617cc59 100644
--- a/openmp/runtime/src/kmp_lock.h
+++ b/openmp/runtime/src/kmp_lock.h
@@ -120,7 +120,8 @@ extern void __kmp_validate_locks(void);
 
 struct kmp_base_tas_lock {
   // KMP_LOCK_FREE(tas) => unlocked; locked: (gtid+1) of owning thread
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ && __LP64__
+#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) && 
\
+__LP64__
   // Flip the ordering of the high and low 32-bit member to be consistent
   // with the memory layout of the address in 64-bit big-endian.
   kmp_int32 depth_locked; // depth locked, for nested locks only

diff  --git a/openmp/runtime/test/tasking/bug_nested_proxy_task.c 
b/openmp/runtime/test/tasking/bug_nested_proxy_task.c
index 24fe1f3fe7607c..9e0b412efce609 100644
--- a/openmp/runtime/test/tasking/bug_nested_proxy_task.c
+++ b/openmp/runtime/test/tasking/bug_nested_proxy_task.c
@@ -50,7 +50,7 @@ typedef struct kmp_depend_info {
  union {
 kmp_uint8 flag; // flag as an unsigned char
 struct { // flag as a set of 8 bits
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
   unsigned all : 1;
   unsigned unused : 3;
   unsigned set : 1;

diff  --git a/openmp/runtime/test/tasking/bug_proxy_task_dep_waiting.c 
b/openmp/runtime/test/tasking/bug_proxy_task_dep_waiting.c
index 688860c035728f..1e86d574f4f6a8 100644
--- a/openmp/runtime/test/tasking/bug_proxy_task_dep_waiting.c
+++ b/openmp/runtime/test/tasking/bug_proxy_task_dep_waiting.c
@@ -47,7 +47,7 @@ typedef struct kmp_depend_info {
  union {
 kmp_uint8 flag; // flag as an unsigned char
 struct { // flag as a set of 8 bits
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
   unsigned all : 1;
   unsigned unused : 3;
   unsigned set : 1;

diff  --git a/openmp/runtime/test/tasking/hidden_helper_task/common.h 
b/openmp/runtime/test/tasking/hidden_helper_task/common.h
index ba57656cbac41d..68e2b584c87739 100644
--- a/openmp/runtime/test/tasking/hidden_helper_task/common.h
+++ b/openmp/runtime/test/tasking/hidden_helper_task/common.h
@@ -17,7 +17,7 @@ typedef struct kmp_depend_info {
   union {
 unsigned char flag;
 struct {
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
   unsigned all : 1;
   unsigned unused : 3;
   unsigned set : 1;



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[llvm-branch-commits] [llvm] ReleaseNotes for LLVM binary utilities (PR #83751)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83751
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[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

The new test is failing on the release/18.x branch.

https://github.com/llvm/llvm-project/pull/84491
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[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Fix infinite loop in select equivalence fold (#84036) (PR #84141)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84141
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[llvm-branch-commits] [llvm] 94d8f15 - [InstCombine] Fix infinite loop in select equivalence fold (#84036)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Nikita Popov
Date: 2024-03-11T13:36:40-07:00
New Revision: 94d8f150ed8b6afb83ba47f68116a0247a23cb52

URL: 
https://github.com/llvm/llvm-project/commit/94d8f150ed8b6afb83ba47f68116a0247a23cb52
DIFF: 
https://github.com/llvm/llvm-project/commit/94d8f150ed8b6afb83ba47f68116a0247a23cb52.diff

LOG: [InstCombine] Fix infinite loop in select equivalence fold (#84036)

When replacing with a non-constant, it's possible that the result of the
simplification is actually more complicated than the original, and may
result in an infinite combine loop.

Mitigate the issue by requiring that either the replacement or
simplification result is constant, which should ensure that it's
simpler. While this check is crude, it does not appear to cause
optimization regressions in real-world code in practice.

Fixes https://github.com/llvm/llvm-project/issues/83127.

(cherry picked from commit 9f45c5e1a65a1abf4920b617d36ed05e73c04bea)

Added: 


Modified: 
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/test/Transforms/InstCombine/select.ll

Removed: 




diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 21bfc91148bfeb..9f220ec003ec33 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -1284,7 +1284,11 @@ Instruction 
*InstCombinerImpl::foldSelectValueEquivalence(SelectInst ,
   isGuaranteedNotToBeUndefOrPoison(CmpRHS, SQ.AC, , )) {
 if (Value *V = simplifyWithOpReplaced(TrueVal, CmpLHS, CmpRHS, SQ,
   /* AllowRefinement */ true))
-  return replaceOperand(Sel, Swapped ? 2 : 1, V);
+  // Require either the replacement or the simplification result to be a
+  // constant to avoid infinite loops.
+  // FIXME: Make this check more precise.
+  if (isa(CmpRHS) || isa(V))
+return replaceOperand(Sel, Swapped ? 2 : 1, V);
 
 // Even if TrueVal does not simplify, we can directly replace a use of
 // CmpLHS with CmpRHS, as long as the instruction is not used anywhere
@@ -1302,7 +1306,8 @@ Instruction 
*InstCombinerImpl::foldSelectValueEquivalence(SelectInst ,
   isGuaranteedNotToBeUndefOrPoison(CmpLHS, SQ.AC, , ))
 if (Value *V = simplifyWithOpReplaced(TrueVal, CmpRHS, CmpLHS, SQ,
   /* AllowRefinement */ true))
-  return replaceOperand(Sel, Swapped ? 2 : 1, V);
+  if (isa(CmpLHS) || isa(V))
+return replaceOperand(Sel, Swapped ? 2 : 1, V);
 
   auto *FalseInst = dyn_cast(FalseVal);
   if (!FalseInst)

diff  --git a/llvm/test/Transforms/InstCombine/select.ll 
b/llvm/test/Transforms/InstCombine/select.ll
index c5f1b77c6d7404..b7e743c14a52ca 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -2849,12 +2849,14 @@ define i8 @select_replacement_sub(i8 %x, i8 %y, i8 %z) {
   ret i8 %sel
 }
 
+; FIXME: This is safe to fold.
 define i8 @select_replacement_shift_noundef(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @select_replacement_shift_noundef(
 ; CHECK-NEXT:[[SHR:%.*]] = lshr exact i8 [[X:%.*]], 1
 ; CHECK-NEXT:call void @use_i8(i8 noundef [[SHR]])
 ; CHECK-NEXT:[[CMP:%.*]] = icmp eq i8 [[SHR]], [[Y:%.*]]
-; CHECK-NEXT:[[SEL:%.*]] = select i1 [[CMP]], i8 [[X]], i8 [[Z:%.*]]
+; CHECK-NEXT:[[SHL:%.*]] = shl i8 [[Y]], 1
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[CMP]], i8 [[SHL]], i8 [[Z:%.*]]
 ; CHECK-NEXT:ret i8 [[SEL]]
 ;
   %shr = lshr exact i8 %x, 1
@@ -2904,6 +2906,40 @@ define i32 @select_replacement_loop2(i32 %arg, i32 
%arg2) {
   ret i32 %sel
 }
 
+define i8 @select_replacement_loop3(i32 noundef %x) {
+; CHECK-LABEL: @select_replacement_loop3(
+; CHECK-NEXT:[[TRUNC:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT:[[REV:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[TRUNC]])
+; CHECK-NEXT:[[EXT:%.*]] = zext i8 [[REV]] to i32
+; CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[EXT]], [[X]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[CMP]], i8 [[TRUNC]], i8 0
+; CHECK-NEXT:ret i8 [[SEL]]
+;
+  %trunc = trunc i32 %x to i8
+  %rev = call i8 @llvm.bitreverse.i8(i8 %trunc)
+  %ext = zext i8 %rev to i32
+  %cmp = icmp eq i32 %ext, %x
+  %sel = select i1 %cmp, i8 %trunc, i8 0
+  ret i8 %sel
+}
+
+define i16 @select_replacement_loop4(i16 noundef %p_12) {
+; CHECK-LABEL: @select_replacement_loop4(
+; CHECK-NEXT:[[CMP1:%.*]] = icmp ult i16 [[P_12:%.*]], 2
+; CHECK-NEXT:[[AND1:%.*]] = and i16 [[P_12]], 1
+; CHECK-NEXT:[[AND2:%.*]] = select i1 [[CMP1]], i16 [[AND1]], i16 0
+; CHECK-NEXT:[[CMP2:%.*]] = icmp eq i16 [[AND2]], [[P_12]]
+; CHECK-NEXT:[[AND3:%.*]] = select i1 [[CMP2]], i16 [[AND1]], i16 0
+; CHECK-NEXT:ret i16 [[AND3]]
+;
+  %cmp1 = icmp ult i16 %p_12, 2
+  %and1 = and i16 %p_12, 1
+  %and2 = select i1 %cmp1, i16 %and1, i16 0
+

[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Fix shift calculation in InstCombineCasts (#84027) (PR #84080)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84080
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[llvm-branch-commits] [llvm] 4c36ecb - [InstCombine] Fix shift calculation in InstCombineCasts (#84027)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Quentin Dian
Date: 2024-03-11T13:33:20-07:00
New Revision: 4c36ecbe0e162155e6032aec75323dcdd7c81b90

URL: 
https://github.com/llvm/llvm-project/commit/4c36ecbe0e162155e6032aec75323dcdd7c81b90
DIFF: 
https://github.com/llvm/llvm-project/commit/4c36ecbe0e162155e6032aec75323dcdd7c81b90.diff

LOG:  [InstCombine] Fix shift calculation in InstCombineCasts (#84027)

Fixes #84025.

(cherry picked from commit e96c0c1d5e0a9916098b1a31acb006ea6c1108fb)

Added: 


Modified: 
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/test/Transforms/InstCombine/bitcast.ll

Removed: 




diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index 58f0763bb0c0cd..c5d3f60176a826 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -2156,14 +2156,14 @@ static bool collectInsertionElements(Value *V, unsigned 
Shift,
 Type *ElementIntTy = IntegerType::get(C->getContext(), ElementSize);
 
 for (unsigned i = 0; i != NumElts; ++i) {
-  unsigned ShiftI = Shift + i * ElementSize;
+  unsigned ShiftI = i * ElementSize;
   Constant *Piece = ConstantFoldBinaryInstruction(
   Instruction::LShr, C, ConstantInt::get(C->getType(), ShiftI));
   if (!Piece)
 return false;
 
   Piece = ConstantExpr::getTrunc(Piece, ElementIntTy);
-  if (!collectInsertionElements(Piece, ShiftI, Elements, VecEltTy,
+  if (!collectInsertionElements(Piece, ShiftI + Shift, Elements, VecEltTy,
 isBigEndian))
 return false;
 }

diff  --git a/llvm/test/Transforms/InstCombine/bitcast.ll 
b/llvm/test/Transforms/InstCombine/bitcast.ll
index 58bd81297b0dd9..5ace1039c37825 100644
--- a/llvm/test/Transforms/InstCombine/bitcast.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast.ll
@@ -686,6 +686,21 @@ define ptr 
@bitcast_from_single_element_pointer_vector_to_pointer(<1 x ptr> %ptr
   ret ptr %ptr
 }
 
+; Sure that we calculate the correct shift.
+define <4 x i32> @bitcast_shl(i32 %arg) {
+; CHECK-LABEL: @bitcast_shl(
+; CHECK-NEXT:[[I5:%.*]] = insertelement <4 x i32> , i32 [[ARG:%.*]], i64 3
+; CHECK-NEXT:ret <4 x i32> [[I5]]
+;
+  %i = zext i32 %arg to i64
+  %i1 = shl i64 %i, 32
+  %i2 = or i64 %i1, 65
+  %i3 = zext i64 %i2 to i128
+  %i4 = shl i128 %i3, 64
+  %i5 = bitcast i128 %i4 to <4 x i32>
+  ret <4 x i32> %i5
+}
+
 declare void @f1()
 declare void @f2()
 define ptr @select_bitcast_unsized_pointer(i1 %c) {



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[llvm-branch-commits] [compiler-rt] release/18.x: [test] Make two sanitize-coverage tests pass with glibc 2.39+ (PR #84239)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84239
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[llvm-branch-commits] [compiler-rt] e90bfdb - [test] Make two sanitize-coverage tests pass with glibc 2.39+

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Fangrui Song
Date: 2024-03-11T13:07:50-07:00
New Revision: e90bfdb4ddced8dff215672ffeceece8ebe60426

URL: 
https://github.com/llvm/llvm-project/commit/e90bfdb4ddced8dff215672ffeceece8ebe60426
DIFF: 
https://github.com/llvm/llvm-project/commit/e90bfdb4ddced8dff215672ffeceece8ebe60426.diff

LOG: [test] Make two sanitize-coverage tests pass with glibc 2.39+

glibc 2.39 added `nonnull` attribute to most libio functions accepting a
`FILE*` parameter, including fprintf[1]. The -fsanitize=undefined mode
checks the argument to fprintf and has extra counters, not expected by
two tests. Specify -fno-sanitize=nonnull-attribute to make the two tests
pass.

Fix #82883

[1]: 
https://sourceware.org/git/?p=glibc.git;a=commit;h=64b1a44183a3094672ed304532bedb9acc707554

Pull Request: https://github.com/llvm/llvm-project/pull/84231

(cherry picked from commit c3acbf6bb06f9039f9850e18e0ae2f2adef63905)

Added: 


Modified: 

compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_inline8bit_counter_default_impl.cpp
compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_symbolize.cpp

Removed: 




diff  --git 
a/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_inline8bit_counter_default_impl.cpp
 
b/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_inline8bit_counter_default_impl.cpp
index 1ac04b53491e14..1d1fbf7299e8b4 100644
--- 
a/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_inline8bit_counter_default_impl.cpp
+++ 
b/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_inline8bit_counter_default_impl.cpp
@@ -3,7 +3,9 @@
 
 // REQUIRES: has_sancovcc,stable-runtime,linux,x86_64-target-arch
 
-// RUN: %clangxx -O0 %s -fsanitize-coverage=inline-8bit-counters,pc-table -o %t
+/// In glibc 2.39+, fprintf has a nonnull attribute. Disable nonnull-attribute,
+/// which would increase counters for ubsan.
+// RUN: %clangxx -O0 %s -fsanitize-coverage=inline-8bit-counters,pc-table 
-fno-sanitize=nonnull-attribute -o %t
 // RUN: rm -f %t-counters %t-pcs
 // RUN: env %tool_options="cov_8bit_counters_out=%t-counters 
cov_pcs_out=%t-pcs verbosity=1" %run %t 2>&1 | FileCheck %s
 

diff  --git 
a/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_symbolize.cpp 
b/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_symbolize.cpp
index daa994c8116251..b168954a1c92cf 100644
--- 
a/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_symbolize.cpp
+++ 
b/compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_symbolize.cpp
@@ -7,7 +7,9 @@
 // RUN: rm -rf $DIR
 // RUN: mkdir -p $DIR
 // RUN: cd $DIR
-// RUN: %clangxx -O0 -fsanitize-coverage=trace-pc-guard %s -o %t
+/// In glibc 2.39+, fprintf has a nonnull attribute. Disable nonnull-attribute,
+/// which would increase counters for ubsan.
+// RUN: %clangxx -O0 -fsanitize-coverage=trace-pc-guard 
-fno-sanitize=nonnull-attribute %s -o %t
 // RUN: %env_tool_opts=coverage=1 %t 2>&1 | FileCheck %s
 // RUN: rm -rf $DIR
 



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[llvm-branch-commits] [llvm] bf45c3a - [DSE] Delay deleting non-memory-defs until end of DSE. (#83411)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Florian Hahn
Date: 2024-03-11T12:53:04-07:00
New Revision: bf45c3a07918c14577ef7a829f16ec339b9ed610

URL: 
https://github.com/llvm/llvm-project/commit/bf45c3a07918c14577ef7a829f16ec339b9ed610
DIFF: 
https://github.com/llvm/llvm-project/commit/bf45c3a07918c14577ef7a829f16ec339b9ed610.diff

LOG: [DSE] Delay deleting non-memory-defs until end of DSE. (#83411)

DSE uses BatchAA, which caches queries using pairs of MemoryLocations.
At the moment, DSE may remove instructions that are used as pointers in
cached MemoryLocations. If a new instruction used by a new MemoryLoation
and this instruction gets allocated at the same address as a previosuly
cached and then removed instruction, we may access an incorrect entry in
the cache.

To avoid this delay removing all instructions except MemoryDefs until
the end of DSE. This should avoid removing any values used in BatchAA's
cache.

Test case by @vporpo from
https://github.com/llvm/llvm-project/pull/83181.
(Test not precommitted because the results are non-determinstic - memset
only sometimes gets removed)

PR: https://github.com/llvm/llvm-project/pull/83411
(cherry picked from commit 10f5e983a9e3162a569cbebeb32168716e391340)

Added: 
llvm/test/Transforms/DeadStoreElimination/batchaa-caching-new-pointers.ll

Modified: 
llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp 
b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
index 11a91bfbe5baff..340fba4fb9c5a2 100644
--- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
@@ -857,6 +857,9 @@ struct DSEState {
   // no longer be captured.
   bool ShouldIterateEndOfFunctionDSE;
 
+  /// Dead instructions to be removed at the end of DSE.
+  SmallVector ToRemove;
+
   // Class contains self-reference, make sure it's not copied/moved.
   DSEState(const DSEState &) = delete;
   DSEState =(const DSEState &) = delete;
@@ -1692,7 +1695,8 @@ struct DSEState {
 return {MaybeDeadAccess};
   }
 
-  // Delete dead memory defs
+  /// Delete dead memory defs and recursively add their operands to ToRemove if
+  /// they became dead.
   void deleteDeadInstruction(Instruction *SI) {
 MemorySSAUpdater Updater();
 SmallVector NowDeadInsts;
@@ -1708,8 +1712,11 @@ struct DSEState {
   salvageKnowledge(DeadInst);
 
   // Remove the Instruction from MSSA.
-  if (MemoryAccess *MA = MSSA.getMemoryAccess(DeadInst)) {
-if (MemoryDef *MD = dyn_cast(MA)) {
+  MemoryAccess *MA = MSSA.getMemoryAccess(DeadInst);
+  bool IsMemDef = MA && isa(MA);
+  if (MA) {
+if (IsMemDef) {
+  auto *MD = cast(MA);
   SkipStores.insert(MD);
   if (auto *SI = dyn_cast(MD->getMemoryInst())) {
 if (SI->getValueOperand()->getType()->isPointerTy()) {
@@ -1730,13 +1737,21 @@ struct DSEState {
   // Remove its operands
   for (Use  : DeadInst->operands())
 if (Instruction *OpI = dyn_cast(O)) {
-  O = nullptr;
+  O.set(PoisonValue::get(O->getType()));
   if (isInstructionTriviallyDead(OpI, ))
 NowDeadInsts.push_back(OpI);
 }
 
   EI.removeInstruction(DeadInst);
-  DeadInst->eraseFromParent();
+  // Remove memory defs directly if they don't produce results, but only
+  // queue other dead instructions for later removal. They may have been
+  // used as memory locations that have been cached by BatchAA. Removing
+  // them here may lead to newly created instructions to be allocated at 
the
+  // same address, yielding stale cache entries.
+  if (IsMemDef && DeadInst->getType()->isVoidTy())
+DeadInst->eraseFromParent();
+  else
+ToRemove.push_back(DeadInst);
 }
   }
 
@@ -2233,6 +2248,12 @@ static bool eliminateDeadStores(Function , 
AliasAnalysis , MemorySSA ,
 
   MadeChange |= State.eliminateRedundantStoresOfExistingValues();
   MadeChange |= State.eliminateDeadWritesAtEndOfFunction();
+
+  while (!State.ToRemove.empty()) {
+Instruction *DeadInst = State.ToRemove.pop_back_val();
+DeadInst->eraseFromParent();
+  }
+
   return MadeChange;
 }
 } // end anonymous namespace

diff  --git 
a/llvm/test/Transforms/DeadStoreElimination/batchaa-caching-new-pointers.ll 
b/llvm/test/Transforms/DeadStoreElimination/batchaa-caching-new-pointers.ll
new file mode 100644
index 00..ee9bd6912e2ae4
--- /dev/null
+++ b/llvm/test/Transforms/DeadStoreElimination/batchaa-caching-new-pointers.ll
@@ -0,0 +1,189 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt -S -passes=dse < %s | FileCheck %s
+;
+; DSE kills `store i32 44, ptr %struct.byte.4, align 4` but should not kill
+; `call void @llvm.memset.p0.i64(...)`  because it has a clobber read:
+; `%ret = load ptr, ptr %struct.byte.8`

[llvm-branch-commits] [llvm] release/18.x: [DSE] Delay deleting non-memory-defs until end of DSE. (#83411) (PR #84227)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84227
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Enable availability based on the compiler instead of __has_extension (#84065) (PR #84374)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

@ldionne Is the test failure legitimate?

https://github.com/llvm/llvm-project/pull/84374
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[llvm-branch-commits] [clang] release/18.x: [clang][fat-lto-objects] Make module flags match non-FatLTO pipelines (#83159) (PR #84290)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84290
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[llvm-branch-commits] [clang] 16ab081 - [clang][fat-lto-objects] Make module flags match non-FatLTO pipelines (#83159)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Paul Kirth
Date: 2024-03-11T12:47:52-07:00
New Revision: 16ab0812d2010dad76f87d4d50da8e79e0e75e71

URL: 
https://github.com/llvm/llvm-project/commit/16ab0812d2010dad76f87d4d50da8e79e0e75e71
DIFF: 
https://github.com/llvm/llvm-project/commit/16ab0812d2010dad76f87d4d50da8e79e0e75e71.diff

LOG: [clang][fat-lto-objects] Make module flags match non-FatLTO pipelines 
(#83159)

In addition to being rather hard to follow, there isn't a good reason
why FatLTO shouldn't just share the same code for setting module flags
for (Thin)LTO. This patch simplifies the logic and makes sure we use set
these flags in a consistent way, independent of FatLTO.

Additionally, we now test that output in the .llvm.lto section actually
matches the output from Full and Thin LTO compilation.

(cherry picked from commit 7d8b50aaab8e0f935e3cb1f3f397e98b9e3ee241)

Added: 


Modified: 
clang/lib/CodeGen/BackendUtil.cpp
clang/test/CodeGen/fat-lto-objects.c

Removed: 




diff  --git a/clang/lib/CodeGen/BackendUtil.cpp 
b/clang/lib/CodeGen/BackendUtil.cpp
index 7877e20d77f772..4f22d35f9d3a94 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -186,6 +186,14 @@ class EmitAssemblyHelper {
TargetTriple.getVendor() != llvm::Triple::Apple;
   }
 
+  /// Check whether we should emit a flag for UnifiedLTO.
+  /// The UnifiedLTO module flag should be set when UnifiedLTO is enabled for
+  /// ThinLTO or Full LTO with module summaries.
+  bool shouldEmitUnifiedLTOModueFlag() const {
+return CodeGenOpts.UnifiedLTO &&
+   (CodeGenOpts.PrepareForThinLTO || shouldEmitRegularLTOSummary());
+  }
+
 public:
   EmitAssemblyHelper(DiagnosticsEngine &_Diags,
  const HeaderSearchOptions ,
@@ -1029,7 +1037,8 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
   if (!actionRequiresCodeGen(Action) && CodeGenOpts.VerifyModule)
 MPM.addPass(VerifierPass());
 
-  if (Action == Backend_EmitBC || Action == Backend_EmitLL) {
+  if (Action == Backend_EmitBC || Action == Backend_EmitLL ||
+  CodeGenOpts.FatLTO) {
 if (CodeGenOpts.PrepareForThinLTO && !CodeGenOpts.DisableLLVMPasses) {
   if (!TheModule->getModuleFlag("EnableSplitLTOUnit"))
 TheModule->addModuleFlag(llvm::Module::Error, "EnableSplitLTOUnit",
@@ -1040,11 +1049,9 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
   if (!ThinLinkOS)
 return;
 }
-if (CodeGenOpts.UnifiedLTO)
-  TheModule->addModuleFlag(llvm::Module::Error, "UnifiedLTO", 
uint32_t(1));
 MPM.addPass(ThinLTOBitcodeWriterPass(
 *OS, ThinLinkOS ? >os() : nullptr));
-  } else {
+  } else if (Action == Backend_EmitLL) {
 MPM.addPass(PrintModulePass(*OS, "", CodeGenOpts.EmitLLVMUseLists,
 /*EmitLTOSummary=*/true));
   }
@@ -1058,24 +1065,17 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
 if (!TheModule->getModuleFlag("EnableSplitLTOUnit"))
   TheModule->addModuleFlag(llvm::Module::Error, "EnableSplitLTOUnit",
uint32_t(1));
-if (CodeGenOpts.UnifiedLTO)
-  TheModule->addModuleFlag(llvm::Module::Error, "UnifiedLTO", 
uint32_t(1));
   }
-  if (Action == Backend_EmitBC)
+  if (Action == Backend_EmitBC) {
 MPM.addPass(BitcodeWriterPass(*OS, CodeGenOpts.EmitLLVMUseLists,
   EmitLTOSummary));
-  else
+  } else if (Action == Backend_EmitLL) {
 MPM.addPass(PrintModulePass(*OS, "", CodeGenOpts.EmitLLVMUseLists,
 EmitLTOSummary));
+  }
 }
-  }
-  if (CodeGenOpts.FatLTO) {
-// Set the EnableSplitLTOUnit and UnifiedLTO module flags, since FatLTO
-// uses a 
diff erent action than Backend_EmitBC or Backend_EmitLL.
-if (!TheModule->getModuleFlag("EnableSplitLTOUnit"))
-  TheModule->addModuleFlag(llvm::Module::Error, "EnableSplitLTOUnit",
-   uint32_t(CodeGenOpts.EnableSplitLTOUnit));
-if (CodeGenOpts.UnifiedLTO && !TheModule->getModuleFlag("UnifiedLTO"))
+
+if (shouldEmitUnifiedLTOModueFlag())
   TheModule->addModuleFlag(llvm::Module::Error, "UnifiedLTO", uint32_t(1));
   }
 

diff  --git a/clang/test/CodeGen/fat-lto-objects.c 
b/clang/test/CodeGen/fat-lto-objects.c
index afce798c5c8194..b50567c024fc8c 100644
--- a/clang/test/CodeGen/fat-lto-objects.c
+++ b/clang/test/CodeGen/fat-lto-objects.c
@@ -11,10 +11,11 @@
 // RUN: llvm-objcopy --dump-section=.llvm.lto=%t.full.split.bc %t.full.split.o
 // RUN: llvm-dis %t.full.split.bc -o - | FileCheck %s 
--check-prefixes=FULL,SPLIT,NOUNIFIED
 
+/// Full LTO always sets EnableSplitLTOUnit when the summary is used.
 // RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full 
-ffat-lto-objects -emit-obj < %s -o %t.full.nosplit.o
 // RUN: llvm-readelf -S

[llvm-branch-commits] [llvm] Lld mac fix (PR #84764)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/84764

>From 2ddb32b50752ca91ca9946cb9c9ea3d92c8616d0 Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Sat, 9 Mar 2024 14:26:47 -0800
Subject: [PATCH 1/2] Bump version to 18.1.2

---
 llvm/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index ddf95cbc6c5175..c5fa66390bba8d 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 1)
+  set(LLVM_VERSION_PATCH 2)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX)

>From 9edcbcbb219c221521894b04e668b6f9f450497f Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Mon, 11 Mar 2024 07:28:58 -0700
Subject: [PATCH 2/2] workflows: Add workaround for lld failures on MacOS

See #81967
---
 .github/workflows/llvm-project-tests.yml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/.github/workflows/llvm-project-tests.yml 
b/.github/workflows/llvm-project-tests.yml
index 43b90193406fc9..64788457fb6d60 100644
--- a/.github/workflows/llvm-project-tests.yml
+++ b/.github/workflows/llvm-project-tests.yml
@@ -118,6 +118,11 @@ jobs:
   else
 builddir="$(pwd)"/build
   fi
+  if [ "${{ runner.os }}" == "MacOS" ]; then
+# Workaround test failure on some lld tests on MacOS
+# https://github.com/llvm/llvm-project/issues/81967
+extra_cmake_args="-DLLVM_DISABLE_ASSEMBLY_FILES=ON"
+  fi
   echo "llvm-builddir=$builddir" >> "$GITHUB_OUTPUT"
   cmake -G Ninja \
 -B "$builddir" \

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[llvm-branch-commits] [llvm] release/18.x: Allow .alt_entry symbols to pass the .cfi nesting check (#82268) (PR #83336)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83336
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[llvm-branch-commits] [llvm] 267d9b1 - Allow .alt_entry symbols to pass the .cfi nesting check (#82268)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Jon Roelofs
Date: 2024-03-11T12:35:50-07:00
New Revision: 267d9b1a74c466fff6bde255a211732aa3bcd7e8

URL: 
https://github.com/llvm/llvm-project/commit/267d9b1a74c466fff6bde255a211732aa3bcd7e8
DIFF: 
https://github.com/llvm/llvm-project/commit/267d9b1a74c466fff6bde255a211732aa3bcd7e8.diff

LOG: Allow .alt_entry symbols to pass the .cfi nesting check (#82268)

A symbol with an `N_ALT_ENTRY` attribute may be defined in the middle of
a subsection, so it is reasonable to opt them out of the
`.cfi_{start,end}proc` nesting check.

Fixes: https://github.com/llvm/llvm-project/issues/82261
(cherry picked from commit 5b91647e3f82c9747c42c3239b7d7f3ade4542a7)

Added: 


Modified: 
llvm/lib/MC/MCParser/AsmParser.cpp
llvm/test/MC/AArch64/cfi-bad-nesting-darwin.s

Removed: 




diff  --git a/llvm/lib/MC/MCParser/AsmParser.cpp 
b/llvm/lib/MC/MCParser/AsmParser.cpp
index 8e508dbdb1c69b..026d252ec5bcd7 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -44,6 +44,7 @@
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCSymbolMachO.h"
 #include "llvm/MC/MCTargetOptions.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/Casting.h"
@@ -1950,7 +1951,8 @@ bool AsmParser::parseStatement(ParseStatementInfo ,
   Lex();
 }
 
-if (MAI.hasSubsectionsViaSymbols() && CFIStartProcLoc && Sym->isExternal())
+if (MAI.hasSubsectionsViaSymbols() && CFIStartProcLoc &&
+Sym->isExternal() && !cast(Sym)->isAltEntry())
   return Error(StartTokLoc, "non-private labels cannot appear between "
 ".cfi_startproc / .cfi_endproc pairs") &&
  Error(*CFIStartProcLoc, "previous .cfi_startproc was here");

diff  --git a/llvm/test/MC/AArch64/cfi-bad-nesting-darwin.s 
b/llvm/test/MC/AArch64/cfi-bad-nesting-darwin.s
index 235b7d44809929..3a5af86defc592 100644
--- a/llvm/test/MC/AArch64/cfi-bad-nesting-darwin.s
+++ b/llvm/test/MC/AArch64/cfi-bad-nesting-darwin.s
@@ -8,6 +8,10 @@
.p2align2
 _locomotive:
.cfi_startproc
+   ; An N_ALT_ENTRY symbol can be defined in the middle of a subsection, so
+   ; these are opted out of the .cfi_{start,end}proc nesting check.
+   .alt_entry _engineer
+_engineer:
ret
 
; It is invalid to have a non-private label between .cfi_startproc and
@@ -17,7 +21,7 @@ _locomotive:
.p2align2
 _caboose:
 ; DARWIN: [[#@LINE-1]]:1: error: non-private labels cannot appear between 
.cfi_startproc / .cfi_endproc pairs
-; DARWIN: [[#@LINE-10]]:2: error: previous .cfi_startproc was here
+; DARWIN: [[#@LINE-14]]:2: error: previous .cfi_startproc was here
ret
.cfi_endproc
 



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[llvm-branch-commits] [llvm] release/18.x: MIPS: fix emitDirectiveCpsetup on N32 (#80534) (PR #83198)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83198
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[llvm-branch-commits] [llvm] 340ba45 - MIPS: fix emitDirectiveCpsetup on N32 (#80534)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: YunQiang Su
Date: 2024-03-11T12:32:11-07:00
New Revision: 340ba4588c8073f97b03fd5da9a4fd5dc3b27d2e

URL: 
https://github.com/llvm/llvm-project/commit/340ba4588c8073f97b03fd5da9a4fd5dc3b27d2e
DIFF: 
https://github.com/llvm/llvm-project/commit/340ba4588c8073f97b03fd5da9a4fd5dc3b27d2e.diff

LOG: MIPS: fix emitDirectiveCpsetup on N32 (#80534)

In gas, .cpsetup may expand to one of two code sequences (one is related to 
`__gnu_local_gp`), depending on -mno-shared and -msym32.
Since Clang doesn't support -mno-shared or -msym32, .cpsetup expands to one 
code sequence.
The N32 condition incorrectly leads to the incorrect `__gnu_local_gp` code 
sequence.

```
 :
   0:   ffbc0008sd  gp,8(sp)
   4:   3c1clui gp,0x0
4: R_MIPS_HI16  __gnu_local_gp
   8:   279caddiu   gp,gp,0
8: R_MIPS_LO16  __gnu_local_gp
```

Fixes: #52785
(cherry picked from commit 860b6edfa9b344fbf8c500c17158c8212ea87d1c)

Added: 


Modified: 
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/test/MC/Mips/cpsetup.s

Removed: 




diff  --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 
b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index 27d7f0f261d100..adfcea73615831 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -1255,7 +1255,9 @@ void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned 
RegNo,
 emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), );
   }
 
-  if (getABI().IsN32()) {
+#if 0
+  // We haven't support -mabicalls -mno-shared yet.
+  if (-mno-shared) {
 MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
 const MipsMCExpr *HiExpr = MipsMCExpr::create(
 MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
@@ -1273,6 +1275,7 @@ void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned 
RegNo,
 
 return;
   }
+#endif
 
   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
   MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(, MCA.getContext()),
@@ -1288,8 +1291,11 @@ void 
MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
   emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
   );
 
-  // daddu  $gp, $gp, $funcreg
-  emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), );
+  // (d)addu  $gp, $gp, $funcreg
+  if (getABI().IsN32())
+emitRRR(Mips::ADDu, GPReg, GPReg, RegNo, SMLoc(), );
+  else
+emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), );
 }
 
 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,

diff  --git a/llvm/test/MC/Mips/cpsetup.s b/llvm/test/MC/Mips/cpsetup.s
index 8e587aea3e7e69..4a027c6e796aea 100644
--- a/llvm/test/MC/Mips/cpsetup.s
+++ b/llvm/test/MC/Mips/cpsetup.s
@@ -4,8 +4,6 @@
 # RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 %s | \
 # RUN:   FileCheck -check-prefixes=ASM,ASM-O32 %s
 
-# FIXME: Now we check .cpsetup expansion for `-mno-shared` case only.
-#We also need to implement/check the `-mshared` case.
 # RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 -filetype=obj -o - 
%s | \
 # RUN:   llvm-objdump --no-print-imm-hex -d -r -z - | \
 # RUN:   FileCheck -check-prefixes=ALL,NXX,N32 %s
@@ -35,11 +33,16 @@ t1:
 
 # NXX-NEXT: sd   $gp, 8($sp)
 # NXX-NEXT: lui  $gp, 0
-# N32-NEXT: R_MIPS_HI16 __gnu_local_gp
 # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  __cerror
+# N32-NEXT: R_MIPS_GPREL16 __cerror
+# N32-NEXT: R_MIPS_SUB
+# N32-NEXT: R_MIPS_HI16
 # NXX-NEXT: addiu$gp, $gp, 0
-# N32-NEXT: R_MIPS_LO16 __gnu_local_gp
 # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  __cerror
+# N32-NEXT: R_MIPS_GPREL16 __cerror
+# N32-NEXT: R_MIPS_SUB
+# N32-NEXT: R_MIPS_LO16
+# N32-NEXT: addu $gp, $gp, $25
 # N64-NEXT: daddu$gp, $gp, $25
 
 # ASM-NEXT: .cpsetup $25, 8, __cerror
@@ -64,11 +67,16 @@ t2:
 
 # NXX-NEXT: move $2, $gp
 # NXX-NEXT: lui  $gp, 0
-# N32-NEXT: R_MIPS_HI16 __gnu_local_gp
 # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  __cerror
+# N32-NEXT: R_MIPS_GPREL16 __cerror
+# N32-NEXT: R_MIPS_SUB
+# N32-NEXT: R_MIPS_HI16
 # NXX-NEXT: addiu$gp, $gp, 0
-# N32-NEXT: R_MIPS_LO16 __gnu_local_gp
 # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  __cerror
+# N32-NEXT: R_MIPS_GPREL16 __cerror
+# N32-NEXT: R_MIPS_SUB
+# N32-NEXT: R_MIPS_LO16
+# N32-NEXT: addu $gp, $gp, $25
 # N64-NEXT: daddu$gp, $gp, $25
 
 # ASM-NEXT: .cpsetup $25, $2, __cerror
@@ -101,11 +109,16 @@ t3:
 
 # NXX-NEXT: move $2, $gp
 # NXX-NEXT: lui  $gp, 0
-# N32-NEXT: {{^ *0+}}38: R_MIPS_HI16 __gnu_local_gp
 # N64-NEXT: {{^ *0+}}40: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 .text
+# N32-NEXT: {{^ *0+}}40: R_MIPS_GPREL16 .text
+# N32-NEXT: R_MIPS_SUB
+# N32-NEXT: R_MIPS_HI16
 # NXX-NEXT: addiu$gp, $gp, 0
-# N32-NEXT: {{^

[llvm-branch-commits] [libcxx] release/18.x: [libc++][modules] Fixes naming inconsistency. (#83036) (PR #83156)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83156
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[llvm-branch-commits] [libcxx] 439e6f8 - [libc++][modules] Fixes naming inconsistency. (#83036)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


Author: Mark de Wever
Date: 2024-03-11T12:24:53-07:00
New Revision: 439e6f81e772956200aa797eab819b72bb64f84b

URL: 
https://github.com/llvm/llvm-project/commit/439e6f81e772956200aa797eab819b72bb64f84b
DIFF: 
https://github.com/llvm/llvm-project/commit/439e6f81e772956200aa797eab819b72bb64f84b.diff

LOG: [libc++][modules] Fixes naming inconsistency. (#83036)

The modules used is-standard-library and is-std-library. The latter is
the name used in the SG15 proposal,

Fixes: https://github.com/llvm/llvm-project/issues/82879
(cherry picked from commit b50bcc7ffb6ad6caa4c141a22915ab59f725b7ae)

Added: 


Modified: 
libcxx/modules/modules.json.in

Removed: 




diff  --git a/libcxx/modules/modules.json.in b/libcxx/modules/modules.json.in
index ddc377f28f9194..759ac92d81f18e 100644
--- a/libcxx/modules/modules.json.in
+++ b/libcxx/modules/modules.json.in
@@ -5,7 +5,7 @@
 {
   "logical-name": "std",
   "source-path": "@LIBCXX_MODULE_RELATIVE_PATH@/std.cppm",
-  "is-standard-library": true,
+  "is-std-library": true,
   "local-arguments": {
 "system-include-directories": [
   "@LIBCXX_MODULE_RELATIVE_PATH@"



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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/81800

>From 064dd621c19b3738af5db29afd5b986a6d739ab1 Mon Sep 17 00:00:00 2001
From: Billy Laws 
Date: Wed, 31 Jan 2024 02:32:15 +
Subject: [PATCH 1/3] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 10 -
 llvm/test/CodeGen/AArch64/arm64ec-varargs.ll  | 37 +++
 llvm/test/CodeGen/AArch64/vararg-tallcall.ll  |  8 
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0287856560e91a..196aa50cf4060b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo ,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-windows-msvc %s -o - | FileCheck %s
 ;

[llvm-branch-commits] [llvm] Bump version to 18.1.2 (PR #84655)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84655
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[llvm-branch-commits] [llvm] Lld mac fix (PR #84764)

2024-03-11 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar created 
https://github.com/llvm/llvm-project/pull/84764

None

>From 2ddb32b50752ca91ca9946cb9c9ea3d92c8616d0 Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Sat, 9 Mar 2024 14:26:47 -0800
Subject: [PATCH 1/2] Bump version to 18.1.2

---
 llvm/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index ddf95cbc6c5175..c5fa66390bba8d 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 1)
+  set(LLVM_VERSION_PATCH 2)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX)

>From 57acd9c5beb3f8dd9cfedac38dca6fd66e68fb2e Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Mon, 11 Mar 2024 07:28:58 -0700
Subject: [PATCH 2/2] workflows: Add workaround for lld failures on MacOS

See #81967
---
 .github/workflows/llvm-project-tests.yml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/.github/workflows/llvm-project-tests.yml 
b/.github/workflows/llvm-project-tests.yml
index 43b90193406fc9..5b28aed576641b 100644
--- a/.github/workflows/llvm-project-tests.yml
+++ b/.github/workflows/llvm-project-tests.yml
@@ -118,6 +118,11 @@ jobs:
   else
 builddir="$(pwd)"/build
   fi
+  if [ "${{ runner.os }}" == "MacOS" ]; then
+# Workaround test failure on some lld tests on MacOS
+# https://github.com/llvm/llvm-project/issues/81967
+extra_cmake_args="LLVM_DISABLE_ASSEMBLY_FILES=ON"
+  fi
   echo "llvm-builddir=$builddir" >> "$GITHUB_OUTPUT"
   cmake -G Ninja \
 -B "$builddir" \

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[llvm-branch-commits] [llvm] Bump version to 18.1.2 (PR #84655)

2024-03-09 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar created 
https://github.com/llvm/llvm-project/pull/84655

None

>From 2ddb32b50752ca91ca9946cb9c9ea3d92c8616d0 Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Sat, 9 Mar 2024 14:26:47 -0800
Subject: [PATCH] Bump version to 18.1.2

---
 llvm/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index ddf95cbc6c5175..c5fa66390bba8d 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 1)
+  set(LLVM_VERSION_PATCH 2)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX)

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[llvm-branch-commits] [llvm] Remove RC suffix (PR #84430)

2024-03-08 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84430
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[llvm-branch-commits] [llvm] dba2a75 - Bump version to 18.1.1

2024-03-08 Thread Tom Stellard via llvm-branch-commits


Author: Tom Stellard
Date: 2024-03-07T21:27:31-08:00
New Revision: dba2a75e9c7ef81fe84774ba5eee5e67e01d801a

URL: 
https://github.com/llvm/llvm-project/commit/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a
DIFF: 
https://github.com/llvm/llvm-project/commit/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a.diff

LOG: Bump version to 18.1.1

Added: 


Modified: 
llvm/CMakeLists.txt

Removed: 




diff  --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 389bd8b6422da4..ddf95cbc6c5175 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 0)
+  set(LLVM_VERSION_PATCH 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX)



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[llvm-branch-commits] [llvm] b92012c - Remove RC suffix

2024-03-08 Thread Tom Stellard via llvm-branch-commits


Author: Tobias Hieta
Date: 2024-03-07T21:18:24-08:00
New Revision: b92012c777e602d557124583651313a0afa33484

URL: 
https://github.com/llvm/llvm-project/commit/b92012c777e602d557124583651313a0afa33484
DIFF: 
https://github.com/llvm/llvm-project/commit/b92012c777e602d557124583651313a0afa33484.diff

LOG: Remove RC suffix

Added: 


Modified: 
llvm/CMakeLists.txt

Removed: 




diff  --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 44f2850b92d522..389bd8b6422da4 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -25,7 +25,7 @@ if(NOT DEFINED LLVM_VERSION_PATCH)
   set(LLVM_VERSION_PATCH 0)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
-  set(LLVM_VERSION_SUFFIX rc)
+  set(LLVM_VERSION_SUFFIX)
 endif()
 
 if (NOT PACKAGE_VERSION)



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[llvm-branch-commits] [llvm] Remove RC suffix (PR #84430)

2024-03-07 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/84430

>From b92012c777e602d557124583651313a0afa33484 Mon Sep 17 00:00:00 2001
From: Tobias Hieta 
Date: Tue, 19 Sep 2023 09:44:33 +0200
Subject: [PATCH 1/2] Remove RC suffix

---
 llvm/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 44f2850b92d522..389bd8b6422da4 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -25,7 +25,7 @@ if(NOT DEFINED LLVM_VERSION_PATCH)
   set(LLVM_VERSION_PATCH 0)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
-  set(LLVM_VERSION_SUFFIX rc)
+  set(LLVM_VERSION_SUFFIX)
 endif()
 
 if (NOT PACKAGE_VERSION)

>From dba2a75e9c7ef81fe84774ba5eee5e67e01d801a Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Thu, 7 Mar 2024 21:27:31 -0800
Subject: [PATCH 2/2] Bump version to 18.1.1

---
 llvm/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 389bd8b6422da4..ddf95cbc6c5175 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 0)
+  set(LLVM_VERSION_PATCH 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX)

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[llvm-branch-commits] [llvm] Remove RC suffix (PR #84430)

2024-03-07 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar created 
https://github.com/llvm/llvm-project/pull/84430

None

>From b92012c777e602d557124583651313a0afa33484 Mon Sep 17 00:00:00 2001
From: Tobias Hieta 
Date: Tue, 19 Sep 2023 09:44:33 +0200
Subject: [PATCH] Remove RC suffix

---
 llvm/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 44f2850b92d522..389bd8b6422da4 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -25,7 +25,7 @@ if(NOT DEFINED LLVM_VERSION_PATCH)
   set(LLVM_VERSION_PATCH 0)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
-  set(LLVM_VERSION_SUFFIX rc)
+  set(LLVM_VERSION_SUFFIX)
 endif()
 
 if (NOT PACKAGE_VERSION)

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[llvm-branch-commits] [llvm] release/18.x: [cmake] Add minor version to library SONAME (#79376) (PR #82409)

2024-03-04 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

@RalfJung Are you configuring LLVM with 
-DLLVM_VERSION_SUFFIX=-rust-1.78.0-nightly ?

https://github.com/llvm/llvm-project/pull/82409
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[llvm-branch-commits] [llvm] release/18.x: [cmake] Add minor version to library SONAME (#79376) (PR #82409)

2024-03-04 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

@RalfJung The intention was that the change would be backwards compatible.  Is 
there a specific problem you see?  We can still fix this in the release/18.x 
branch if necessary.

https://github.com/llvm/llvm-project/pull/82409
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[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)

2024-02-27 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/83105
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[llvm-branch-commits] [llvm] 461274b - MIPS: Fix asm constraints "f" and "r" for softfloat (#79116)

2024-02-27 Thread Tom Stellard via llvm-branch-commits


Author: YunQiang Su
Date: 2024-02-27T09:18:54-08:00
New Revision: 461274b81d8641eab64d494accddc81d7db8a09e

URL: 
https://github.com/llvm/llvm-project/commit/461274b81d8641eab64d494accddc81d7db8a09e
DIFF: 
https://github.com/llvm/llvm-project/commit/461274b81d8641eab64d494accddc81d7db8a09e.diff

LOG: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116)

This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.

Currently, 'f' is accpeted by clang, then LLVM meets an internal error.

'r' is rejected by LLVM by: couldn't allocate input reg for constraint
'r'.

Fixes: #64241, #63632

-

Co-authored-by: Fangrui Song 
(cherry picked from commit c88beb4112d5bbf07d76a615ab7f13ba2ba023e6)

Added: 
clang/test/CodeGen/Mips/inline-asm-constraints.c
clang/test/Sema/inline-asm-validate-mips.c
llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll

Modified: 
clang/lib/Basic/Targets/Mips.h
llvm/lib/Target/Mips/MipsISelLowering.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..23d4e1b598fa1e 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -237,12 +237,14 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public 
TargetInfo {
 case 'r': // CPU registers.
 case 'd': // Equivalent to "r" unless generating MIPS16 code.
 case 'y': // Equivalent to "r", backward compatibility only.
-case 'f': // floating-point registers.
 case 'c': // $25 for indirect jumps
 case 'l': // lo register
 case 'x': // hilo register pair
   Info.setAllowsRegister();
   return true;
+case 'f': // floating-point registers.
+  Info.setAllowsRegister();
+  return FloatABI != SoftFloat;
 case 'I': // Signed 16-bit constant
 case 'J': // Integer 0
 case 'K': // Unsigned 16-bit constant

diff  --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c 
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00..88afe8735083b4
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -emit-llvm -triple mips -target-feature +soft-float %s -o - 
| FileCheck %s --check-prefix=SOFT_FLOAT
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(float %1)
+void read_float(float *p) {
+  __asm__("" ::"r"(*p));
+}
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(double %1)
+void read_double(double *p) {
+  __asm__("" :: "r"(*p));
+}

diff  --git a/clang/test/Sema/inline-asm-validate-mips.c 
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00..7da248fe417b5c
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple mips64 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple mips64 -target-feature +soft-float -fsyntax-only 
-verify=softfloat %s
+
+// expected-no-diagnostics
+
+void test_f(float p) {
+  float result = p;
+  __asm__("" :: "f"(result)); // softfloat-error{{invalid input constraint 'f' 
in asm}}
+}

diff  --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp 
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d431d3d91494f6..88b226eaaccfab 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const 
TargetRegisterInfo *TRI,
 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
 case 'y': // Same as 'r'. Exists for compatibility.
 case 'r':
-  if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+  if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+   VT == MVT::i1) ||
+  (VT == MVT::f32 && Subtarget.useSoftFloat())) {
 if (Subtarget.inMips16Mode())
   return std::make_pair(0U, ::CPU16RegsRegClass);
 return std::make_pair(0U, ::GPR32RegClass);
   }
-  if (VT == MVT::i64 && !Subtarget.isGP64bit())
+  if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+  !Subtarget.isGP64bit())
 return std::make_pair(0U, ::GPR32RegClass);
-  if (VT == MVT::i64 && Subtarget.isGP64bit())
+  if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+  Subtarget.isGP64bit())
 return std::make_pair(0U, ::GPR64RegClass);
   // This will generate an error message
   return std::make_pair(0U, nullptr);

diff  --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll 
b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
new file mode 100644
index 00..705570f808ce00
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS:

[llvm-branch-commits] [lld] [llvm] release/18.x: [Mips] Fix unable to handle inline assembly ends with compat-branch o… (#77291) (PR #82870)

2024-02-27 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/82870
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[llvm-branch-commits] [llvm] e2182a6 - [Mips] Fix unable to handle inline assembly ends with compat-branch o… (#77291)

2024-02-27 Thread Tom Stellard via llvm-branch-commits


Author: yingopq
Date: 2024-02-27T09:17:42-08:00
New Revision: e2182a6b91f5001bd9b52e3b1fe6beac434e5fe5

URL: 
https://github.com/llvm/llvm-project/commit/e2182a6b91f5001bd9b52e3b1fe6beac434e5fe5
DIFF: 
https://github.com/llvm/llvm-project/commit/e2182a6b91f5001bd9b52e3b1fe6beac434e5fe5.diff

LOG: [Mips] Fix unable to handle inline assembly ends with compat-branch o… 
(#77291)

…n MIPS

Modify:
Add a global variable 'CurForbiddenSlotAttr' to save current
instruction's forbidden slot and whether set reorder. This is the
judgment condition for whether to add nop. We would add a couple of
'.set noreorder' and '.set reorder' to wrap the current instruction and
the next instruction.
Then we can get previous instruction`s forbidden slot attribute and
whether set reorder by 'CurForbiddenSlotAttr'.
If previous instruction has forbidden slot and .set reorder is active
and current instruction is CTI. Then emit a NOP after it.

Fix https://github.com/llvm/llvm-project/issues/61045.

Because https://reviews.llvm.org/D158589 was 'Needs Review' state, not
ending, so we commit pull request again.

(cherry picked from commit 96abee5eef31274415681018553e1d4a16dc16c9)

Added: 
llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll
llvm/test/MC/Mips/forbidden-slot.s

Modified: 
lld/test/ELF/mips-pc-relocs.s
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/test/MC/Mips/mips32r6/relocations.s
llvm/test/MC/Mips/mips64r6/relocations.s
llvm/test/MC/Mips/relocation.s

Removed: 




diff  --git a/lld/test/ELF/mips-pc-relocs.s b/lld/test/ELF/mips-pc-relocs.s
index 5e7dbed94ca7c4..7d23f9d7469a48 100644
--- a/lld/test/ELF/mips-pc-relocs.s
+++ b/lld/test/ELF/mips-pc-relocs.s
@@ -40,11 +40,13 @@ __start:
 # ^-- (0x20020-0x2)>>2
 # CHECK-NEXT:20004:   beqc$5, $6, 0x20020
 # ^-- (0x20020-4-0x20004)>>2
-# CHECK-NEXT:20008:   beqzc   $9, 0x20020
-# ^-- (0x20020-4-0x20008)>>2
-# CHECK-NEXT:2000c:   bc  0x20020
-# ^-- (0x20020-4-0x2000c)>>2
-# CHECK-NEXT:20010:   aluipc  $2, 0
-# ^-- %hi(0x20020-0x20010)
-# CHECK-NEXT:20014:   addiu   $2, $2, 12
-# ^-- %lo(0x20020-0x20014)
+# CHECK-NEXT:20008:   nop
+# CHECK-NEXT:2000c:   beqzc   $9, 0x20020
+# ^-- (0x20020-4-0x2000c)>>2
+# CHECK-NEXT:20010:   nop
+# CHECK-NEXT:20014:   bc  0x20020
+# ^-- (0x20020-4-0x200014)>>2
+# CHECK-NEXT:20018:   aluipc  $2, 0
+# ^-- %hi(0x20020-0x20018)
+# CHECK-NEXT:2001c:   addiu   $2, $2, 4
+# ^-- %lo(0x20020-0x2001c)

diff  --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 36aab383da68d2..9d6e8dc573a8d1 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -150,6 +150,7 @@ class MipsAsmParser : public MCTargetAsmParser {
   bool IsLittleEndian;
   bool IsPicEnabled;
   bool IsCpRestoreSet;
+  bool CurForbiddenSlotAttr;
   int CpRestoreOffset;
   unsigned GPReg;
   unsigned CpSaveLocation;
@@ -552,6 +553,7 @@ class MipsAsmParser : public MCTargetAsmParser {
 
 CurrentFn = nullptr;
 
+CurForbiddenSlotAttr = false;
 IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();
 
 IsCpRestoreSet = false;
@@ -723,6 +725,16 @@ class MipsAsmParser : public MCTargetAsmParser {
 return getSTI().hasFeature(Mips::FeatureGINV);
   }
 
+  bool hasForbiddenSlot(const MCInstrDesc ) const {
+return !inMicroMipsMode() && (MCID.TSFlags & MipsII::HasForbiddenSlot);
+  }
+
+  bool SafeInForbiddenSlot(const MCInstrDesc ) const {
+return !(MCID.TSFlags & MipsII::IsCTI);
+  }
+
+  void onEndOfFile() override;
+
   /// Warn if RegIndex is the same as the current AT.
   void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
 
@@ -2307,7 +2319,41 @@ bool MipsAsmParser::processInstruction(MCInst , 
SMLoc IDLoc,
 
   bool FillDelaySlot =
   MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
-  if (FillDelaySlot)
+
+  // Get previous instruction`s forbidden slot attribute and
+  // whether set reorder.
+  bool PrevForbiddenSlotAttr = CurForbiddenSlotAttr;
+
+  // Flag represents we set reorder after nop.
+  bool SetReorderAfterNop = false;
+
+  // If previous instruction has forbidden slot and .set reorder
+  // is active and current instruction is CTI.
+  // Then emit a NOP after it.
+  if (PrevForbiddenSlotAttr && !SafeInForbiddenSlot(MCID)) {
+TOut.emitEmptyDelaySlot(false, IDLoc, STI);
+//

[llvm-branch-commits] release/18.x: [llvm-shlib] Change libLLVM-$MAJOR.so symlink to point to versioned SO (#82660) (PR #83067)

2024-02-27 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

Merged: 4cc7a75aa6ac272a5774ef7ca3f6b2ad095425e3

https://github.com/llvm/llvm-project/pull/83067
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[llvm-branch-commits] [clang] 8328334 - [AArch64] Add the Ampere1B core (#81297)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


Author: Philipp Tomsich
Date: 2024-02-26T17:38:41-08:00
New Revision: 83283342c38e03fc501c84b9fad7cd62f1d629d3

URL: 
https://github.com/llvm/llvm-project/commit/83283342c38e03fc501c84b9fad7cd62f1d629d3
DIFF: 
https://github.com/llvm/llvm-project/commit/83283342c38e03fc501c84b9fad7cd62f1d629d3.diff

LOG: [AArch64] Add the Ampere1B core (#81297)

The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-channel mitigation and architectural support for
defense against ROP/JOP style software attacks.

Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT
WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all
features of the second-generation Ampere1A, such as the Memory Tagging
Extension and SM3/SM4 cryptography instructions.

(cherry picked from commit fbba818a78f591d89f25768ba31783714d526532)

Added: 


Modified: 
clang/test/Driver/aarch64-cssc.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/TargetParser/Host.cpp
llvm/test/CodeGen/AArch64/cpus.ll
llvm/test/CodeGen/AArch64/neon-dot-product.ll
llvm/test/CodeGen/AArch64/remat.ll
llvm/test/MC/AArch64/armv8.2a-dotprod.s
llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
llvm/unittests/TargetParser/Host.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp

Removed: 




diff  --git a/clang/test/Driver/aarch64-cssc.c 
b/clang/test/Driver/aarch64-cssc.c
index a3e18663279bbd..5df0ea79d7c850 100644
--- a/clang/test/Driver/aarch64-cssc.c
+++ b/clang/test/Driver/aarch64-cssc.c
@@ -9,6 +9,7 @@
 // RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a   
 %s 2>&1 | FileCheck %s
 // RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf 
-march=armv9.4-a+cssc   %s 2>&1 | FileCheck %s
 // RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf 
-march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -mcpu=ampere1b 
 %s 2>&1 | FileCheck %s
 
 // CHECK: "target-features"="{{.*}},+cssc
 // NO_CSSC: "target-features"="{{.*}},-cssc

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 2f10bfb1fd82fe..39ed02f50950dd 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, 
cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, 
cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, 
cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, 
neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, 
neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, 
grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, 
cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, 
cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, 
cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, 
neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, 
neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, 
cobalt-100, grace{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, 
cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64] Backport Ampere1B support (#81297 , #81341, and #81744) (PR #81857)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81857
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[llvm-branch-commits] [llvm] 6d8f929 - [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1 (#81744)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


Author: Philipp Tomsich
Date: 2024-02-26T17:38:41-08:00
New Revision: 6d8f9290b6afa5e61841124ae1bdeb96d9ada820

URL: 
https://github.com/llvm/llvm-project/commit/6d8f9290b6afa5e61841124ae1bdeb96d9ada820
DIFF: 
https://github.com/llvm/llvm-project/commit/6d8f9290b6afa5e61841124ae1bdeb96d9ada820.diff

LOG: [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1 (#81744)

One of the whitespace fixes didn't get added to the commit introducing
the Ampere1B model.
Clean it up.

(cherry picked from commit 3369e341288b3d9bb59827f9a2911ebf3d36408d)

Added: 


Modified: 
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td 
b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 7e041dbd2abaea..613db353cb0aaa 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -29,7 +29,7 @@ def NeoverseV1Model : SchedMachineModel {
   list UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
 SMEUnsupported.F,
 [HasMTE, HasCPA,
-   HasCSSC]);
+HasCSSC]);
 }
 
 
//===--===//



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[llvm-branch-commits] [clang] b4b76bd - [AArch64] Make +pauth enabled in Armv8.3-a by default (#78027)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


Author: Anatoly Trosinenko
Date: 2024-02-26T17:38:41-08:00
New Revision: b4b76bdbf1dab6199e4112781f37e96f1902bfcd

URL: 
https://github.com/llvm/llvm-project/commit/b4b76bdbf1dab6199e4112781f37e96f1902bfcd
DIFF: 
https://github.com/llvm/llvm-project/commit/b4b76bdbf1dab6199e4112781f37e96f1902bfcd.diff

LOG: [AArch64] Make +pauth enabled in Armv8.3-a by default (#78027)

Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.

After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed
when trying to format an error message, thus update a format string in
AssertSameExtensionFlags to account for bitmask being pre-formatted as
std::string.

The CHECK-PAUTH* lines in aarch64-target-features.c are updated to
account for the fact that FEAT_PAUTH support and pac-ret can be enabled
independently and all four combinations are possible.

(cherry picked from commit a52eea66795018550e95c4b060165a7250899298)

Added: 


Modified: 
clang/lib/Basic/Targets/AArch64.cpp
clang/test/CodeGen/aarch64-targetattr.c
clang/test/Preprocessor/aarch64-target-features.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/unittests/TargetParser/TargetParserTest.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index 3036f461c1ded1..f5a5d689fa095c 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -258,7 +258,6 @@ void AArch64TargetInfo::getTargetDefinesARMV83A(const 
LangOptions ,
 MacroBuilder ) const {
   Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
   Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
-  Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
   // Also include the Armv8.2 defines
   getTargetDefinesARMV82A(Opts, Builder);
 }

diff  --git a/clang/test/CodeGen/aarch64-targetattr.c 
b/clang/test/CodeGen/aarch64-targetattr.c
index 02da18264da0a3..1a3a84a73dbad1 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -97,19 +97,19 @@ void minusarch() {}
 // CHECK: attributes #0 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
 // CHECK: attributes #1 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
 }
 // CHECK: attributes #2 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
 }
-// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
+// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
 // CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm"
 }
 // CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" }
 // CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" }
 // CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" }
 // CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" 
"target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs"
 "tune-cpu"="cortex-a710" }
 // CHECK: attributes #9 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2"
 }
-// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve"
 }
+// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2"
 }
+// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve"
 }
 // CHECK: attributes #12 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
 // CHECK: attributes #13 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
 // CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" }
-//

[llvm-branch-commits] [clang] [Clang] Fixes to immediate-escalating functions (#82281) (PR #82609)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

Merged a7a74ece1d6b8dc95bf6fb0b7e06b8e0ba9b9559

https://github.com/llvm/llvm-project/pull/82609
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[llvm-branch-commits] [clang] [Clang] Fixes to immediate-escalating functions (#82281) (PR #82609)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/82609
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[llvm-branch-commits] [clang] a7a74ec - [Clang] Fixes to immediate-escalating functions (#82281)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


Author: cor3ntin
Date: 2024-02-26T17:03:46-08:00
New Revision: a7a74ece1d6b8dc95bf6fb0b7e06b8e0ba9b9559

URL: 
https://github.com/llvm/llvm-project/commit/a7a74ece1d6b8dc95bf6fb0b7e06b8e0ba9b9559
DIFF: 
https://github.com/llvm/llvm-project/commit/a7a74ece1d6b8dc95bf6fb0b7e06b8e0ba9b9559.diff

LOG: [Clang] Fixes to immediate-escalating functions (#82281)

* Consider that immediate escalating function can appear at global
scope, fixing a crash

* Lambda conversion to function pointer was sometimes not performed in
an immediate function context when it should be.

Fixes #82258

(cherry picked from commit baf6bd303bd58a521809d456dd9b179636982fc5)

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaExpr.cpp
clang/test/SemaCXX/cxx2b-consteval-propagate.cpp

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 2411e97c750c72..fc27297aea2d6c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1099,6 +1099,11 @@ Bug Fixes to C++ Support
 - Fix incorrect code generation caused by the object argument of ``static 
operator()`` and ``static operator[]`` calls not being evaluated.
   Fixes (`#67976 `_)
 
+- Fix crash when using an immediate-escalated function at global scope.
+  (`#82258 `_)
+- Correctly immediate-escalate lambda conversion functions.
+  (`#82258 `_)
+
 Bug Fixes to AST Handling
 ^
 - Fixed an import failure of recursive friend class template.

diff  --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 1f1cbd11ff7358..6adb8fb7966b3f 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -1090,7 +1090,9 @@ class Sema final {
   if (FD) {
 FD->setWillHaveBody(true);
 S.ExprEvalContexts.back().InImmediateFunctionContext =
-FD->isImmediateFunction();
+FD->isImmediateFunction() ||
+S.ExprEvalContexts[S.ExprEvalContexts.size() - 2]
+.isConstantEvaluated();
 S.ExprEvalContexts.back().InImmediateEscalatingFunctionContext =
 S.getLangOpts().CPlusPlus20 && FD->isImmediateEscalating();
   } else

diff  --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 0d9c087ed0cd19..4cce0abc231505 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -18294,7 +18294,6 @@ void Sema::CheckUnusedVolatileAssignment(Expr *E) {
 }
 
 void Sema::MarkExpressionAsImmediateEscalating(Expr *E) {
-  assert(!FunctionScopes.empty() && "Expected a function scope");
   assert(getLangOpts().CPlusPlus20 &&
  ExprEvalContexts.back().InImmediateEscalatingFunctionContext &&
  "Cannot mark an immediate escalating expression outside of an "
@@ -18311,7 +18310,8 @@ void Sema::MarkExpressionAsImmediateEscalating(Expr *E) 
{
   } else {
 assert(false && "expected an immediately escalating expression");
   }
-  getCurFunction()->FoundImmediateEscalatingExpression = true;
+  if (FunctionScopeInfo *FI = getCurFunction())
+FI->FoundImmediateEscalatingExpression = true;
 }
 
 ExprResult Sema::CheckForImmediateInvocation(ExprResult E, FunctionDecl *Decl) 
{

diff  --git a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp 
b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
index 531a6262287335..4a75392045d05a 100644
--- a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
+++ b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
@@ -368,3 +368,29 @@ vector v{};
 // expected-note@-2 {{in call to 'vector()'}}
 
 }
+
+
+namespace GH82258 {
+
+template 
+constexpr auto none_of(R&& r, Pred pred) -> bool { return true; }
+
+struct info { int value; };
+consteval auto is_invalid(info i) -> bool { return false; }
+constexpr info types[] = { {1}, {3}, {5}};
+
+static_assert(none_of(
+types,
++[](info i) consteval {
+return is_invalid(i);
+}
+));
+
+static_assert(none_of(
+types,
+[]{
+return is_invalid;
+}()
+));
+
+}



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[llvm-branch-commits] [llvm] 4cc7a75 - [llvm-shlib] Change libLLVM-$MAJOR.so symlink to point to versioned SO (#82660)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


Author: Tom Stellard
Date: 2024-02-26T16:57:21-08:00
New Revision: 4cc7a75aa6ac272a5774ef7ca3f6b2ad095425e3

URL: 
https://github.com/llvm/llvm-project/commit/4cc7a75aa6ac272a5774ef7ca3f6b2ad095425e3
DIFF: 
https://github.com/llvm/llvm-project/commit/4cc7a75aa6ac272a5774ef7ca3f6b2ad095425e3.diff

LOG: [llvm-shlib] Change libLLVM-$MAJOR.so symlink to point to versioned SO 
(#82660)

This symlink was added in 91a384621e5b762d9c173ffd247cfeadd5f436a2 to
maintain backwards compatibility, but it needs to point to
libLLVM.so.$MAJOR.$MINOR rather than libLLVM.so. This works better for
distros that ship libLLVM.so and libLLVM.so.$MAJOR.$MINOR in separate
packages and also prevents mistakes like
libLLVM-19.so -> libLLVM.so -> libLLVM.so.18.1

Fixes #82647

(cherry picked from commit 10c48a772742b7afe665a815b7eba2047f17dc4b)

Added: 


Modified: 
llvm/cmake/modules/AddLLVM.cmake
llvm/tools/llvm-shlib/CMakeLists.txt

Removed: 




diff  --git a/llvm/cmake/modules/AddLLVM.cmake 
b/llvm/cmake/modules/AddLLVM.cmake
index 5fc663d10b8f77..3bc78b0dc9355a 100644
--- a/llvm/cmake/modules/AddLLVM.cmake
+++ b/llvm/cmake/modules/AddLLVM.cmake
@@ -2074,7 +2074,7 @@ function(add_lit_testsuites project directory)
 endfunction()
 
 function(llvm_install_library_symlink name dest type)
-  cmake_parse_arguments(ARG "" "COMPONENT" "" ${ARGN})
+  cmake_parse_arguments(ARG "" "COMPONENT;SOVERSION" "" ${ARGN})
   foreach(path ${CMAKE_MODULE_PATH})
 if(EXISTS ${path}/LLVMInstallSymlink.cmake)
   set(INSTALL_SYMLINK ${path}/LLVMInstallSymlink.cmake)
@@ -2088,7 +2088,11 @@ function(llvm_install_library_symlink name dest type)
   endif()
 
   set(full_name 
${CMAKE_${type}_LIBRARY_PREFIX}${name}${CMAKE_${type}_LIBRARY_SUFFIX})
-  set(full_dest 
${CMAKE_${type}_LIBRARY_PREFIX}${dest}${CMAKE_${type}_LIBRARY_SUFFIX})
+  if (ARG_SOVERSION)
+set(full_dest 
${CMAKE_${type}_LIBRARY_PREFIX}${dest}${CMAKE_${type}_LIBRARY_SUFFIX}.${ARG_SOVERSION})
+  else()
+set(full_dest 
${CMAKE_${type}_LIBRARY_PREFIX}${dest}${CMAKE_${type}_LIBRARY_SUFFIX})
+  endif()
 
   if(LLVM_USE_SYMLINKS)
 set(LLVM_LINK_OR_COPY create_symlink)

diff  --git a/llvm/tools/llvm-shlib/CMakeLists.txt 
b/llvm/tools/llvm-shlib/CMakeLists.txt
index 09c15e304614c4..eba1672faee7fa 100644
--- a/llvm/tools/llvm-shlib/CMakeLists.txt
+++ b/llvm/tools/llvm-shlib/CMakeLists.txt
@@ -35,8 +35,8 @@ if(LLVM_BUILD_LLVM_DYLIB)
   endif()
   add_llvm_library(LLVM SHARED DISABLE_LLVM_LINK_LLVM_DYLIB OUTPUT_NAME LLVM 
${INSTALL_WITH_TOOLCHAIN} ${SOURCES})
   # Add symlink for backwards compatibility with old library name
-  get_target_property(LLVM_DYLIB_FILENAME LLVM OUTPUT_NAME)
-  
llvm_install_library_symlink(LLVM-${LLVM_VERSION_MAJOR}${LLVM_VERSION_SUFFIX} 
${LLVM_DYLIB_FILENAME} SHARED COMPONENT LLVM)
+  get_target_property(LLVM_DYLIB_SOVERSION LLVM SOVERSION)
+  
llvm_install_library_symlink(LLVM-${LLVM_VERSION_MAJOR}${LLVM_VERSION_SUFFIX} 
LLVM SHARED COMPONENT LLVM SOVERSION ${LLVM_DYLIB_SOVERSION})
 
   list(REMOVE_DUPLICATES LIB_NAMES)
   if("${CMAKE_SYSTEM_NAME}" STREQUAL "Darwin")



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[llvm-branch-commits] [llvm] [llvm][AArch64] Do not inline a function with different signing scheme. (#80642) (PR #82743)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/82743
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[llvm-branch-commits] [clang] release/18.x: [clang][CodeGen] Keep processing the rest of AST after encountering unsupported MC/DC expressions (#82464) (PR #82866)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/82866
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[llvm-branch-commits] [clang] 9274829 - [clang][CodeGen] Keep processing the rest of AST after encountering unsupported MC/DC expressions (#82464)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


Author: Wentao Zhang
Date: 2024-02-26T15:09:20-08:00
New Revision: 9274829eb689c261aecf7b100561594385816b0b

URL: 
https://github.com/llvm/llvm-project/commit/9274829eb689c261aecf7b100561594385816b0b
DIFF: 
https://github.com/llvm/llvm-project/commit/9274829eb689c261aecf7b100561594385816b0b.diff

LOG: [clang][CodeGen] Keep processing the rest of AST after encountering 
unsupported MC/DC expressions (#82464)

Currently, upon seeing unsupported decisions (more than 6 conditions, or
split nesting), the post-visitor hook dataTraverseStmtPost() returns a
false. As a result, in the rest of tree even supported decisions will
be skipped as well. Like in the below code:

{ // CompoundStmt
  a && b;   // 1: BinaryOperator (supported)
  a && foo(b && c); // 2: BinaryOperator (not yet supported due to split
//nesting)
  a && b;   // 3: BinaryOperator (supported)
}

Decision 3 will not be processed at all. And only one "Decision" region
will be emitted. Compiler explorer example:
https://godbolt.org/z/Px61sesoo

We hope to process such cases and emit two "Decision" regions (1 and 3)
in the above example.

(cherry picked from commit d4bfca3b2e673789f7c278d46a199ae8910ddd37)

Added: 


Modified: 
clang/lib/CodeGen/CodeGenPGO.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CodeGenPGO.cpp 
b/clang/lib/CodeGen/CodeGenPGO.cpp
index 5d7c3847745762..fb4e86e8bd8053 100644
--- a/clang/lib/CodeGen/CodeGenPGO.cpp
+++ b/clang/lib/CodeGen/CodeGenPGO.cpp
@@ -240,9 +240,12 @@ struct MapRegionCounters : public 
RecursiveASTVisitor {
 if (MCDCMaxCond == 0)
   return true;
 
-/// At the top of the logical operator nest, reset the number of 
conditions.
-if (LogOpStack.empty())
+/// At the top of the logical operator nest, reset the number of 
conditions,
+/// also forget previously seen split nesting cases.
+if (LogOpStack.empty()) {
   NumCond = 0;
+  SplitNestedLogicalOp = false;
+}
 
 if (const Expr *E = dyn_cast(S)) {
   const BinaryOperator *BinOp = 
dyn_cast(E->IgnoreParens());
@@ -293,7 +296,7 @@ struct MapRegionCounters : public 
RecursiveASTVisitor {
 "contains an operation with a nested boolean expression. "
 "Expression will not be covered");
 Diag.Report(S->getBeginLoc(), DiagID);
-return false;
+return true;
   }
 
   /// Was the maximum number of conditions encountered?
@@ -304,7 +307,7 @@ struct MapRegionCounters : public 
RecursiveASTVisitor {
 "number of conditions (%0) exceeds max (%1). "
 "Expression will not be covered");
 Diag.Report(S->getBeginLoc(), DiagID) << NumCond << MCDCMaxCond;
-return false;
+return true;
   }
 
   // Otherwise, allocate the number of bytes required for the bitmap



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[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64] Backport Ampere1B support (#81297 , #81341, and #81744) (PR #81857)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


tstellar wrote:

I've decided to merge this.  A feature like this that is self-contained in a 
single backend is inline with the kind of changes I've merged before during the 
RC phase.  If this were some other feature, with a wider impact, it probably 
wouldn't be accepted.


https://github.com/llvm/llvm-project/pull/81857
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[llvm-branch-commits] [openmp] c8b11e9 - Fix build on musl by including stdint.h (#81434)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


Author: Daniel Martinez
Date: 2024-02-26T13:55:13-08:00
New Revision: c8b11e93004af9aa8bd8116e5cf01946546f0283

URL: 
https://github.com/llvm/llvm-project/commit/c8b11e93004af9aa8bd8116e5cf01946546f0283
DIFF: 
https://github.com/llvm/llvm-project/commit/c8b11e93004af9aa8bd8116e5cf01946546f0283.diff

LOG: Fix build on musl by including stdint.h (#81434)

openmp fails to build on musl since it lacks the defines for int32_t

Co-authored-by: Daniel Martinez 
(cherry picked from commit 45fe67dd61a6ac7df84d3a586e41c36a4767757f)

Added: 


Modified: 
openmp/libomptarget/include/Shared/SourceInfo.h

Removed: 




diff  --git a/openmp/libomptarget/include/Shared/SourceInfo.h 
b/openmp/libomptarget/include/Shared/SourceInfo.h
index 7ce5fd43efc07f..711f06a04d017f 100644
--- a/openmp/libomptarget/include/Shared/SourceInfo.h
+++ b/openmp/libomptarget/include/Shared/SourceInfo.h
@@ -13,6 +13,7 @@
 #ifndef OMPTARGET_SHARED_SOURCE_INFO_H
 #define OMPTARGET_SHARED_SOURCE_INFO_H
 
+#include 
 #include 
 
 #ifdef _WIN32



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[llvm-branch-commits] [openmp] release/18.x: Fix build on musl by including stdint.h (#81434) (PR #82897)

2024-02-26 Thread Tom Stellard via llvm-branch-commits


https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/82897
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