date:20161205

Re: [PATCH] drm/amdgpu: don't add files at control minor debugfs directory

2016-12-05 Thread Michel Dänzer

On 06/12/16 05:07 AM, Alex Deucher wrote:
> Since commit 8a357d10043c ("drm: Nerf DRM_CONTROL nodes"), a
> struct drm_device's ->control member is always NULL.
> 
> In the case of CONFIG_DEBUG_FS=y, amdgpu_debugfs_add_files() accesses
> ->control->debugfs_root though. This results in the following Oops:
> 
> [9.627636] BUG: unable to handle kernel NULL pointer dereference at 
> 0018
> [9.628274] IP: amdgpu_debugfs_add_files+0x8d/0x100 [amdgpu]
> [9.628867] PGD 2514c7067
> [9.628876] PUD 2514c8067
> [9.629448] PMD 0
> [9.630026] Oops:  [#1] PREEMPT SMP
> [...]
> [9.639906] Call Trace:
> [9.640538]  amdgpu_fence_driver_init+0x1e/0x40 [amdgpu]
> [9.641186]  amdgpu_device_init+0xa6d/0x1410 [amdgpu]
> [9.641900]  ? kmalloc_order_trace+0x2e/0x100
> [9.642587]  amdgpu_driver_load_kms+0x5b/0x200 [amdgpu]
> [9.643355]  drm_dev_register+0xa7/0xd0
> [9.644016]  drm_get_pci_dev+0xde/0x1d0
> [9.644659]  amdgpu_pci_probe+0xbe/0xf0 [amdgpu]
> [...]
> 
> Fix this by omitting the drm_debugfs_create_files() call for the
> control minor debugfs directory which is now non-existent anyway.
> 
> Port of Nicolai Stange's radeon patch to amdgpu.
> 
> bug: https://bugs.freedesktop.org/show_bug.cgi?id=98915

Not sure about the kernel, but in other projects the convention is

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98915


> Fixes: 8a357d10043c ("drm: Nerf DRM_CONTROL nodes")
> Signed-off-by: Alex Deucher 

Regardless of the above,

Reviewed-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/3] drm/amd/amdgpu: Add debugfs support for reading GPRs

2016-12-05 Thread Edward O'Callaghan

Hi Tom,

On 12/06/2016 05:36 AM, Tom St Denis wrote:
> Implemented for SGPRs for GFX v8 initially.
> 
> Signed-off-by: Tom St Denis 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 72 
> ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 25 +++
>  3 files changed, 99 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 4f64bb16a8d3..2834451eef8a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -844,6 +844,8 @@ struct amdgpu_gfx_funcs {
>   uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
>   void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 
> sh_num, u32 instance);
>   void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 
> uint32_t wave, uint32_t *dst, int *no_fields);
> + void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 
> uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
> + void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 
> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
>  };
>  
>  struct amdgpu_gfx {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 25ad736b5ca5..7f9cb1c85d75 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3055,6 +3055,71 @@ static ssize_t amdgpu_debugfs_wave_read(struct file 
> *f, char __user *buf,
>   return result;
>  }
>  
> +static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = f->f_inode->i_private;

Could f potentially be null here?

> + int r;
> + ssize_t result=0;

result = 0

> + uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
> +
> + if (size & 3 || *pos & 3)
> + return -EINVAL;
> +
> + /* decode offset */
> + offset = (*pos & 0xFFF);
> + se = ((*pos >> 12) & 0xFF);
> + sh = ((*pos >> 20) & 0xFF);
> + cu = ((*pos >> 28) & 0xFF);
> + wave = ((*pos >> 36) & 0xFF);
> + simd = ((*pos >> 44) & 0xFF);
> + thread = ((*pos >> 52) & 0xFF);
> + bank = ((*pos >> 60) & 1);
> +
> + /* sanity check offset/size */
> + if (offset + size > (adev->gfx.config.max_gprs << 2))
> + return -EINVAL;
> +
> + data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + /* switch to the specific se/sh/cu */
> + mutex_lock(>grbm_idx_mutex);
> + amdgpu_gfx_select_se_sh(adev, se, sh, cu);
> +
> + if (bank == 0) {
> + if (adev->gfx.funcs->read_wave_vgprs)
> + adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, 
> thread, offset>>2, size>>2, data);
> + } else {
> + if (adev->gfx.funcs->read_wave_sgprs)
> + adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, 
> offset>>2, size>>2, data);
> + }
> +
> + amdgpu_gfx_select_se_sh(adev, 0x, 0x, 0x);
> + mutex_unlock(>grbm_idx_mutex);
> +
> + while (size) {
> + uint32_t value;
> +
> + value = data[offset >> 2];
> + r = put_user(value, (uint32_t *)buf);
> + if (r) {
> + result = r;
> + goto err;
> + }
> +
> + result += 4;
> + buf += 4;
> + offset += 4;
> + size -= 4;
> + }
> +
> +err:
> + kfree(data);
> + return result;
> +}
> +
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>   .owner = THIS_MODULE,
>   .read = amdgpu_debugfs_regs_read,
> @@ -3097,6 +3162,11 @@ static const struct file_operations 
> amdgpu_debugfs_wave_fops = {
>   .read = amdgpu_debugfs_wave_read,
>   .llseek = default_llseek
>  };
> +static const struct file_operations amdgpu_debugfs_gpr_fops = {
> + .owner = THIS_MODULE,
> + .read = amdgpu_debugfs_gpr_read,
> + .llseek = default_llseek
> +};
>  
>  static const struct file_operations *debugfs_regs[] = {
>   _debugfs_regs_fops,
> @@ -3106,6 +3176,7 @@ static const struct file_operations *debugfs_regs[] = {
>   _debugfs_gca_config_fops,
>   _debugfs_sensors_fops,
>   _debugfs_wave_fops,
> + _debugfs_gpr_fops,
>  };
>  
>  static const char *debugfs_regs_names[] = {
> @@ -3116,6 +3187,7 @@ static const char *debugfs_regs_names[] = {
>   "amdgpu_gca_config",
>   "amdgpu_sensors",
>   "amdgpu_wave",
> + "amdgpu_gpr",
>  };
>  
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index

[PATCH 1/3] drm/amd/amdgpu: Add debugfs support for reading GPRs

2016-12-05 Thread Tom St Denis

Implemented for SGPRs for GFX v8 initially.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 72 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 25 +++
 3 files changed, 99 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4f64bb16a8d3..2834451eef8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -844,6 +844,8 @@ struct amdgpu_gfx_funcs {
uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 
sh_num, u32 instance);
void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t *dst, int *no_fields);
+   void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
+   void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
 };
 
 struct amdgpu_gfx {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 25ad736b5ca5..7f9cb1c85d75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3055,6 +3055,71 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, 
char __user *buf,
return result;
 }
 
+static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
+   size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = f->f_inode->i_private;
+   int r;
+   ssize_t result=0;
+   uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
+
+   if (size & 3 || *pos & 3)
+   return -EINVAL;
+
+   /* decode offset */
+   offset = (*pos & 0xFFF);
+   se = ((*pos >> 12) & 0xFF);
+   sh = ((*pos >> 20) & 0xFF);
+   cu = ((*pos >> 28) & 0xFF);
+   wave = ((*pos >> 36) & 0xFF);
+   simd = ((*pos >> 44) & 0xFF);
+   thread = ((*pos >> 52) & 0xFF);
+   bank = ((*pos >> 60) & 1);
+
+   /* sanity check offset/size */
+   if (offset + size > (adev->gfx.config.max_gprs << 2))
+   return -EINVAL;
+
+   data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
+   if (!data)
+   return -ENOMEM;
+
+   /* switch to the specific se/sh/cu */
+   mutex_lock(>grbm_idx_mutex);
+   amdgpu_gfx_select_se_sh(adev, se, sh, cu);
+
+   if (bank == 0) {
+   if (adev->gfx.funcs->read_wave_vgprs)
+   adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, 
thread, offset>>2, size>>2, data);
+   } else {
+   if (adev->gfx.funcs->read_wave_sgprs)
+   adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, 
offset>>2, size>>2, data);
+   }
+
+   amdgpu_gfx_select_se_sh(adev, 0x, 0x, 0x);
+   mutex_unlock(>grbm_idx_mutex);
+
+   while (size) {
+   uint32_t value;
+
+   value = data[offset >> 2];
+   r = put_user(value, (uint32_t *)buf);
+   if (r) {
+   result = r;
+   goto err;
+   }
+
+   result += 4;
+   buf += 4;
+   offset += 4;
+   size -= 4;
+   }
+
+err:
+   kfree(data);
+   return result;
+}
+
 static const struct file_operations amdgpu_debugfs_regs_fops = {
.owner = THIS_MODULE,
.read = amdgpu_debugfs_regs_read,
@@ -3097,6 +3162,11 @@ static const struct file_operations 
amdgpu_debugfs_wave_fops = {
.read = amdgpu_debugfs_wave_read,
.llseek = default_llseek
 };
+static const struct file_operations amdgpu_debugfs_gpr_fops = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_debugfs_gpr_read,
+   .llseek = default_llseek
+};
 
 static const struct file_operations *debugfs_regs[] = {
_debugfs_regs_fops,
@@ -3106,6 +3176,7 @@ static const struct file_operations *debugfs_regs[] = {
_debugfs_gca_config_fops,
_debugfs_sensors_fops,
_debugfs_wave_fops,
+   _debugfs_gpr_fops,
 };
 
 static const char *debugfs_regs_names[] = {
@@ -3116,6 +3187,7 @@ static const char *debugfs_regs_names[] = {
"amdgpu_gca_config",
"amdgpu_sensors",
"amdgpu_wave",
+   "amdgpu_gpr",
 };
 
 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 9b8d3fe67adb..180309f5784c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5184,6 +5184,21 @@ static uint32_t wave_read_ind(struct amdgpu_device 
*adev, uint32_t simd, uint32_
return

[PATCH 2/3] drm/amd/amdgpu: Add gpr reading for GFX v6

2016-12-05 Thread Tom St Denis

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index c0b2f4ebadea..01b58c65f37c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2827,6 +2827,21 @@ static uint32_t wave_read_ind(struct amdgpu_device 
*adev, uint32_t simd, uint32_
return RREG32(mmSQ_IND_DATA);
 }
 
+static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
+  uint32_t wave, uint32_t thread,
+  uint32_t regno, uint32_t num, uint32_t *out)
+{
+   WREG32(mmSQ_IND_INDEX,
+   (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
+   (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
+   (regno << SQ_IND_INDEX__INDEX__SHIFT) |
+   (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
+   (SQ_IND_INDEX__FORCE_READ_MASK) |
+   (SQ_IND_INDEX__AUTO_INCR_MASK));
+   while (num--)
+   *(out++) = RREG32(mmSQ_IND_DATA);
+}
+
 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t *dst, int *no_fields)
 {
/* type 0 wave data */
@@ -2851,10 +2866,20 @@ static void gfx_v6_0_read_wave_data(struct 
amdgpu_device *adev, uint32_t simd, u
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
 }
 
+static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
+uint32_t wave, uint32_t start,
+uint32_t size, uint32_t *dst)
+{
+   wave_read_regs(
+   adev, simd, wave, 0,
+   start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
+}
+
 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
.get_gpu_clock_counter = _v6_0_get_gpu_clock_counter,
.select_se_sh = _v6_0_select_se_sh,
.read_wave_data = _v6_0_read_wave_data,
+   .read_wave_sgprs = _v6_0_read_wave_sgprs,
 };
 
 static int gfx_v6_0_early_init(void *handle)
-- 
2.10.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/3] drm/amd/amdgpu: Add gpr reading for GFX v7

2016-12-05 Thread Tom St Denis

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index bbef2e86ea1f..4c4fb9bdd185 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4374,6 +4374,21 @@ static uint32_t wave_read_ind(struct amdgpu_device 
*adev, uint32_t simd, uint32_
return RREG32(mmSQ_IND_DATA);
 }
 
+static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
+  uint32_t wave, uint32_t thread,
+  uint32_t regno, uint32_t num, uint32_t *out)
+{
+   WREG32(mmSQ_IND_INDEX,
+   (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
+   (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
+   (regno << SQ_IND_INDEX__INDEX__SHIFT) |
+   (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
+   (SQ_IND_INDEX__FORCE_READ_MASK) |
+   (SQ_IND_INDEX__AUTO_INCR_MASK));
+   while (num--)
+   *(out++) = RREG32(mmSQ_IND_DATA);
+}
+
 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t *dst, int *no_fields)
 {
/* type 0 wave data */
@@ -4398,10 +4413,20 @@ static void gfx_v7_0_read_wave_data(struct 
amdgpu_device *adev, uint32_t simd, u
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
 }
 
+static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
+uint32_t wave, uint32_t start,
+uint32_t size, uint32_t *dst)
+{
+   wave_read_regs(
+   adev, simd, wave, 0,
+   start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
+}
+
 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
.get_gpu_clock_counter = _v7_0_get_gpu_clock_counter,
.select_se_sh = _v7_0_select_se_sh,
.read_wave_data = _v7_0_read_wave_data,
+   .read_wave_sgprs = _v7_0_read_wave_sgprs,
 };
 
 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
-- 
2.10.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

debugfs support for reading GPRs

2016-12-05 Thread Tom St Denis

The following patches add support for GFX v6, v7, and v8 to allow
userspace to read GPRs (SGPRs) via debugfs.  

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/2] drm/amdgpu/si: load the proper firmware on 0x87 oland boards

2016-12-05 Thread Alex Deucher

New variant.

Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 95c4e25..6c65a1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7716,6 +7716,7 @@ static int si_dpm_init_microcode(struct amdgpu_device 
*adev)
(adev->pdev->revision == 0x80) ||
(adev->pdev->revision == 0x81) ||
(adev->pdev->revision == 0x83) ||
+   (adev->pdev->revision == 0x87) ||
(adev->pdev->device == 0x6604) ||
(adev->pdev->device == 0x6605))
chip_name = "oland_k";
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: bypass fan table setup if no fan connected

2016-12-05 Thread Bernhard Froemel

On Thu, Dec 1, 2016 at 3:59 PM, Deucher, Alexander
 wrote:
>> -Original Message-
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Hawking Zhang
>> Sent: Thursday, December 01, 2016 4:16 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Zhang, Hawking
>> Subject: [PATCH] drm/amd/powerplay: bypass fan table setup if no fan
>> connected
>>
>> If vBIOS noFan bit is set, the fan table parameters in thermal controller
>> will not get initialized. The driver should avoid to use these uninitialized
>> parameter to do calculation. Otherwise, it may trigger divide 0 error.
>>
>> Change-Id: I76680a5ec5411f59742b65bb70eb7b4a08bda3ef
>> Signed-off-by: Hawking Zhang 
>
> Reviewed-by: Alex Deucher 
Tested-by: Bernhard Froemel 

Thanks, this exactly fixes one of the issues with the MacBookPro13,3:
https://lists.freedesktop.org/archives/amd-gfx/2016-November/003673.html

>
>> ---
>>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c  | 6 ++
>>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c   | 6 ++
>>  drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c | 6 ++
>>  drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c | 6 ++
>>  4 files changed, 24 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> index 34523fe..6aeb1d2 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> @@ -1958,6 +1958,12 @@ int fiji_thermal_setup_fan_table(struct
>> pp_hwmgr *hwmgr)
>>   int res;
>>   uint64_t tmp64;
>>
>> + if (hwmgr->thermal_controller.fanInfo.bNoFan) {
>> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> + PHM_PlatformCaps_MicrocodeFanControl);
>> + return 0;
>> + }
>> +
>>   if (smu_data->smu7_data.fan_table_start == 0) {
>>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   PHM_PlatformCaps_MicrocodeFanControl);
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> index b579f0c..a24971a 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> @@ -2006,6 +2006,12 @@ int iceland_thermal_setup_fan_table(struct
>> pp_hwmgr *hwmgr)
>>   if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_MicrocodeFanControl))
>>   return 0;
>>
>> + if (hwmgr->thermal_controller.fanInfo.bNoFan) {
>> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> + PHM_PlatformCaps_MicrocodeFanControl);
>> + return 0;
>> + }
>> +
>>   if (0 == smu7_data->fan_table_start) {
>>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_MicrocodeFanControl);
>>   return 0;
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
>> index 8db8e20..5190e82 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
>> @@ -1885,6 +1885,12 @@ int polaris10_thermal_setup_fan_table(struct
>> pp_hwmgr *hwmgr)
>>   int res;
>>   uint64_t tmp64;
>>
>> + if (hwmgr->thermal_controller.fanInfo.bNoFan) {
>> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> + PHM_PlatformCaps_MicrocodeFanControl);
>> + return 0;
>> + }
>> +
>>   if (smu_data->smu7_data.fan_table_start == 0) {
>>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   PHM_PlatformCaps_MicrocodeFanControl);
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
>> index d08f6f1..2e1493c 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
>> @@ -2496,6 +2496,12 @@ int tonga_thermal_setup_fan_table(struct
>> pp_hwmgr *hwmgr)
>>
>>   PHM_PlatformCaps_MicrocodeFanControl))
>>   return 0;
>>
>> + if (hwmgr->thermal_controller.fanInfo.bNoFan) {
>> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> + PHM_PlatformCaps_MicrocodeFanControl);
>> + return 0;
>> + }
>> +
>>   if (0 == smu_data->smu7_data.fan_table_start) {
>>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>
>>   PHM_PlatformCaps_MicrocodeFanControl);
>> --
>> 2.7.4
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>

Re: [PATCH] drm/amdgpu: don't add files at control minor debugfs directory

Re: [PATCH 1/3] drm/amd/amdgpu: Add debugfs support for reading GPRs

[PATCH 1/3] drm/amd/amdgpu: Add debugfs support for reading GPRs

[PATCH 2/3] drm/amd/amdgpu: Add gpr reading for GFX v6

[PATCH 3/3] drm/amd/amdgpu: Add gpr reading for GFX v7

debugfs support for reading GPRs

[PATCH 2/2] drm/amdgpu/si: load the proper firmware on 0x87 oland boards

Re: [PATCH] drm/amd/powerplay: bypass fan table setup if no fan connected

8 matches

Site Navigation

Mail list logo

Footer information