[PATCH xf86-video-ati] Don't handle Option "SwapbuffersWait" at all with glamor

[Michel Dänzer]

From: Michel Dänzer 

It never had any effect with glamor.

Signed-off-by: Michel Dänzer 
---
 src/radeon_kms.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 446852564..58efd6ee5 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1801,10 +1801,12 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
}
 }
 
-info->swapBuffersWait = xf86ReturnOptValBool(info->Options,
-OPTION_SWAPBUFFERS_WAIT, TRUE);
-xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-  "SwapBuffers wait for vsync: %sabled\n", info->swapBuffersWait ? 
"en" : "dis");
+if (!info->use_glamor) {
+   info->swapBuffersWait = xf86ReturnOptValBool(info->Options,
+OPTION_SWAPBUFFERS_WAIT, 
TRUE);
+   xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+  "SwapBuffers wait for vsync: %sabled\n", 
info->swapBuffersWait ? "en" : "dis");
+}
 
 if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) {
 info->drmmode.delete_dp_12_displays = TRUE;
-- 
2.11.0

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[PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

[Michel Dänzer]

From: Michel Dänzer 

vram_size is supposed to be the total amount of VRAM that can be used by
userspace, which corresponds to the TTM VRAM manager size (which is
normally the full amount of VRAM, but can be just the visible VRAM when
DMA can't be used for BO migration for some reason).

The above was incorrectly used for vram_visible before, resulting in
generally too large values being reported.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
 drivers/gpu/drm/radeon/radeon_gem.c | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index a252bc407aa2..88c41d43ec3d 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -97,9 +97,10 @@
  *   2.46.0 - Add PFP_SYNC_ME support on evergreen
  *   2.47.0 - Add UVD_NO_OP register support
  *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
+ *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible 
values
  */
 #define KMS_DRIVER_MAJOR   2
-#define KMS_DRIVER_MINOR   48
+#define KMS_DRIVER_MINOR   49
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 0bcffd8a7bd3..96683f5b2b1b 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void 
*data,
 
man = &rdev->mman.bdev.man[TTM_PL_VRAM];
 
-   args->vram_size = rdev->mc.real_vram_size;
-   args->vram_visible = (u64)man->size << PAGE_SHIFT;
+   args->vram_size = (u64)man->size << PAGE_SHIFT;
+   args->vram_visible = rdev->mc.visible_vram_size;
args->vram_visible -= rdev->vram_pin_size;
args->gart_size = rdev->mc.gtt_size;
args->gart_size -= rdev->gart_pin_size;
-- 
2.11.0

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[PATCH] winsys/radeon: Allow visible VRAM size > 256MB with kernel driver >= 2.49

[Michel Dänzer]

From: Michel Dänzer 

The kernel driver reports correct values now.

Signed-off-by: Michel Dänzer 
---
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index a8da62fd36..cacd683879 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -372,7 +372,12 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
 }
 ws->info.gart_size = gem_info.gart_size;
 ws->info.vram_size = gem_info.vram_size;
-ws->info.vram_vis_size = MIN2(gem_info.vram_visible, 256*1024*1024);
+ws->info.vram_vis_size = gem_info.vram_visible;
+/* Older versions of the kernel driver reported incorrect values, and
+ * didn't support more than 256MB of visible VRAM anyway
+ */
+if (ws->info.drm_minor < 49)
+ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
 
 /* Radeon allocates all buffers as contigous, which makes large allocations
  * unlikely to succeed. */
-- 
2.11.0

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RE: [PATCH v1 2/2] drm/radeon: make MacBook Pro d3_delay quirk more generic

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Bjorn Helgaas
> Sent: Monday, January 30, 2017 3:41 PM
> To: Deucher, Alexander; Koenig, Christian
> Cc: linux...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; Maarten Lankhorst
> Subject: [PATCH v1 2/2] drm/radeon: make MacBook Pro d3_delay quirk
> more generic
> 
> The PCI Power Management Spec, r1.2, sec 5.6.1, requires a 10 millisecond
> delay when powering on a device, i.e., transitioning from state D3hot to
> D0.
> 
> Apparently some devices require more time, and d1f9809ed131
> ("drm/radeon:
> add quirk for d3 delay during switcheroo poweron for apple macbooks")
> added
> an additional delay for the Radeon device in a MacBook Pro.  4807c5a8a0c8
> ("drm/radeon: add a PX quirk list") made the affected device more explicit.
> 
> Add a generic PCI quirk to increase the d3_delay.  This means we will use
> the additional delay for *all* wakeups from D3, not just those initiated by
> radeon_switcheroo_set_state().
> 
> Signed-off-by: Bjorn Helgaas 
> CC: Maarten Lankhorst 

For the series:
Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/radeon/radeon_device.c |   12 
>  drivers/pci/quirks.c   |   13 +
>  2 files changed, 13 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_device.c
> b/drivers/gpu/drm/radeon/radeon_device.c
> index 8a1df2a1afbd..8b8fd981cae5 100644
> --- a/drivers/gpu/drm/radeon/radeon_device.c
> +++ b/drivers/gpu/drm/radeon/radeon_device.c
> @@ -113,7 +113,6 @@ static inline bool radeon_is_atpx_hybrid(void) {
> return false; }
>  #endif
> 
>  #define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
> -#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
> 
>  struct radeon_px_quirk {
>   u32 chip_vendor;
> @@ -136,9 +135,6 @@ static struct radeon_px_quirk radeon_px_quirk_list[]
> = {
>* https://bugzilla.kernel.org/show_bug.cgi?id=51381
>*/
>   { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122,
> RADEON_PX_QUIRK_DISABLE_PX },
> - /* macbook pro 8.2 */
> - { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2,
> RADEON_PX_QUIRK_LONG_WAKEUP },
> - { 0, 0, 0, 0, 0 },
>  };
> 
>  bool radeon_is_px(struct drm_device *dev)
> @@ -1241,25 +1237,17 @@ static void radeon_check_arguments(struct
> radeon_device *rdev)
>  static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum
> vga_switcheroo_state state)
>  {
>   struct drm_device *dev = pci_get_drvdata(pdev);
> - struct radeon_device *rdev = dev->dev_private;
> 
>   if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
>   return;
> 
>   if (state == VGA_SWITCHEROO_ON) {
> - unsigned d3_delay = dev->pdev->d3_delay;
> -
>   printk(KERN_INFO "radeon: switched on\n");
>   /* don't suspend or resume card normally */
>   dev->switch_power_state =
> DRM_SWITCH_POWER_CHANGING;
> 
> - if (d3_delay < 20 && (rdev->px_quirk_flags &
> RADEON_PX_QUIRK_LONG_WAKEUP))
> - dev->pdev->d3_delay = 20;
> -
>   radeon_resume_kms(dev, true, true);
> 
> - dev->pdev->d3_delay = d3_delay;
> -
>   dev->switch_power_state = DRM_SWITCH_POWER_ON;
>   drm_kms_helper_poll_enable(dev);
>   } else {
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 1800befa8b8b..512d7a875d62 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -1683,6 +1683,19 @@
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,  0x2609,
> quirk_intel_pcie_pm);
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a,
> quirk_intel_pcie_pm);
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b,
> quirk_intel_pcie_pm);
> 
> +static void quirk_radeon_pm(struct pci_dev *dev)
> +{
> + if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
> + dev->subsystem_device == 0x00e2) {
> + if (dev->d3_delay < 20) {
> + dev->d3_delay = 20;
> + dev_info(&dev->dev, "extending delay after power-
> on from D3 to %d msec\n",
> +  dev->d3_delay);
> + }
> + }
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741,
> quirk_radeon_pm);
> +
>  #ifdef CONFIG_X86_IO_APIC
>  /*
>   * Boot interrupts on some chipsets cannot be turned off. For these
> chipsets,
> 
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[PATCH v1 0/2] drm amdgpu/radeon: clean up d3_delay usage

[Bjorn Helgaas]

amdgpu doesn't need to touch pdev->d3_delay at all.

radeon has a d3_delay quirk for MacBook Pro, but it only affects
radeon_switcheroo_set_state().  I think it should affect wakeups done by
the PCI core as well.

---

Bjorn Helgaas (2):
  drm/amdgpu: remove unnecessary save/restore of pdev->d3_delay
  drm/radeon: make MacBook Pro d3_delay quirk more generic


 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |4 
 drivers/gpu/drm/radeon/radeon_device.c |   12 
 drivers/pci/quirks.c   |   13 +
 3 files changed, 13 insertions(+), 16 deletions(-)
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[PATCH v1 1/2] drm/amdgpu: remove unnecessary save/restore of pdev->d3_delay

[Bjorn Helgaas]

Remove unnecessary save/restore of pdev->d3_delay.

The only assignments to pdev->d3_delay are in radeon_switcheroo_set_state()
and some quirks, none of which should be relevant in the
amdgpu_switcheroo_set_state() path.

Signed-off-by: Bjorn Helgaas 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 60bd4afe45c8..3a403a87ec62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1042,16 +1042,12 @@ static void amdgpu_switcheroo_set_state(struct pci_dev 
*pdev, enum vga_switchero
return;
 
if (state == VGA_SWITCHEROO_ON) {
-   unsigned d3_delay = dev->pdev->d3_delay;
-
printk(KERN_INFO "amdgpu: switched on\n");
/* don't suspend or resume card normally */
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
amdgpu_device_resume(dev, true, true);
 
-   dev->pdev->d3_delay = d3_delay;
-
dev->switch_power_state = DRM_SWITCH_POWER_ON;
drm_kms_helper_poll_enable(dev);
} else {

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[PATCH v1 2/2] drm/radeon: make MacBook Pro d3_delay quirk more generic

[Bjorn Helgaas]

The PCI Power Management Spec, r1.2, sec 5.6.1, requires a 10 millisecond
delay when powering on a device, i.e., transitioning from state D3hot to
D0.

Apparently some devices require more time, and d1f9809ed131 ("drm/radeon:
add quirk for d3 delay during switcheroo poweron for apple macbooks") added
an additional delay for the Radeon device in a MacBook Pro.  4807c5a8a0c8
("drm/radeon: add a PX quirk list") made the affected device more explicit.

Add a generic PCI quirk to increase the d3_delay.  This means we will use
the additional delay for *all* wakeups from D3, not just those initiated by
radeon_switcheroo_set_state().

Signed-off-by: Bjorn Helgaas 
CC: Maarten Lankhorst 
---
 drivers/gpu/drm/radeon/radeon_device.c |   12 
 drivers/pci/quirks.c   |   13 +
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_device.c 
b/drivers/gpu/drm/radeon/radeon_device.c
index 8a1df2a1afbd..8b8fd981cae5 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -113,7 +113,6 @@ static inline bool radeon_is_atpx_hybrid(void) { return 
false; }
 #endif
 
 #define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
-#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
 
 struct radeon_px_quirk {
u32 chip_vendor;
@@ -136,9 +135,6 @@ static struct radeon_px_quirk radeon_px_quirk_list[] = {
 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
 */
{ PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX 
},
-   /* macbook pro 8.2 */
-   { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, 
RADEON_PX_QUIRK_LONG_WAKEUP },
-   { 0, 0, 0, 0, 0 },
 };
 
 bool radeon_is_px(struct drm_device *dev)
@@ -1241,25 +1237,17 @@ static void radeon_check_arguments(struct radeon_device 
*rdev)
 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum 
vga_switcheroo_state state)
 {
struct drm_device *dev = pci_get_drvdata(pdev);
-   struct radeon_device *rdev = dev->dev_private;
 
if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
return;
 
if (state == VGA_SWITCHEROO_ON) {
-   unsigned d3_delay = dev->pdev->d3_delay;
-
printk(KERN_INFO "radeon: switched on\n");
/* don't suspend or resume card normally */
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
-   if (d3_delay < 20 && (rdev->px_quirk_flags & 
RADEON_PX_QUIRK_LONG_WAKEUP))
-   dev->pdev->d3_delay = 20;
-
radeon_resume_kms(dev, true, true);
 
-   dev->pdev->d3_delay = d3_delay;
-
dev->switch_power_state = DRM_SWITCH_POWER_ON;
drm_kms_helper_poll_enable(dev);
} else {
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 1800befa8b8b..512d7a875d62 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1683,6 +1683,19 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, 
quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   0x260a, quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   0x260b, quirk_intel_pcie_pm);
 
+static void quirk_radeon_pm(struct pci_dev *dev)
+{
+   if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+   dev->subsystem_device == 0x00e2) {
+   if (dev->d3_delay < 20) {
+   dev->d3_delay = 20;
+   dev_info(&dev->dev, "extending delay after power-on 
from D3 to %d msec\n",
+dev->d3_delay);
+   }
+   }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
+
 #ifdef CONFIG_X86_IO_APIC
 /*
  * Boot interrupts on some chipsets cannot be turned off. For these chipsets,

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RE: [v3 PATCH 1/3] drm/atomic: Save flip flags in drm_crtct_state

[Grodzovsky, Andrey]

> -Original Message-
> From: Laurent Pinchart [mailto:laurent.pinch...@ideasonboard.com]
> Sent: Monday, January 30, 2017 6:05 AM
> To: Grodzovsky, Andrey
> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
> nouv...@lists.freedesktop.org; daniel.vet...@intel.com; dc_upstream
> Subject: Re: [v3 PATCH 1/3] drm/atomic: Save flip flags in drm_crtct_state
> 
> Hi Andrey,
> 
> Thank you for the patch.
> 
> On Saturday 28 Jan 2017 21:26:49 Andrey Grodzovsky wrote:
> > Allows using atomic flip helpers for drivers using ASYNC flip.
> > Remove ASYNC_FLIP restriction in helpers and caches the page flip
> > flags in drm_crtc_state to be used in the low level drivers.
> >
> > v2:
> > Resending the patch since the original was broken.
> >
> > v3:
> > Save flag in crtc_state instead of plane_state
> >
> > Signed-off-by: Andrey Grodzovsky 
> > ---
> >  drivers/gpu/drm/drm_atomic_helper.c | 19 +--
> >  include/drm/drm_crtc.h  |  8 +++-
> >  include/drm/drm_plane.h |  1 +
> >  3 files changed, 13 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c index a4e5477..28065ee 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -2737,7 +2737,8 @@ static int page_flip_common(
> > struct drm_atomic_state *state,
> > struct drm_crtc *crtc,
> > struct drm_framebuffer *fb,
> > -   struct drm_pending_vblank_event *event)
> > +   struct drm_pending_vblank_event *event,
> > +   uint32_t flags)
> >  {
> > struct drm_plane *plane = crtc->primary;
> > struct drm_plane_state *plane_state; @@ -2749,12 +2750,12 @@
> static
> > int page_flip_common(
> > return PTR_ERR(crtc_state);
> >
> > crtc_state->event = event;
> > +   crtc_state->pflip_flags = flags;
> >
> > plane_state = drm_atomic_get_plane_state(state, plane);
> > if (IS_ERR(plane_state))
> > return PTR_ERR(plane_state);
> >
> > -
> > ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
> > if (ret != 0)
> > return ret;
> > @@ -2781,10 +2782,6 @@ static int page_flip_common(
> >   * Provides a default &drm_crtc_funcs.page_flip implementation
> >   * using the atomic driver interface.
> >   *
> > - * Note that for now so called async page flips (i.e. updates which
> > are not
> > - * synchronized to vblank) are not supported, since the atomic
> > interfaces have - * no provisions for this yet.
> > - *
> >   * Returns:
> >   * Returns 0 on success, negative errno numbers on failure.
> >   *
> > @@ -2800,9 +2797,6 @@ int drm_atomic_helper_page_flip(struct drm_crtc
> > *crtc, struct drm_atomic_state *state;
> > int ret = 0;
> >
> > -   if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
> > -   return -EINVAL;
> > -
> > state = drm_atomic_state_alloc(plane->dev);
> > if (!state)
> > return -ENOMEM;
> > @@ -2810,7 +2804,7 @@ int drm_atomic_helper_page_flip(struct drm_crtc
> > *crtc,
> > state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
> >
> >  retry:
> > -   ret = page_flip_common(state, crtc, fb, event);
> > +   ret = page_flip_common(state, crtc, fb, event, flags);
> > if (ret != 0)
> > goto fail;
> >
> > @@ -2865,9 +2859,6 @@ int drm_atomic_helper_page_flip_target(
> > struct drm_crtc_state *crtc_state;
> > int ret = 0;
> >
> > -   if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
> > -   return -EINVAL;
> > -
> > state = drm_atomic_state_alloc(plane->dev);
> > if (!state)
> > return -ENOMEM;
> > @@ -2875,7 +2866,7 @@ int drm_atomic_helper_page_flip_target(
> > state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
> >
> >  retry:
> > -   ret = page_flip_common(state, crtc, fb, event);
> > +   ret = page_flip_common(state, crtc, fb, event, flags);
> > if (ret != 0)
> > goto fail;
> >
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> > 5c77c3f..76457a4 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -162,10 +162,16 @@ struct drm_crtc_state {
> >  * Target vertical blank period when a page flip
> >  * should take effect.
> >  */
> > -
> > u32 target_vblank;
> >
> > /**
> > +* @pflip_flags:
> > +*
> > +* Flip related config options
> 
> This isn't detailed enough. I propose something along the lines of
> 
> "DRM_MODE_PAGE_FLIP_* page flip flags, as passed to the page flip ioctl.
> Always zero for atomic commits that don't originate from a page flip ioctl."
> 
> You will then also need to reset the field to 0 at an appropriate point, as 
> it's
> more an atomic commit transaction information than a state. Apart from that
> this patch looks good to me.
Thanks for your comments, i am not sure I under

Re: [PATCH 1/2] drm/amdgpu: fix race in GEM VA map IOCTL

[Nicolai Hähnle]

On 30.01.2017 10:45, Christian König wrote:

From: Christian König 

Somebody could try to free the bo_va between mapping and updating it.

Signed-off-by: Christian König 


Nice catch! Both patches:

Reviewed-by: Nicolai Hähnle 


---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 45 ++---
 1 file changed, 14 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7a265d9..ec5b184 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -489,67 +489,50 @@ static int amdgpu_gem_va_check(void *param, struct 
amdgpu_bo *bo)
  *
  * @adev: amdgpu_device pointer
  * @bo_va: bo_va to update
+ * @list: validation list
+ * opration: map or unmap
  *
  * Update the bo_va directly after setting it's address. Errors are not
  * vital here, so they are not reported back to userspace.
  */
 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
+   struct list_head *list,
uint32_t operation)
 {
-   struct ttm_validate_buffer tv, *entry;
-   struct amdgpu_bo_list_entry vm_pd;
-   struct ww_acquire_ctx ticket;
-   struct list_head list, duplicates;
-   int r;
-
-   INIT_LIST_HEAD(&list);
-   INIT_LIST_HEAD(&duplicates);
-
-   tv.bo = &bo_va->bo->tbo;
-   tv.shared = true;
-   list_add(&tv.head, &list);
-
-   amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
-
-   /* Provide duplicates to avoid -EALREADY */
-   r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
-   if (r)
-   goto error_print;
+   struct ttm_validate_buffer *entry;
+   int r = -ERESTARTSYS;

-   list_for_each_entry(entry, &list, head) {
+   list_for_each_entry(entry, list, head) {
struct amdgpu_bo *bo =
container_of(entry->bo, struct amdgpu_bo, tbo);

/* if anything is swapped out don't swap it in here,
   just abort and wait for the next CS */
if (!amdgpu_bo_gpu_accessible(bo))
-   goto error_unreserve;
+   goto error;

if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
-   goto error_unreserve;
+   goto error;
}

r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check,
  NULL);
if (r)
-   goto error_unreserve;
+   goto error;

r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
if (r)
-   goto error_unreserve;
+   goto error;

r = amdgpu_vm_clear_freed(adev, bo_va->vm);
if (r)
-   goto error_unreserve;
+   goto error;

if (operation == AMDGPU_VA_OP_MAP)
r = amdgpu_vm_bo_update(adev, bo_va, false);

-error_unreserve:
-   ttm_eu_backoff_reservation(&ticket, &list);
-
-error_print:
+error:
if (r && r != -ERESTARTSYS)
DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 }
@@ -642,10 +625,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void 
*data,
default:
break;
}
-   ttm_eu_backoff_reservation(&ticket, &list);
if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
!amdgpu_vm_debug)
-   amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
+   amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
+   ttm_eu_backoff_reservation(&ticket, &list);

drm_gem_object_unreference_unlocked(gobj);
return r;



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Re: [v3 PATCH 3/3] drm/amd/display: Switch to using atomic_helper for flip.

[Harry Wentland]

On 2017-01-28 09:26 PM, Andrey Grodzovsky wrote:
> Swicth to use atomic helper.
> Start using actual user's given target_vblank value for flip 
> instead of current value.
> 
> v3:
> Update for movig pflip flags to crtc_state
> 
> Change-Id: I25dae6d8c29de5d022a42aa99a18a32674b56cda
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |   1 -
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 109 
> -
>  2 files changed, 19 insertions(+), 91 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> index 4c0a86e..3ff3c14 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> @@ -443,7 +443,6 @@ struct amdgpu_crtc {
>   enum amdgpu_interrupt_state vsync_timer_enabled;
>  
>   int otg_inst;
> - uint32_t flip_flags;
>   /* After Set Mode target will be non-NULL */
>   struct dc_target *target;
>  };
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
> index a443b70..148780d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
> @@ -1060,83 +1060,6 @@ static int dm_crtc_funcs_atomic_set_property(
>   return 0;
>  }
>  
> -
> -static int amdgpu_atomic_helper_page_flip(struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_pending_vblank_event *event,
> - uint32_t flags)
> -{
> - struct drm_plane *plane = crtc->primary;
> - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
> - struct drm_atomic_state *state;
> - struct drm_plane_state *plane_state;
> - struct drm_crtc_state *crtc_state;
> - int ret = 0;
> -
> - state = drm_atomic_state_alloc(plane->dev);
> - if (!state)
> - return -ENOMEM;
> -
> - ret = drm_crtc_vblank_get(crtc);
> - if (ret)
> - return ret;
> -
> - state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
> -retry:
> - crtc_state = drm_atomic_get_crtc_state(state, crtc);
> - if (IS_ERR(crtc_state)) {
> - ret = PTR_ERR(crtc_state);
> - goto fail;
> - }
> - crtc_state->event = event;
> -
> - plane_state = drm_atomic_get_plane_state(state, plane);
> - if (IS_ERR(plane_state)) {
> - ret = PTR_ERR(plane_state);
> - goto fail;
> - }
> -
> - ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
> - if (ret != 0)
> - goto fail;
> - drm_atomic_set_fb_for_plane(plane_state, fb);
> -
> - /* Make sure we don't accidentally do a full modeset. */
> - state->allow_modeset = false;
> - if (!crtc_state->active) {
> - DRM_DEBUG_ATOMIC("[CRTC:%d] disabled, rejecting legacy flip\n",
> -  crtc->base.id);
> - ret = -EINVAL;
> - goto fail;
> - }
> - acrtc->flip_flags = flags;
> -
> - ret = drm_atomic_nonblocking_commit(state);
> -
> -fail:
> - if (ret == -EDEADLK)
> - goto backoff;
> -
> - if (ret)
> - drm_crtc_vblank_put(crtc);
> -
> - drm_atomic_state_put(state);
> -
> - return ret;
> -backoff:
> - drm_atomic_state_clear(state);
> - drm_atomic_legacy_backoff(state);
> -
> - /*
> -  * Someone might have exchanged the framebuffer while we dropped locks
> -  * in the backoff code. We need to fix up the fb refcount tracking the
> -  * core does for us.
> -  */
> - plane->old_fb = plane->fb;
> -
> - goto retry;
> -}
> -
>  /* Implemented only the options currently availible for the driver */
>  static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
>   .reset = drm_atomic_helper_crtc_reset,
> @@ -1145,7 +1068,7 @@ static int amdgpu_atomic_helper_page_flip(struct 
> drm_crtc *crtc,
>   .destroy = amdgpu_dm_crtc_destroy,
>   .gamma_set = amdgpu_dm_atomic_crtc_gamma_set,
>   .set_config = drm_atomic_helper_set_config,
> - .page_flip = amdgpu_atomic_helper_page_flip,
> + .page_flip_target = drm_atomic_helper_page_flip_target,
>   .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
>   .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
>   .atomic_set_property = dm_crtc_funcs_atomic_set_property
> @@ -1626,7 +1549,8 @@ static void clear_unrelated_fields(struct 
> drm_plane_state *state)
>  static bool page_flip_needed(
>   const struct drm_plane_state *new_state,
>   const struct drm_plane_state *old_state,
> - bool commit_surface_required)
> + bool commit_surface_required,
> + uint32_t pflip_flags)
>  {
>   struct drm_plane_state old_state_tmp;
>   struct drm_plane_state new_state_tmp;
> @@ -1679,7 +1603,7 @@ static bool page_flip_needed(
>

Re: PRT support for amdgpu

[Nicolai Hähnle]

[ Cc John for addrlib ]

On 30.01.2017 13:57, Christian König wrote:

An open problem with the proposal is that we don't know when or if we want to 
add the userspace implementation into radeonsi.

So price question could you guys use this for radv as well? Or is it sufficient 
to just write an unit test for it?


For radeonsi, I think the question is more "when", not "if". At least 
PRT/sparse textures are necessarily immutable, so the associated Mesa 
headache should be bounded, but still...


As you know, I think the ioctl interface is good.

One thing to keep in mind is that I don't know how well PRT layout is 
supported by the open addrlib. There have been a bunch of PRT-related 
fixes in the internal copy of addrlib, but opening them has been stuck 
in review limbo for a while now...


Cheers,
Nicolai



Best regards,
Christian.

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Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

[StDenis, Tom]

Hi Christian,


I have SI,CI,VI gear in my office if you have a unit test to try it with.


Cheers,

Tom



From: Christian König 
Sent: Monday, January 30, 2017 09:14
To: StDenis, Tom; b...@basnieuwenhuizen.nl; airl...@gmail.com
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

The changes to the GFX6/7/8 look reasonable though only question is you read 
from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL .  Is that expected?
Not at all! Looks like a copy&paste error while modifying the original patch. 
Thanks for catching this.

Also the whole set is so far only compile tested, still need to give it a run 
on all hardware generations anyway.

Christian.

Am 30.01.2017 um 14:59 schrieb StDenis, Tom:

Minor nit: the comment says v8 [??]


The changes to the GFX6/7/8 look reasonable though only question is you read 
from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL .  Is that expected?


Tom



From: amd-gfx 

 on behalf of Christian König 

Sent: Monday, January 30, 2017 07:57
To: b...@basnieuwenhuizen.nl; 
airl...@gmail.com
Cc: amd-gfx@lists.freedesktop.org
Subject: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

From: Christian König 


Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Christian König 

---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 63 +++
 1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index e2b0b16..c23503e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,68 @@ static void gmc_v6_0_set_fault_enable_default(struct 
amdgpu_device *adev,
 WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }

+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
 int r, i;
@@ -1080,6 +1142,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 static const struct amdgpu_gart

Re: [PATCH 1/6] drm/amdgpu: add support for BO_VAs without BO

[Nicolai Hähnle]

On 30.01.2017 13:57, Christian König wrote:

From: Christian König 

For PRT support we need mappings which aren't backed by any memory.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 ++--
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8e6030d..87eae9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1117,7 +1117,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct fence *exclusive;
int r;

-   if (clear) {
+   if (clear || !bo_va->bo) {
mem = NULL;
nodes = NULL;
exclusive = NULL;
@@ -1134,9 +1134,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
}

-   flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
-   gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
-   adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? flags : 0;
+   if (bo_va->bo) {
+   flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
+   gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
+   adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
+   flags : 0;
+   } else {
+   flags = 0x0;
+   gtt_flags = ~0x0;
+   }

spin_lock(&vm->status_lock);
if (!list_empty(&bo_va->vm_status))
@@ -1271,7 +1277,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct 
amdgpu_device *adev,
INIT_LIST_HEAD(&bo_va->invalids);
INIT_LIST_HEAD(&bo_va->vm_status);

-   list_add_tail(&bo_va->bo_list, &bo->va);
+   if (bo)
+   list_add_tail(&bo_va->bo_list, &bo->va);

return bo_va;
 }
@@ -1309,7 +1316,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,

/* make sure object fit at this offset */
eaddr = saddr + size - 1;
-   if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
+   if (bo_va->bo && (saddr >= eaddr ||
+ (offset + size > amdgpu_bo_size(bo_va->bo
return -EINVAL;


At least the saddr >= eaddr check should probably apply apply.

Come to think of it, what if offset + size wraps around? There should 
probably be an explicit check for that.


Cheers,
Nicolai



last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;



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Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

[Christian König]

Thanks, going to come back to that when I actually write the unit test.

But I will wait what Dave&Bas says to the interface.

Regards,
Christian.

Am 30.01.2017 um 15:15 schrieb StDenis, Tom:


Hi Christian,


I have SI,CI,VI gear in my office if you have a unit test to try it with.


Cheers,

Tom




*From:* Christian König 
*Sent:* Monday, January 30, 2017 09:14
*To:* StDenis, Tom; b...@basnieuwenhuizen.nl; airl...@gmail.com
*Cc:* amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6
The changes to the GFX6/7/8 look reasonable though only question is 
you read from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL . 
 Is that expected?
Not at all! Looks like a copy&paste error while modifying the original 
patch. Thanks for catching this.


Also the whole set is so far only compile tested, still need to give 
it a run on all hardware generations anyway.


Christian.

Am 30.01.2017 um 14:59 schrieb StDenis, Tom:


Minor nit: the comment says v8 ��


The changes to the GFX6/7/8 look reasonable though only question is 
you read from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL . 
 Is that expected?



Tom




*From:* amd-gfx  on behalf of 
Christian König 

*Sent:* Monday, January 30, 2017 07:57
*To:* b...@basnieuwenhuizen.nl; airl...@gmail.com
*Cc:* amd-gfx@lists.freedesktop.org
*Subject:* [PATCH 4/6] drm/amdgpu: implement PRT for GFX6
From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 63 
+++

 1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

index e2b0b16..c23503e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,68 @@ static void 
gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,

 WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }

+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of 
PRT request!\n");

+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ L2_CACHE_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ L1_TLB_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> 
AMDGPU_GPU_PAGE_SHIFT;

+   uint32_t high = adev->vm_manager.max_pfn;
+
+ WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+ WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+ WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+ WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+ WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+ WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+ WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+ WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+ WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+ WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+ WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+ WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+ WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+ WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+ WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+ WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
 int r, i;
@@ -1080,6 +1142,7 @@ static const struct amd_ip_funcs 
gmc_v6_0_ip_funcs = {

 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
+   .set_prt = gmc_v6_0_set_prt,
 };

 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
--
2.5.0

___
amd-gfx mailin

Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

[Christian König]

The changes to the GFX6/7/8 look reasonable though only question is 
you read from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL .  Is 
that expected?
Not at all! Looks like a copy&paste error while modifying the original 
patch. Thanks for catching this.


Also the whole set is so far only compile tested, still need to give it 
a run on all hardware generations anyway.


Christian.

Am 30.01.2017 um 14:59 schrieb StDenis, Tom:


Minor nit: the comment says v8 😊


The changes to the GFX6/7/8 look reasonable though only question is 
you read from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL .  Is 
that expected?



Tom




*From:* amd-gfx  on behalf of 
Christian König 

*Sent:* Monday, January 30, 2017 07:57
*To:* b...@basnieuwenhuizen.nl; airl...@gmail.com
*Cc:* amd-gfx@lists.freedesktop.org
*Subject:* [PATCH 4/6] drm/amdgpu: implement PRT for GFX6
From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 63 
+++

 1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

index e2b0b16..c23503e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,68 @@ static void 
gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,

 WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }

+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of 
PRT request!\n");

+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ L2_CACHE_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+ L1_TLB_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> 
AMDGPU_GPU_PAGE_SHIFT;

+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
 int r, i;
@@ -1080,6 +1142,7 @@ static const struct amd_ip_funcs 
gmc_v6_0_ip_funcs = {

 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
+   .set_prt = gmc_v6_0_set_prt,
 };

 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
--
2.5.0

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___

Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

[StDenis, Tom]

Minor nit: the comment says v8 [😊]


The changes to the GFX6/7/8 look reasonable though only question is you read 
from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL .  Is that expected?


Tom



From: amd-gfx  on behalf of Christian 
König 
Sent: Monday, January 30, 2017 07:57
To: b...@basnieuwenhuizen.nl; airl...@gmail.com
Cc: amd-gfx@lists.freedesktop.org
Subject: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 63 +++
 1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index e2b0b16..c23503e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,68 @@ static void gmc_v6_0_set_fault_enable_default(struct 
amdgpu_device *adev,
 WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }

+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
 int r, i;
@@ -1080,6 +1142,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
+   .set_prt = gmc_v6_0_set_prt,
 };

 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
--
2.5.0

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[PATCH 4/6] drm/amdgpu: implement PRT for GFX6

[Christian König]

From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 63 +++
 1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index e2b0b16..c23503e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,68 @@ static void gmc_v6_0_set_fault_enable_default(struct 
amdgpu_device *adev,
WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }
 
+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
int r, i;
@@ -1080,6 +1142,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
+   .set_prt = gmc_v6_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
-- 
2.5.0

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[PATCH 2/6] drm/amdgpu: add basic PRT support

[Christian König]

From: Christian König 

Future hardware generations can handle PRT flags on a per page basis,
but current hardware can only turn it on globally.

Add the basic handling for both, a global callback to enable/disable
triggered by setting a per mapping flag.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 101 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |   6 ++
 3 files changed, 98 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 402a895..34a971a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -296,6 +296,8 @@ struct amdgpu_gart_funcs {
   uint32_t gpu_page_idx, /* pte/pde to update */
   uint64_t addr, /* addr to write into pte/pde */
   uint32_t flags); /* access flags */
+   /* enable/disable PRT support */
+   void (*set_prt)(struct amdgpu_device *adev, bool enable);
 };
 
 /* provided by the ih block */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 87eae9b..5d0afca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -69,6 +69,12 @@ struct amdgpu_pte_update_params {
bool shadow;
 };
 
+/* Helper to disable partial resident texture feature from a fence callback */
+struct amdgpu_prt_cb {
+   struct amdgpu_device *adev;
+   struct fence_cb cb;
+};
+
 /**
  * amdgpu_vm_num_pde - return the number of page directory entries
  *
@@ -989,11 +995,8 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
goto error_free;
 
amdgpu_bo_fence(vm->page_directory, f, true);
-   if (fence) {
-   fence_put(*fence);
-   *fence = fence_get(f);
-   }
-   fence_put(f);
+   fence_put(*fence);
+   *fence = f;
return 0;
 
 error_free:
@@ -1177,6 +1180,61 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 }
 
 /**
+ * amdgpu_vm_update_prt_state - update the global PRT state
+ */
+static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
+{
+   unsigned long flags;
+   bool enable;
+
+   spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
+   enable = !!atomic_read(&adev->vm_manager.num_prt_mappings);
+   adev->gart.gart_funcs->set_prt(adev, enable);
+   spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
+}
+
+/**
+ * amdgpu_vm_prt - callback for updating the PRT status
+ */
+static void amdgpu_vm_prt_cb(struct fence *fence, struct fence_cb *_cb)
+{
+   struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
+
+   amdgpu_vm_update_prt_state(cb->adev);
+   kfree(cb);
+}
+
+/**
+ * amdgpu_vm_free_mapping - free a mapping
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requested vm
+ * @mapping: mapping to be freed
+ * @fence: fence of the unmap operation
+ *
+ * Free a mapping and make sure we decrease the PRT usage count if applicable.
+ */
+static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
+  struct amdgpu_vm *vm,
+  struct amdgpu_bo_va_mapping *mapping,
+  struct fence *fence)
+{
+   if ((mapping->flags & AMDGPU_PTE_PRT) &&
+   atomic_dec_return(&adev->vm_manager.num_prt_mappings) == 0) {
+   struct amdgpu_prt_cb *cb = kmalloc(sizeof(struct amdgpu_prt_cb),
+  GFP_KERNEL);
+
+   cb->adev = adev;
+   if (!fence || fence_add_callback(fence, &cb->cb,
+amdgpu_vm_prt_cb)) {
+   amdgpu_vm_update_prt_state(adev);
+   kfree(cb);
+   }
+   }
+   kfree(mapping);
+}
+
+/**
  * amdgpu_vm_clear_freed - clear freed BOs in the PT
  *
  * @adev: amdgpu_device pointer
@@ -1191,6 +1249,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
  struct amdgpu_vm *vm)
 {
struct amdgpu_bo_va_mapping *mapping;
+   struct fence *fence = NULL;
int r;
 
while (!list_empty(&vm->freed)) {
@@ -1199,12 +1258,15 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
list_del(&mapping->list);
 
r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
-  0, 0, NULL);
-   kfree(mapping);
-   if (r)
+  0, 0, &fence);
+   amdgpu_vm_free_mapping(adev, vm, mapping, fence);
+   if (r) {
+   fence_put(fence);
return r;
+   }
 
}
+   fence_put(fence);
return 0;
 
 }
@@ -1314,6 +

[PATCH 5/6] drm/amdgpu: implement PRT for GFX7

[Christian König]

From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Junwei Zhang 
Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 57 +++
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 99ca5e8..d8516dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -571,6 +571,7 @@ struct amdgpu_mc {
uint32_tvram_type;
uint32_tsrbm_soft_reset;
struct amdgpu_mode_mc_save save;
+   boolprt_warning;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 8d05e0c..1f4a2b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -481,6 +481,62 @@ static void gmc_v7_0_set_fault_enable_default(struct 
amdgpu_device *adev,
 }
 
 /**
+ * gmc_v7_0_set_prt - set PRT VM fault
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable VM fault handling for PRT
+ */
+static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   uint32_t tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
+/**
  * gmc_v7_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -1259,6 +1315,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
.flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
.set_pte_pde = gmc_v7_0_gart_set_pte_pde,
+   .set_prt = gmc_v7_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
-- 
2.5.0

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[PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v3

[Christian König]

From: Junwei Zhang 

Till GFX8 we can only enable PRT support globally, but with the next hardware
generation we can do this on a per page basis.

Keep the interface consistent by adding PRT mappings and enable
support globally on current hardware when the first mapping is made.

v2: disable PRT support delayed and on all error paths
v3: PRT and other permissions are mutal exclusive,
PRT mappings don't need a BO.

Signed-off-by: Junwei Zhang 
Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 62 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++
 include/uapi/drm/amdgpu_drm.h   |  2 ++
 4 files changed, 51 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 34a971a..99ca5e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -703,6 +703,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
 
 struct amdgpu_fpriv {
struct amdgpu_vmvm;
+   struct amdgpu_bo_va *prt_va;
struct mutexbo_list_lock;
struct idr  bo_list_handles;
struct amdgpu_ctx_mgr   ctx_mgr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 9dd41e7..af430c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -540,6 +540,12 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device 
*adev,
 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
  struct drm_file *filp)
 {
+   const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
+   AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
+   AMDGPU_VM_PAGE_EXECUTABLE;
+   const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
+   AMDGPU_VM_PAGE_PRT;
+
struct drm_amdgpu_gem_va *args = data;
struct drm_gem_object *gobj;
struct amdgpu_device *adev = dev->dev_private;
@@ -550,7 +556,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct list_head list;
-   uint32_t invalid_flags, va_flags = 0;
+   uint32_t va_flags = 0;
int r = 0;
 
if (!adev->vm_manager.enabled)
@@ -564,11 +570,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
}
 
-   invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
-   AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
-   if ((args->flags & invalid_flags)) {
-   dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
-   args->flags, invalid_flags);
+   if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
+   dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
+   args->flags);
return -EINVAL;
}
 
@@ -582,28 +586,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void 
*data,
return -EINVAL;
}
 
-   gobj = drm_gem_object_lookup(filp, args->handle);
-   if (gobj == NULL)
-   return -ENOENT;
-   abo = gem_to_amdgpu_bo(gobj);
INIT_LIST_HEAD(&list);
-   tv.bo = &abo->tbo;
-   tv.shared = false;
-   list_add(&tv.head, &list);
+   if (!(args->flags & AMDGPU_VM_PAGE_PRT)) {
+   gobj = drm_gem_object_lookup(filp, args->handle);
+   if (gobj == NULL)
+   return -ENOENT;
+   abo = gem_to_amdgpu_bo(gobj);
+   tv.bo = &abo->tbo;
+   tv.shared = false;
+   list_add(&tv.head, &list);
+   } else {
+   gobj = NULL;
+   abo = NULL;
+   }
 
amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 
r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
-   if (r) {
-   drm_gem_object_unreference_unlocked(gobj);
-   return r;
-   }
+   if (r)
+   goto error_unref;
 
-   bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
-   if (!bo_va) {
-   ttm_eu_backoff_reservation(&ticket, &list);
-   drm_gem_object_unreference_unlocked(gobj);
-   return -ENOENT;
+   if (abo) {
+   bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
+   if (!bo_va) {
+   r = -ENOENT;
+   goto error_backoff;
+   }
+   } else {
+   bo_va = fpriv->prt_va;
}
 
switch (args->operation) {
@@ -614,6 +624,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
va_flags |= AMDGPU_PTE_WRITEABLE;
if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
  

PRT support for amdgpu

[Christian König]

Hi Dave and Bas,

Hi Dave and Bas,

the following set of patches is a proposal for adding support for partial 
resident textures (PRT) to the amdgpu kernel module.

The basic idea behind PRT support is that you turn of VM fault reporting and 
only map parts of a texture into your virtual address space.

When a shader now tries to sample from a not present page it gets a 
notification instead of a VM fault and can react gracefully by switch to a 
different LOD for example.

On our current available hardware generation you can unfortunately only turn of 
VM faults globally, but on future generation you can do this on a per page 
basis. So my proposal is to have a consistent interface over all generations 
with a per mapping PRT flag, but enable/disable it globally on current hardware 
when the first/last mapping is made/destroyed.

An open problem with the proposal is that we don't know when or if we want to 
add the userspace implementation into radeonsi.

So price question could you guys use this for radv as well? Or is it sufficient 
to just write an unit test for it?

Best regards,
Christian.

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[PATCH 6/6] drm/amdgpu: implement PRT for GFX8

[Christian König]

From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Junwei Zhang 
Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 7669b32..d950a03 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -595,6 +595,62 @@ static void gmc_v8_0_set_fault_enable_default(struct 
amdgpu_device *adev,
 }
 
 /**
+ * gmc_v8_0_set_prt - set PRT VM fault
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable VM fault handling for PRT
+*/
+static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
+/**
  * gmc_v8_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -1485,6 +1541,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
.flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
.set_pte_pde = gmc_v8_0_gart_set_pte_pde,
+   .set_prt = gmc_v8_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
-- 
2.5.0

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[PATCH 1/6] drm/amdgpu: add support for BO_VAs without BO

[Christian König]

From: Christian König 

For PRT support we need mappings which aren't backed by any memory.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 ++--
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8e6030d..87eae9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1117,7 +1117,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct fence *exclusive;
int r;
 
-   if (clear) {
+   if (clear || !bo_va->bo) {
mem = NULL;
nodes = NULL;
exclusive = NULL;
@@ -1134,9 +1134,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
}
 
-   flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
-   gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
-   adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? flags : 0;
+   if (bo_va->bo) {
+   flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
+   gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
+   adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
+   flags : 0;
+   } else {
+   flags = 0x0;
+   gtt_flags = ~0x0;
+   }
 
spin_lock(&vm->status_lock);
if (!list_empty(&bo_va->vm_status))
@@ -1271,7 +1277,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct 
amdgpu_device *adev,
INIT_LIST_HEAD(&bo_va->invalids);
INIT_LIST_HEAD(&bo_va->vm_status);
 
-   list_add_tail(&bo_va->bo_list, &bo->va);
+   if (bo)
+   list_add_tail(&bo_va->bo_list, &bo->va);
 
return bo_va;
 }
@@ -1309,7 +1316,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 
/* make sure object fit at this offset */
eaddr = saddr + size - 1;
-   if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
+   if (bo_va->bo && (saddr >= eaddr ||
+ (offset + size > amdgpu_bo_size(bo_va->bo
return -EINVAL;
 
last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
-- 
2.5.0

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Re: [v3 PATCH 1/3] drm/atomic: Save flip flags in drm_crtct_state

[Laurent Pinchart]

Hi Andrey,

Thank you for the patch.

On Saturday 28 Jan 2017 21:26:49 Andrey Grodzovsky wrote:
> Allows using atomic flip helpers for drivers
> using ASYNC flip.
> Remove ASYNC_FLIP restriction in helpers and
> caches the page flip flags in drm_crtc_state
> to be used in the low level drivers.
> 
> v2:
> Resending the patch since the original was broken.
> 
> v3:
> Save flag in crtc_state instead of plane_state
> 
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/drm_atomic_helper.c | 19 +--
>  include/drm/drm_crtc.h  |  8 +++-
>  include/drm/drm_plane.h |  1 +
>  3 files changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c index a4e5477..28065ee 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -2737,7 +2737,8 @@ static int page_flip_common(
>   struct drm_atomic_state *state,
>   struct drm_crtc *crtc,
>   struct drm_framebuffer *fb,
> - struct drm_pending_vblank_event *event)
> + struct drm_pending_vblank_event *event,
> + uint32_t flags)
>  {
>   struct drm_plane *plane = crtc->primary;
>   struct drm_plane_state *plane_state;
> @@ -2749,12 +2750,12 @@ static int page_flip_common(
>   return PTR_ERR(crtc_state);
> 
>   crtc_state->event = event;
> + crtc_state->pflip_flags = flags;
> 
>   plane_state = drm_atomic_get_plane_state(state, plane);
>   if (IS_ERR(plane_state))
>   return PTR_ERR(plane_state);
> 
> -
>   ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
>   if (ret != 0)
>   return ret;
> @@ -2781,10 +2782,6 @@ static int page_flip_common(
>   * Provides a default &drm_crtc_funcs.page_flip implementation
>   * using the atomic driver interface.
>   *
> - * Note that for now so called async page flips (i.e. updates which are not
> - * synchronized to vblank) are not supported, since the atomic interfaces
> have - * no provisions for this yet.
> - *
>   * Returns:
>   * Returns 0 on success, negative errno numbers on failure.
>   *
> @@ -2800,9 +2797,6 @@ int drm_atomic_helper_page_flip(struct drm_crtc *crtc,
> struct drm_atomic_state *state;
>   int ret = 0;
> 
> - if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
> - return -EINVAL;
> -
>   state = drm_atomic_state_alloc(plane->dev);
>   if (!state)
>   return -ENOMEM;
> @@ -2810,7 +2804,7 @@ int drm_atomic_helper_page_flip(struct drm_crtc *crtc,
> state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
> 
>  retry:
> - ret = page_flip_common(state, crtc, fb, event);
> + ret = page_flip_common(state, crtc, fb, event, flags);
>   if (ret != 0)
>   goto fail;
> 
> @@ -2865,9 +2859,6 @@ int drm_atomic_helper_page_flip_target(
>   struct drm_crtc_state *crtc_state;
>   int ret = 0;
> 
> - if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
> - return -EINVAL;
> -
>   state = drm_atomic_state_alloc(plane->dev);
>   if (!state)
>   return -ENOMEM;
> @@ -2875,7 +2866,7 @@ int drm_atomic_helper_page_flip_target(
>   state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
> 
>  retry:
> - ret = page_flip_common(state, crtc, fb, event);
> + ret = page_flip_common(state, crtc, fb, event, flags);
>   if (ret != 0)
>   goto fail;
> 
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 5c77c3f..76457a4 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -162,10 +162,16 @@ struct drm_crtc_state {
>* Target vertical blank period when a page flip
>* should take effect.
>*/
> -
>   u32 target_vblank;
> 
>   /**
> +  * @pflip_flags:
> +  *
> +  * Flip related config options

This isn't detailed enough. I propose something along the lines of

"DRM_MODE_PAGE_FLIP_* page flip flags, as passed to the page flip ioctl. 
Always zero for atomic commits that don't originate from a page flip ioctl."

You will then also need to reset the field to 0 at an appropriate point, as 
it's more an atomic commit transaction information than a state. Apart from 
that this patch looks good to me.

> +  */
> + u32 pflip_flags;
> +
> + /**
>* @event:
>*
>* Optional pointer to a DRM event to signal upon completion of the
> diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
> index db3bbde..57414ae 100644
> --- a/include/drm/drm_plane.h
> +++ b/include/drm/drm_plane.h
> @@ -122,6 +122,7 @@ struct drm_plane_state {
>*/
>   bool visible;
> 
>   struct drm_atomic_state *state;
>  };

-- 
Regards,

Laurent Pinchart

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[PATCH 2/2] drm/amdgpu: stop reserving a shared fence for VA updates

[Christian König]

From: Christian König 

We don't add any fences do the buffer, but just use it's address.

Additional to that we don't need a duplicates list here.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index ec5b184..9dd41e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -549,7 +549,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct amdgpu_bo_list_entry vm_pd;
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
-   struct list_head list, duplicates;
+   struct list_head list;
uint32_t invalid_flags, va_flags = 0;
int r = 0;
 
@@ -587,14 +587,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void 
*data,
return -ENOENT;
abo = gem_to_amdgpu_bo(gobj);
INIT_LIST_HEAD(&list);
-   INIT_LIST_HEAD(&duplicates);
tv.bo = &abo->tbo;
-   tv.shared = true;
+   tv.shared = false;
list_add(&tv.head, &list);
 
amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 
-   r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
+   r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
if (r) {
drm_gem_object_unreference_unlocked(gobj);
return r;
-- 
2.5.0

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[PATCH 1/2] drm/amdgpu: fix race in GEM VA map IOCTL

[Christian König]

From: Christian König 

Somebody could try to free the bo_va between mapping and updating it.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 45 ++---
 1 file changed, 14 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7a265d9..ec5b184 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -489,67 +489,50 @@ static int amdgpu_gem_va_check(void *param, struct 
amdgpu_bo *bo)
  *
  * @adev: amdgpu_device pointer
  * @bo_va: bo_va to update
+ * @list: validation list
+ * opration: map or unmap
  *
  * Update the bo_va directly after setting it's address. Errors are not
  * vital here, so they are not reported back to userspace.
  */
 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
+   struct list_head *list,
uint32_t operation)
 {
-   struct ttm_validate_buffer tv, *entry;
-   struct amdgpu_bo_list_entry vm_pd;
-   struct ww_acquire_ctx ticket;
-   struct list_head list, duplicates;
-   int r;
-
-   INIT_LIST_HEAD(&list);
-   INIT_LIST_HEAD(&duplicates);
-
-   tv.bo = &bo_va->bo->tbo;
-   tv.shared = true;
-   list_add(&tv.head, &list);
-
-   amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
-
-   /* Provide duplicates to avoid -EALREADY */
-   r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
-   if (r)
-   goto error_print;
+   struct ttm_validate_buffer *entry;
+   int r = -ERESTARTSYS;
 
-   list_for_each_entry(entry, &list, head) {
+   list_for_each_entry(entry, list, head) {
struct amdgpu_bo *bo =
container_of(entry->bo, struct amdgpu_bo, tbo);
 
/* if anything is swapped out don't swap it in here,
   just abort and wait for the next CS */
if (!amdgpu_bo_gpu_accessible(bo))
-   goto error_unreserve;
+   goto error;
 
if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
-   goto error_unreserve;
+   goto error;
}
 
r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check,
  NULL);
if (r)
-   goto error_unreserve;
+   goto error;
 
r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
if (r)
-   goto error_unreserve;
+   goto error;
 
r = amdgpu_vm_clear_freed(adev, bo_va->vm);
if (r)
-   goto error_unreserve;
+   goto error;
 
if (operation == AMDGPU_VA_OP_MAP)
r = amdgpu_vm_bo_update(adev, bo_va, false);
 
-error_unreserve:
-   ttm_eu_backoff_reservation(&ticket, &list);
-
-error_print:
+error:
if (r && r != -ERESTARTSYS)
DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 }
@@ -642,10 +625,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void 
*data,
default:
break;
}
-   ttm_eu_backoff_reservation(&ticket, &list);
if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
!amdgpu_vm_debug)
-   amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
+   amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
+   ttm_eu_backoff_reservation(&ticket, &list);
 
drm_gem_object_unreference_unlocked(gobj);
return r;
-- 
2.5.0

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Re: [v3 PATCH 0/3] Allow ASYNC flip with atomic helpers.

[Emil Velikov]

Hi Andrey,

Unrelated suggestion:

A handy trick - to save yourself a bit of time (and "get it right")
you can use `git format-patch -vX ...' [it also works with send-email]
to have the version in the subject prefix.
Feel free to share it with the team - it seems that many people
manually edit the patch(es).

-Emil
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Re: [PATCH libdrm 0/3] some -pro patches for integration

[Christian König]

Reviewed-by: Christian König .

Am 29.01.2017 um 23:51 schrieb Edward O'Callaghan:

This series is,
Reviewed-by: Edward O'Callaghan 

On 01/29/2017 06:49 AM, Grazvydas Ignotas wrote:

I've taken several patches from amdgpu-pro libdrm that look useful
to me and I think can be applied already. The only things I did was
rebasing, fixing some typos and dropping Change-Id.

Alex Xie (3):
   amdgpu: Free/uninit vamgr_32 in theoretically correct order
   amdgpu: vamgr can be a struct instead of a pointer
   amdgpu: vamgr_32 can be a struct instead of a pointer

  amdgpu/amdgpu_device.c   | 24 +++-
  amdgpu/amdgpu_internal.h |  4 ++--
  amdgpu/amdgpu_vamgr.c|  6 +++---
  3 files changed, 12 insertions(+), 22 deletions(-)




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