Re: [PATCH 4/4] drm/amdgpu: extend profiling mode.

2017-01-31 Thread Andy Furniss 

Andy Furniss wrote:

Rex Zhu wrote:

in profiling mode, powerplay will fix power state
as stable as possible.and disable gfx cg and LBPW feature.

profile_standard: as a prerequisite, ensure power and thermal
sustainable, set clocks ratio as close to the highest clock
ratio as possible.
profile_min_sclk: fix mclk as profile_normal, set lowest sclk
profile_min_mclk: fix sclk as profile_normal, set lowest mclk
profile_peak: set highest sclk and mclk, power and thermal not
sustainable
profile_exit: exit profile mode. enable gfx cg/lbpw feature.


Testing R9 285 Tonga on drm-next-4.11-wip

This commit has the effect that doing

echo high > /sys/class/drm/card0/device/power_dpm_force_performance_level

instantly forces fan to (I guess) max, where normally it doesn't
need anything like as fast with the clocks high when doing nothing else.


Ping - just in case this got missed, still the same on current 
drm-next-4.11-wip



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Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

2017-01-31 Thread Alex Deucher 
On Tue, Jan 31, 2017 at 5:06 PM, Emil Velikov  wrote:
> On 31 January 2017 at 15:43, Deucher, Alexander
>  wrote:
>>> -Original Message-
>>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>>> Of Dieter Nützel
>>> Sent: Tuesday, January 31, 2017 6:25 AM
>>> To: Michel Dänzer
>>> Cc: Alex Deucher; mesa-...@lists.freedesktop.org; amd-
>>> g...@lists.freedesktop.org
>>> Subject: Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in
>>> DRM_RADEON_GEM_INFO ioctl
>>>
>>> Hello Michel,
>>>
>>> as this is for radeon, do you think this could/should fix
>>> the wrong reported VRAM size with Unigine_Heaven/-Valley, too?
>>> Maybe speed things up? ;-)
>>>
>>> Unigine_Valley-1.0
>>>
>>> GPU: Unknown GPU x1
>>> System memory: 24102 MB
>>> Video memory:  256 MB
>>> Sync threads:  7
>>> Async threads: 8
>>>
>>> I'll try patching openSUSE Kernel:stable 4.9.6-2 with this
>>> and maybe this could then go into 4.10-rc7 'cause it is a
>>> bugfix. - Alex?
>>
>> This patch just fixes the case of the HUD reporting the wrong amount of 
>> visible vram.  Most 3D apps just default to 256MB if they don't know how 
>> much vram is.  The problem is GL never provided a core way to determine how 
>> much vram is available on a GPU so lots of vendor specific extensions and 
>> driver specific methods popped up to address this.
>>
> vram_size is used for available_texture_mem in st/nine and
> GLX_RENDERER_VIDEO_MEMORY_MESA via GLX_MESA_query_renderer.
> So maybe we want this in older/stable kernel and mesa releases ? Not
> sure how many apps use/honour these though ;-)

vram_size was always correct.  it was just visible vram size that was wrong.

Alex
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Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

2017-01-31 Thread Emil Velikov 
On 31 January 2017 at 15:43, Deucher, Alexander
 wrote:
>> -Original Message-
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Dieter Nützel
>> Sent: Tuesday, January 31, 2017 6:25 AM
>> To: Michel Dänzer
>> Cc: Alex Deucher; mesa-...@lists.freedesktop.org; amd-
>> g...@lists.freedesktop.org
>> Subject: Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in
>> DRM_RADEON_GEM_INFO ioctl
>>
>> Hello Michel,
>>
>> as this is for radeon, do you think this could/should fix
>> the wrong reported VRAM size with Unigine_Heaven/-Valley, too?
>> Maybe speed things up? ;-)
>>
>> Unigine_Valley-1.0
>>
>> GPU: Unknown GPU x1
>> System memory: 24102 MB
>> Video memory:  256 MB
>> Sync threads:  7
>> Async threads: 8
>>
>> I'll try patching openSUSE Kernel:stable 4.9.6-2 with this
>> and maybe this could then go into 4.10-rc7 'cause it is a
>> bugfix. - Alex?
>
> This patch just fixes the case of the HUD reporting the wrong amount of 
> visible vram.  Most 3D apps just default to 256MB if they don't know how much 
> vram is.  The problem is GL never provided a core way to determine how much 
> vram is available on a GPU so lots of vendor specific extensions and driver 
> specific methods popped up to address this.
>
vram_size is used for available_texture_mem in st/nine and
GLX_RENDERER_VIDEO_MEMORY_MESA via GLX_MESA_query_renderer.
So maybe we want this in older/stable kernel and mesa releases ? Not
sure how many apps use/honour these though ;-)

-Emil
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Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

2017-01-31 Thread Dieter Nützel 

Am 31.01.2017 16:43, schrieb Deucher, Alexander:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Dieter Nützel
Sent: Tuesday, January 31, 2017 6:25 AM
To: Michel Dänzer
Cc: Alex Deucher; mesa-...@lists.freedesktop.org; amd-
g...@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible 
values in

DRM_RADEON_GEM_INFO ioctl

Hello Michel,

as this is for radeon, do you think this could/should fix
the wrong reported VRAM size with Unigine_Heaven/-Valley, too?
Maybe speed things up? ;-)

Unigine_Valley-1.0

GPU: Unknown GPU x1
System memory: 24102 MB
Video memory:  256 MB
Sync threads:  7
Async threads: 8

I'll try patching openSUSE Kernel:stable 4.9.6-2 with this
and maybe this could then go into 4.10-rc7 'cause it is a
bugfix. - Alex?


This patch just fixes the case of the HUD reporting the wrong amount
of visible vram.  Most 3D apps just default to 256MB if they don't
know how much vram is.  The problem is GL never provided a core way to
determine how much vram is available on a GPU so lots of vendor
specific extensions and driver specific methods popped up to address
this.

Alex


Ah, no hurry then.

Thanks for clarification.

Dieter


Greetings,
Dieter

Am 31.01.2017 07:54, schrieb Michel Dänzer:
> From: Michel Dänzer 
>
> vram_size is supposed to be the total amount of VRAM that can be used
> by
> userspace, which corresponds to the TTM VRAM manager size (which is
> normally the full amount of VRAM, but can be just the visible VRAM when
> DMA can't be used for BO migration for some reason).
>
> The above was incorrectly used for vram_visible before, resulting in
> generally too large values being reported.
>
> Signed-off-by: Michel Dänzer 
> ---
>  drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
>  drivers/gpu/drm/radeon/radeon_gem.c | 4 ++--
>  2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index a252bc407aa2..88c41d43ec3d 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -97,9 +97,10 @@
>   *   2.46.0 - Add PFP_SYNC_ME support on evergreen
>   *   2.47.0 - Add UVD_NO_OP register support
>   *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
> + *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct
> vram_size/visible values
>   */
>  #define KMS_DRIVER_MAJOR  2
> -#define KMS_DRIVER_MINOR  48
> +#define KMS_DRIVER_MINOR  49
>  #define KMS_DRIVER_PATCHLEVEL 0
>  int radeon_driver_load_kms(struct drm_device *dev, unsigned long
> flags);
>  int radeon_driver_unload_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
> b/drivers/gpu/drm/radeon/radeon_gem.c
> index 0bcffd8a7bd3..96683f5b2b1b 100644
> --- a/drivers/gpu/drm/radeon/radeon_gem.c
> +++ b/drivers/gpu/drm/radeon/radeon_gem.c
> @@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev,
> void *data,
>
>man = &rdev->mman.bdev.man[TTM_PL_VRAM];
>
> -  args->vram_size = rdev->mc.real_vram_size;
> -  args->vram_visible = (u64)man->size << PAGE_SHIFT;
> +  args->vram_size = (u64)man->size << PAGE_SHIFT;
> +  args->vram_visible = rdev->mc.visible_vram_size;
>args->vram_visible -= rdev->vram_pin_size;
>args->gart_size = rdev->mc.gtt_size;
>args->gart_size -= rdev->gart_pin_size;
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[PATCH 11/13] drm/amd/display: add dcfclk reporting to pplib

2017-01-31 Thread Harry Wentland 
From: Dmytro Laktyushkin 

Change-Id: I378d9305bb94d2e0a89da804e63d8a1fa7aee51d
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 48 +
 drivers/gpu/drm/amd/display/dc/inc/core_types.h |  1 +
 2 files changed, 18 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e05e4199e38a..9d2f78f21748 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1065,7 +1065,7 @@ bool dc_pre_update_surfaces_to_stream(
 {
int i, j;
struct core_dc *core_dc = DC_TO_CORE(dc);
-   uint32_t prev_disp_clk = 
core_dc->current_context->bw_results.dispclk_khz;
+   int prev_disp_clk = core_dc->current_context->bw_results.dispclk_khz;
int new_disp_clk;
struct dc_stream_status *stream_status = NULL;
struct validate_context *context;
@@ -1146,36 +1146,23 @@ bool dc_pre_update_surfaces_to_stream(
}
}
 
-   if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, context) != 
DC_OK) {
-   BREAK_TO_DEBUGGER();
-   ret = false;
-   goto unexpected_fail;
-   }
-   new_disp_clk = context->bw_results.dispclk_khz;
-
-   if (core_dc->res_pool->funcs->apply_clk_constraints) {
-   temp_context = core_dc->res_pool->funcs->apply_clk_constraints(
-   core_dc,
-   context);
-   if (!temp_context) {
-   dm_error("%s:failed apply clk constraints\n", __func__);
+   if (core_dc->res_pool->funcs->validate_bandwidth)
+   if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, 
context) != DC_OK) {
+   BREAK_TO_DEBUGGER();
ret = false;
goto unexpected_fail;
}
-   resource_validate_ctx_destruct(context);
-   ASSERT(core_dc->scratch_val_ctx == temp_context);
-   core_dc->scratch_val_ctx = context;
-   context = temp_context;
-   }
+   new_disp_clk = context->bw_results.dispclk_khz;
 
-   if (prev_disp_clk < new_disp_clk) {
+   if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)
+   && prev_disp_clk < new_disp_clk) {
pplib_apply_display_requirements(core_dc, context,
&context->pp_display_cfg);
context->res_ctx.pool->display_clock->funcs->set_clock(
context->res_ctx.pool->display_clock,
-   context->bw_results.dispclk_khz * 115 / 100);
-   core_dc->current_context->bw_results.dispclk_khz =
-   context->bw_results.dispclk_khz;
+   new_disp_clk * 115 / 100);
+   core_dc->current_context->bw_results.dispclk_khz = new_disp_clk;
+   core_dc->current_context->dispclk_khz = new_disp_clk;
}
 
for (i = 0; i < new_surface_count; i++)
@@ -1209,15 +1196,14 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == 
NULL) {
core_dc->current_context->res_ctx.pipe_ctx[i].pipe_idx 
= i;
core_dc->hwss.power_down_front_end(
-   core_dc, 
&core_dc->current_context->res_ctx.pipe_ctx[i]);
+   core_dc, 
&core_dc->current_context->res_ctx.pipe_ctx[i]);
+   }
+   if (core_dc->res_pool->funcs->validate_bandwidth)
+   if (core_dc->res_pool->funcs->validate_bandwidth(
+   core_dc, core_dc->current_context) != DC_OK) {
+   BREAK_TO_DEBUGGER();
+   return false;
}
-
-
-   if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, 
core_dc->current_context)
-   != DC_OK) {
-   BREAK_TO_DEBUGGER();
-   return false;
-   }
 
core_dc->hwss.set_bandwidth(core_dc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 1a81e83d1785..124df6795b34 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -316,6 +316,7 @@ struct validate_context {
struct bw_calcs_output bw_results;
/* Note: these are big structures, do *not* put on stack! */
struct dm_pp_display_configuration pp_display_cfg;
+   int dispclk_khz;
 };
 
 #endif /* _CORE_TYPES_H_ */
-- 
2.9.3

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[PATCH 13/13] drm/amd/display: remove CV-specific timing standard

2017-01-31 Thread Harry Wentland 
From: Charlene Liu 

Change-Id: I6a9cb83cf5963e8b64e1ecf01a25921511a91972
Signed-off-by: Charlene Liu 
Reviewed-by: Jordan Lazare 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c| 5 -
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 --
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 4 
 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c | 5 -
 4 files changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 9f462a299ff3..6cd1e93b5084 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -66,11 +66,6 @@ void color_space_to_black_color(
}
 
switch (colorspace) {
-   case COLOR_SPACE_YPBPR601:
-   *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_TV];
-   break;
-
-   case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YCBCR601_LIMITED:
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 53c73de75da9..21092f33c83b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -435,8 +435,6 @@ enum dc_color_space {
COLOR_SPACE_UNKNOWN,
COLOR_SPACE_SRGB,
COLOR_SPACE_SRGB_LIMITED,
-   COLOR_SPACE_YPBPR601,
-   COLOR_SPACE_YPBPR709,
COLOR_SPACE_YCBCR601,
COLOR_SPACE_YCBCR709,
COLOR_SPACE_YCBCR601_LIMITED,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 62f01911639f..9247afd4d42f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -827,14 +827,12 @@ static bool configure_graphics_mode(
OUTPUT_CSC_GRPH_MODE, 1);
break;
case COLOR_SPACE_YCBCR601:
-   case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_GRPH_MODE, 2);
break;
case COLOR_SPACE_YCBCR709:
-   case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR709_LIMITED:
/* YCbCr709 */
REG_SET(OUTPUT_CSC_CONTROL, 0,
@@ -858,14 +856,12 @@ static bool configure_graphics_mode(
OUTPUT_CSC_GRPH_MODE, 1);
break;
case COLOR_SPACE_YCBCR601:
-   case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_GRPH_MODE, 2);
break;
case COLOR_SPACE_YCBCR709:
-   case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR709_LIMITED:
 /* YCbCr709 */
REG_SET(OUTPUT_CSC_CONTROL, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
index 6995a3de7564..019effe4c99c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
@@ -383,8 +383,6 @@ static bool configure_graphics_mode_v(
/* not supported for underlay on CZ */
return false;
 
-   case COLOR_SPACE_YCBCR601:
-   case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
set_reg_field_value(
@@ -394,7 +392,6 @@ static bool configure_graphics_mode_v(
OUTPUT_CSC_MODE);
break;
case COLOR_SPACE_YCBCR709:
-   case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR709_LIMITED:
/* YCbCr709 */
set_reg_field_value(
@@ -421,7 +418,6 @@ static bool configure_graphics_mode_v(
/* not supported for underlay on CZ */
return false;
case COLOR_SPACE_YCBCR601:
-   case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
set_reg_field_value(
@@ -431,7 +427,6 @@ static bool configure_graphics_mode_v(
OUTPUT_CSC_MODE);

[PATCH 10/13] drm/amd/display: Debug option to force enable ABM

2017-01-31 Thread Harry Wentland 
From: Anthony Koo 

Change-Id: I3c17972edb18ebb39621ca5593fdd40050252afc
Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1308af59d839..d7f848495d8a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -143,6 +143,7 @@ struct dc_debug {
bool disable_dfs_bypass;
bool disable_clock_gate;
bool disable_dmcu;
+   bool force_abm_enable;
 };
 
 struct dc {
-- 
2.9.3

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[PATCH 12/13] drm/amd/display: surface validation on dce100

2017-01-31 Thread Harry Wentland 
From: Leon Elazar 

Change-Id: Ifbb174d965a5059b835c1de6b7f21a5c7c68408e
Signed-off-by: Leon Elazar 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 6ae334b42fbf..800b22e70c7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -789,9 +789,9 @@ static bool dce100_validate_surface_sets(
return false;
 
if (set[i].surfaces[0]->clip_rect.width
-   != set[i].stream->src.width
+   < set[i].stream->src.width
|| set[i].surfaces[0]->clip_rect.height
-   != set[i].stream->src.height)
+   < set[i].stream->src.height)
return false;
if (set[i].surfaces[0]->format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-- 
2.9.3

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[PATCH 08/13] drm/amd/display: Support ABM without PPlib

2017-01-31 Thread Harry Wentland 
From: Anthony Koo 

Fix problem with loading IRAM

Change-Id: I255dfd27195714e718c8976817de96dd878f2e1a
Signed-off-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h  |  7 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  | 26 +++---
 2 files changed, 9 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index b026157a2eea..33c1754f04f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -30,6 +30,7 @@
 #include "dmcu.h"
 
 #define DMCU_COMMON_REG_LIST_DCE_BASE() \
+   SR(DMCU_CTRL), \
SR(DMCU_RAM_ACCESS_CTRL), \
SR(DMCU_IRAM_WR_CTRL), \
SR(DMCU_IRAM_WR_DATA)
@@ -42,6 +43,8 @@
.field_name = reg_name ## __ ## field_name ## post_fix
 
 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
+   DMCU_SF(DMCU_CTRL, \
+   DMCU_ENABLE, mask_sh), \
DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
IRAM_HOST_ACCESS_EN, mask_sh), \
DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
@@ -55,7 +58,8 @@
 #define DMCU_REG_FIELD_LIST(type) \
type DMCU_IRAM_MEM_PWR_STATE; \
type IRAM_HOST_ACCESS_EN; \
-   type IRAM_WR_ADDR_AUTO_INC
+   type IRAM_WR_ADDR_AUTO_INC; \
+   type DMCU_ENABLE
 
 struct dce_dmcu_shift {
DMCU_REG_FIELD_LIST(uint8_t);
@@ -66,6 +70,7 @@ struct dce_dmcu_mask {
 };
 
 struct dce_dmcu_registers {
+   uint32_t DMCU_CTRL;
uint32_t DMCU_RAM_ACCESS_CTRL;
uint32_t DCI_MEM_PWR_STATUS;
uint32_t DMU_MEM_PWR_CNTL;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 053f72b91b3c..8a07665e693b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -39,18 +39,13 @@
SRI(DC_HPD_CONTROL, HPD, id)
 
 #define LE_COMMON_REG_LIST_BASE(id) \
-   SR(BL_PWM_CNTL), \
-   SR(BL_PWM_GRP1_REG_LOCK), \
-   SR(BL_PWM_PERIOD_CNTL), \
-   SR(LVTMA_PWRSEQ_CNTL), \
-   SR(LVTMA_PWRSEQ_STATE), \
-   SR(BL_PWM_CNTL2), \
-   SR(LVTMA_PWRSEQ_REF_DIV), \
SR(MASTER_COMM_DATA_REG1), \
SR(MASTER_COMM_DATA_REG2), \
SR(MASTER_COMM_DATA_REG3), \
SR(MASTER_COMM_CMD_REG), \
SR(MASTER_COMM_CNTL_REG), \
+   SR(LVTMA_PWRSEQ_CNTL), \
+   SR(LVTMA_PWRSEQ_STATE), \
SR(DMCU_RAM_ACCESS_CTRL), \
SR(DMCU_IRAM_RD_CTRL), \
SR(DMCU_IRAM_RD_DATA), \
@@ -81,22 +76,16 @@
LE_COMMON_REG_LIST_BASE(id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-   SR(BIOS_SCRATCH_2), \
-   SR(BL1_PWM_USER_LEVEL), \
SR(DCI_MEM_PWR_STATUS)
 
#define LE_DCE110_REG_LIST(id)\
LE_COMMON_REG_LIST_BASE(id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-   SR(BIOS_SCRATCH_2), \
-   SR(BL1_PWM_USER_LEVEL), \
SR(DCI_MEM_PWR_STATUS)
 
#define LE_DCE80_REG_LIST(id)\
-   SR(BIOS_SCRATCH_2), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-   SR(BL1_PWM_USER_LEVEL), \
LE_COMMON_REG_LIST_BASE(id)
 
 
@@ -110,24 +99,16 @@ struct dce110_link_enc_hpd_registers {
 };
 
 struct dce110_link_enc_registers {
-   /* BL registers */
-   uint32_t BL_PWM_CNTL;
-   uint32_t BL_PWM_GRP1_REG_LOCK;
-   uint32_t BL_PWM_PERIOD_CNTL;
+   /* Backlight registers */
uint32_t LVTMA_PWRSEQ_CNTL;
uint32_t LVTMA_PWRSEQ_STATE;
-   uint32_t BL_PWM_CNTL2;
-   uint32_t LVTMA_PWRSEQ_REF_DIV;
 
/* DMCU registers */
-   uint32_t BL1_PWM_USER_LEVEL;
-   uint32_t ABM0_BL1_PWM_USER_LEVEL;
uint32_t MASTER_COMM_DATA_REG1;
uint32_t MASTER_COMM_DATA_REG2;
uint32_t MASTER_COMM_DATA_REG3;
uint32_t MASTER_COMM_CMD_REG;
uint32_t MASTER_COMM_CNTL_REG;
-   uint32_t BIOS_SCRATCH_2;
uint32_t DMCU_RAM_ACCESS_CTRL;
uint32_t DCI_MEM_PWR_STATUS;
uint32_t DMU_MEM_PWR_CNTL;
@@ -136,7 +117,6 @@ struct dce110_link_enc_registers {
uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
uint32_t SMU_INTERRUPT_CONTROL;
 
-
/* Common DP registers */
uint32_t DIG_BE_CNTL;
uint32_t DIG_BE_EN_CNTL;
-- 
2.9.3

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[PATCH 02/13] drm/amd/display: Expose hw sequencer gamma function

2017-01-31 Thread Harry Wentland 
From: Yongqiang Sun 

Change-Id: I82bc709bb81faad5becdfe238de2d36b3183ea7c
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c3e0865f3148..6acb9faf29f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -578,7 +578,7 @@ static bool convert_to_custom_float(
return true;
 }
 
-static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
+bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
*output_tf, struct pwl_params *regamma_params)
 {
struct curve_points *arr_points;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
index a6b4d0d2429f..68632dd28155 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -58,5 +58,8 @@ void dce110_power_down(struct core_dc *dc);
 
 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx);
 
+bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
+   *output_tf, struct pwl_params *regamma_params);
+
 #endif /* __DC_HWSS_DCE110_H__ */
 
-- 
2.9.3

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[PATCH 09/13] drm/amd/display: Changes for enable dcc mode.

2017-01-31 Thread Harry Wentland 
From: Yongqiang Sun 

Change-Id: I7b027fbf1680c359f724347844258296ff688cda
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h  |  7 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  | 26 +++---
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 33c1754f04f1..b026157a2eea 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -30,7 +30,6 @@
 #include "dmcu.h"
 
 #define DMCU_COMMON_REG_LIST_DCE_BASE() \
-   SR(DMCU_CTRL), \
SR(DMCU_RAM_ACCESS_CTRL), \
SR(DMCU_IRAM_WR_CTRL), \
SR(DMCU_IRAM_WR_DATA)
@@ -43,8 +42,6 @@
.field_name = reg_name ## __ ## field_name ## post_fix
 
 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
-   DMCU_SF(DMCU_CTRL, \
-   DMCU_ENABLE, mask_sh), \
DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
IRAM_HOST_ACCESS_EN, mask_sh), \
DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
@@ -58,8 +55,7 @@
 #define DMCU_REG_FIELD_LIST(type) \
type DMCU_IRAM_MEM_PWR_STATE; \
type IRAM_HOST_ACCESS_EN; \
-   type IRAM_WR_ADDR_AUTO_INC; \
-   type DMCU_ENABLE
+   type IRAM_WR_ADDR_AUTO_INC
 
 struct dce_dmcu_shift {
DMCU_REG_FIELD_LIST(uint8_t);
@@ -70,7 +66,6 @@ struct dce_dmcu_mask {
 };
 
 struct dce_dmcu_registers {
-   uint32_t DMCU_CTRL;
uint32_t DMCU_RAM_ACCESS_CTRL;
uint32_t DCI_MEM_PWR_STATUS;
uint32_t DMU_MEM_PWR_CNTL;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 8a07665e693b..053f72b91b3c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -39,13 +39,18 @@
SRI(DC_HPD_CONTROL, HPD, id)
 
 #define LE_COMMON_REG_LIST_BASE(id) \
+   SR(BL_PWM_CNTL), \
+   SR(BL_PWM_GRP1_REG_LOCK), \
+   SR(BL_PWM_PERIOD_CNTL), \
+   SR(LVTMA_PWRSEQ_CNTL), \
+   SR(LVTMA_PWRSEQ_STATE), \
+   SR(BL_PWM_CNTL2), \
+   SR(LVTMA_PWRSEQ_REF_DIV), \
SR(MASTER_COMM_DATA_REG1), \
SR(MASTER_COMM_DATA_REG2), \
SR(MASTER_COMM_DATA_REG3), \
SR(MASTER_COMM_CMD_REG), \
SR(MASTER_COMM_CNTL_REG), \
-   SR(LVTMA_PWRSEQ_CNTL), \
-   SR(LVTMA_PWRSEQ_STATE), \
SR(DMCU_RAM_ACCESS_CTRL), \
SR(DMCU_IRAM_RD_CTRL), \
SR(DMCU_IRAM_RD_DATA), \
@@ -76,16 +81,22 @@
LE_COMMON_REG_LIST_BASE(id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+   SR(BIOS_SCRATCH_2), \
+   SR(BL1_PWM_USER_LEVEL), \
SR(DCI_MEM_PWR_STATUS)
 
#define LE_DCE110_REG_LIST(id)\
LE_COMMON_REG_LIST_BASE(id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+   SR(BIOS_SCRATCH_2), \
+   SR(BL1_PWM_USER_LEVEL), \
SR(DCI_MEM_PWR_STATUS)
 
#define LE_DCE80_REG_LIST(id)\
+   SR(BIOS_SCRATCH_2), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+   SR(BL1_PWM_USER_LEVEL), \
LE_COMMON_REG_LIST_BASE(id)
 
 
@@ -99,16 +110,24 @@ struct dce110_link_enc_hpd_registers {
 };
 
 struct dce110_link_enc_registers {
-   /* Backlight registers */
+   /* BL registers */
+   uint32_t BL_PWM_CNTL;
+   uint32_t BL_PWM_GRP1_REG_LOCK;
+   uint32_t BL_PWM_PERIOD_CNTL;
uint32_t LVTMA_PWRSEQ_CNTL;
uint32_t LVTMA_PWRSEQ_STATE;
+   uint32_t BL_PWM_CNTL2;
+   uint32_t LVTMA_PWRSEQ_REF_DIV;
 
/* DMCU registers */
+   uint32_t BL1_PWM_USER_LEVEL;
+   uint32_t ABM0_BL1_PWM_USER_LEVEL;
uint32_t MASTER_COMM_DATA_REG1;
uint32_t MASTER_COMM_DATA_REG2;
uint32_t MASTER_COMM_DATA_REG3;
uint32_t MASTER_COMM_CMD_REG;
uint32_t MASTER_COMM_CNTL_REG;
+   uint32_t BIOS_SCRATCH_2;
uint32_t DMCU_RAM_ACCESS_CTRL;
uint32_t DCI_MEM_PWR_STATUS;
uint32_t DMU_MEM_PWR_CNTL;
@@ -117,6 +136,7 @@ struct dce110_link_enc_registers {
uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
uint32_t SMU_INTERRUPT_CONTROL;
 
+
/* Common DP registers */
uint32_t DIG_BE_CNTL;
uint32_t DIG_BE_EN_CNTL;
-- 
2.9.3

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[PATCH 06/13] drm/amd/display: Move backlight from encoder to ABM

2017-01-31 Thread Harry Wentland 
From: Anthony Koo 

Change-Id: Ib35cfb683cb78a3d111400864f12acba60c25579
Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  34 ---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  63 +++--
 drivers/gpu/drm/amd/display/dc/dc.h|   5 -
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c   | 264 +++--
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h   |  35 ++-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 260 
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  24 --
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|   4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h|   5 +
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |   5 -
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   4 -
 .../amd/display/dc/virtual/virtual_link_encoder.c  |  13 -
 12 files changed, 316 insertions(+), 400 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 152c694cc044..499ef561bbfc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -240,34 +240,6 @@ static void stream_update_scaling(
}
 }
 
-static bool set_backlight(struct dc *dc, unsigned int backlight_level,
-   unsigned int frame_ramp, const struct dc_stream *stream)
-{
-   struct core_dc *core_dc = DC_TO_CORE(dc);
-   int i;
-
-   if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
-   for (i = 0; i < core_dc->link_count; i++)
-   dc_link_set_backlight_level(&core_dc->links[i]->public,
-   backlight_level, frame_ramp, stream);
-   }
-
-   return true;
-
-}
-
-static bool init_dmcu_backlight_settings(struct dc *dc)
-{
-   struct core_dc *core_dc = DC_TO_CORE(dc);
-   int i;
-
-   for (i = 0; i < core_dc->link_count; i++)
-   dc_link_init_dmcu_backlight_settings
-   (&core_dc->links[i]->public);
-
-   return true;
-}
-
 static bool set_psr_enable(struct dc *dc, bool enable)
 {
struct core_dc *core_dc = DC_TO_CORE(dc);
@@ -390,12 +362,6 @@ static void allocate_dc_stream_funcs(struct core_dc 
*core_dc)
core_dc->public.stream_funcs.set_gamut_remap =
set_gamut_remap;
 
-   core_dc->public.stream_funcs.set_backlight =
-   set_backlight;
-
-   core_dc->public.stream_funcs.init_dmcu_backlight_settings =
-   init_dmcu_backlight_settings;
-
core_dc->public.stream_funcs.set_psr_enable =
set_psr_enable;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 84efc25d0e33..2bceb3aa24b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -37,6 +37,7 @@
 #include "link_encoder.h"
 #include "hw_sequencer.h"
 #include "resource.h"
+#include "abm.h"
 #include "fixed31_32.h"
 #include "dpcd_defs.h"
 
@@ -1386,48 +1387,40 @@ bool dc_link_set_backlight_level(const struct dc_link 
*dc_link, uint32_t level,
uint32_t frame_ramp, const struct dc_stream *stream)
 {
struct core_link *link = DC_LINK_TO_CORE(dc_link);
-   struct dc_context *ctx = link->ctx;
-   struct core_dc *core_dc = DC_TO_CORE(ctx->dc);
-   struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
+   struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
+   struct core_stream *core_stream = NULL;
+   struct abm *abm = core_dc->res_pool->abm;
unsigned int controller_id = 0;
int i;
-   uint32_t dmcu_status;
 
-   dm_logger_write(ctx->logger, LOG_BACKLIGHT,
-   "New Backlight level: %d (0x%X)\n", level, level);
+   if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
+   return false;
 
-   dmcu_status = dm_read_reg(ctx, mmDMCU_STATUS);
+   dm_logger_write(link->ctx->logger, LOG_BACKLIGHT,
+   "New Backlight level: %d (0x%X)\n", level, level);
 
-   /* If DMCU is in reset state, DMCU is uninitialized */
-   if (get_reg_field_value(dmcu_status, mmDMCU_STATUS, UC_IN_RESET)) {
-   link->link_enc->funcs->set_lcd_backlight_level(link->link_enc,
-   level);
-   } else {
-   for (i = 0; i < MAX_PIPES; i++) {
-   if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
-   == core_stream)
-   /* dmcu -1 for all controller id values,
-* therefore +1 here
-*/
-   controller_id = 
core_dc->current_context->res_ctx.
-   pi

[PATCH 07/13] drm/amd/display: Make new pixel clock more obvious

2017-01-31 Thread Harry Wentland 
From: Dmytro Laktyushkin 

Change-Id: I9fc95de2518a0b54300961ec039a693657df8602
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 499ef561bbfc..e05e4199e38a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1066,6 +1066,7 @@ bool dc_pre_update_surfaces_to_stream(
int i, j;
struct core_dc *core_dc = DC_TO_CORE(dc);
uint32_t prev_disp_clk = 
core_dc->current_context->bw_results.dispclk_khz;
+   int new_disp_clk;
struct dc_stream_status *stream_status = NULL;
struct validate_context *context;
struct validate_context *temp_context;
@@ -1150,6 +1151,7 @@ bool dc_pre_update_surfaces_to_stream(
ret = false;
goto unexpected_fail;
}
+   new_disp_clk = context->bw_results.dispclk_khz;
 
if (core_dc->res_pool->funcs->apply_clk_constraints) {
temp_context = core_dc->res_pool->funcs->apply_clk_constraints(
@@ -1166,7 +1168,7 @@ bool dc_pre_update_surfaces_to_stream(
context = temp_context;
}
 
-   if (prev_disp_clk < context->bw_results.dispclk_khz) {
+   if (prev_disp_clk < new_disp_clk) {
pplib_apply_display_requirements(core_dc, context,
&context->pp_display_cfg);
context->res_ctx.pool->display_clock->funcs->set_clock(
-- 
2.9.3

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[PATCH 05/13] drm/amd/display: DMCU Compile and Load

2017-01-31 Thread Harry Wentland 
From: Anthony Koo 

Change-Id: I8534864ab5d33b43d29c130e7dcfe381e8e0a52f
Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  16 --
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  12 --
 drivers/gpu/drm/amd/display/dc/dc.h|   4 +-
 drivers/gpu/drm/amd/display/dc/dce/Makefile|   2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c   | 214 +
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h   | 157 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c  | 127 
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h  |  91 +
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  |  40 +---
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|   6 +
 .../drm/amd/display/dc/dce110/dce110_resource.c|  52 +
 .../drm/amd/display/dc/dce112/dce112_resource.c|  51 +
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h|  40 
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h   |  42 
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |   1 -
 16 files changed, 788 insertions(+), 70 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 474c2d42525d..152c694cc044 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -268,19 +268,6 @@ static bool init_dmcu_backlight_settings(struct dc *dc)
return true;
 }
 
-
-static bool set_abm_level(struct dc *dc, unsigned int abm_level)
-{
-   struct core_dc *core_dc = DC_TO_CORE(dc);
-   int i;
-
-   for (i = 0; i < core_dc->link_count; i++)
-   dc_link_set_abm_level(&core_dc->links[i]->public,
-   abm_level);
-
-   return true;
-}
-
 static bool set_psr_enable(struct dc *dc, bool enable)
 {
struct core_dc *core_dc = DC_TO_CORE(dc);
@@ -409,9 +396,6 @@ static void allocate_dc_stream_funcs(struct core_dc 
*core_dc)
core_dc->public.stream_funcs.init_dmcu_backlight_settings =
init_dmcu_backlight_settings;
 
-   core_dc->public.stream_funcs.set_abm_level =
-   set_abm_level;
-
core_dc->public.stream_funcs.set_psr_enable =
set_psr_enable;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f4f46d4f0cf0..84efc25d0e33 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1432,18 +1432,6 @@ bool dc_link_init_dmcu_backlight_settings(const struct 
dc_link *dc_link)
return true;
 }
 
-bool dc_link_set_abm_level(const struct dc_link *dc_link, uint32_t level)
-{
-   struct core_link *link = DC_LINK_TO_CORE(dc_link);
-   struct dc_context *ctx = link->ctx;
-
-   dm_logger_write(ctx->logger, LOG_BACKLIGHT,
-   "New abm level: %d (0x%X)\n", level, level);
-
-   link->link_enc->funcs->set_dmcu_abm_level(link->link_enc, level);
-   return true;
-}
-
 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable)
 {
struct core_link *link = DC_LINK_TO_CORE(dc_link);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index f485f70bf3ef..8cb53b626641 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -103,7 +103,6 @@ struct dc_stream_funcs {
bool (*set_backlight)(struct dc *dc, unsigned int backlight_level,
unsigned int frame_ramp, const struct dc_stream *stream);
bool (*init_dmcu_backlight_settings)(struct dc *dc);
-   bool (*set_abm_level)(struct dc *dc, unsigned int abm_level);
bool (*set_psr_enable)(struct dc *dc, bool enable);
bool (*setup_psr)(struct dc *dc, const struct dc_stream *stream);
 };
@@ -575,8 +574,6 @@ bool dc_link_set_backlight_level(const struct dc_link 
*dc_link, uint32_t level,
 
 bool dc_link_init_dmcu_backlight_settings(const struct dc_link *dc_link);
 
-bool dc_link_set_abm_level(const struct dc_link *dc_link, uint32_t level);
-
 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
 
 bool dc_link_setup_psr(const struct dc_link *dc_link,
@@ -730,4 +727,5 @@ bool dc_submit_i2c(
uint32_t link_index,
struct i2c_command *cmd);
 
+
 #endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile 
b/drive

[PATCH 04/13] drm/amd/display: Change power gating off sequence to fix hang

2017-01-31 Thread Harry Wentland 
From: Yongqiang Sun 

Power off plane clear all the reg values includes cursor.
When OS call set cursor position, cursor address reg is cleared,
results in system hard hang.

Change-Id: Id4f2fce5fab34cc0091e0a4a51e1274e9205ea48
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 75718151356d..474c2d42525d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1254,9 +1254,12 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
post_surface_trace(dc);
 
for (i = 0; i < core_dc->current_context->res_ctx.pool->pipe_count; i++)
-   if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == 
NULL)
+   if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == 
NULL) {
+   core_dc->current_context->res_ctx.pipe_ctx[i].pipe_idx 
= i;
core_dc->hwss.power_down_front_end(
-   core_dc, 
&core_dc->current_context->res_ctx.pipe_ctx[i]);
+   core_dc, 
&core_dc->current_context->res_ctx.pipe_ctx[i]);
+   }
+
 
if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, 
core_dc->current_context)
!= DC_OK) {
-- 
2.9.3

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[PATCH 00/13] DC Patches Jan 31, 2017

2017-01-31 Thread Harry Wentland 
* warning fixes
* DMCU loader
* some cleanup
* some fixes

Anthony Koo (5):
  drm/amd/display: Fix compile warnings
  drm/amd/display: DMCU Compile and Load
  drm/amd/display: Move backlight from encoder to ABM
  drm/amd/display: Support ABM without PPlib
  drm/amd/display: Debug option to force enable ABM

Charlene Liu (1):
  drm/amd/display: remove CV-specific timing standard

Dmytro Laktyushkin (2):
  drm/amd/display: Make new pixel clock more obvious
  drm/amd/display: add dcfclk reporting to pplib

Leon Elazar (2):
  drm/amd/display: DP compliance automation test fixes
  drm/amd/display: surface validation on dce100

Yongqiang Sun (3):
  drm/amd/display: Expose hw sequencer gamma function
  drm/amd/display: Change power gating off sequence to fix hang
  drm/amd/display: Changes for enable dcc mode.

 drivers/gpu/drm/amd/display/dc/core/dc.c   | 101 +
 .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c  |   5 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  75 ++--
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  19 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c |   4 +
 drivers/gpu/drm/amd/display/dc/dc.h|  10 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |   2 -
 drivers/gpu/drm/amd/display/dc/dce/Makefile|   2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c   | 448 +
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h   | 184 +
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c  | 127 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h  |  91 +
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 298 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  24 --
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c   |   4 -
 .../drm/amd/display/dc/dce100/dce100_resource.c|   4 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  10 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.h|   3 +
 .../drm/amd/display/dc/dce110/dce110_opp_csc_v.c   |   5 -
 .../drm/amd/display/dc/dce110/dce110_resource.c|  52 +++
 .../drm/amd/display/dc/dce112/dce112_resource.c|  51 +++
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   4 +
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h|  45 +++
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h   |  42 ++
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |   6 -
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   4 -
 .../amd/display/dc/virtual/virtual_link_encoder.c  |  13 -
 .../drm/amd/display/modules/freesync/freesync.c|   7 +-
 29 files changed, 1121 insertions(+), 522 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

-- 
2.9.3

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[PATCH 03/13] drm/amd/display: DP compliance automation test fixes

2017-01-31 Thread Harry Wentland 
From: Leon Elazar 

Fixes:
1. Removing pending flag since we are executing teh entire flow without context 
switches
2. Adding stream enablment - connection between DIG BE to DIG FE during test 
link training

Change-Id: I56d3904c37adb85adca9c84387d638295bb57177
Signed-off-by: Leon Elazar 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 19 +--
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c |  4 
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h   |  3 +--
 3 files changed, 6 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index bc0667d55cf0..96d69b4d2d17 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1738,8 +1738,7 @@ static void handle_automated_test(struct core_link *link)
}
if (test_request.bits.LINK_TEST_PATTRN) {
dp_test_send_link_test_pattern(link);
-   link->public.compliance_test_state.bits.
-   SET_TEST_PATTERN_PENDING = 1;
+   test_response.bits.ACK = 1;
}
if (test_request.bits.PHY_TEST_PATTERN) {
dp_test_send_phy_test_pattern(link);
@@ -2308,11 +2307,9 @@ bool dc_link_dp_set_test_pattern(
unsigned int i;
unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
union dpcd_training_pattern training_pattern;
-   union test_response test_response;
enum dpcd_phy_test_patterns pattern;
 
memset(&training_pattern, 0, sizeof(training_pattern));
-   memset(&test_response, 0, sizeof(test_response));
 
for (i = 0; i < MAX_PIPES; i++) {
if (pipes[i].stream->sink->link == core_link) {
@@ -2442,20 +2439,6 @@ bool dc_link_dp_set_test_pattern(
set_crtc_test_pattern(core_link, &pipe_ctx, test_pattern);
/* Set Test Pattern state */
core_link->public.test_pattern_enabled = true;
-
-   /* If this is called because of compliance test request,
-* we respond ack here.
-*/
-   if (core_link->public.compliance_test_state.bits.
-   SET_TEST_PATTERN_PENDING == 1) {
-   core_link->public.compliance_test_state.bits.
-   SET_TEST_PATTERN_PENDING = 0;
-   test_response.bits.ACK = 1;
-   core_link_write_dpcd(core_link,
-   DP_TEST_RESPONSE,
-   &test_response.raw,
-   sizeof(test_response));
-   }
}
 
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index b0ac94d673c4..3b814592fd70 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -251,6 +251,8 @@ void dp_retrain_link_dp_test(struct core_link *link,
 
dp_receiver_power_ctrl(link, false);
 
+   link->dc->hwss.disable_stream(&pipes[i]);
+
link->link_enc->funcs->disable_output(
link->link_enc,
SIGNAL_TYPE_DISPLAY_PORT);
@@ -273,6 +275,8 @@ void dp_retrain_link_dp_test(struct core_link *link,
 
link->public.cur_link_settings = *link_setting;
 
+   link->dc->hwss.enable_stream(&pipes[i]);
+
link->dc->hwss.unblank_stream(&pipes[i],
link_setting);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 1666f10a1e5c..cd2323a71760 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -432,8 +432,7 @@ union phy_test_pattern {
 union compliance_test_state {
struct {
unsigned char STEREO_3D_RUNNING: 1;
-   unsigned char SET_TEST_PATTERN_PENDING : 1;
-   unsigned char RESERVED : 6;
+   unsigned char RESERVED : 7;
} bits;
unsigned char raw;
 };
-- 
2.9.3

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[PATCH 01/13] drm/amd/display: Fix compile warnings

2017-01-31 Thread Harry Wentland 
From: Anthony Koo 

1. Fix init of integer
2. Fix mixed declarations

Change-Id: Ib6777dc7c59fd6edaf3cc310c4ad1b66874aecad
Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index e0703c588e47..1ee732768f6e 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -208,6 +208,8 @@ bool mod_freesync_add_stream(struct mod_freesync 
*mod_freesync,
struct core_stream *core_stream = NULL;
struct core_dc *core_dc = NULL;
struct core_freesync *core_freesync = NULL;
+   int persistent_freesync_enable = 0;
+   struct persistent_data_flag flag;
 
if (mod_freesync == NULL)
return false;
@@ -216,9 +218,6 @@ bool mod_freesync_add_stream(struct mod_freesync 
*mod_freesync,
core_stream = DC_STREAM_TO_CORE(stream);
core_dc = DC_TO_CORE(core_freesync->dc);
 
-   int persistent_freesync_enable = 0;
-   struct persistent_data_flag flag;
-
flag.save_per_edid = true;
flag.save_per_link = false;
 
@@ -779,7 +778,7 @@ bool mod_freesync_get_state(struct mod_freesync 
*mod_freesync,
const struct dc_stream *stream,
struct mod_freesync_params *freesync_params)
 {
-   unsigned int index = NULL;
+   unsigned int index = 0;
struct core_freesync *core_freesync = NULL;
 
if (mod_freesync == NULL)
-- 
2.9.3

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Re: PRT support for amdgpu

2017-01-31 Thread Christian König 

Am 31.01.2017 um 17:09 schrieb Alex Deucher:

On Mon, Jan 30, 2017 at 7:57 AM, Christian König
 wrote:

Hi Dave and Bas,

Hi Dave and Bas,

the following set of patches is a proposal for adding support for partial 
resident textures (PRT) to the amdgpu kernel module.

The basic idea behind PRT support is that you turn of VM fault reporting and 
only map parts of a texture into your virtual address space.

When a shader now tries to sample from a not present page it gets a 
notification instead of a VM fault and can react gracefully by switch to a 
different LOD for example.

Do we actually need to disable faults?  I guess the shader hw probably
requires it to get the proper result in the shader?


Yes, you need to disable the VM faults for the PRT range otherwise the 
interrupt ring will just be flooded with faults.


Keep in mind that faults (or rather NACKs from the MC) are considered 
normal with that approach. This is also the reason why we need to change 
the TLB rules and also keep invalid entries in there.


Regards,
Christian.



Alex


On our current available hardware generation you can unfortunately only turn of 
VM faults globally, but on future generation you can do this on a per page 
basis. So my proposal is to have a consistent interface over all generations 
with a per mapping PRT flag, but enable/disable it globally on current hardware 
when the first/last mapping is made/destroyed.

An open problem with the proposal is that we don't know when or if we want to 
add the userspace implementation into radeonsi.

So price question could you guys use this for radv as well? Or is it sufficient 
to just write an unit test for it?

Best regards,
Christian.

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Re: PRT support for amdgpu

2017-01-31 Thread Christian König 

Am 31.01.2017 um 14:06 schrieb Bas Nieuwenhuizen:


On Mon, Jan 30, 2017, at 13:57, Christian König wrote:

Hi Dave and Bas,

Hi Dave and Bas,

the following set of patches is a proposal for adding support for partial
resident textures (PRT) to the amdgpu kernel module.

The basic idea behind PRT support is that you turn of VM fault reporting
and only map parts of a texture into your virtual address space.

If we add some backing to a range, do we need to unmap the PRT range,
split and map two PRt ranges? Or will this be handled like mmap and a
new map just overrides the earlier maps for that range?


Currently the idea is to unmap the PRT range first and then map the new 
stuff. But I've already discussed internally with Nicolai a couple of 
alternatives.


The problem is that IOCTL are supposed to be transactional, e.g. they 
either fail completely or they success completely. But that is rather 
tricky when you need to split mappings like you suggested as well.


So at least for the initial implementation I would like to stick to 
manual unmap calls we can still add the ability to split mappings later 
on if we find performance problems with that approach



When a shader now tries to sample from a not present page it gets a
notification instead of a VM fault and can react gracefully by switch to
a different LOD for example.

So to confirm this is just using texture instruction with the TFE bit
enabled, no trap handlers or such?


I'm not so deeply into the shader instructions, but I think so yes.


On our current available hardware generation you can unfortunately only
turn of VM faults globally, but on future generation you can do this on a
per page basis. So my proposal is to have a consistent interface over all
generations with a per mapping PRT flag, but enable/disable it globally
on current hardware when the first/last mapping is made/destroyed.

An open problem with the proposal is that we don't know when or if we
want to add the userspace implementation into radeonsi.

So price question could you guys use this for radv as well? Or is it
sufficient to just write an unit test for it?

So this API seems usable, and I think this is something we can use for
radv. However, I'm not sure how much time it takes for us to implement,
as the TFE variants are not in LLVM yet and I haven't figured out what
values the NACKs get.


Actually this is also useful without the special NACK handling. E.g. 
when you sample from a texture part which isn't present you always get 
zero and writes are ignored.


The TFE bit and the extra signaling to for special handling in shader 
code are only optional if I'm not completely mistaken.



Furthermore, if addrlib is missing stuff like Nicolai suggests then that
could result in complications. I can try if I can get something working
over the weekend, but no promises.


Not sure what concern Nicolai has about addrlib here. In general we 
should know where the different parts of a texture start (LODs, layers 
etc...) and as far as I can see that's all you need to know.



As far as an unit test being sufficient, I assume you mean as open
source user for inclusion into the kernel?


Yes.


I think that'd be a question
answered better by Dave.


Yeah, though so as well. Dave can you comment?

Thanks for the comments,
Christian.




Best regards,
Christian.

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Re: PRT support for amdgpu

2017-01-31 Thread Alex Deucher 
On Mon, Jan 30, 2017 at 7:57 AM, Christian König
 wrote:
> Hi Dave and Bas,
>
> Hi Dave and Bas,
>
> the following set of patches is a proposal for adding support for partial 
> resident textures (PRT) to the amdgpu kernel module.
>
> The basic idea behind PRT support is that you turn of VM fault reporting and 
> only map parts of a texture into your virtual address space.
>
> When a shader now tries to sample from a not present page it gets a 
> notification instead of a VM fault and can react gracefully by switch to a 
> different LOD for example.

Do we actually need to disable faults?  I guess the shader hw probably
requires it to get the proper result in the shader?

Alex

>
> On our current available hardware generation you can unfortunately only turn 
> of VM faults globally, but on future generation you can do this on a per page 
> basis. So my proposal is to have a consistent interface over all generations 
> with a per mapping PRT flag, but enable/disable it globally on current 
> hardware when the first/last mapping is made/destroyed.
>
> An open problem with the proposal is that we don't know when or if we want to 
> add the userspace implementation into radeonsi.
>
> So price question could you guys use this for radv as well? Or is it 
> sufficient to just write an unit test for it?
>
> Best regards,
> Christian.
>
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RE: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

2017-01-31 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Dieter Nützel
> Sent: Tuesday, January 31, 2017 6:25 AM
> To: Michel Dänzer
> Cc: Alex Deucher; mesa-...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org
> Subject: Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in
> DRM_RADEON_GEM_INFO ioctl
> 
> Hello Michel,
> 
> as this is for radeon, do you think this could/should fix
> the wrong reported VRAM size with Unigine_Heaven/-Valley, too?
> Maybe speed things up? ;-)
> 
> Unigine_Valley-1.0
> 
> GPU: Unknown GPU x1
> System memory: 24102 MB
> Video memory:  256 MB
> Sync threads:  7
> Async threads: 8
> 
> I'll try patching openSUSE Kernel:stable 4.9.6-2 with this
> and maybe this could then go into 4.10-rc7 'cause it is a
> bugfix. - Alex?

This patch just fixes the case of the HUD reporting the wrong amount of visible 
vram.  Most 3D apps just default to 256MB if they don't know how much vram is.  
The problem is GL never provided a core way to determine how much vram is 
available on a GPU so lots of vendor specific extensions and driver specific 
methods popped up to address this.

Alex

> 
> Greetings,
> Dieter
> 
> Am 31.01.2017 07:54, schrieb Michel Dänzer:
> > From: Michel Dänzer 
> >
> > vram_size is supposed to be the total amount of VRAM that can be used
> > by
> > userspace, which corresponds to the TTM VRAM manager size (which is
> > normally the full amount of VRAM, but can be just the visible VRAM when
> > DMA can't be used for BO migration for some reason).
> >
> > The above was incorrectly used for vram_visible before, resulting in
> > generally too large values being reported.
> >
> > Signed-off-by: Michel Dänzer 
> > ---
> >  drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
> >  drivers/gpu/drm/radeon/radeon_gem.c | 4 ++--
> >  2 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
> > b/drivers/gpu/drm/radeon/radeon_drv.c
> > index a252bc407aa2..88c41d43ec3d 100644
> > --- a/drivers/gpu/drm/radeon/radeon_drv.c
> > +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> > @@ -97,9 +97,10 @@
> >   *   2.46.0 - Add PFP_SYNC_ME support on evergreen
> >   *   2.47.0 - Add UVD_NO_OP register support
> >   *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
> > + *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct
> > vram_size/visible values
> >   */
> >  #define KMS_DRIVER_MAJOR   2
> > -#define KMS_DRIVER_MINOR   48
> > +#define KMS_DRIVER_MINOR   49
> >  #define KMS_DRIVER_PATCHLEVEL  0
> >  int radeon_driver_load_kms(struct drm_device *dev, unsigned long
> > flags);
> >  int radeon_driver_unload_kms(struct drm_device *dev);
> > diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
> > b/drivers/gpu/drm/radeon/radeon_gem.c
> > index 0bcffd8a7bd3..96683f5b2b1b 100644
> > --- a/drivers/gpu/drm/radeon/radeon_gem.c
> > +++ b/drivers/gpu/drm/radeon/radeon_gem.c
> > @@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev,
> > void *data,
> >
> > man = &rdev->mman.bdev.man[TTM_PL_VRAM];
> >
> > -   args->vram_size = rdev->mc.real_vram_size;
> > -   args->vram_visible = (u64)man->size << PAGE_SHIFT;
> > +   args->vram_size = (u64)man->size << PAGE_SHIFT;
> > +   args->vram_visible = rdev->mc.visible_vram_size;
> > args->vram_visible -= rdev->vram_pin_size;
> > args->gart_size = rdev->mc.gtt_size;
> > args->gart_size -= rdev->gart_pin_size;
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RE: [PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

2017-01-31 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, January 31, 2017 1:54 AM
> To: amd-gfx@lists.freedesktop.org; mesa-...@lists.freedesktop.org
> Subject: [PATCH] drm/radeon: Fix vram_size/visible values in
> DRM_RADEON_GEM_INFO ioctl
> 
> From: Michel Dänzer 
> 
> vram_size is supposed to be the total amount of VRAM that can be used by
> userspace, which corresponds to the TTM VRAM manager size (which is
> normally the full amount of VRAM, but can be just the visible VRAM when
> DMA can't be used for BO migration for some reason).
> 
> The above was incorrectly used for vram_visible before, resulting in
> generally too large values being reported.
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
>  drivers/gpu/drm/radeon/radeon_gem.c | 4 ++--
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index a252bc407aa2..88c41d43ec3d 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -97,9 +97,10 @@
>   *   2.46.0 - Add PFP_SYNC_ME support on evergreen
>   *   2.47.0 - Add UVD_NO_OP register support
>   *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
> + *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct
> vram_size/visible values
>   */
>  #define KMS_DRIVER_MAJOR 2
> -#define KMS_DRIVER_MINOR 48
> +#define KMS_DRIVER_MINOR 49
>  #define KMS_DRIVER_PATCHLEVEL0
>  int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
>  int radeon_driver_unload_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
> b/drivers/gpu/drm/radeon/radeon_gem.c
> index 0bcffd8a7bd3..96683f5b2b1b 100644
> --- a/drivers/gpu/drm/radeon/radeon_gem.c
> +++ b/drivers/gpu/drm/radeon/radeon_gem.c
> @@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev,
> void *data,
> 
>   man = &rdev->mman.bdev.man[TTM_PL_VRAM];
> 
> - args->vram_size = rdev->mc.real_vram_size;
> - args->vram_visible = (u64)man->size << PAGE_SHIFT;
> + args->vram_size = (u64)man->size << PAGE_SHIFT;
> + args->vram_visible = rdev->mc.visible_vram_size;
>   args->vram_visible -= rdev->vram_pin_size;
>   args->gart_size = rdev->mc.gtt_size;
>   args->gart_size -= rdev->gart_pin_size;
> --
> 2.11.0
> 
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RE: [PATCH] winsys/radeon: Allow visible VRAM size > 256MB with kernel driver >= 2.49

2017-01-31 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, January 31, 2017 1:54 AM
> To: amd-gfx@lists.freedesktop.org; mesa-...@lists.freedesktop.org
> Subject: [PATCH] winsys/radeon: Allow visible VRAM size > 256MB with
> kernel driver >= 2.49
> 
> From: Michel Dänzer 
> 
> The kernel driver reports correct values now.
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> index a8da62fd36..cacd683879 100644
> --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> @@ -372,7 +372,12 @@ static bool do_winsys_init(struct
> radeon_drm_winsys *ws)
>  }
>  ws->info.gart_size = gem_info.gart_size;
>  ws->info.vram_size = gem_info.vram_size;
> -ws->info.vram_vis_size = MIN2(gem_info.vram_visible, 256*1024*1024);
> +ws->info.vram_vis_size = gem_info.vram_visible;
> +/* Older versions of the kernel driver reported incorrect values, and
> + * didn't support more than 256MB of visible VRAM anyway
> + */
> +if (ws->info.drm_minor < 49)
> +ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size,
> 256*1024*1024);
> 
>  /* Radeon allocates all buffers as contigous, which makes large 
> allocations
>   * unlikely to succeed. */
> --
> 2.11.0
> 
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RE: [PATCH xf86-video-ati] Don't handle Option "SwapbuffersWait" at all with glamor

2017-01-31 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, January 31, 2017 2:28 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-ati] Don't handle Option "SwapbuffersWait" at all
> with glamor
> 
> From: Michel Dänzer 
> 
> It never had any effect with glamor.
> 
> Signed-off-by: Michel Dänzer 

Good catch!

Reviewed-by: Alex Deucher 

> ---
>  src/radeon_kms.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/src/radeon_kms.c b/src/radeon_kms.c
> index 446852564..58efd6ee5 100644
> --- a/src/radeon_kms.c
> +++ b/src/radeon_kms.c
> @@ -1801,10 +1801,12 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int
> flags)
>   }
>  }
> 
> -info->swapBuffersWait = xf86ReturnOptValBool(info->Options,
> -
> OPTION_SWAPBUFFERS_WAIT, TRUE);
> -xf86DrvMsg(pScrn->scrnIndex, X_INFO,
> -"SwapBuffers wait for vsync: %sabled\n", info->swapBuffersWait
> ? "en" : "dis");
> +if (!info->use_glamor) {
> + info->swapBuffersWait = xf86ReturnOptValBool(info->Options,
> +
> OPTION_SWAPBUFFERS_WAIT, TRUE);
> + xf86DrvMsg(pScrn->scrnIndex, X_INFO,
> +"SwapBuffers wait for vsync: %sabled\n", info-
> >swapBuffersWait ? "en" : "dis");
> +}
> 
>  if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) {
>  info->drmmode.delete_dp_12_displays = TRUE;
> --
> 2.11.0
> 
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Re: PRT support for amdgpu

2017-01-31 Thread Bas Nieuwenhuizen 


On Mon, Jan 30, 2017, at 13:57, Christian König wrote:
> Hi Dave and Bas,
> 
> Hi Dave and Bas,
> 
> the following set of patches is a proposal for adding support for partial
> resident textures (PRT) to the amdgpu kernel module.
> 
> The basic idea behind PRT support is that you turn of VM fault reporting
> and only map parts of a texture into your virtual address space.

If we add some backing to a range, do we need to unmap the PRT range,
split and map two PRt ranges? Or will this be handled like mmap and a
new map just overrides the earlier maps for that range?

> 
> When a shader now tries to sample from a not present page it gets a
> notification instead of a VM fault and can react gracefully by switch to
> a different LOD for example.

So to confirm this is just using texture instruction with the TFE bit
enabled, no trap handlers or such?

> 
> On our current available hardware generation you can unfortunately only
> turn of VM faults globally, but on future generation you can do this on a
> per page basis. So my proposal is to have a consistent interface over all
> generations with a per mapping PRT flag, but enable/disable it globally
> on current hardware when the first/last mapping is made/destroyed.
> 
> An open problem with the proposal is that we don't know when or if we
> want to add the userspace implementation into radeonsi.
> 
> So price question could you guys use this for radv as well? Or is it
> sufficient to just write an unit test for it?

So this API seems usable, and I think this is something we can use for
radv. However, I'm not sure how much time it takes for us to implement,
as the TFE variants are not in LLVM yet and I haven't figured out what
values the NACKs get. 

Furthermore, if addrlib is missing stuff like Nicolai suggests then that
could result in complications. I can try if I can get something working
over the weekend, but no promises.

As far as an unit test being sufficient, I assume you mean as open
source user for inclusion into the kernel? I think that'd be a question
answered better by Dave.

> 
> Best regards,
> Christian.
> 
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Re: [PATCH] winsys/radeon: Allow visible VRAM size > 256MB with kernel driver >= 2.49

2017-01-31 Thread Nicolai Hähnle 

Both patches:

Reviewed-by: Nicolai Hähnle 

On 31.01.2017 07:54, Michel Dänzer wrote:

From: Michel Dänzer 

The kernel driver reports correct values now.

Signed-off-by: Michel Dänzer 
---
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index a8da62fd36..cacd683879 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -372,7 +372,12 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
 }
 ws->info.gart_size = gem_info.gart_size;
 ws->info.vram_size = gem_info.vram_size;
-ws->info.vram_vis_size = MIN2(gem_info.vram_visible, 256*1024*1024);
+ws->info.vram_vis_size = gem_info.vram_visible;
+/* Older versions of the kernel driver reported incorrect values, and
+ * didn't support more than 256MB of visible VRAM anyway
+ */
+if (ws->info.drm_minor < 49)
+ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);

 /* Radeon allocates all buffers as contigous, which makes large allocations
  * unlikely to succeed. */



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Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

2017-01-31 Thread Dieter Nützel 

Hello Michel,

as this is for radeon, do you think this could/should fix
the wrong reported VRAM size with Unigine_Heaven/-Valley, too?
Maybe speed things up? ;-)

Unigine_Valley-1.0

GPU: Unknown GPU x1
System memory: 24102 MB
Video memory:  256 MB
Sync threads:  7
Async threads: 8

I'll try patching openSUSE Kernel:stable 4.9.6-2 with this
and maybe this could then go into 4.10-rc7 'cause it is a
bugfix. - Alex?

Greetings,
Dieter

Am 31.01.2017 07:54, schrieb Michel Dänzer:

From: Michel Dänzer 

vram_size is supposed to be the total amount of VRAM that can be used 
by

userspace, which corresponds to the TTM VRAM manager size (which is
normally the full amount of VRAM, but can be just the visible VRAM when
DMA can't be used for BO migration for some reason).

The above was incorrectly used for vram_visible before, resulting in
generally too large values being reported.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
 drivers/gpu/drm/radeon/radeon_gem.c | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index a252bc407aa2..88c41d43ec3d 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -97,9 +97,10 @@
  *   2.46.0 - Add PFP_SYNC_ME support on evergreen
  *   2.47.0 - Add UVD_NO_OP register support
  *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
+ *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct
vram_size/visible values
  */
 #define KMS_DRIVER_MAJOR   2
-#define KMS_DRIVER_MINOR   48
+#define KMS_DRIVER_MINOR   49
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long 
flags);

 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
b/drivers/gpu/drm/radeon/radeon_gem.c
index 0bcffd8a7bd3..96683f5b2b1b 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev,
void *data,

man = &rdev->mman.bdev.man[TTM_PL_VRAM];

-   args->vram_size = rdev->mc.real_vram_size;
-   args->vram_visible = (u64)man->size << PAGE_SHIFT;
+   args->vram_size = (u64)man->size << PAGE_SHIFT;
+   args->vram_visible = rdev->mc.visible_vram_size;
args->vram_visible -= rdev->vram_pin_size;
args->gart_size = rdev->mc.gtt_size;
args->gart_size -= rdev->gart_pin_size;

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Re: [PATCH] winsys/radeon: Allow visible VRAM size > 256MB with kernel driver >= 2.49

2017-01-31 Thread Samuel Pitoiset 

Thanks for fixing this Michel.

Reviewed-by: Samuel Pitoiset 

On 01/31/2017 07:54 AM, Michel Dänzer wrote:

From: Michel Dänzer 

The kernel driver reports correct values now.

Signed-off-by: Michel Dänzer 
---
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index a8da62fd36..cacd683879 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -372,7 +372,12 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
 }
 ws->info.gart_size = gem_info.gart_size;
 ws->info.vram_size = gem_info.vram_size;
-ws->info.vram_vis_size = MIN2(gem_info.vram_visible, 256*1024*1024);
+ws->info.vram_vis_size = gem_info.vram_visible;
+/* Older versions of the kernel driver reported incorrect values, and
+ * didn't support more than 256MB of visible VRAM anyway
+ */
+if (ws->info.drm_minor < 49)
+ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);

 /* Radeon allocates all buffers as contigous, which makes large allocations
  * unlikely to succeed. */


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Re: [PATCH] drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl

2017-01-31 Thread Christian König 

Am 31.01.2017 um 07:54 schrieb Michel Dänzer:

From: Michel Dänzer 

vram_size is supposed to be the total amount of VRAM that can be used by
userspace, which corresponds to the TTM VRAM manager size (which is
normally the full amount of VRAM, but can be just the visible VRAM when
DMA can't be used for BO migration for some reason).

The above was incorrectly used for vram_visible before, resulting in
generally too large values being reported.

Signed-off-by: Michel Dänzer 


Good catch, I wonder how long we have that in here.

Reviewed-by: Christian König  for this one as 
well the mesa patch.


Regards,
Christian.


---
  drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
  drivers/gpu/drm/radeon/radeon_gem.c | 4 ++--
  2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index a252bc407aa2..88c41d43ec3d 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -97,9 +97,10 @@
   *   2.46.0 - Add PFP_SYNC_ME support on evergreen
   *   2.47.0 - Add UVD_NO_OP register support
   *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
+ *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible 
values
   */
  #define KMS_DRIVER_MAJOR  2
-#define KMS_DRIVER_MINOR   48
+#define KMS_DRIVER_MINOR   49
  #define KMS_DRIVER_PATCHLEVEL 0
  int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
  int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 0bcffd8a7bd3..96683f5b2b1b 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void 
*data,
  
  	man = &rdev->mman.bdev.man[TTM_PL_VRAM];
  
-	args->vram_size = rdev->mc.real_vram_size;

-   args->vram_visible = (u64)man->size << PAGE_SHIFT;
+   args->vram_size = (u64)man->size << PAGE_SHIFT;
+   args->vram_visible = rdev->mc.visible_vram_size;
args->vram_visible -= rdev->vram_pin_size;
args->gart_size = rdev->mc.gtt_size;
args->gart_size -= rdev->gart_pin_size;



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