date:20170208

Change-Id: I37901358f0dc3e24c0b05df5d2231947cc717c93
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 73086d0..be9e27d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1716,7 +1716,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) 
(adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
 #define amdgpu_gfx_get_gpu_clock_counter(adev) 
(adev)->gfx.funcs->get_gpu_clock_counter((adev))
 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) 
(adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
-#define amdgpu_gds_switch(adev, r, v, d, w, a) 
(adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
 
 /* Common functions */
 int amdgpu_gpu_reset(struct amdgpu_device *adev);
-- 
2.7.4

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[PATCH] drm/amdgpu:use hw_init for sriov_gpu_reset

no suspend invoked so after VF FLR by host, we just
call hw_init to reinitialize IPs.

Change-Id: If09cb42b09bee6acc84e6b239ef537ad5a3df41c
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0d33bc9..7e64110 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1604,7 +1604,7 @@ int amdgpu_suspend(struct amdgpu_device *adev)
return 0;
 }
 
-static int amdgpu_sriov_resume_early(struct amdgpu_device *adev)
+static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
 {
int i, r;
 
@@ -1615,7 +1615,7 @@ static int amdgpu_sriov_resume_early(struct amdgpu_device 
*adev)
if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||
adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_GMC ||
adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_IH)
-   r = adev->ip_blocks[i].version->funcs->resume(adev);
+   r = adev->ip_blocks[i].version->funcs->hw_init(adev);
 
if (r) {
DRM_ERROR("resume of IP block <%s> failed %d\n",
@@ -1627,7 +1627,7 @@ static int amdgpu_sriov_resume_early(struct amdgpu_device 
*adev)
return 0;
 }
 
-static int amdgpu_sriov_resume_late(struct amdgpu_device *adev)
+static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
 {
int i, r;
 
@@ -1640,7 +1640,7 @@ static int amdgpu_sriov_resume_late(struct amdgpu_device 
*adev)
adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_IH )
continue;
 
-   r = adev->ip_blocks[i].version->funcs->resume(adev);
+   r = adev->ip_blocks[i].version->funcs->hw_init(adev);
if (r) {
DRM_ERROR("resume of IP block <%s> failed %d\n",
  adev->ip_blocks[i].version->funcs->name, r);
@@ -2433,13 +2433,13 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, 
bool voluntary)
 
 
/* Resume IP prior to SMC */
-   amdgpu_sriov_resume_early(adev);
+   amdgpu_sriov_reinit_early(adev);
 
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_ttm_recover_gart(adev);
 
/* now we are okay to resume SMC/CP/SDMA */
-   amdgpu_sriov_resume_late(adev);
+   amdgpu_sriov_reinit_late(adev);
 
amdgpu_irq_gpu_reset_resume_helper(adev);
 
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: shut up #warning for compile testing

2017-02-08 Thread Alex Deucher

On Fri, Feb 3, 2017 at 5:15 AM, Michel Dänzer  wrote:
> On 02/02/17 06:36 PM, Christian König wrote:
>> Am 02.02.2017 um 07:09 schrieb Michel Dänzer:
>>> [SNIP]
>>> OTOH the people running the kernel aren't always the same people
>>> building it, so the downside is that this would potentially delay
>>> getting X86_PAT enabled.
>>
>> And exactly for this reason I would rather like to keep the warning.
>
> Right, so let's take the patch as is:
>
> Reviewed-by: Michel Dänzer 
>

Applied.  thanks!

Alex

>
> Arnd, can you make the corresponding patch for radeon as well? Otherwise
> I can probably do it next week.
>
>
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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RE: [PATCH 2/2] drm/amdgpu:cleanup

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 10:50 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 2/2] drm/amdgpu:cleanup
> 
> 1)remove braces not needed
> 2)don't return failure on debugfs_firmware_init failed

I'd split these in two, one that is pure cleanup, and the second which drops 
the early return.  With that fixed:
Reviewed-by: Alex Deucher 

> 
> Change-Id: I90ec3197184d0fdda54575bfbad7b705aa178698
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++---
>  1 file changed, 3 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index abd7e15..0d33bc9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1931,20 +1931,16 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
>   amdgpu_fbdev_init(adev);
> 
>   r = amdgpu_gem_debugfs_init(adev);
> - if (r) {
> + if (r)
>   DRM_ERROR("registering gem debugfs failed (%d).\n", r);
> - }
> 
>   r = amdgpu_debugfs_regs_init(adev);
> - if (r) {
> + if (r)
>   DRM_ERROR("registering register debugfs failed (%d).\n", r);
> - }
> 
>   r = amdgpu_debugfs_firmware_init(adev);
> - if (r) {
> + if (r)
>   DRM_ERROR("registering firmware debugfs failed (%d).\n",
> r);
> - return r;
> - }
> 
>   if ((amdgpu_testing & 1)) {
>   if (adev->accel_working)
> --
> 2.7.4
> 
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RE: [PATCH 1/2] drm/amdgpu:fix amdgpu_sa_bo_new error(v2)



> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 10:50 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 1/2] drm/amdgpu:fix amdgpu_sa_bo_new error(v2)
> 
> ib_pool init should prior to fbdev_init, otherwise
> there will be error from amdgpu_sa_bo_new
> (amdgpu_sa.c:323)
> 
> fbdev_init will call ttm_validate which further call
> amdgpu_sa_bo_new.
> 
> v2:
> move fbdev_init behind ib test.
> 
> Change-Id: I3a969570d443f61a44f67b0d76b3871ca5c3ea81
> Signed-off-by: Monk Liu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index afcae15..abd7e15 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1918,8 +1918,6 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
>   /* Get a log2 for easy divisions. */
>   adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
> 
> - amdgpu_fbdev_init(adev);
> -
>   r = amdgpu_ib_pool_init(adev);
>   if (r) {
>   dev_err(adev->dev, "IB initialization failed (%d).\n", r);
> @@ -1930,6 +1928,8 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
>   if (r)
>   DRM_ERROR("ib ring test failed (%d).\n", r);
> 
> + amdgpu_fbdev_init(adev);
> +
>   r = amdgpu_gem_debugfs_init(adev);
>   if (r) {
>   DRM_ERROR("registering gem debugfs failed (%d).\n", r);
> --
> 2.7.4
> 
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[PATCH 2/2] drm/amdgpu:cleanup

1)remove braces not needed
2)don't return failure on debugfs_firmware_init failed

Change-Id: I90ec3197184d0fdda54575bfbad7b705aa178698
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abd7e15..0d33bc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1931,20 +1931,16 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
 
r = amdgpu_gem_debugfs_init(adev);
-   if (r) {
+   if (r)
DRM_ERROR("registering gem debugfs failed (%d).\n", r);
-   }
 
r = amdgpu_debugfs_regs_init(adev);
-   if (r) {
+   if (r)
DRM_ERROR("registering register debugfs failed (%d).\n", r);
-   }
 
r = amdgpu_debugfs_firmware_init(adev);
-   if (r) {
+   if (r)
DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
-   return r;
-   }
 
if ((amdgpu_testing & 1)) {
if (adev->accel_working)
-- 
2.7.4

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[PATCH 1/2] drm/amdgpu:fix amdgpu_sa_bo_new error(v2)

ib_pool init should prior to fbdev_init, otherwise
there will be error from amdgpu_sa_bo_new
(amdgpu_sa.c:323)

fbdev_init will call ttm_validate which further call
amdgpu_sa_bo_new.

v2:
move fbdev_init behind ib test.

Change-Id: I3a969570d443f61a44f67b0d76b3871ca5c3ea81
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index afcae15..abd7e15 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1918,8 +1918,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* Get a log2 for easy divisions. */
adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
 
-   amdgpu_fbdev_init(adev);
-
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1930,6 +1928,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
 
+   amdgpu_fbdev_init(adev);
+
r = amdgpu_gem_debugfs_init(adev);
if (r) {
DRM_ERROR("registering gem debugfs failed (%d).\n", r);
-- 
2.7.4

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Re: [PATCH] drm/amdgpu/virt: fix double kfree on bo_va

2017-02-08 Thread Alex Deucher

On Fri, Feb 3, 2017 at 3:23 PM, Colin King  wrote:
> From: Colin Ian King 
>
> bo_va is being kfree'd twice, once in the call to amdgpu_vm_bo_rmv
> and then a short while later. Fix this double free by removing
> the 2nd kfree.
>
> Detected by CoverityScan, CID#1399524 ("Double Free")
>
> Signed-off-by: Colin Ian King 

Applied.  thanks!

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 3fd951c..dcfb7df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -83,7 +83,6 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, 
> struct amdgpu_vm *vm)
> DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
> amdgpu_vm_bo_rmv(adev, bo_va);
> ttm_eu_backoff_reservation(&ticket, &list);
> -   kfree(bo_va);
> return r;
> }
>
> --
> 2.10.2
>
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Re: [patch] drm/radeon: remove some dead code

2017-02-08 Thread Alex Deucher

On Tue, Feb 7, 2017 at 8:16 AM, Dan Carpenter  wrote:
> If "rdev->bios" is NULL then we don't need to free it.
>
> Signed-off-by: Dan Carpenter 

applied.  thanks!

>
> diff --git a/drivers/gpu/drm/radeon/radeon_bios.c 
> b/drivers/gpu/drm/radeon/radeon_bios.c
> index 00cfb5d2875f..04c0ed41374f 100644
> --- a/drivers/gpu/drm/radeon/radeon_bios.c
> +++ b/drivers/gpu/drm/radeon/radeon_bios.c
> @@ -638,10 +638,8 @@ static bool radeon_acpi_vfct_bios(struct radeon_device 
> *rdev)
>  vhdr->ImageLength,
>  GFP_KERNEL);
>
> -   if (!rdev->bios) {
> -   kfree(rdev->bios);
> +   if (!rdev->bios)
> return false;
> -   }
> return true;
> }
> }
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RE: [PATCH 11/11] drm/amdgpu:fix kiq_resume routine (V2)

Reviewed-by: Xiangliang Yu 



Thanks!
Xiangliang Yu


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk 
> Subject: [PATCH 11/11] drm/amdgpu:fix kiq_resume routine (V2)
> 
> v2:
> use in_rest to fix compute ring test failure issue which occured after
> FLR/gpu_reset.
> 
> we need backup a clean status of MQD which was created in drv load stage,
> and use it in resume stage, otherwise KCQ and KIQ all may faild in ring/ib 
> test.
> 
> Change-Id: I41be940454a6638e9a8a05f096601eaa1fbebaab
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 44
> ++
>  2 files changed, 35 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5215fc5..afcae15 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2410,6 +2410,7 @@ int amdgpu_sriov_gpu_reset(struct
> amdgpu_device *adev, bool voluntary)
> 
>   mutex_lock(&adev->virt.lock_reset);
>   atomic_inc(&adev->gpu_reset_counter);
> + adev->gfx.in_reset = true;
> 
>   /* block TTM */
>   resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
> @@ -2494,6 +2495,7 @@ int amdgpu_sriov_gpu_reset(struct
> amdgpu_device *adev, bool voluntary)
>   dev_info(adev->dev, "GPU reset failed\n");
>   }
> 
> + adev->gfx.in_reset = false;
>   mutex_unlock(&adev->virt.lock_reset);
>   return r;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 6584173..1822420 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4877,24 +4877,46 @@ static int gfx_v8_0_kiq_init_queue(struct
> amdgpu_ring *ring,
>   struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>   uint64_t eop_gpu_addr;
>   bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
> + int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
> 
>   if (is_kiq) {
>   eop_gpu_addr = kiq->eop_gpu_addr;
>   gfx_v8_0_kiq_setting(&kiq->ring);
> - } else
> + } else {
>   eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
>   ring->queue * MEC_HPD_SIZE;
> + mqd_idx = ring - &adev->gfx.compute_ring[0];
> + }
> 
> - mutex_lock(&adev->srbm_mutex);
> - vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> + if (!adev->gfx.in_reset) {
> + memset((void *)mqd, 0, sizeof(*mqd));
> + mutex_lock(&adev->srbm_mutex);
> + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> + gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr,
> eop_gpu_addr, ring);
> + if (is_kiq)
> + gfx_v8_0_kiq_init_register(adev, mqd, ring);
> + vi_srbm_select(adev, 0, 0, 0, 0);
> + mutex_unlock(&adev->srbm_mutex);
> 
> - gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr,
> ring);
> + if (adev->gfx.mec.mqd_backup[mqd_idx])
> + memcpy(adev->gfx.mec.mqd_backup[mqd_idx],
> mqd, sizeof(*mqd));
> + } else { /* for GPU_RESET case */
> + /* reset MQD to a clean status */
> + if (adev->gfx.mec.mqd_backup[mqd_idx])
> + memcpy(mqd, adev-
> >gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
> 
> - if (is_kiq)
> - gfx_v8_0_kiq_init_register(adev, mqd, ring);
> -
> - vi_srbm_select(adev, 0, 0, 0, 0);
> - mutex_unlock(&adev->srbm_mutex);
> + /* reset ring buffer */
> + ring->wptr = 0;
> + amdgpu_ring_clear_ring(ring);
> +
> + if (is_kiq) {
> + mutex_lock(&adev->srbm_mutex);
> + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue,
> 0);
> + gfx_v8_0_kiq_init_register(adev, mqd, ring);
> + vi_srbm_select(adev, 0, 0, 0, 0);
> + mutex_unlock(&adev->srbm_mutex);
> + }
> + }
> 
>   if (is_kiq)
>   gfx_v8_0_kiq_enable(ring);
> @@ -4913,9 +4935,9 @@ static int gfx_v8_0_kiq_resume(struct
> amdgpu_device *adev)
> 
>   ring = &adev->gfx.kiq.ring;
>   if (!amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr)) {
> - memset((void *)ring->mqd_ptr, 0, sizeof(struct vi_mqd));
>   r = gfx_v8_0_kiq_init_queue(ring, ring->mqd_ptr, ring-
> >mqd_gpu_addr);
>   amdgpu_bo_kunmap(ring->mqd_obj);
> + ring->mqd_ptr = NULL;
>   if (r)
>   return r;
>   } else {
> @@ -4925,9 +4947,9 @@ static int gfx_v8_0_kiq_resume(struct
> amdgpu_device *adev)
>   for (i = 0; i < adev->gfx.num_co

RE: [PATCH 08/11] drm/amdgpu:alloc mqd backup

Reviewed-by: Xiangliang Yu 




Thanks!
Xiangliang Yu


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk 
> Subject: [PATCH 08/11] drm/amdgpu:alloc mqd backup
> 
> this is required for restoring the mqds after GPU reset.
> 
> Change-Id: I84f821faa657a5d942c33d30f206eb66b579c2f8
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index acd9970..73086d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -781,6 +781,7 @@ struct amdgpu_mec {
>   u32 num_pipe;
>   u32 num_mec;
>   u32 num_queue;
> + struct vi_mqd   *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS +
> 1];
>  };
> 
>  struct amdgpu_kiq {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 8f545992..b0612d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -7309,6 +7309,11 @@ static int gfx_v8_0_compute_mqd_soft_init(struct
> amdgpu_device *adev)
>   dev_warn(adev->dev, "failed to create ring mqd ob
> (%d)", r);
>   return r;
>   }
> +
> + /* prepare MQD backup */
> + adev-
> >gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] =
> kmalloc(sizeof(struct vi_mqd), GFP_KERNEL);
> + if (!adev-
> >gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
> + dev_warn(adev->dev, "no memory to create
> MQD backup for ring %s\n", ring->name);
>   }
> 
>   /* create MQD for each KCQ */
> @@ -7323,6 +7328,11 @@ static int gfx_v8_0_compute_mqd_soft_init(struct
> amdgpu_device *adev)
>   dev_warn(adev->dev, "failed to create ring
> mqd ob (%d)", r);
>   return r;
>   }
> +
> + /* prepare MQD backup */
> + adev->gfx.mec.mqd_backup[i] =
> kmalloc(sizeof(struct vi_mqd), GFP_KERNEL);
> + if (!adev->gfx.mec.mqd_backup[i])
> + dev_warn(adev->dev, "no memory to create
> MQD backup for ring %s\n", ring->name);
>   }
>   }
> 
> --
> 2.7.4
> 
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 04/11] drm/amdgpu:no kiq for mailbox registers access

Reviewed-by: Xiangliang Yu 



Thanks!
Xiangliang Yu


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk 
> Subject: [PATCH 04/11] drm/amdgpu:no kiq for mailbox registers access
> 
> Use no kiq version reg access due to:
> 1) better performance
> 2) INTR context consideration (some routine in mailbox is in
>INTR context e.g.xgpu_vi_mailbox_rcv_irq)
> 
> Change-Id: I383d7ce858a136d7b112180f86e3d632d37b4d1c
> Signed-off-by: Monk Liu 
> Reviewed-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 32 
> 
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index b8edfe5..7c7420f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -321,12 +321,12 @@ static void xgpu_vi_mailbox_send_ack(struct
> amdgpu_device *adev)
>   int timeout = VI_MAILBOX_TIMEDOUT;
>   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL,
> RCV_MSG_VALID);
> 
> - reg = RREG32(mmMAILBOX_CONTROL);
> + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
>   reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
> - WREG32(mmMAILBOX_CONTROL, reg);
> + WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
> 
>   /*Wait for RCV_MSG_VALID to be 0*/
> - reg = RREG32(mmMAILBOX_CONTROL);
> + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
>   while (reg & mask) {
>   if (timeout <= 0) {
>   pr_err("RCV_MSG_VALID is not cleared\n"); @@ -
> 335,7 +335,7 @@ static void xgpu_vi_mailbox_send_ack(struct
> amdgpu_device *adev)
>   mdelay(1);
>   timeout -=1;
> 
> - reg = RREG32(mmMAILBOX_CONTROL);
> + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
>   }
>  }
> 
> @@ -343,10 +343,10 @@ static void xgpu_vi_mailbox_set_valid(struct
> amdgpu_device *adev, bool val)  {
>   u32 reg;
> 
> - reg = RREG32(mmMAILBOX_CONTROL);
> + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
>   reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,
>   TRN_MSG_VALID, val ? 1 : 0);
> - WREG32(mmMAILBOX_CONTROL, reg);
> + WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
>  }
> 
>  static void xgpu_vi_mailbox_trans_msg(struct amdgpu_device *adev, @@ -
> 354,10 +354,10 @@ static void xgpu_vi_mailbox_trans_msg(struct
> amdgpu_device *adev,  {
>   u32 reg;
> 
> - reg = RREG32(mmMAILBOX_MSGBUF_TRN_DW0);
> + reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
>   reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
>   MSGBUF_DATA, event);
> - WREG32(mmMAILBOX_MSGBUF_TRN_DW0, reg);
> + WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
> 
>   xgpu_vi_mailbox_set_valid(adev, true);  } @@ -368,11 +368,11 @@
> static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device *adev,
>   u32 reg;
>   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL,
> RCV_MSG_VALID);
> 
> - reg = RREG32(mmMAILBOX_CONTROL);
> + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
>   if (!(reg & mask))
>   return -ENOENT;
> 
> - reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0);
> + reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
>   if (reg != event)
>   return -ENOENT;
> 
> @@ -388,7 +388,7 @@ static int xgpu_vi_poll_ack(struct amdgpu_device
> *adev)
>   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);
>   u32 reg;
> 
> - reg = RREG32(mmMAILBOX_CONTROL);
> + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
>   while (!(reg & mask)) {
>   if (timeout <= 0) {
>   pr_err("Doesn't get ack from pf.\n"); @@ -398,7
> +398,7 @@ static int xgpu_vi_poll_ack(struct amdgpu_device *adev)
>   msleep(1);
>   timeout -= 1;
> 
> - reg = RREG32(mmMAILBOX_CONTROL);
> + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
>   }
> 
>   return r;
> @@ -490,11 +490,11 @@ static int xgpu_vi_set_mailbox_ack_irq(struct
> amdgpu_device *adev,
>  unsigned type,
>  enum amdgpu_interrupt_state state)  {
> - u32 tmp = RREG32(mmMAILBOX_INT_CNTL);
> + u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
> 
>   tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,
>   (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
> - WREG32(mmMAILBOX_INT_CNTL, tmp);
> + WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
> 
>   return 0;
>  }
> @@ -519,11 +519,11 @@ static int xgpu_vi_set_mailbox_rcv_irq(struct
> amdgpu_device *adev,
>  unsigned type,
>  enum amdgpu_interrupt_state state)  {
> - u32 tmp = RREG32(mmMAILBOX_INT_CNTL);
> + u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
> 
>

RE: [PATCH 03/11] drm/amdgpu:Refine handshake of mailbox

Reviewed-by: Xiangliang Yu 


Thanks!
Xiangliang Yu


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Xue, Ken 
> Subject: [PATCH 03/11] drm/amdgpu:Refine handshake of mailbox
> 
> From: Ken Xue 
> 
> Change-Id: If3a7d05824847234759b86563e8052949e171972
> Signed-off-by: Ken Xue 
> Acked-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 24
> +++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index d2622b6..b8edfe5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
> amdgpu_device *adev)  static void xgpu_vi_mailbox_send_ack(struct
> amdgpu_device *adev)  {
>   u32 reg;
> + int timeout = VI_MAILBOX_TIMEDOUT;
> + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL,
> RCV_MSG_VALID);
> 
>   reg = RREG32(mmMAILBOX_CONTROL);
>   reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
>   WREG32(mmMAILBOX_CONTROL, reg);
> +
> + /*Wait for RCV_MSG_VALID to be 0*/
> + reg = RREG32(mmMAILBOX_CONTROL);
> + while (reg & mask) {
> + if (timeout <= 0) {
> + pr_err("RCV_MSG_VALID is not cleared\n");
> + break;
> + }
> + mdelay(1);
> + timeout -=1;
> +
> + reg = RREG32(mmMAILBOX_CONTROL);
> + }
>  }
> 
>  static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
> @@ -351,6 +366,11 @@ static int xgpu_vi_mailbox_rcv_msg(struct
> amdgpu_device *adev,
>  enum idh_event event)
>  {
>   u32 reg;
> + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL,
> RCV_MSG_VALID);
> +
> + reg = RREG32(mmMAILBOX_CONTROL);
> + if (!(reg & mask))
> + return -ENOENT;
> 
>   reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0);
>   if (reg != event)
> @@ -419,7 +439,9 @@ static int xgpu_vi_send_access_requests(struct
> amdgpu_device *adev,
>   xgpu_vi_mailbox_set_valid(adev, false);
> 
>   /* start to check msg if request is idh_req_gpu_init_access */
> - if (request == IDH_REQ_GPU_INIT_ACCESS) {
> + if (request == IDH_REQ_GPU_INIT_ACCESS ||
> + request == IDH_REQ_GPU_FINI_ACCESS ||
> + request == IDH_REQ_GPU_RESET_ACCESS) {
>   r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
>   if (r)
>   return r;
> --
> 2.7.4
> 
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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RE: [PATCH 02/11] drm/amdgpu:impl RREG32 no kiq version

Reviewed-by: Xiangliang.Yu 


Thanks!
Xiangliang Yu


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk 
> Subject: [PATCH 02/11] drm/amdgpu:impl RREG32 no kiq version
> 
> some registers are PF & VF copy, and we can safely use mmio method to
> access them.
> 
> and sometime we are forbid to use kiq to access registers for example in
> INTR context.
> 
> we need a MACRO that always disable KIQ for regs accessing
> 
> Change-Id: Ie6dc323dc86829a4a6ceb7073c269b106b534c4a
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 21 ++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++--
>  2 files changed, 20 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 402a895..74bffca8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1510,9 +1510,9 @@ void amdgpu_device_fini(struct amdgpu_device
> *adev);  int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
> 
>  uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> - bool always_indirect);
> + uint32_t acc_flags);
>  void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg,
> uint32_t v,
> - bool always_indirect);
> + uint32_t acc_flags);
>  u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);  void
> amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
> 
> @@ -1523,11 +1523,18 @@ bool amdgpu_device_has_dc_support(struct
> amdgpu_device *adev);
>  /*
>   * Registers read & write functions.
>   */
> -#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) -#define
> RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) -#define DREG32(reg)
> printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev,
> (reg), false)) -#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v),
> false) -#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v),
> true)
> +
> +#define AMDGPU_REGS_IDX   (1<<0)
> +#define AMDGPU_REGS_NO_KIQ(1<<1)
> +
> +#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg),
> +AMDGPU_REGS_NO_KIQ) #define WREG32_NO_KIQ(reg, v)
> amdgpu_mm_wreg(adev,
> +(reg), (v), AMDGPU_REGS_NO_KIQ)
> +
> +#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) #define
> +RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
> #define
> +DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n",
> +amdgpu_mm_rreg(adev, (reg), 0)) #define WREG32(reg, v)
> +amdgpu_mm_wreg(adev, (reg), (v), 0) #define WREG32_IDX(reg, v)
> +amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
>  #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
> #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
> #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3534089..5215fc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -91,16 +91,16 @@ bool amdgpu_device_is_px(struct drm_device *dev)
>   * MMIO register access helper functions.
>   */
>  uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> - bool always_indirect)
> + uint32_t acc_flags)
>  {
>   uint32_t ret;
> 
> - if (amdgpu_sriov_runtime(adev)) {
> + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
> amdgpu_sriov_runtime(adev)) {
>   BUG_ON(in_interrupt());
>   return amdgpu_virt_kiq_rreg(adev, reg);
>   }
> 
> - if ((reg * 4) < adev->rmmio_size && !always_indirect)
> + if ((reg * 4) < adev->rmmio_size && !(acc_flags &
> AMDGPU_REGS_IDX))
>   ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
>   else {
>   unsigned long flags;
> @@ -115,16 +115,16 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device
> *adev, uint32_t reg,  }
> 
>  void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg,
> uint32_t v,
> - bool always_indirect)
> + uint32_t acc_flags)
>  {
>   trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
> 
> - if (amdgpu_sriov_runtime(adev)) {
> + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
> amdgpu_sriov_runtime(adev)) {
>   BUG_ON(in_interrupt());
>   return amdgpu_virt_kiq_wreg(adev, reg, v);
>   }
> 
> - if ((reg * 4) < adev->rmmio_size && !always_indirect)
> + if ((reg * 4) < adev->rmmio_size && !(acc_flags &
> AMDGPU_REGS_IDX))
>   writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
>   else {
>   unsigned long flags;
> --
> 2.7.4
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.

RE: [PATCH 06/11] drm/amdgpu:RUNTIME flag should clr later

Reviewed-by: Xiangliang.Yu 


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk 
> Subject: [PATCH 06/11] drm/amdgpu:RUNTIME flag should clr later
> 
> this flag will get cleared by request gpu access
> 
> Change-Id: Ie484bb0141420055370e019dcd8c110fb34f8a1b
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index 5f156d3..98cbcd9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -505,9 +505,7 @@ static void xgpu_vi_mailbox_flr_work(struct
> work_struct *work)
>   struct amdgpu_device *adev = container_of(virt, struct
> amdgpu_device, virt);
> 
>   /* wait until RCV_MSG become 3 */
> - if (!xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL))
> - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
> - else {
> + if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
>   pr_err("failed to recieve FLR_CMPL\n");
>   return;
>   }
> --
> 2.7.4
> 
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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RE: [PATCH 05/11] drm/amdgpu:use work instead of delay-work

Reviewed-by: Xiangliang Yu 


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk 
> Subject: [PATCH 05/11] drm/amdgpu:use work instead of delay-work
> 
> no need to use a delay work since we don't know how much time hypervisor
> takes on FLR, so just polling and waiting in a work.
> 
> Change-Id: I41b6336baa00b1fd299311349402a17951b585a2
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |  2 +-
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c| 36 +++
> -
>  2 files changed, 18 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 4b05568..846f29c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -50,7 +50,7 @@ struct amdgpu_virt {
>   struct mutexlock_reset;
>   struct amdgpu_irq_src   ack_irq;
>   struct amdgpu_irq_src   rcv_irq;
> - struct delayed_work flr_work;
> + struct work_struct  flr_work;
>   const struct amdgpu_virt_ops*ops;
>  };
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index 7c7420f..5f156d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -501,17 +501,19 @@ static int xgpu_vi_set_mailbox_ack_irq(struct
> amdgpu_device *adev,
> 
>  static void xgpu_vi_mailbox_flr_work(struct work_struct *work)  {
> - struct amdgpu_virt *virt = container_of(work,
> - struct amdgpu_virt, flr_work.work);
> - struct amdgpu_device *adev = container_of(virt,
> - struct amdgpu_device, virt);
> - int r = 0;
> -
> - r = xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL);
> - if (r)
> - DRM_ERROR("failed to get flr cmpl msg from hypervior.\n");
> + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt,
> flr_work);
> + struct amdgpu_device *adev = container_of(virt, struct
> amdgpu_device,
> +virt);
> +
> + /* wait until RCV_MSG become 3 */
> + if (!xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL))
> + adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
> + else {
> + pr_err("failed to recieve FLR_CMPL\n");
> + return;
> + }
> 
> - /* TODO: need to restore gfx states */
> + /* Trigger recovery due to world switch failure */
> + amdgpu_sriov_gpu_reset(adev, false);
>  }
> 
>  static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, @@ -
> 534,15 +536,12 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device
> *adev,  {
>   int r;
> 
> - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
> + /* see what event we get */
>   r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
> - /* do nothing for other msg */
> - if (r)
> - return 0;
> 
> - /* TODO: need to save gfx states */
> - schedule_delayed_work(&adev->virt.flr_work,
> -   msecs_to_jiffies(VI_MAILBOX_RESET_TIME));
> + /* only handle FLR_NOTIFY now */
> + if (!r)
> + schedule_work(&adev->virt.flr_work);
> 
>   return 0;
>  }
> @@ -595,14 +594,13 @@ int xgpu_vi_mailbox_get_irq(struct
> amdgpu_device *adev)
>   return r;
>   }
> 
> - INIT_DELAYED_WORK(&adev->virt.flr_work,
> xgpu_vi_mailbox_flr_work);
> + INIT_WORK(&adev->virt.flr_work, xgpu_vi_mailbox_flr_work);
> 
>   return 0;
>  }
> 
>  void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev)  {
> - cancel_delayed_work_sync(&adev->virt.flr_work);
>   amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
>   amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  }
> --
> 2.7.4
> 
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Re: [PATCH 2/2] drm/amdgpu: report the number of bytes moved at buffer creation

On 09/02/17 08:35 AM, Samuel Pitoiset wrote:
> Like ttm_bo_validate(), ttm_bo_init() might need to move BO and
> the number of bytes moved by TTM should be reported. This can help
> the throttle buffer migration mechanism to make a better decision.
> 
> Signed-off-by: Samuel Pitoiset 

[...]

> @@ -399,10 +400,15 @@ int amdgpu_bo_create_restricted(struct amdgpu_device 
> *adev,
>   locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock);
>   WARN_ON(!locked);
>   }
> +
> + initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
>   r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
>   &bo->placement, page_align, !kernel, NULL,
>   acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
>   &amdgpu_ttm_bo_destroy);
> + amdgpu_cs_report_moved_bytes(adev,
> + initial_bytes_moved - atomic64_read(&adev->num_bytes_moved));

This looks backwards, should be 

atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved);

?


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Re: [PATCH 1/2] drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted()

On 09/02/17 08:35 AM, Samuel Pitoiset wrote:
> When ttm_bo_init() fails, the reservation mutex should be unlocked.
> 
> In debug build, the kernel reported "possible recursive locking
> detected" in this codepath. For debugging purposes, I also added
> a "WARN_ON(ww_mutex_is_locked())" when ttm_bo_init() fails and the
> mutex was locked as expected.
> 
> This should fix (random) GPU hangs. The easy way to reproduce the
> issue is to change the "Super Sampling" option from 1.0 to 2.0 in
> Hitman. It will create a huge buffer, evict a bunch of buffers
> (around ~5k) and deadlock.
> 
> This regression has been introduced pretty recently.
> 
> Fixes: "drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2)"

Please add at least the first ~12 characters of the commit hash
(f45dc74c93241ad0125fbc08c48b2ebe20f2f472) to the Fixes tag.


> @@ -403,8 +403,10 @@ int amdgpu_bo_create_restricted(struct amdgpu_device 
> *adev,
>   &bo->placement, page_align, !kernel, NULL,
>   acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
>   &amdgpu_ttm_bo_destroy);
> - if (unlikely(r != 0))
> + if (unlikely(r != 0)) {
> + ww_mutex_unlock(&bo->tbo.resv->lock);
>   return r;
> + }

This must only be done if (!resv).


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[PATCH 1/2] drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted()

2017-02-08 Thread Samuel Pitoiset

When ttm_bo_init() fails, the reservation mutex should be unlocked.

In debug build, the kernel reported "possible recursive locking
detected" in this codepath. For debugging purposes, I also added
a "WARN_ON(ww_mutex_is_locked())" when ttm_bo_init() fails and the
mutex was locked as expected.

This should fix (random) GPU hangs. The easy way to reproduce the
issue is to change the "Super Sampling" option from 1.0 to 2.0 in
Hitman. It will create a huge buffer, evict a bunch of buffers
(around ~5k) and deadlock.

This regression has been introduced pretty recently.

Fixes: "drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2)"
Signed-off-by: Samuel Pitoiset 
---

Here's the report: https://hastebin.com/durodivoma.xml

 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index d1ef1d064de4..531e16ce256e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -403,8 +403,10 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
&bo->placement, page_align, !kernel, NULL,
acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
&amdgpu_ttm_bo_destroy);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   ww_mutex_unlock(&bo->tbo.resv->lock);
return r;
+   }
 
bo->tbo.priority = ilog2(bo->tbo.num_pages);
if (kernel)
-- 
2.11.1

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[PATCH 2/2] drm/amdgpu: report the number of bytes moved at buffer creation

2017-02-08 Thread Samuel Pitoiset

Like ttm_bo_validate(), ttm_bo_init() might need to move BO and
the number of bytes moved by TTM should be reported. This can help
the throttle buffer migration mechanism to make a better decision.

Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 ++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 402a8954c6d8..5227e4d1d5db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1720,6 +1720,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, 
void *data);
 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
   u32 ip_instance, u32 ring,
   struct amdgpu_ring **out_ring);
+void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 6e948e4986ec..dade2fa9593a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -351,8 +351,7 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct 
amdgpu_device *adev)
  * submission. This can result in a debt that can stop buffer migrations
  * temporarily.
  */
-static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev,
-u64 num_bytes)
+void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes)
 {
spin_lock(&adev->mm_stats.lock);
adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 531e16ce256e..28c4615a6128 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -323,6 +323,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
struct amdgpu_bo *bo;
enum ttm_bo_type type;
unsigned long page_align;
+   u64 initial_bytes_moved;
size_t acc_size;
int r;
 
@@ -399,10 +400,15 @@ int amdgpu_bo_create_restricted(struct amdgpu_device 
*adev,
locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock);
WARN_ON(!locked);
}
+
+   initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
&bo->placement, page_align, !kernel, NULL,
acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
&amdgpu_ttm_bo_destroy);
+   amdgpu_cs_report_moved_bytes(adev,
+   initial_bytes_moved - atomic64_read(&adev->num_bytes_moved));
+
if (unlikely(r != 0)) {
ww_mutex_unlock(&bo->tbo.resv->lock);
return r;
-- 
2.11.1

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Re: Change queue/pipe split between amdkfd and amdgpu

2017-02-08 Thread Andres Rodriguez


Thank you Oded.

- Andres

On 2017-02-08 02:32 PM, Oded Gabbay wrote:

On Wed, Feb 8, 2017 at 6:23 PM, Andres Rodriguez  wrote:

Hey Felix,

Thanks for the pointer to the ROCm mqd commit. I like that the workarounds
are easy to spot. I'll add that to a new patch series I'm working on for
some bug-fixes for perf being lower on pipes other than pipe 0.

I haven't tested this yet on kaveri/carrizo. I'm hoping someone with the HW
will be able to give it a go. I put in a few small hacks to get KFD to boot
but do nothing on polaris10.

Regards,
Andres


On 2017-02-06 03:20 PM, Felix Kuehling wrote:

Hi Andres,

Thank you for tackling this task. It's more involved than I expected,
mostly because I didn't have much awareness of the MQD management in
amdgpu.

I made one comment in a separate message about the unified MQD commit
function, if you want to bring that more in line with our latest ROCm
release on github.

Also, were you able to test the upstream KFD with your changes on a
Kaveri or Carrizo?

Regards,
   Felix


On 17-02-03 11:51 PM, Andres Rodriguez wrote:

The current queue/pipe split policy is for amdgpu to take the first pipe
of
MEC0 and leave the rest for amdkfd to use. This policy is taken as an
assumption in a few areas of the implementation.

This patch series aims to allow for flexible/tunable queue/pipe split
policies
between kgd and kfd. It also updates the queue/pipe split policy to one
that
allows better compute app concurrency for both drivers.

In the process some duplicate code and hardcoded constants were removed.

Any suggestions or feedback on improvements welcome.


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Hi Andres,
I will try to find sometime to test it on my Kaveri machine.

Oded


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Re: Change queue/pipe split between amdkfd and amdgpu

2017-02-08 Thread Oded Gabbay

On Wed, Feb 8, 2017 at 6:23 PM, Andres Rodriguez  wrote:
> Hey Felix,
>
> Thanks for the pointer to the ROCm mqd commit. I like that the workarounds
> are easy to spot. I'll add that to a new patch series I'm working on for
> some bug-fixes for perf being lower on pipes other than pipe 0.
>
> I haven't tested this yet on kaveri/carrizo. I'm hoping someone with the HW
> will be able to give it a go. I put in a few small hacks to get KFD to boot
> but do nothing on polaris10.
>
> Regards,
> Andres
>
>
> On 2017-02-06 03:20 PM, Felix Kuehling wrote:
>>
>> Hi Andres,
>>
>> Thank you for tackling this task. It's more involved than I expected,
>> mostly because I didn't have much awareness of the MQD management in
>> amdgpu.
>>
>> I made one comment in a separate message about the unified MQD commit
>> function, if you want to bring that more in line with our latest ROCm
>> release on github.
>>
>> Also, were you able to test the upstream KFD with your changes on a
>> Kaveri or Carrizo?
>>
>> Regards,
>>   Felix
>>
>>
>> On 17-02-03 11:51 PM, Andres Rodriguez wrote:
>>>
>>> The current queue/pipe split policy is for amdgpu to take the first pipe
>>> of
>>> MEC0 and leave the rest for amdkfd to use. This policy is taken as an
>>> assumption in a few areas of the implementation.
>>>
>>> This patch series aims to allow for flexible/tunable queue/pipe split
>>> policies
>>> between kgd and kfd. It also updates the queue/pipe split policy to one
>>> that
>>> allows better compute app concurrency for both drivers.
>>>
>>> In the process some duplicate code and hardcoded constants were removed.
>>>
>>> Any suggestions or feedback on improvements welcome.
>>>
>>
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Hi Andres,
I will try to find sometime to test it on my Kaveri machine.

Oded
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Re: Staging kernel failing to build on 32bit

2017-02-08 Thread Tom St Denis


On 08/02/17 11:53 AM, Jeremy Newton wrote:

Hi,

Heads up to whoever is using or developing for the following kernel branch:

https://cgit.freedesktop.org/~agd5f/linux/tree/?h=amd-staging-4.9

It seems like a recent commit has caused 32bit builds to fail. I haven't
been able to look into it myself or do a bisect, but it seems like it
was something committed between Jan 25th (d0c15b8) and Feb 2nd (99eb22d)
caused it.

Here's the error output:

ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
Makefile:1200: recipe for target 'modules' failed
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2

After a quick glance, it seems similar to a previous kernel
commit: 
https://cgit.freedesktop.org/~agd5f/linux/commit/?id=1f827f5138292a6124430cdd37bcb68f30c05467


just a shot in the dark, but it could be caused by this commit:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=amd-staging-4.9&id=7adb2bbcdf7259533c5afc95c4a788b59bb59306

As it's the only one I see with 64 bit division in it. As I said, shot
in the dark here.


Thanks.  We have a patch in our internal stg-4.9 tree for this.  It 
should be promoted externally soonish.


Cheers,
Tom
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Staging kernel failing to build on 32bit

2017-02-08 Thread Jeremy Newton

Hi,

Heads up to whoever is using or developing for the following kernel branch:

https://cgit.freedesktop.org/~agd5f/linux/tree/?h=amd-staging-4.9

It seems like a recent commit has caused 32bit builds to fail. I haven't
been able to look into it myself or do a bisect, but it seems like it was
something committed between Jan 25th (d0c15b8) and Feb 2nd (99eb22d) caused
it.

Here's the error output:

ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
Makefile:1200: recipe for target 'modules' failed
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2

After a quick glance, it seems similar to a previous kernel commit:
https://cgit.freedesktop.org/~agd5f/linux/commit/?id=1f827f5138292a6124430cdd37bcb68f30c05467


just a shot in the dark, but it could be caused by this commit:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=amd-staging-4.9&id=7adb2bbcdf7259533c5afc95c4a788b59bb59306

As it's the only one I see with 64 bit division in it. As I said, shot in
the dark here.

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RE: [PATCH 02/11] drm/amdgpu:impl RREG32 no kiq version

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 02/11] drm/amdgpu:impl RREG32 no kiq version
> 
> some registers are PF & VF copy, and we can safely use
> mmio method to access them.
> 
> and sometime we are forbid to use kiq to access registers
> for example in INTR context.
> 
> we need a MACRO that always disable KIQ for regs accessing
> 
> Change-Id: Ie6dc323dc86829a4a6ceb7073c269b106b534c4a
> Signed-off-by: Monk Liu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 21 ++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++--
>  2 files changed, 20 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 402a895..74bffca8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1510,9 +1510,9 @@ void amdgpu_device_fini(struct amdgpu_device
> *adev);
>  int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
> 
>  uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> - bool always_indirect);
> + uint32_t acc_flags);
>  void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg,
> uint32_t v,
> - bool always_indirect);
> + uint32_t acc_flags);
>  u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
>  void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
> 
> @@ -1523,11 +1523,18 @@ bool amdgpu_device_has_dc_support(struct
> amdgpu_device *adev);
>  /*
>   * Registers read & write functions.
>   */
> -#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
> -#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
> -#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n",
> amdgpu_mm_rreg(adev, (reg), false))
> -#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
> -#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
> +
> +#define AMDGPU_REGS_IDX   (1<<0)
> +#define AMDGPU_REGS_NO_KIQ(1<<1)
> +
> +#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg),
> AMDGPU_REGS_NO_KIQ)
> +#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v),
> AMDGPU_REGS_NO_KIQ)
> +
> +#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
> +#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg),
> AMDGPU_REGS_IDX)
> +#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n",
> amdgpu_mm_rreg(adev, (reg), 0))
> +#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
> +#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v),
> AMDGPU_REGS_IDX)
>  #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
>  #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
>  #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3534089..5215fc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -91,16 +91,16 @@ bool amdgpu_device_is_px(struct drm_device *dev)
>   * MMIO register access helper functions.
>   */
>  uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> - bool always_indirect)
> + uint32_t acc_flags)
>  {
>   uint32_t ret;
> 
> - if (amdgpu_sriov_runtime(adev)) {
> + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
> amdgpu_sriov_runtime(adev)) {
>   BUG_ON(in_interrupt());
>   return amdgpu_virt_kiq_rreg(adev, reg);
>   }
> 
> - if ((reg * 4) < adev->rmmio_size && !always_indirect)
> + if ((reg * 4) < adev->rmmio_size && !(acc_flags &
> AMDGPU_REGS_IDX))
>   ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
>   else {
>   unsigned long flags;
> @@ -115,16 +115,16 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device
> *adev, uint32_t reg,
>  }
> 
>  void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg,
> uint32_t v,
> - bool always_indirect)
> + uint32_t acc_flags)
>  {
>   trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
> 
> - if (amdgpu_sriov_runtime(adev)) {
> + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
> amdgpu_sriov_runtime(adev)) {
>   BUG_ON(in_interrupt());
>   return amdgpu_virt_kiq_wreg(adev, reg, v);
>   }
> 
> - if ((reg * 4) < adev->rmmio_size && !always_indirect)
> + if ((reg * 4) < adev->rmmio_size && !(acc_flags &
> AMDGPU_REGS_IDX))
>   writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
>   else {
>   unsigned long flags;
> --
> 2.7.4
> 
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Re: [PATCH libdrm] amdgpu: add PRT unit test


On 08.02.2017 16:06, Christian König wrote:

From: Christian König 

Just a simple test if PRT works or not.

Signed-off-by: Christian König 


Reviewed-by: Nicolai Hähnle 

Too bad we can't ask the kernel whether a VM fault happened :/

I haven't pushed my libdrm patches yet because my understanding is that 
the kernel changes should come first. I saw your v3 series, I'll 
probably give it a go with my Mesa changes tomorrow.


Cheers,
Nicolai


---
 tests/amdgpu/basic_tests.c | 66 --
 1 file changed, 64 insertions(+), 2 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index bfda21b..24dd605 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -48,6 +48,7 @@ static void amdgpu_command_submission_compute(void);
 static void amdgpu_command_submission_sdma(void);
 static void amdgpu_userptr_test(void);
 static void amdgpu_semaphore_test(void);
+static void amdgpu_prt_test(void);

 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -61,6 +62,7 @@ CU_TestInfo basic_tests[] = {
{ "Command submission Test (Compute)", 
amdgpu_command_submission_compute },
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
{ "SW semaphore Test",  amdgpu_semaphore_test },
+   { "PRT Test",  amdgpu_prt_test },
CU_TEST_INFO_NULL,
 };
 #define BUFFER_SIZE (8 * 1024)
@@ -734,7 +736,6 @@ static void 
amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,

/* prepare CS */
CU_ASSERT_NOT_EQUAL(pm4_src, NULL);
-   CU_ASSERT_NOT_EQUAL(resources, NULL);
CU_ASSERT_NOT_EQUAL(ib_info, NULL);
CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
CU_ASSERT_TRUE(pm4_dw <= 1024);
@@ -759,7 +760,8 @@ static void 
amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
ibs_request->ibs = ib_info;
ibs_request->fence_info.handle = NULL;

-   memcpy(all_res, resources, sizeof(resources[0]) * res_cnt);
+   if (resources)
+   memcpy(all_res, resources, sizeof(resources[0]) * res_cnt);
all_res[res_cnt] = ib_result_handle;

r = amdgpu_bo_list_create(device_handle, res_cnt+1, all_res,
@@ -1208,3 +1210,63 @@ static void amdgpu_userptr_test(void)
r = amdgpu_cs_ctx_free(context_handle);
CU_ASSERT_EQUAL(r, 0);
 }
+
+static void amdgpu_prt_test(void)
+{
+   int i, r, j;
+   uint32_t *pm4 = NULL;
+   uint64_t bo_mc;
+   int pm4_dw = 256;
+   int sdma_write_length = 4;
+   amdgpu_context_handle context_handle;
+   struct amdgpu_cs_ib_info *ib_info;
+   struct amdgpu_cs_request *ibs_request;
+   amdgpu_va_handle va_handle;
+
+   pm4 = calloc(pm4_dw, sizeof(*pm4));
+   CU_ASSERT_NOT_EQUAL(pm4, NULL);
+
+   ib_info = calloc(1, sizeof(*ib_info));
+   CU_ASSERT_NOT_EQUAL(ib_info, NULL);
+
+   ibs_request = calloc(1, sizeof(*ibs_request));
+   CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
+
+   r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_va_range_alloc(device_handle,
+ amdgpu_gpu_va_range_general,
+ BUFFER_SIZE, 1, 0, &bo_mc,
+ &va_handle, 0);
+   CU_ASSERT_EQUAL(r, 0);
+
+   /*r = amdgpu_bo_va_op_raw(device_handle, NULL, 0, BUFFER_SIZE, bo_mc,
+   AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
+   CU_ASSERT_EQUAL(r, 0);*/
+
+   j = i = 0;
+   pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length);
+   pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+   pm4[i++] = 0xfffc & bo_mc;
+   pm4[i++] = (0x & bo_mc) >> 32;
+   while(j++ < sdma_write_length)
+   pm4[i++] = 0xdeadbeaf;
+
+   amdgpu_test_exec_cs_helper(context_handle,
+  AMDGPU_HW_IP_GFX, 0,
+  i, pm4, 0, NULL,
+  ib_info, ibs_request);
+   free(ibs_request);
+   free(ib_info);
+   free(pm4);
+
+   r = amdgpu_bo_va_op_raw(device_handle, NULL, 0, BUFFER_SIZE, bo_mc,
+   AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_UNMAP);
+   CU_ASSERT_EQUAL(r, 0);
+   r = amdgpu_va_range_free(va_handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_cs_ctx_free(context_handle);
+   CU_ASSERT_EQUAL(r, 0);
+}



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RE: [PATCH 06/11] drm/amdgpu:RUNTIME flag should clr later

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 06/11] drm/amdgpu:RUNTIME flag should clr later
> 
> this flag will get cleared by request gpu access
> 
> Change-Id: Ie484bb0141420055370e019dcd8c110fb34f8a1b
> Signed-off-by: Monk Liu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index 5f156d3..98cbcd9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -505,9 +505,7 @@ static void xgpu_vi_mailbox_flr_work(struct
> work_struct *work)
>   struct amdgpu_device *adev = container_of(virt, struct
> amdgpu_device, virt);
> 
>   /* wait until RCV_MSG become 3 */
> - if (!xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL))
> - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
> - else {
> + if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
>   pr_err("failed to recieve FLR_CMPL\n");
>   return;
>   }
> --
> 2.7.4
> 
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RE: [PATCH 11/11] drm/amdgpu:fix kiq_resume routine (V2)

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 11/11] drm/amdgpu:fix kiq_resume routine (V2)
> 
> v2:
> use in_rest to fix compute ring test failure issue
> which occured after FLR/gpu_reset.
> 
> we need backup a clean status of MQD which was created in drv load
> stage, and use it in resume stage, otherwise KCQ and KIQ all may
> faild in ring/ib test.
> 
> Change-Id: I41be940454a6638e9a8a05f096601eaa1fbebaab
> Signed-off-by: Monk Liu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 44
> ++
>  2 files changed, 35 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5215fc5..afcae15 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2410,6 +2410,7 @@ int amdgpu_sriov_gpu_reset(struct
> amdgpu_device *adev, bool voluntary)
> 
>   mutex_lock(&adev->virt.lock_reset);
>   atomic_inc(&adev->gpu_reset_counter);
> + adev->gfx.in_reset = true;
> 
>   /* block TTM */
>   resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
> @@ -2494,6 +2495,7 @@ int amdgpu_sriov_gpu_reset(struct
> amdgpu_device *adev, bool voluntary)
>   dev_info(adev->dev, "GPU reset failed\n");
>   }
> 
> + adev->gfx.in_reset = false;
>   mutex_unlock(&adev->virt.lock_reset);
>   return r;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 6584173..1822420 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4877,24 +4877,46 @@ static int gfx_v8_0_kiq_init_queue(struct
> amdgpu_ring *ring,
>   struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>   uint64_t eop_gpu_addr;
>   bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
> + int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
> 
>   if (is_kiq) {
>   eop_gpu_addr = kiq->eop_gpu_addr;
>   gfx_v8_0_kiq_setting(&kiq->ring);
> - } else
> + } else {
>   eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
>   ring->queue * MEC_HPD_SIZE;
> + mqd_idx = ring - &adev->gfx.compute_ring[0];
> + }
> 
> - mutex_lock(&adev->srbm_mutex);
> - vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> + if (!adev->gfx.in_reset) {
> + memset((void *)mqd, 0, sizeof(*mqd));
> + mutex_lock(&adev->srbm_mutex);
> + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> + gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr,
> eop_gpu_addr, ring);
> + if (is_kiq)
> + gfx_v8_0_kiq_init_register(adev, mqd, ring);
> + vi_srbm_select(adev, 0, 0, 0, 0);
> + mutex_unlock(&adev->srbm_mutex);
> 
> - gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr,
> ring);
> + if (adev->gfx.mec.mqd_backup[mqd_idx])
> + memcpy(adev->gfx.mec.mqd_backup[mqd_idx],
> mqd, sizeof(*mqd));
> + } else { /* for GPU_RESET case */
> + /* reset MQD to a clean status */
> + if (adev->gfx.mec.mqd_backup[mqd_idx])
> + memcpy(mqd, adev-
> >gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
> 
> - if (is_kiq)
> - gfx_v8_0_kiq_init_register(adev, mqd, ring);
> -
> - vi_srbm_select(adev, 0, 0, 0, 0);
> - mutex_unlock(&adev->srbm_mutex);
> + /* reset ring buffer */
> + ring->wptr = 0;
> + amdgpu_ring_clear_ring(ring);
> +
> + if (is_kiq) {
> + mutex_lock(&adev->srbm_mutex);
> + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue,
> 0);
> + gfx_v8_0_kiq_init_register(adev, mqd, ring);
> + vi_srbm_select(adev, 0, 0, 0, 0);
> + mutex_unlock(&adev->srbm_mutex);
> + }
> + }
> 
>   if (is_kiq)
>   gfx_v8_0_kiq_enable(ring);
> @@ -4913,9 +4935,9 @@ static int gfx_v8_0_kiq_resume(struct
> amdgpu_device *adev)
> 
>   ring = &adev->gfx.kiq.ring;
>   if (!amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr)) {
> - memset((void *)ring->mqd_ptr, 0, sizeof(struct vi_mqd));
>   r = gfx_v8_0_kiq_init_queue(ring, ring->mqd_ptr, ring-
> >mqd_gpu_addr);
>   amdgpu_bo_kunmap(ring->mqd_obj);
> + ring->mqd_ptr = NULL;
>   if (r)
>   return r;
>   } else {
> @@ -4925,9 +4947,9 @@ static int gfx_v8_0_kiq_resume(struct
> amdgpu_device *adev)
>   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
>

RE: [PATCH 08/11] drm/amdgpu:alloc mqd backup

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 08/11] drm/amdgpu:alloc mqd backup
> 
> this is required for restoring the mqds after GPU reset.
> 
> Change-Id: I84f821faa657a5d942c33d30f206eb66b579c2f8
> Signed-off-by: Monk Liu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index acd9970..73086d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -781,6 +781,7 @@ struct amdgpu_mec {
>   u32 num_pipe;
>   u32 num_mec;
>   u32 num_queue;
> + struct vi_mqd   *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS +
> 1];
>  };
> 
>  struct amdgpu_kiq {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 8f545992..b0612d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -7309,6 +7309,11 @@ static int gfx_v8_0_compute_mqd_soft_init(struct
> amdgpu_device *adev)
>   dev_warn(adev->dev, "failed to create ring mqd ob
> (%d)", r);
>   return r;
>   }
> +
> + /* prepare MQD backup */
> + adev-
> >gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] =
> kmalloc(sizeof(struct vi_mqd), GFP_KERNEL);
> + if (!adev-
> >gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
> + dev_warn(adev->dev, "no memory to create
> MQD backup for ring %s\n", ring->name);
>   }
> 
>   /* create MQD for each KCQ */
> @@ -7323,6 +7328,11 @@ static int gfx_v8_0_compute_mqd_soft_init(struct
> amdgpu_device *adev)
>   dev_warn(adev->dev, "failed to create ring
> mqd ob (%d)", r);
>   return r;
>   }
> +
> + /* prepare MQD backup */
> + adev->gfx.mec.mqd_backup[i] =
> kmalloc(sizeof(struct vi_mqd), GFP_KERNEL);
> + if (!adev->gfx.mec.mqd_backup[i])
> + dev_warn(adev->dev, "no memory to create
> MQD backup for ring %s\n", ring->name);
>   }
>   }
> 
> --
> 2.7.4
> 
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RE: [PATCH 07/11] drm/amdgpu:new field in_resete introduced for gfx

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 07/11] drm/amdgpu:new field in_resete introduced for gfx
> 
> use it to seperate driver load and gpu reset/resume
> because gfx IP need different approach for different
> hw_init trigger source
> 
> Change-Id: I991e0da52ccd197716d279bf9014de46d39acfea
> Signed-off-by: Monk Liu 

Typo in the patch title (resete), with that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 74bffca8..acd9970 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -901,6 +901,7 @@ struct amdgpu_gfx {
>   /* reset mask */
>   uint32_tgrbm_soft_reset;
>   uint32_tsrbm_soft_reset;
> + boolin_reset;
>  };
> 
>  int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> --
> 2.7.4
> 
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RE: [PATCH 10/11] drm/amdgpu:use clear_ring to clr RB

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 10/11] drm/amdgpu:use clear_ring to clr RB
> 
> In resume routine, we need clr RB prior to the
> ring test of engine, otherwise some engine hang
> duplicated during GPU reset.
> 
> Change-Id: Ie28f5aa677074f922e4a1a2eeeb7fe06461d9bdb
> Signed-off-by: Monk Liu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 1 +
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 1 +
>  3 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 7bacf3c..37d8422 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -230,7 +230,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev,
> struct amdgpu_ring *ring,
>   dev_err(adev->dev, "(%d) ring create failed\n", r);
>   return r;
>   }
> - memset((void *)ring->ring, 0, ring->ring_size);
> + amdgpu_ring_clear_ring(ring);
>   }
>   ring->ptr_mask = (ring->ring_size / 4) - 1;
>   ring->max_dw = max_dw;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index b0612d1..6584173 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4509,6 +4509,7 @@ static int gfx_v8_0_cp_gfx_resume(struct
> amdgpu_device *adev)
>   }
> 
>   /* start the ring */
> + amdgpu_ring_clear_ring(ring);
>   gfx_v8_0_cp_gfx_start(adev);
>   ring->ready = true;
>   r = amdgpu_ring_test_ring(ring);
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 9394ca6..d5206f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -615,6 +615,7 @@ static int sdma_v3_0_gfx_resume(struct
> amdgpu_device *adev)
> 
>   for (i = 0; i < adev->sdma.num_instances; i++) {
>   ring = &adev->sdma.instance[i].ring;
> + amdgpu_ring_clear_ring(ring);
>   wb_offset = (ring->rptr_offs * 4);
> 
>   mutex_lock(&adev->srbm_mutex);
> --
> 2.7.4
> 
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RE: [PATCH 09/11] drm/amdgpu:imple ring clear

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 09/11] drm/amdgpu:imple ring clear
> 
> we can use it clear ring buffer instead of fullfill
> 0, which is not correct for engine
> 
> Change-Id: I89dcd7b6c4de558f9b2860209a2739c7d4af262d
> Signed-off-by: Monk Liu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 0e57b04..3fd4ce8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -186,5 +186,12 @@ int amdgpu_ring_init(struct amdgpu_device *adev,
> struct amdgpu_ring *ring,
>unsigned ring_size, struct amdgpu_irq_src *irq_src,
>unsigned irq_type);
>  void amdgpu_ring_fini(struct amdgpu_ring *ring);
> +static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
> +{
> + int i = 0;
> + while (i <= ring->ptr_mask)
> + ring->ring[i++] = ring->funcs->nop;
> +
> +}
> 
>  #endif
> --
> 2.7.4
> 
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RE: [PATCH 05/11] drm/amdgpu:use work instead of delay-work

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 05/11] drm/amdgpu:use work instead of delay-work
> 
> no need to use a delay work since we don't know how
> much time hypervisor takes on FLR, so just polling
> and waiting in a work.
> 
> Change-Id: I41b6336baa00b1fd299311349402a17951b585a2
> Signed-off-by: Monk Liu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |  2 +-
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c| 36 +++
> -
>  2 files changed, 18 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 4b05568..846f29c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -50,7 +50,7 @@ struct amdgpu_virt {
>   struct mutexlock_reset;
>   struct amdgpu_irq_src   ack_irq;
>   struct amdgpu_irq_src   rcv_irq;
> - struct delayed_work flr_work;
> + struct work_struct  flr_work;
>   const struct amdgpu_virt_ops*ops;
>  };
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index 7c7420f..5f156d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -501,17 +501,19 @@ static int xgpu_vi_set_mailbox_ack_irq(struct
> amdgpu_device *adev,
> 
>  static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
>  {
> - struct amdgpu_virt *virt = container_of(work,
> - struct amdgpu_virt, flr_work.work);
> - struct amdgpu_device *adev = container_of(virt,
> - struct amdgpu_device, virt);
> - int r = 0;
> -
> - r = xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL);
> - if (r)
> - DRM_ERROR("failed to get flr cmpl msg from hypervior.\n");
> + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt,
> flr_work);
> + struct amdgpu_device *adev = container_of(virt, struct
> amdgpu_device, virt);
> +
> + /* wait until RCV_MSG become 3 */
> + if (!xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL))
> + adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
> + else {
> + pr_err("failed to recieve FLR_CMPL\n");
> + return;
> + }
> 
> - /* TODO: need to restore gfx states */
> + /* Trigger recovery due to world switch failure */
> + amdgpu_sriov_gpu_reset(adev, false);
>  }
> 
>  static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
> @@ -534,15 +536,12 @@ static int xgpu_vi_mailbox_rcv_irq(struct
> amdgpu_device *adev,
>  {
>   int r;
> 
> - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
> + /* see what event we get */
>   r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
> - /* do nothing for other msg */
> - if (r)
> - return 0;
> 
> - /* TODO: need to save gfx states */
> - schedule_delayed_work(&adev->virt.flr_work,
> -   msecs_to_jiffies(VI_MAILBOX_RESET_TIME));
> + /* only handle FLR_NOTIFY now */
> + if (!r)
> + schedule_work(&adev->virt.flr_work);
> 
>   return 0;
>  }
> @@ -595,14 +594,13 @@ int xgpu_vi_mailbox_get_irq(struct
> amdgpu_device *adev)
>   return r;
>   }
> 
> - INIT_DELAYED_WORK(&adev->virt.flr_work,
> xgpu_vi_mailbox_flr_work);
> + INIT_WORK(&adev->virt.flr_work, xgpu_vi_mailbox_flr_work);
> 
>   return 0;
>  }
> 
>  void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev)
>  {
> - cancel_delayed_work_sync(&adev->virt.flr_work);
>   amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
>   amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
>  }
> --
> 2.7.4
> 
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RE: [PATCH 01/11] drm/amdgpu:use MACRO like other places

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, February 08, 2017 4:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 01/11] drm/amdgpu:use MACRO like other places
> 
> Change-Id: Ica8f86577a50d817119de4b4fb95068dc72652a9
> Signed-off-by: Monk Liu 

With Michel's comments addressed, the patch is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 6734e55..8f545992 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4068,10 +4068,10 @@ static int gfx_v8_0_init_save_restore_list(struct
> amdgpu_device *adev)
>   data = mmRLC_SRM_INDEX_CNTL_DATA_0;
>   for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
>   if (unique_indices[i] != 0) {
> - amdgpu_mm_wreg(adev, temp + i,
> - unique_indices[i] & 0x3, false);
> - amdgpu_mm_wreg(adev, data + i,
> - unique_indices[i] >> 20, false);
> + WREG32(temp + i,
> + unique_indices[i] & 0x3);
> + WREG32(data + i,
> + unique_indices[i] >> 20);
>   }
>   }
>   kfree(register_list_format);
> --
> 2.7.4
> 
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Re: [PATCH 02/13] drm/amdgpu: doorbell registers need only be set once

2017-02-08 Thread Andres Rodriguez




On 2017-02-06 03:31 AM, Christian König wrote:

Am 04.02.2017 um 05:51 schrieb Andres Rodriguez:

The CP_MEC_DOORBELL_RANGE_* and CP_PQ_STATUS.DOORBELL_ENABLE registers
are not HQD specific.

They only need to be set once if at least 1 pipe requested doorbell
support.

Signed-off-by: Andres Rodriguez 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 1 +
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
  2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 147ce0e..9740800 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1427,6 +1427,7 @@ struct amdgpu_device {
  unsignednum_rings;
  struct amdgpu_ring*rings[AMDGPU_MAX_RINGS];
  boolib_pool_ready;
+booldoorbell_enabled;


Better put that into amdgpu_gfx and not amdgpu_device, cause that is a
gfx (CP) specific state.

Apart from that the patch looks good to me.

Christian.


Thanks for the review Christian.

If you don't mind I'll fix this in a followup that also includes a bit 
of changes to interrupt management.


Andres




  struct amdgpu_sa_managerring_tmp_bo;
/* interrupts */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index cf738e5..5d0e2c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4796,7 +4796,7 @@ static void gfx_v8_0_enable_doorbell(struct
amdgpu_device *adev, bool enable)
  {
  uint32_t tmp;
  -if (!enable)
+if (!enable || adev->doorbell_enabled)
  return;
if ((adev->asic_type == CHIP_CARRIZO) ||
@@ -4811,6 +4811,8 @@ static void gfx_v8_0_enable_doorbell(struct
amdgpu_device *adev, bool enable)
  tmp = RREG32(mmCP_PQ_STATUS);
  tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
  WREG32(mmCP_PQ_STATUS, tmp);
+
+adev->doorbell_enabled = true;
  }
static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, struct
vi_mqd *mqd)
@@ -5108,6 +5110,8 @@ static int gfx_v8_0_cp_resume(struct
amdgpu_device *adev)
  {
  int r;
  +adev->doorbell_enabled = false;
+
  if (!(adev->flags & AMD_IS_APU))
  gfx_v8_0_enable_gui_idle_interrupt(adev, false);





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Re: Change queue/pipe split between amdkfd and amdgpu

2017-02-08 Thread Andres Rodriguez


Hey Felix,

Thanks for the pointer to the ROCm mqd commit. I like that the 
workarounds are easy to spot. I'll add that to a new patch series I'm 
working on for some bug-fixes for perf being lower on pipes other than 
pipe 0.


I haven't tested this yet on kaveri/carrizo. I'm hoping someone with the 
HW will be able to give it a go. I put in a few small hacks to get KFD 
to boot but do nothing on polaris10.


Regards,
Andres

On 2017-02-06 03:20 PM, Felix Kuehling wrote:

Hi Andres,

Thank you for tackling this task. It's more involved than I expected,
mostly because I didn't have much awareness of the MQD management in amdgpu.

I made one comment in a separate message about the unified MQD commit
function, if you want to bring that more in line with our latest ROCm
release on github.

Also, were you able to test the upstream KFD with your changes on a
Kaveri or Carrizo?

Regards,
  Felix


On 17-02-03 11:51 PM, Andres Rodriguez wrote:

The current queue/pipe split policy is for amdgpu to take the first pipe of
MEC0 and leave the rest for amdkfd to use. This policy is taken as an
assumption in a few areas of the implementation.

This patch series aims to allow for flexible/tunable queue/pipe split policies
between kgd and kfd. It also updates the queue/pipe split policy to one that
allows better compute app concurrency for both drivers.

In the process some duplicate code and hardcoded constants were removed.

Any suggestions or feedback on improvements welcome.




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答复: 答复: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

that's because some customer modified QEMU and trap each VF's memory access, 
which cost too much time if using CPU access FB,

emmm, I guess we have no better choice by far,  do as you suggested,

to kill risk the negative effect that we may have no console if ib test failed, 
I suggest we don't block driver proceeding after ib test failure detected , 
doable ?

发件人: Christian König 
发送时间: 2017年2月8日 23:59:10
收件人: Liu, Monk; Michel Dänzer
抄送: amd-gfx@lists.freedesktop.org
主题: Re: 答复: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

Am 08.02.2017 um 16:53 schrieb Liu, Monk:

agreed, why not just use cpu to clear it ? is it because performance ?

Pixel Ding removed the CPU clear because "There's a failure caused by this is 
that handshaking gets timeout of SRIOV virtual function."

I can only assume that this is really adding to much delay at bootup.

发件人: Michel Dänzer 
发送时间: 2017年2月8日 23:52:02
收件人: Christian König; Liu, Monk
抄送: amd-gfx@lists.freedesktop.org
主题: Re: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

On 09/02/17 12:30 AM, Christian König wrote:
> The IB test make the decision if the hardware is working or not.
>
> So they should be the first commands (except for the ring tests) we send
> to the hardware.
>
> When we allocate the fb before the test we send the clear command to the
> hardware without knowing if the hardware really works or not.
>
> Not a big issue, but I think the order makes more sense that way.

I just wonder if it's worth all the trouble, just to clear the fbcon
buffer[0], if the result is that the console output is delayed, possibly
indefinitely.

Actually that change is quite beneficial because the IB tests where usually 
revealing any problem.

Not 100% sure, but when we initialize the fb later that might actually allow us 
to better track such problems down.

Going to check that,
Christian.

[0] We don't have any other hardware acceleration for fbcon, so its BO
is only accessed by the CPU and display hardware after this, and has to
be pinned in the CPU visible area of VRAM at all times anyway.

--
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Libre software enthusiast | Mesa and X developer

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Re: 答复: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

Am 08.02.2017 um 16:53 schrieb Liu, Monk:

agreed, why not just use cpu to clear it ? is it because performance ?

Pixel Ding removed the CPU clear because "There's a failure caused by 
this is that handshaking gets timeout of SRIOV virtual function."

I can only assume that this is really adding to much delay at bootup.

*发件人:* Michel Dänzer 
*发送时间:* 2017年2月8日 23:52:02
*收件人:* Christian König; Liu, Monk
*抄送:* amd-gfx@lists.freedesktop.org
*主题:* Re: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error
On 09/02/17 12:30 AM, Christian König wrote:
> The IB test make the decision if the hardware is working or not.
>
> So they should be the first commands (except for the ring tests) we send
> to the hardware.
>
> When we allocate the fb before the test we send the clear command to the
> hardware without knowing if the hardware really works or not.
>
> Not a big issue, but I think the order makes more sense that way.

I just wonder if it's worth all the trouble, just to clear the fbcon
buffer[0], if the result is that the console output is delayed, possibly
indefinitely.

Actually that change is quite beneficial because the IB tests where 
usually revealing any problem.

Not 100% sure, but when we initialize the fb later that might actually 
allow us to better track such problems down.

Going to check that,
Christian.

[0] We don't have any other hardware acceleration for fbcon, so its BO
is only accessed by the CPU and display hardware after this, and has to
be pinned in the CPU visible area of VRAM at all times anyway.

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答复: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

agreed, why not just use cpu to clear it ? is it because performance ?

发件人: Michel Dänzer 
发送时间: 2017年2月8日 23:52:02
收件人: Christian König; Liu, Monk
抄送: amd-gfx@lists.freedesktop.org
主题: Re: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

On 09/02/17 12:30 AM, Christian König wrote:
> The IB test make the decision if the hardware is working or not.
>
> So they should be the first commands (except for the ring tests) we send
> to the hardware.
>
> When we allocate the fb before the test we send the clear command to the
> hardware without knowing if the hardware really works or not.
>
> Not a big issue, but I think the order makes more sense that way.

I just wonder if it's worth all the trouble, just to clear the fbcon
buffer[0], if the result is that the console output is delayed, possibly
indefinitely.

[0] We don't have any other hardware acceleration for fbcon, so its BO
is only accessed by the CPU and display hardware after this, and has to
be pinned in the CPU visible area of VRAM at all times anyway.

--
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Libre software enthusiast | Mesa and X developer
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Re: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

On 09/02/17 12:30 AM, Christian König wrote:
> The IB test make the decision if the hardware is working or not.
> 
> So they should be the first commands (except for the ring tests) we send
> to the hardware.
> 
> When we allocate the fb before the test we send the clear command to the
> hardware without knowing if the hardware really works or not.
> 
> Not a big issue, but I think the order makes more sense that way.

I just wonder if it's worth all the trouble, just to clear the fbcon
buffer[0], if the result is that the console output is delayed, possibly
indefinitely.

[0] We don't have any other hardware acceleration for fbcon, so its BO
is only accessed by the CPU and display hardware after this, and has to
be pinned in the CPU visible area of VRAM at all times anyway.

-- 
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Libre software enthusiast | Mesa and X developer
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答复: 答复: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

we will send another patch to fix it later that using ->hw_init instead of
->resume .

BR Monk

发件人: amd-gfx 代表 Liu, Monk

发送时间: 2017年2月8日 23:40:35
收件人: Christian König; amd-gfx@lists.freedesktop.org
主题: 答复: 答复: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

If I understand you correct you really don't need all that reload and restore
dance. Instead what you need for the SRIOV case is just reinitializing the
hardware, isn't it?

That this works is just pure coincident because we don't have backup/restore
function for the blocks enabled for SRIOV.

ML：

yeah, I use amdgpu_sriov_resume_early/late because according to the current
code sequence there is nothing bad introduced without invoking suspend first.
call hw_init on each IP should behaves the same as my patch.

I misunderstand you that I thought you insist invoking suspend() and resume()
in pair ..

I agree use hw_init without suspend is more reasonable

thanks

发件人: Christian König
发送时间: 2017年2月8日 下午 11:27
收件人: Liu, Monk; amd-gfx@lists.freedesktop.org
主题: Re: 答复: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

do you mean turn VM into s3 mode ?

if so we not get that step, the S3 suspend/resume function is not supported by
SRIOV vf case.

Then just try to unbind the fb and unload the module.

The idea of the suspend/resume callbacks are that they are only called in pairs.

See suspend is supposed to unpin all BOs and backup all resources from VRAM to
GTT and preserve the general hardware state.

Now what resume does is to reload BOs and restore the state previously saved
during the suspend backup.

If I understand you correct you really don't need all that reload and restore
dance. Instead what you need for the SRIOV case is just reinitializing the
hardware, isn't it?

That this works is just pure coincident because we don't have backup/restore
function for the blocks enabled for SRIOV.

Regards,
Christian.

Am 08.02.2017 um 16:17 schrieb Liu, Monk:

wait a minutes ...

》3. suspend the VM with glxgears running

do you mean turn VM into s3 mode ?

if so we not get that step, the S3 suspend/resume function is not supported by
SRIOV vf case.

发件人: Christian König
发送时间: 2017年2月8日 23:13:46
收件人: Liu, Monk;
amd-gfx@lists.freedesktop.org
主题: Re: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

and like I said, this approach is correct and verified by hang test
Completely irrelevant.

Please try the following:
1. Trigger a hang
2. Reset the GPU
3. Suspend the VM with glxgears running
4. Resume the VM

I'm pretty sure that with your approach that either suspending or resuming the
VM with an application running will just hang.

Anyway even if all the code path you break here (UVD/VCE at minimum) are
disabled in the SRIOV case it's still not a good idea completely breaking the
design just to satisfy the SRIOV feature.

So that is still a clear NAK on that. Please do as I told you and use the
hw_init() callback instead, it is especially made for this use case.

Regards,
Christian.

Am 08.02.2017 um 15:57 schrieb Liu, Monk:

》As I wrote in the other thread as well calling amdgpu_resume() without proper
suspend will just mess up a whole bunch of internal structures.

please name at least one, I'll check and see how to improve

and like I said, this approach is correct and verified by hang test, if
internal structures messed up I don't think the test will easy pass. hw_init()
just call resume per engine.

you can take a deep look into sriov_gpu_reset and judge later

发件人: Christian König
发送时间: 2017年2月8日 18:49:57
收件人: Liu, Monk;
amd-gfx@lists.freedesktop.org
主题: Re: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

+ /* now we are okay to resume SMC/CP/SDMA */
+ amdgpu_resume_late(adev);
As I wrote in the other thread as well calling amdgpu_resume() without proper
suspend will just mess up a whole bunch of internal structures.

So a clear NAK on that approach. If you don't need the hw stop which
amdgpu_suspend() does for SRIOV then please try to just use the hw_init()
callback and not the resume() callback.

Regards,
Christian.

Am 07.02.2017 um 07:26 schrieb Liu, Monk:

patch 1-8 are some fixes for sriov gpu reset feature

patch 9 -20 are for sriov gpu reset

BR Monk

发件人: amd-gfx

代表 Monk Liu
发送时间: 2017年2月7日 14:11:07
收件人: amd-gfx@lists.freedesktop.org
抄送: Liu, Monk
主题: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 158 +++

Re: 答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error


The IB test make the decision if the hardware is working or not.

So they should be the first commands (except for the ring tests) we send 
to the hardware.


When we allocate the fb before the test we send the clear command to the 
hardware without knowing if the hardware really works or not.


Not a big issue, but I think the order makes more sense that way.

Regards,
Christian.

Am 08.02.2017 um 16:21 schrieb Liu, Monk:


yeah, make sense

@Christian, why move fbdev_init() further down after ib test ? any 
consideration ?



*发件人:* Michel Dänzer 
*发送时间:* 2017年2月8日 23:19:23
*收件人:* Christian König; Liu, Monk
*抄送:* amd-gfx@lists.freedesktop.org
*主题:* Re: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error
On 08/02/17 07:52 PM, Christian König wrote:
> Am 08.02.2017 um 10:41 schrieb Monk Liu:
>> ib_pool init should prior to fbdev_init, otherwise
>> there will be error from amdgpu_sa_bo_new
>> (amdgpu_sa.c:323)
>>
>> fbdev_init will call ttm_validate which further call
>> amdgpu_sa_bo_new.
>>
>> Change-Id: I3a969570d443f61a44f67b0d76b3871ca5c3ea81
>> Signed-off-by: Monk Liu 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index afcae15..4169bb1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1918,14 +1918,14 @@ int amdgpu_device_init(struct amdgpu_device
>> *adev,
>>   /* Get a log2 for easy divisions. */
>>   adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
>>   -amdgpu_fbdev_init(adev);
>> -
>>   r = amdgpu_ib_pool_init(adev);
>>   if (r) {
>>   dev_err(adev->dev, "IB initialization failed (%d).\n", r);
>>   goto failed;
>>   }
>>   +amdgpu_fbdev_init(adev);
>> +
>
> As noted internally as well, please more that one more further down
> behind the call to amdgpu_ib_ring_tests().

If I understand correctly, that could result in no console output in the
worst case if there's trouble with the ring & IB tests? That doesn't
seem very good.


--
Earthling Michel Dänzer   | http://www.amd.com 


Libre software enthusiast | Mesa and X developer


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



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答复: 答复: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

If I understand you correct you really don't need all that reload and restore 
dance. Instead what you need for the SRIOV case is just reinitializing the 
hardware, isn't it?

That this works is just pure coincident because we don't have backup/restore 
function for the blocks enabled for SRIOV.


ML：

yeah,  I use amdgpu_sriov_resume_early/late because according to the current 
code sequence there is nothing bad introduced without invoking suspend first. 
call hw_init on each IP should behaves the same as my patch.


I misunderstand you that I thought you insist invoking suspend() and resume() 
in pair ..

I agree use hw_init without suspend is more reasonable


thanks




发件人: Christian König 
发送时间: 2017年2月8日 下午 11:27
收件人: Liu, Monk; amd-gfx@lists.freedesktop.org
主题: Re: 答复: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset


do you mean turn VM into s3 mode ?

if so we not get that step, the S3 suspend/resume function is not supported by 
SRIOV vf case.

Then just try to unbind the fb and unload the module.

The idea of the suspend/resume callbacks are that they are only called in pairs.

See suspend is supposed to unpin all BOs and backup all resources from VRAM to 
GTT and preserve the general hardware state.

Now what resume does is to reload BOs and restore the state previously saved 
during the suspend backup.

If I understand you correct you really don't need all that reload and restore 
dance. Instead what you need for the SRIOV case is just reinitializing the 
hardware, isn't it?

That this works is just pure coincident because we don't have backup/restore 
function for the blocks enabled for SRIOV.

Regards,
Christian.

Am 08.02.2017 um 16:17 schrieb Liu, Monk:

wait a minutes ...


》3. suspend the VM with glxgears running


do you mean turn VM into s3 mode ?

if so we not get that step, the S3 suspend/resume function is not supported by 
SRIOV vf case.






发件人: Christian König 
发送时间: 2017年2月8日 23:13:46
收件人: Liu, Monk; 
amd-gfx@lists.freedesktop.org
主题: Re: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

and like I said, this approach is correct and verified by hang test
Completely irrelevant.

Please try the following:
1. Trigger a hang
2. Reset the GPU
3. Suspend the VM with glxgears running
4. Resume the VM

I'm pretty sure that with your approach that either suspending or resuming the 
VM with an application running will just hang.

Anyway even if all the code path you break here (UVD/VCE at minimum) are 
disabled in the SRIOV case it's still not a good idea completely breaking the 
design just to satisfy the SRIOV feature.

So that is still a clear NAK on that. Please do as I told you and use the 
hw_init() callback instead, it is especially made for this use case.

Regards,
Christian.

Am 08.02.2017 um 15:57 schrieb Liu, Monk:

》As I wrote in the other thread as well calling amdgpu_resume() without proper 
suspend will just mess up a whole bunch of internal structures.

please name at least one, I'll check and see how to improve

and like I said, this approach is correct and verified by hang test, if 
internal structures messed up I don't think the test will easy pass. hw_init() 
just call resume per engine.

you can take a deep look into sriov_gpu_reset and judge later




发件人: Christian König 
发送时间: 2017年2月8日 18:49:57
收件人: Liu, Monk; 
amd-gfx@lists.freedesktop.org
主题: Re: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

+   /* now we are okay to resume SMC/CP/SDMA */
+   amdgpu_resume_late(adev);
As I wrote in the other thread as well calling amdgpu_resume() without proper 
suspend will just mess up a whole bunch of internal structures.

So a clear NAK on that approach. If you don't need the hw stop which 
amdgpu_suspend() does for SRIOV then please try to just use the hw_init() 
callback and not the resume() callback.

Regards,
Christian.

Am 07.02.2017 um 07:26 schrieb Liu, Monk:

patch 1-8 are some fixes for sriov gpu reset feature

patch 9 -20 are for sriov gpu reset


BR Monk


发件人: amd-gfx 

 代表 Monk Liu 
发送时间: 2017年2月7日 14:11:07
收件人: amd-gfx@lists.freedesktop.org
抄送: Liu, Monk
主题: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 158 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |   1 +
 2 files changed, 158 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e926f84..2b404ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/dri

Re: 答复: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset


do you mean turn VM into s3 mode ?

if so we not get that step, the S3 suspend/resume function is not 
supported by SRIOV vf case.



Then just try to unbind the fb and unload the module.

The idea of the suspend/resume callbacks are that they are only called 
in pairs.


See suspend is supposed to unpin all BOs and backup all resources from 
VRAM to GTT and preserve the general hardware state.


Now what resume does is to reload BOs and restore the state previously 
saved during the suspend backup.


If I understand you correct you really don't need all that reload and 
restore dance. Instead what you need for the SRIOV case is just 
reinitializing the hardware, isn't it?


That this works is just pure coincident because we don't have 
backup/restore function for the blocks enabled for SRIOV.


Regards,
Christian.

Am 08.02.2017 um 16:17 schrieb Liu, Monk:


wait a minutes ...


》3. suspend the VM with glxgears running


do you mean turn VM into s3 mode ?

if so we not get that step, the S3 suspend/resume function is not 
supported by SRIOV vf case.







*发件人:* Christian König 
*发送时间:* 2017年2月8日 23:13:46
*收件人:* Liu, Monk; amd-gfx@lists.freedesktop.org
*主题:* Re: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV 
gpu_reset

and like I said, this approach is correct and verified by hang test

Completely irrelevant.

Please try the following:
1. Trigger a hang
2. Reset the GPU
3. Suspend the VM with glxgears running
4. Resume the VM

I'm pretty sure that with your approach that either suspending or 
resuming the VM with an application running will just hang.


Anyway even if all the code path you break here (UVD/VCE at minimum) 
are disabled in the SRIOV case it's still not a good idea completely 
breaking the design just to satisfy the SRIOV feature.


So that is still a clear NAK on that. Please do as I told you and use 
the hw_init() callback instead, it is especially made for this use case.


Regards,
Christian.

Am 08.02.2017 um 15:57 schrieb Liu, Monk:


》As I wrote in the other thread as well calling amdgpu_resume() 
without proper suspend will just mess up a whole bunch of internal 
structures.



please name at least one, I'll check and see how to improve

and like I said, this approach is correct and verified by hang test, 
if internal structures messed up I don't think the test will easy 
pass. hw_init() just call resume per engine.


you can take a deep look into sriov_gpu_reset and judge later



*发件人:* Christian König 
*发送时间:* 2017年2月8日 18:49:57
*收件人:* Liu, Monk; amd-gfx@lists.freedesktop.org
*主题:* Re: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV 
gpu_reset

+   /* now we are okay to resume SMC/CP/SDMA */
+   amdgpu_resume_late(adev);
As I wrote in the other thread as well calling amdgpu_resume() 
without proper suspend will just mess up a whole bunch of internal 
structures.


So a clear NAK on that approach. If you don't need the hw stop which 
amdgpu_suspend() does for SRIOV then please try to just use the 
hw_init() callback and not the resume() callback.


Regards,
Christian.

Am 07.02.2017 um 07:26 schrieb Liu, Monk:


patch 1-8 are some fixes for sriov gpu reset feature

patch 9 -20 are for sriov gpu reset


BR Monk


*发件人:* amd-gfx  代表 Monk Liu 


*发送时间:* 2017年2月7日 14:11:07
*收件人:* amd-gfx@lists.freedesktop.org
*抄送:* Liu, Monk
*主题:* [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 158 
-

 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |   1 +
 2 files changed, 158 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index e926f84..2b404ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1604,6 +1604,53 @@ int amdgpu_suspend(struct amdgpu_device *adev)
 return 0;
 }

+static int amdgpu_resume_early(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||

+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
+   r = 
adev->ip_blocks[i].version->funcs->resume(adev);

+
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
+static int amdgpu_resume_late(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev-

答复: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

yeah, make sense

@Christian, why move fbdev_init() further down after ib test ? any 
consideration ?


发件人: Michel Dänzer 
发送时间: 2017年2月8日 23:19:23
收件人: Christian König; Liu, Monk
抄送: amd-gfx@lists.freedesktop.org
主题: Re: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

On 08/02/17 07:52 PM, Christian König wrote:
> Am 08.02.2017 um 10:41 schrieb Monk Liu:
>> ib_pool init should prior to fbdev_init, otherwise
>> there will be error from amdgpu_sa_bo_new
>> (amdgpu_sa.c:323)
>>
>> fbdev_init will call ttm_validate which further call
>> amdgpu_sa_bo_new.
>>
>> Change-Id: I3a969570d443f61a44f67b0d76b3871ca5c3ea81
>> Signed-off-by: Monk Liu 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index afcae15..4169bb1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1918,14 +1918,14 @@ int amdgpu_device_init(struct amdgpu_device
>> *adev,
>>   /* Get a log2 for easy divisions. */
>>   adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
>>   -amdgpu_fbdev_init(adev);
>> -
>>   r = amdgpu_ib_pool_init(adev);
>>   if (r) {
>>   dev_err(adev->dev, "IB initialization failed (%d).\n", r);
>>   goto failed;
>>   }
>>   +amdgpu_fbdev_init(adev);
>> +
>
> As noted internally as well, please more that one more further down
> behind the call to amdgpu_ib_ring_tests().

If I understand correctly, that could result in no console output in the
worst case if there's trouble with the ring & IB tests? That doesn't
seem very good.


--
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

On 08/02/17 07:52 PM, Christian König wrote:
> Am 08.02.2017 um 10:41 schrieb Monk Liu:
>> ib_pool init should prior to fbdev_init, otherwise
>> there will be error from amdgpu_sa_bo_new
>> (amdgpu_sa.c:323)
>>
>> fbdev_init will call ttm_validate which further call
>> amdgpu_sa_bo_new.
>>
>> Change-Id: I3a969570d443f61a44f67b0d76b3871ca5c3ea81
>> Signed-off-by: Monk Liu 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index afcae15..4169bb1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1918,14 +1918,14 @@ int amdgpu_device_init(struct amdgpu_device
>> *adev,
>>   /* Get a log2 for easy divisions. */
>>   adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
>>   -amdgpu_fbdev_init(adev);
>> -
>>   r = amdgpu_ib_pool_init(adev);
>>   if (r) {
>>   dev_err(adev->dev, "IB initialization failed (%d).\n", r);
>>   goto failed;
>>   }
>>   +amdgpu_fbdev_init(adev);
>> +
> 
> As noted internally as well, please more that one more further down
> behind the call to amdgpu_ib_ring_tests().

If I understand correctly, that could result in no console output in the
worst case if there's trouble with the ring & IB tests? That doesn't
seem very good.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

答复: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

wait a minutes ...


》3. suspend the VM with glxgears running


do you mean turn VM into s3 mode ?

if so we not get that step, the S3 suspend/resume function is not supported by 
SRIOV vf case.






发件人: Christian König 
发送时间: 2017年2月8日 23:13:46
收件人: Liu, Monk; amd-gfx@lists.freedesktop.org
主题: Re: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

and like I said, this approach is correct and verified by hang test
Completely irrelevant.

Please try the following:
1. Trigger a hang
2. Reset the GPU
3. Suspend the VM with glxgears running
4. Resume the VM

I'm pretty sure that with your approach that either suspending or resuming the 
VM with an application running will just hang.

Anyway even if all the code path you break here (UVD/VCE at minimum) are 
disabled in the SRIOV case it's still not a good idea completely breaking the 
design just to satisfy the SRIOV feature.

So that is still a clear NAK on that. Please do as I told you and use the 
hw_init() callback instead, it is especially made for this use case.

Regards,
Christian.

Am 08.02.2017 um 15:57 schrieb Liu, Monk:

》As I wrote in the other thread as well calling amdgpu_resume() without proper 
suspend will just mess up a whole bunch of internal structures.

please name at least one, I'll check and see how to improve

and like I said, this approach is correct and verified by hang test, if 
internal structures messed up I don't think the test will easy pass. hw_init() 
just call resume per engine.

you can take a deep look into sriov_gpu_reset and judge later




发件人: Christian König 
发送时间: 2017年2月8日 18:49:57
收件人: Liu, Monk; 
amd-gfx@lists.freedesktop.org
主题: Re: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

+   /* now we are okay to resume SMC/CP/SDMA */
+   amdgpu_resume_late(adev);
As I wrote in the other thread as well calling amdgpu_resume() without proper 
suspend will just mess up a whole bunch of internal structures.

So a clear NAK on that approach. If you don't need the hw stop which 
amdgpu_suspend() does for SRIOV then please try to just use the hw_init() 
callback and not the resume() callback.

Regards,
Christian.

Am 07.02.2017 um 07:26 schrieb Liu, Monk:

patch 1-8 are some fixes for sriov gpu reset feature

patch 9 -20 are for sriov gpu reset


BR Monk


发件人: amd-gfx 

 代表 Monk Liu 
发送时间: 2017年2月7日 14:11:07
收件人: amd-gfx@lists.freedesktop.org
抄送: Liu, Monk
主题: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 158 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |   1 +
 2 files changed, 158 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e926f84..2b404ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1604,6 +1604,53 @@ int amdgpu_suspend(struct amdgpu_device *adev)
 return 0;
 }

+static int amdgpu_resume_early(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_GMC ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_IH)
+   r = adev->ip_blocks[i].version->funcs->resume(adev);
+
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
+static int amdgpu_resume_late(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_GMC ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_IH )
+   continue;
+
+   r = adev->ip_blocks[i].version->funcs->resume(adev);
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   re

Re: 答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset


and like I said, this approach is correct and verified by hang test

Completely irrelevant.

Please try the following:
1. Trigger a hang
2. Reset the GPU
3. Suspend the VM with glxgears running
4. Resume the VM

I'm pretty sure that with your approach that either suspending or 
resuming the VM with an application running will just hang.


Anyway even if all the code path you break here (UVD/VCE at minimum) are 
disabled in the SRIOV case it's still not a good idea completely 
breaking the design just to satisfy the SRIOV feature.


So that is still a clear NAK on that. Please do as I told you and use 
the hw_init() callback instead, it is especially made for this use case.


Regards,
Christian.

Am 08.02.2017 um 15:57 schrieb Liu, Monk:


》As I wrote in the other thread as well calling amdgpu_resume() 
without proper suspend will just mess up a whole bunch of internal 
structures.



please name at least one, I'll check and see how to improve

and like I said, this approach is correct and verified by hang test, 
if internal structures messed up I don't think the test will easy 
pass. hw_init() just call resume per engine.


you can take a deep look into sriov_gpu_reset and judge later



*发件人:* Christian König 
*发送时间:* 2017年2月8日 18:49:57
*收件人:* Liu, Monk; amd-gfx@lists.freedesktop.org
*主题:* Re: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV 
gpu_reset

+   /* now we are okay to resume SMC/CP/SDMA */
+   amdgpu_resume_late(adev);
As I wrote in the other thread as well calling amdgpu_resume() without 
proper suspend will just mess up a whole bunch of internal structures.


So a clear NAK on that approach. If you don't need the hw stop which 
amdgpu_suspend() does for SRIOV then please try to just use the 
hw_init() callback and not the resume() callback.


Regards,
Christian.

Am 07.02.2017 um 07:26 schrieb Liu, Monk:


patch 1-8 are some fixes for sriov gpu reset feature

patch 9 -20 are for sriov gpu reset


BR Monk


*发件人:* amd-gfx  代表 Monk Liu 


*发送时间:* 2017年2月7日 14:11:07
*收件人:* amd-gfx@lists.freedesktop.org
*抄送:* Liu, Monk
*主题:* [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 158 
-

 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |   1 +
 2 files changed, 158 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index e926f84..2b404ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1604,6 +1604,53 @@ int amdgpu_suspend(struct amdgpu_device *adev)
 return 0;
 }

+static int amdgpu_resume_early(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||

+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
+   r = 
adev->ip_blocks[i].version->funcs->resume(adev);

+
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
+static int amdgpu_resume_late(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||

+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
+   continue;
+
+   r = adev->ip_blocks[i].version->funcs->resume(adev);
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
 static int amdgpu_resume(struct amdgpu_device *adev)
 {
 int i, r;
@@ -2343,6 +2390,115 @@ static int 
amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,

 }

 /**
+ * amdgpu_sriov_gpu_reset - reset the asic
+ *
+ * @adev: amdgpu device pointer
+ * @voluntary: if this reset is requested by guest.
+ * (true means by guest and false means by HYPERVISOR )
+ *
+ * Attempt the reset the GPU if it has hung (all asics).
+ * for SRIOV case.
+ * Returns 0 for success or an error on failure.
+ */
+int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
+{
+   int i, r = 0;
+   int resched;
+   struct amdgpu_bo

[PATCH libdrm] amdgpu: add PRT unit test

From: Christian König 

Just a simple test if PRT works or not.

Signed-off-by: Christian König 
---
 tests/amdgpu/basic_tests.c | 66 --
 1 file changed, 64 insertions(+), 2 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index bfda21b..24dd605 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -48,6 +48,7 @@ static void amdgpu_command_submission_compute(void);
 static void amdgpu_command_submission_sdma(void);
 static void amdgpu_userptr_test(void);
 static void amdgpu_semaphore_test(void);
+static void amdgpu_prt_test(void);
 
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -61,6 +62,7 @@ CU_TestInfo basic_tests[] = {
{ "Command submission Test (Compute)", 
amdgpu_command_submission_compute },
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
{ "SW semaphore Test",  amdgpu_semaphore_test },
+   { "PRT Test",  amdgpu_prt_test },
CU_TEST_INFO_NULL,
 };
 #define BUFFER_SIZE (8 * 1024)
@@ -734,7 +736,6 @@ static void 
amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
 
/* prepare CS */
CU_ASSERT_NOT_EQUAL(pm4_src, NULL);
-   CU_ASSERT_NOT_EQUAL(resources, NULL);
CU_ASSERT_NOT_EQUAL(ib_info, NULL);
CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
CU_ASSERT_TRUE(pm4_dw <= 1024);
@@ -759,7 +760,8 @@ static void 
amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
ibs_request->ibs = ib_info;
ibs_request->fence_info.handle = NULL;
 
-   memcpy(all_res, resources, sizeof(resources[0]) * res_cnt);
+   if (resources)
+   memcpy(all_res, resources, sizeof(resources[0]) * res_cnt);
all_res[res_cnt] = ib_result_handle;
 
r = amdgpu_bo_list_create(device_handle, res_cnt+1, all_res,
@@ -1208,3 +1210,63 @@ static void amdgpu_userptr_test(void)
r = amdgpu_cs_ctx_free(context_handle);
CU_ASSERT_EQUAL(r, 0);
 }
+
+static void amdgpu_prt_test(void)
+{
+   int i, r, j;
+   uint32_t *pm4 = NULL;
+   uint64_t bo_mc;
+   int pm4_dw = 256;
+   int sdma_write_length = 4;
+   amdgpu_context_handle context_handle;
+   struct amdgpu_cs_ib_info *ib_info;
+   struct amdgpu_cs_request *ibs_request;
+   amdgpu_va_handle va_handle;
+
+   pm4 = calloc(pm4_dw, sizeof(*pm4));
+   CU_ASSERT_NOT_EQUAL(pm4, NULL);
+
+   ib_info = calloc(1, sizeof(*ib_info));
+   CU_ASSERT_NOT_EQUAL(ib_info, NULL);
+
+   ibs_request = calloc(1, sizeof(*ibs_request));
+   CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
+
+   r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_va_range_alloc(device_handle,
+ amdgpu_gpu_va_range_general,
+ BUFFER_SIZE, 1, 0, &bo_mc,
+ &va_handle, 0);
+   CU_ASSERT_EQUAL(r, 0);
+
+   /*r = amdgpu_bo_va_op_raw(device_handle, NULL, 0, BUFFER_SIZE, bo_mc,
+   AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
+   CU_ASSERT_EQUAL(r, 0);*/
+
+   j = i = 0;
+   pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length);
+   pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+   pm4[i++] = 0xfffc & bo_mc;
+   pm4[i++] = (0x & bo_mc) >> 32;
+   while(j++ < sdma_write_length)
+   pm4[i++] = 0xdeadbeaf;
+
+   amdgpu_test_exec_cs_helper(context_handle,
+  AMDGPU_HW_IP_GFX, 0,
+  i, pm4, 0, NULL,
+  ib_info, ibs_request);
+   free(ibs_request);
+   free(ib_info);
+   free(pm4);
+
+   r = amdgpu_bo_va_op_raw(device_handle, NULL, 0, BUFFER_SIZE, bo_mc,
+   AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_UNMAP);
+   CU_ASSERT_EQUAL(r, 0);
+   r = amdgpu_va_range_free(va_handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_cs_ctx_free(context_handle);
+   CU_ASSERT_EQUAL(r, 0);
+}
-- 
2.5.0

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[PATCH 6/6] drm/amdgpu: implement PRT for GFX8 v2

From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: set correct register

Signed-off-by: Junwei Zhang 
Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 7669b32..a68b850 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -595,6 +595,62 @@ static void gmc_v8_0_set_fault_enable_default(struct 
amdgpu_device *adev,
 }
 
 /**
+ * gmc_v8_0_set_prt - set PRT VM fault
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable VM fault handling for PRT
+*/
+static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_PRT_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
+/**
  * gmc_v8_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -1485,6 +1541,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
.flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
.set_pte_pde = gmc_v8_0_gart_set_pte_pde,
+   .set_prt = gmc_v8_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
-- 
2.5.0

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[PATCH 5/6] drm/amdgpu: implement PRT for GFX7 v2

From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: set correct register

Signed-off-by: Junwei Zhang 
Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 8d05e0c..4b38d06 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -481,6 +481,62 @@ static void gmc_v7_0_set_fault_enable_default(struct 
amdgpu_device *adev,
 }
 
 /**
+ * gmc_v7_0_set_prt - set PRT VM fault
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable VM fault handling for PRT
+ */
+static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   uint32_t tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES, enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   MASK_PDE0_FAULT, enable);
+   WREG32(mmVM_PRT_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
+/**
  * gmc_v7_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -1259,6 +1315,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
.flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
.set_pte_pde = gmc_v7_0_gart_set_pte_pde,
+   .set_prt = gmc_v7_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
-- 
2.5.0

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[PATCH 1/6] drm/amdgpu: add support for BO_VAs without BO v2

From: Christian König 

For PRT support we need mappings which aren't backed by any memory.

v2: fix parameter checking

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 ++--
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8e6030d..64f04c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1117,7 +1117,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct fence *exclusive;
int r;
 
-   if (clear) {
+   if (clear || !bo_va->bo) {
mem = NULL;
nodes = NULL;
exclusive = NULL;
@@ -1134,9 +1134,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
}
 
-   flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
-   gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
-   adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? flags : 0;
+   if (bo_va->bo) {
+   flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
+   gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
+   adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
+   flags : 0;
+   } else {
+   flags = 0x0;
+   gtt_flags = ~0x0;
+   }
 
spin_lock(&vm->status_lock);
if (!list_empty(&bo_va->vm_status))
@@ -1271,7 +1277,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct 
amdgpu_device *adev,
INIT_LIST_HEAD(&bo_va->invalids);
INIT_LIST_HEAD(&bo_va->vm_status);
 
-   list_add_tail(&bo_va->bo_list, &bo->va);
+   if (bo)
+   list_add_tail(&bo_va->bo_list, &bo->va);
 
return bo_va;
 }
@@ -1309,7 +1316,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 
/* make sure object fit at this offset */
eaddr = saddr + size - 1;
-   if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
+   if (saddr >= eaddr ||
+   (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
return -EINVAL;
 
last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
-- 
2.5.0

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[PATCH 4/6] drm/amdgpu: implement PRT for GFX6 v2

From: Christian König 

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: write to the correct register, adjust bits to that hw generation
v3: fix compilation, add the missing register bit definitions

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 55 ++
 .../drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h |  4 ++
 3 files changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 99ca5e8..d8516dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -571,6 +571,7 @@ struct amdgpu_mc {
uint32_tvram_type;
uint32_tsrbm_soft_reset;
struct amdgpu_mode_mc_save save;
+   boolprt_warning;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index e2b0b16..b9b5c24 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,60 @@ static void gmc_v6_0_set_fault_enable_default(struct 
amdgpu_device *adev,
WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }
 
+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+   u32 tmp;
+
+   if (enable && !adev->mc.prt_warning) {
+   dev_warn(adev->dev, "Disabling VM faults because of PRT 
request!\n");
+   adev->mc.prt_warning = true;
+   }
+
+   tmp = RREG32(mmVM_PRT_CNTL);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L2_CACHE_STORE_INVALID_ENTRIES,
+   enable);
+   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+   L1_TLB_STORE_INVALID_ENTRIES,
+   enable);
+   WREG32(mmVM_PRT_CNTL, tmp);
+
+   if (enable) {
+   uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+   uint32_t high = adev->vm_manager.max_pfn;
+
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+   } else {
+   WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfff);
+   WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+   WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+   }
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
int r, i;
@@ -1080,6 +1134,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
+   .set_prt = gmc_v6_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
index 0f6c6c8..7155312 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
@@ -11891,5 +11891,9 @@
 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x0003
 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x0004L
 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x0002
+#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x0001L
+#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x
+#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x0002L
+#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0001
 
 #endif
-- 
2.5.0

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[PATCH 2/6] drm/amdgpu: add basic PRT support

From: Christian König 

Future hardware generations can handle PRT flags on a per page basis,
but current hardware can only turn it on globally.

Add the basic handling for both, a global callback to enable/disable
triggered by setting a per mapping flag.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 101 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |   6 ++
 3 files changed, 98 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 402a895..34a971a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -296,6 +296,8 @@ struct amdgpu_gart_funcs {
   uint32_t gpu_page_idx, /* pte/pde to update */
   uint64_t addr, /* addr to write into pte/pde */
   uint32_t flags); /* access flags */
+   /* enable/disable PRT support */
+   void (*set_prt)(struct amdgpu_device *adev, bool enable);
 };
 
 /* provided by the ih block */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 64f04c7..bc32239 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -69,6 +69,12 @@ struct amdgpu_pte_update_params {
bool shadow;
 };
 
+/* Helper to disable partial resident texture feature from a fence callback */
+struct amdgpu_prt_cb {
+   struct amdgpu_device *adev;
+   struct fence_cb cb;
+};
+
 /**
  * amdgpu_vm_num_pde - return the number of page directory entries
  *
@@ -989,11 +995,8 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
goto error_free;
 
amdgpu_bo_fence(vm->page_directory, f, true);
-   if (fence) {
-   fence_put(*fence);
-   *fence = fence_get(f);
-   }
-   fence_put(f);
+   fence_put(*fence);
+   *fence = f;
return 0;
 
 error_free:
@@ -1177,6 +1180,61 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 }
 
 /**
+ * amdgpu_vm_update_prt_state - update the global PRT state
+ */
+static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
+{
+   unsigned long flags;
+   bool enable;
+
+   spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
+   enable = !!atomic_read(&adev->vm_manager.num_prt_mappings);
+   adev->gart.gart_funcs->set_prt(adev, enable);
+   spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
+}
+
+/**
+ * amdgpu_vm_prt - callback for updating the PRT status
+ */
+static void amdgpu_vm_prt_cb(struct fence *fence, struct fence_cb *_cb)
+{
+   struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
+
+   amdgpu_vm_update_prt_state(cb->adev);
+   kfree(cb);
+}
+
+/**
+ * amdgpu_vm_free_mapping - free a mapping
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requested vm
+ * @mapping: mapping to be freed
+ * @fence: fence of the unmap operation
+ *
+ * Free a mapping and make sure we decrease the PRT usage count if applicable.
+ */
+static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
+  struct amdgpu_vm *vm,
+  struct amdgpu_bo_va_mapping *mapping,
+  struct fence *fence)
+{
+   if ((mapping->flags & AMDGPU_PTE_PRT) &&
+   atomic_dec_return(&adev->vm_manager.num_prt_mappings) == 0) {
+   struct amdgpu_prt_cb *cb = kmalloc(sizeof(struct amdgpu_prt_cb),
+  GFP_KERNEL);
+
+   cb->adev = adev;
+   if (!fence || fence_add_callback(fence, &cb->cb,
+amdgpu_vm_prt_cb)) {
+   amdgpu_vm_update_prt_state(adev);
+   kfree(cb);
+   }
+   }
+   kfree(mapping);
+}
+
+/**
  * amdgpu_vm_clear_freed - clear freed BOs in the PT
  *
  * @adev: amdgpu_device pointer
@@ -1191,6 +1249,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
  struct amdgpu_vm *vm)
 {
struct amdgpu_bo_va_mapping *mapping;
+   struct fence *fence = NULL;
int r;
 
while (!list_empty(&vm->freed)) {
@@ -1199,12 +1258,15 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
list_del(&mapping->list);
 
r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
-  0, 0, NULL);
-   kfree(mapping);
-   if (r)
+  0, 0, &fence);
+   amdgpu_vm_free_mapping(adev, vm, mapping, fence);
+   if (r) {
+   fence_put(fence);
return r;
+   }
 
}
+   fence_put(fence);
return 0;
 
 }
@@ -1314,6 +

PRT support for amdgpu v3

Hi guys,

ok I finally found time to write an unit test for this and hammered out the 
last few bugs.

Seems to work fine on my Tonga now. Please note that this set is based on "fix 
race in GEM VA map IOCTL v2", without that patch you will run into a NULL 
pointer dereference during PRT mapping.

Going to send out the unit test in a minute.

Regards,
Christian.

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[PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v4

From: Junwei Zhang 

Till GFX8 we can only enable PRT support globally, but with the next hardware
generation we can do this on a per page basis.

Keep the interface consistent by adding PRT mappings and enable
support globally on current hardware when the first mapping is made.

v2: disable PRT support delayed and on all error paths
v3: PRT and other permissions are mutal exclusive,
PRT mappings don't need a BO.
v4: update PRT mappings durign CS as well, make va_flags 64bit

Signed-off-by: Junwei Zhang 
Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 16 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 62 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++
 include/uapi/drm/amdgpu_drm.h   |  2 ++
 5 files changed, 64 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 34a971a..99ca5e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -703,6 +703,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
 
 struct amdgpu_fpriv {
struct amdgpu_vmvm;
+   struct amdgpu_bo_va *prt_va;
struct mutexbo_list_lock;
struct idr  bo_list_handles;
struct amdgpu_ctx_mgr   ctx_mgr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 6e948e4..433254b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -758,10 +758,11 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser 
*parser, int error, bo
amdgpu_bo_unref(&parser->uf_entry.robj);
 }
 
-static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
-  struct amdgpu_vm *vm)
+static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 {
struct amdgpu_device *adev = p->adev;
+   struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
+   struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_bo_va *bo_va;
struct amdgpu_bo *bo;
int i, r;
@@ -778,6 +779,15 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p,
if (r)
return r;
 
+   r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
+   if (r)
+   return r;
+
+   r = amdgpu_sync_fence(adev, &p->job->sync,
+ fpriv->prt_va->last_pt_update);
+   if (r)
+   return r;
+
if (amdgpu_sriov_vf(adev)) {
struct fence *f;
bo_va = vm->csa_bo_va;
@@ -854,7 +864,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
if (p->job->vm) {
p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
 
-   r = amdgpu_bo_vm_update_pte(p, vm);
+   r = amdgpu_bo_vm_update_pte(p);
if (r)
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 1dc59aa..7f530f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -540,6 +540,12 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device 
*adev,
 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
  struct drm_file *filp)
 {
+   const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
+   AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
+   AMDGPU_VM_PAGE_EXECUTABLE;
+   const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
+   AMDGPU_VM_PAGE_PRT;
+
struct drm_amdgpu_gem_va *args = data;
struct drm_gem_object *gobj;
struct amdgpu_device *adev = dev->dev_private;
@@ -550,7 +556,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct list_head list;
-   uint32_t invalid_flags, va_flags = 0;
+   uint64_t va_flags = 0;
int r = 0;
 
if (!adev->vm_manager.enabled)
@@ -564,11 +570,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
}
 
-   invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
-   AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
-   if ((args->flags & invalid_flags)) {
-   dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
-   args->flags, invalid_flags);
+   if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
+   dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
+   args->flags);
return -EINVAL;
}
 
@@ -582,28 +586,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void 
*data,
return -E

答复: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

》As I wrote in the other thread as well calling amdgpu_resume() without proper 
suspend will just mess up a whole bunch of internal structures.

please name at least one, I'll check and see how to improve

and like I said, this approach is correct and verified by hang test, if 
internal structures messed up I don't think the test will easy pass. hw_init() 
just call resume per engine.

you can take a deep look into sriov_gpu_reset and judge later




发件人: Christian König 
发送时间: 2017年2月8日 18:49:57
收件人: Liu, Monk; amd-gfx@lists.freedesktop.org
主题: Re: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

+   /* now we are okay to resume SMC/CP/SDMA */
+   amdgpu_resume_late(adev);
As I wrote in the other thread as well calling amdgpu_resume() without proper 
suspend will just mess up a whole bunch of internal structures.

So a clear NAK on that approach. If you don't need the hw stop which 
amdgpu_suspend() does for SRIOV then please try to just use the hw_init() 
callback and not the resume() callback.

Regards,
Christian.

Am 07.02.2017 um 07:26 schrieb Liu, Monk:

patch 1-8 are some fixes for sriov gpu reset feature

patch 9 -20 are for sriov gpu reset


BR Monk


发件人: amd-gfx 

 代表 Monk Liu 
发送时间: 2017年2月7日 14:11:07
收件人: amd-gfx@lists.freedesktop.org
抄送: Liu, Monk
主题: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset

Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 158 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |   1 +
 2 files changed, 158 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e926f84..2b404ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1604,6 +1604,53 @@ int amdgpu_suspend(struct amdgpu_device *adev)
 return 0;
 }

+static int amdgpu_resume_early(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_GMC ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_IH)
+   r = adev->ip_blocks[i].version->funcs->resume(adev);
+
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
+static int amdgpu_resume_late(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_GMC ||
+   adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_IH )
+   continue;
+
+   r = adev->ip_blocks[i].version->funcs->resume(adev);
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
 static int amdgpu_resume(struct amdgpu_device *adev)
 {
 int i, r;
@@ -2343,6 +2390,115 @@ static int amdgpu_recover_vram_from_shadow(struct 
amdgpu_device *adev,
 }

 /**
+ * amdgpu_sriov_gpu_reset - reset the asic
+ *
+ * @adev: amdgpu device pointer
+ * @voluntary: if this reset is requested by guest.
+ * (true means by guest and false means by HYPERVISOR )
+ *
+ * Attempt the reset the GPU if it has hung (all asics).
+ * for SRIOV case.
+ * Returns 0 for success or an error on failure.
+ */
+int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
+{
+   int i, r = 0;
+   int resched;
+   struct amdgpu_bo *bo, *tmp;
+   struct amdgpu_ring *ring;
+   struct fence *fence = NULL, *next = NULL;
+
+   mutex_lock(&adev->virt.lock_reset);
+   atomic_inc(&adev->gpu_reset_counter);
+
+   /* block TTM */
+   resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
+
+   /* block scheduler */
+   for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+   ring = adev->rings[i];
+
+   if (!ring || !ring->sched.thread)
+   continue;
+
+   kthread_park(ring->sched.thread);
+

Re: [PATCH libdrm 2/2] amdgpu: add amdgpu_bo_va_op_raw


On 08.02.2017 13:39, Christian König wrote:

Am 08.02.2017 um 13:34 schrieb Nicolai Hähnle:

From: Nicolai Hähnle 

This variant allows the caller full control over flags and size, and
allows passing a NULL bo (for PRT support).

Cc: Christian König 
Cc: Bas Nieuwenhuizen 
Cc: Jerry Zhang 
Signed-off-by: Nicolai Hähnle 


Reviewed-by: Christian König .

You have a perfect timing, just wanted to ask if anybody has already
done the unit test or if I should tackle it?


I actually started hacking on radeonsi support while traveling and 
decided to push that towards a somewhat usable state, so a series for 
Mesa is going out now :)


A unit test in libdrm is still a good idea, but I haven't done that.

Cheers,
Nicolai



Regards,
Christian.


---
  amdgpu/amdgpu.h| 28 
  amdgpu/amdgpu_bo.c | 25 -
  2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 7b26a04..6b2ded8 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1186,6 +1186,34 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
  uint32_t ops);
/**
+ *  VA mapping/unmapping for a buffer object or PRT region.
+ *
+ * This is not a simple drop-in extension for amdgpu_bo_va_op;
instead, all
+ * parameters are treated "raw", i.e. size is not automatically
aligned, and
+ * all flags must be specified explicitly.
+ *
+ * \param  dev- \c [in] device handle
+ * \param  bo- \c [in] BO handle (may be NULL)
+ * \param  offset- \c [in] Start offset to map
+ * \param  size- \c [in] Size to map
+ * \param  addr- \c [in] Start virtual address.
+ * \param  flags- \c [in] Supported flags for mapping/unmapping
+ * \param  ops- \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+*/
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+amdgpu_bo_handle bo,
+uint64_t offset,
+uint64_t size,
+uint64_t addr,
+uint64_t flags,
+uint32_t ops);
+
+/**
   *  create semaphore
   *
   * \param   sem   - \c [out] semaphore handle
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d30fd1e..f725bfd 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -683,6 +683,23 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
   uint32_t ops)
  {
  amdgpu_device_handle dev = bo->dev;
+
+size = ALIGN(size, getpagesize());
+
+return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
+   AMDGPU_VM_PAGE_READABLE |
+   AMDGPU_VM_PAGE_WRITEABLE |
+   AMDGPU_VM_PAGE_EXECUTABLE, ops);
+}
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+amdgpu_bo_handle bo,
+uint64_t offset,
+uint64_t size,
+uint64_t addr,
+uint64_t flags,
+uint32_t ops)
+{
  struct drm_amdgpu_gem_va va;
  int r;
  @@ -690,14 +707,12 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
  return -EINVAL;
memset(&va, 0, sizeof(va));
-va.handle = bo->handle;
+va.handle = bo ? bo->handle : 0;
  va.operation = ops;
-va.flags = AMDGPU_VM_PAGE_READABLE |
-   AMDGPU_VM_PAGE_WRITEABLE |
-   AMDGPU_VM_PAGE_EXECUTABLE;
+va.flags = flags;
  va.va_address = addr;
  va.offset_in_bo = offset;
-va.map_size = ALIGN(size, getpagesize());
+va.map_size = size;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va,
sizeof(va));






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Re: [PATCH libdrm 2/2] amdgpu: add amdgpu_bo_va_op_raw


Am 08.02.2017 um 13:55 schrieb Nicolai Hähnle:

On 08.02.2017 13:44, Nicolai Hähnle wrote:

On 08.02.2017 13:39, Christian König wrote:

Am 08.02.2017 um 13:34 schrieb Nicolai Hähnle:

From: Nicolai Hähnle 

This variant allows the caller full control over flags and size, and
allows passing a NULL bo (for PRT support).

Cc: Christian König 
Cc: Bas Nieuwenhuizen 
Cc: Jerry Zhang 
Signed-off-by: Nicolai Hähnle 


Reviewed-by: Christian König .

You have a perfect timing, just wanted to ask if anybody has already
done the unit test or if I should tackle it?


I actually started hacking on radeonsi support while traveling and
decided to push that towards a somewhat usable state, so a series for
Mesa is going out now :)

A unit test in libdrm is still a good idea, but I haven't done that.


FWIW, I don't plan to write such a unit test, but I did send out a 
basic piglit test as well that works for me with the Mesa series -- 
minus the fact I still get GPU VM faults when I change the test to not 
commit pages.


Ok, I've hacked together a quick unit test to write a few dw to a PRT 
mapping using the SDMA.


Seems to cause a VM fault as well without a message that we turned PRT 
handling on.


Going to investigate, looks like another issue with the kernel patches 
to me.


Regards,
Christian.



Nicolai




Cheers,
Nicolai



Regards,
Christian.


---
  amdgpu/amdgpu.h| 28 
  amdgpu/amdgpu_bo.c | 25 -
  2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 7b26a04..6b2ded8 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1186,6 +1186,34 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
  uint32_t ops);
/**
+ *  VA mapping/unmapping for a buffer object or PRT region.
+ *
+ * This is not a simple drop-in extension for amdgpu_bo_va_op;
instead, all
+ * parameters are treated "raw", i.e. size is not automatically
aligned, and
+ * all flags must be specified explicitly.
+ *
+ * \param  dev- \c [in] device handle
+ * \param  bo- \c [in] BO handle (may be NULL)
+ * \param  offset- \c [in] Start offset to map
+ * \param  size- \c [in] Size to map
+ * \param  addr- \c [in] Start virtual address.
+ * \param  flags- \c [in] Supported flags for mapping/unmapping
+ * \param  ops- \c [in] AMDGPU_VA_OP_MAP or 
AMDGPU_VA_OP_UNMAP

+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+*/
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+amdgpu_bo_handle bo,
+uint64_t offset,
+uint64_t size,
+uint64_t addr,
+uint64_t flags,
+uint32_t ops);
+
+/**
   *  create semaphore
   *
   * \param   sem   - \c [out] semaphore handle
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d30fd1e..f725bfd 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -683,6 +683,23 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
   uint32_t ops)
  {
  amdgpu_device_handle dev = bo->dev;
+
+size = ALIGN(size, getpagesize());
+
+return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
+   AMDGPU_VM_PAGE_READABLE |
+   AMDGPU_VM_PAGE_WRITEABLE |
+   AMDGPU_VM_PAGE_EXECUTABLE, ops);
+}
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+amdgpu_bo_handle bo,
+uint64_t offset,
+uint64_t size,
+uint64_t addr,
+uint64_t flags,
+uint32_t ops)
+{
  struct drm_amdgpu_gem_va va;
  int r;
  @@ -690,14 +707,12 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
  return -EINVAL;
memset(&va, 0, sizeof(va));
-va.handle = bo->handle;
+va.handle = bo ? bo->handle : 0;
  va.operation = ops;
-va.flags = AMDGPU_VM_PAGE_READABLE |
-   AMDGPU_VM_PAGE_WRITEABLE |
-   AMDGPU_VM_PAGE_EXECUTABLE;
+va.flags = flags;
  va.va_address = addr;
  va.offset_in_bo = offset;
-va.map_size = ALIGN(size, getpagesize());
+va.map_size = size;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va,
sizeof(va));










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Re: [PATCH libdrm 2/2] amdgpu: add amdgpu_bo_va_op_raw


Am 08.02.2017 um 13:34 schrieb Nicolai Hähnle:

From: Nicolai Hähnle 

This variant allows the caller full control over flags and size, and
allows passing a NULL bo (for PRT support).

Cc: Christian König 
Cc: Bas Nieuwenhuizen 
Cc: Jerry Zhang 
Signed-off-by: Nicolai Hähnle 


Reviewed-by: Christian König .

You have a perfect timing, just wanted to ask if anybody has already 
done the unit test or if I should tackle it?


Regards,
Christian.


---
  amdgpu/amdgpu.h| 28 
  amdgpu/amdgpu_bo.c | 25 -
  2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 7b26a04..6b2ded8 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1186,6 +1186,34 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
uint32_t ops);
  
  /**

+ *  VA mapping/unmapping for a buffer object or PRT region.
+ *
+ * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all
+ * parameters are treated "raw", i.e. size is not automatically aligned, and
+ * all flags must be specified explicitly.
+ *
+ * \param  dev - \c [in] device handle
+ * \param  bo  - \c [in] BO handle (may be NULL)
+ * \param  offset  - \c [in] Start offset to map
+ * \param  size- \c [in] Size to map
+ * \param  addr- \c [in] Start virtual address.
+ * \param  flags   - \c [in] Supported flags for mapping/unmapping
+ * \param  ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+*/
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+   amdgpu_bo_handle bo,
+   uint64_t offset,
+   uint64_t size,
+   uint64_t addr,
+   uint64_t flags,
+   uint32_t ops);
+
+/**
   *  create semaphore
   *
   * \param   sem  - \c [out] semaphore handle
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d30fd1e..f725bfd 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -683,6 +683,23 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
 uint32_t ops)
  {
amdgpu_device_handle dev = bo->dev;
+
+   size = ALIGN(size, getpagesize());
+
+   return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
+  AMDGPU_VM_PAGE_READABLE |
+  AMDGPU_VM_PAGE_WRITEABLE |
+  AMDGPU_VM_PAGE_EXECUTABLE, ops);
+}
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+   amdgpu_bo_handle bo,
+   uint64_t offset,
+   uint64_t size,
+   uint64_t addr,
+   uint64_t flags,
+   uint32_t ops)
+{
struct drm_amdgpu_gem_va va;
int r;
  
@@ -690,14 +707,12 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,

return -EINVAL;
  
  	memset(&va, 0, sizeof(va));

-   va.handle = bo->handle;
+   va.handle = bo ? bo->handle : 0;
va.operation = ops;
-   va.flags = AMDGPU_VM_PAGE_READABLE |
-  AMDGPU_VM_PAGE_WRITEABLE |
-  AMDGPU_VM_PAGE_EXECUTABLE;
+   va.flags = flags;
va.va_address = addr;
va.offset_in_bo = offset;
-   va.map_size = ALIGN(size, getpagesize());
+   va.map_size = size;
  
  	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
  



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Re: [PATCH libdrm 2/2] amdgpu: add amdgpu_bo_va_op_raw


On 08.02.2017 13:44, Nicolai Hähnle wrote:

On 08.02.2017 13:39, Christian König wrote:

Am 08.02.2017 um 13:34 schrieb Nicolai Hähnle:

From: Nicolai Hähnle 

This variant allows the caller full control over flags and size, and
allows passing a NULL bo (for PRT support).

Cc: Christian König 
Cc: Bas Nieuwenhuizen 
Cc: Jerry Zhang 
Signed-off-by: Nicolai Hähnle 


Reviewed-by: Christian König .

You have a perfect timing, just wanted to ask if anybody has already
done the unit test or if I should tackle it?


I actually started hacking on radeonsi support while traveling and
decided to push that towards a somewhat usable state, so a series for
Mesa is going out now :)

A unit test in libdrm is still a good idea, but I haven't done that.


FWIW, I don't plan to write such a unit test, but I did send out a basic 
piglit test as well that works for me with the Mesa series -- minus the 
fact I still get GPU VM faults when I change the test to not commit pages.


Nicolai




Cheers,
Nicolai



Regards,
Christian.


---
  amdgpu/amdgpu.h| 28 
  amdgpu/amdgpu_bo.c | 25 -
  2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 7b26a04..6b2ded8 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1186,6 +1186,34 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
  uint32_t ops);
/**
+ *  VA mapping/unmapping for a buffer object or PRT region.
+ *
+ * This is not a simple drop-in extension for amdgpu_bo_va_op;
instead, all
+ * parameters are treated "raw", i.e. size is not automatically
aligned, and
+ * all flags must be specified explicitly.
+ *
+ * \param  dev- \c [in] device handle
+ * \param  bo- \c [in] BO handle (may be NULL)
+ * \param  offset- \c [in] Start offset to map
+ * \param  size- \c [in] Size to map
+ * \param  addr- \c [in] Start virtual address.
+ * \param  flags- \c [in] Supported flags for mapping/unmapping
+ * \param  ops- \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+*/
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+amdgpu_bo_handle bo,
+uint64_t offset,
+uint64_t size,
+uint64_t addr,
+uint64_t flags,
+uint32_t ops);
+
+/**
   *  create semaphore
   *
   * \param   sem   - \c [out] semaphore handle
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d30fd1e..f725bfd 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -683,6 +683,23 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
   uint32_t ops)
  {
  amdgpu_device_handle dev = bo->dev;
+
+size = ALIGN(size, getpagesize());
+
+return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
+   AMDGPU_VM_PAGE_READABLE |
+   AMDGPU_VM_PAGE_WRITEABLE |
+   AMDGPU_VM_PAGE_EXECUTABLE, ops);
+}
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+amdgpu_bo_handle bo,
+uint64_t offset,
+uint64_t size,
+uint64_t addr,
+uint64_t flags,
+uint32_t ops)
+{
  struct drm_amdgpu_gem_va va;
  int r;
  @@ -690,14 +707,12 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
  return -EINVAL;
memset(&va, 0, sizeof(va));
-va.handle = bo->handle;
+va.handle = bo ? bo->handle : 0;
  va.operation = ops;
-va.flags = AMDGPU_VM_PAGE_READABLE |
-   AMDGPU_VM_PAGE_WRITEABLE |
-   AMDGPU_VM_PAGE_EXECUTABLE;
+va.flags = flags;
  va.va_address = addr;
  va.offset_in_bo = offset;
-va.map_size = ALIGN(size, getpagesize());
+va.map_size = size;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va,
sizeof(va));








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[PATCH libdrm 1/2] amdgpu: add AMDGPU_VM_PAGE_PRT

From: Nicolai Hähnle 

This is a new kernel interface.

Signed-off-by: Nicolai Hähnle 
---
 include/drm/amdgpu_drm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d8f2497..7012515 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -329,6 +329,8 @@ struct drm_amdgpu_gem_op {
 #define AMDGPU_VM_PAGE_WRITEABLE   (1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE  (1 << 3)
+/* partially resident texture */
+#define AMDGPU_VM_PAGE_PRT (1 << 4)
 
 struct drm_amdgpu_gem_va {
/** GEM object handle */
-- 
2.9.3

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[PATCH libdrm 2/2] amdgpu: add amdgpu_bo_va_op_raw

From: Nicolai Hähnle 

This variant allows the caller full control over flags and size, and
allows passing a NULL bo (for PRT support).

Cc: Christian König 
Cc: Bas Nieuwenhuizen 
Cc: Jerry Zhang 
Signed-off-by: Nicolai Hähnle 
---
 amdgpu/amdgpu.h| 28 
 amdgpu/amdgpu_bo.c | 25 -
 2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 7b26a04..6b2ded8 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1186,6 +1186,34 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
uint32_t ops);
 
 /**
+ *  VA mapping/unmapping for a buffer object or PRT region.
+ *
+ * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all
+ * parameters are treated "raw", i.e. size is not automatically aligned, and
+ * all flags must be specified explicitly.
+ *
+ * \param  dev - \c [in] device handle
+ * \param  bo  - \c [in] BO handle (may be NULL)
+ * \param  offset  - \c [in] Start offset to map
+ * \param  size- \c [in] Size to map
+ * \param  addr- \c [in] Start virtual address.
+ * \param  flags   - \c [in] Supported flags for mapping/unmapping
+ * \param  ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+*/
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+   amdgpu_bo_handle bo,
+   uint64_t offset,
+   uint64_t size,
+   uint64_t addr,
+   uint64_t flags,
+   uint32_t ops);
+
+/**
  *  create semaphore
  *
  * \param   sem   - \c [out] semaphore handle
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d30fd1e..f725bfd 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -683,6 +683,23 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
 uint32_t ops)
 {
amdgpu_device_handle dev = bo->dev;
+
+   size = ALIGN(size, getpagesize());
+
+   return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
+  AMDGPU_VM_PAGE_READABLE |
+  AMDGPU_VM_PAGE_WRITEABLE |
+  AMDGPU_VM_PAGE_EXECUTABLE, ops);
+}
+
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+   amdgpu_bo_handle bo,
+   uint64_t offset,
+   uint64_t size,
+   uint64_t addr,
+   uint64_t flags,
+   uint32_t ops)
+{
struct drm_amdgpu_gem_va va;
int r;
 
@@ -690,14 +707,12 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
return -EINVAL;
 
memset(&va, 0, sizeof(va));
-   va.handle = bo->handle;
+   va.handle = bo ? bo->handle : 0;
va.operation = ops;
-   va.flags = AMDGPU_VM_PAGE_READABLE |
-  AMDGPU_VM_PAGE_WRITEABLE |
-  AMDGPU_VM_PAGE_EXECUTABLE;
+   va.flags = flags;
va.va_address = addr;
va.offset_in_bo = offset;
-   va.map_size = ALIGN(size, getpagesize());
+   va.map_size = size;
 
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
 
-- 
2.9.3

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Re: [PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error


Am 08.02.2017 um 10:41 schrieb Monk Liu:

ib_pool init should prior to fbdev_init, otherwise
there will be error from amdgpu_sa_bo_new
(amdgpu_sa.c:323)

fbdev_init will call ttm_validate which further call
amdgpu_sa_bo_new.

Change-Id: I3a969570d443f61a44f67b0d76b3871ca5c3ea81
Signed-off-by: Monk Liu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index afcae15..4169bb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1918,14 +1918,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* Get a log2 for easy divisions. */
adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
  
-	amdgpu_fbdev_init(adev);

-
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
goto failed;
}
  
+	amdgpu_fbdev_init(adev);

+


As noted internally as well, please more that one more further down 
behind the call to amdgpu_ib_ring_tests().


With that changed the patch is Reviewed-by: Christian König 
.


Regards,
Christian.


r = amdgpu_ib_ring_tests(adev);
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);



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Re: SPAM //答复: [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset


+   /* now we are okay to resume SMC/CP/SDMA */
+   amdgpu_resume_late(adev);
As I wrote in the other thread as well calling amdgpu_resume() without 
proper suspend will just mess up a whole bunch of internal structures.


So a clear NAK on that approach. If you don't need the hw stop which 
amdgpu_suspend() does for SRIOV then please try to just use the 
hw_init() callback and not the resume() callback.


Regards,
Christian.

Am 07.02.2017 um 07:26 schrieb Liu, Monk:


patch 1-8 are some fixes for sriov gpu reset feature

patch 9 -20 are for sriov gpu reset


BR Monk


*发件人:* amd-gfx  代表 Monk Liu 


*发送时间:* 2017年2月7日 14:11:07
*收件人:* amd-gfx@lists.freedesktop.org
*抄送:* Liu, Monk
*主题:* [PATCH 09/20] drm/amdgpu:implement SRIOV gpu_reset
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 158 
-

 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |   1 +
 2 files changed, 158 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index e926f84..2b404ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1604,6 +1604,53 @@ int amdgpu_suspend(struct amdgpu_device *adev)
 return 0;
 }

+static int amdgpu_resume_early(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||

+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
+   r = 
adev->ip_blocks[i].version->funcs->resume(adev);

+
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
+static int amdgpu_resume_late(struct amdgpu_device *adev)
+{
+   int i, r;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+
+   if (adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_COMMON ||

+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
+   continue;
+
+   r = adev->ip_blocks[i].version->funcs->resume(adev);
+   if (r) {
+   DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+
+   return 0;
+}
+
 static int amdgpu_resume(struct amdgpu_device *adev)
 {
 int i, r;
@@ -2343,6 +2390,115 @@ static int 
amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,

 }

 /**
+ * amdgpu_sriov_gpu_reset - reset the asic
+ *
+ * @adev: amdgpu device pointer
+ * @voluntary: if this reset is requested by guest.
+ * (true means by guest and false means by HYPERVISOR )
+ *
+ * Attempt the reset the GPU if it has hung (all asics).
+ * for SRIOV case.
+ * Returns 0 for success or an error on failure.
+ */
+int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
+{
+   int i, r = 0;
+   int resched;
+   struct amdgpu_bo *bo, *tmp;
+   struct amdgpu_ring *ring;
+   struct fence *fence = NULL, *next = NULL;
+
+   mutex_lock(&adev->virt.lock_reset);
+   atomic_inc(&adev->gpu_reset_counter);
+
+   /* block TTM */
+   resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
+
+   /* block scheduler */
+   for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+   ring = adev->rings[i];
+
+   if (!ring || !ring->sched.thread)
+   continue;
+
+   kthread_park(ring->sched.thread);
+   amd_sched_hw_job_reset(&ring->sched);
+   }
+
+   /* after all hw jobs are reset, hw fence is meaningless, so 
force_completion */

+   amdgpu_fence_driver_force_completion(adev);
+
+   /* request to take full control of GPU before 
re-initialization  */

+   if (voluntary)
+   amdgpu_virt_reset_gpu(adev);
+   else
+   amdgpu_virt_request_full_gpu(adev, true);
+
+
+   /* Resume IP prior to SMC */
+   amdgpu_resume_early(adev);
+
+   /* we need recover gart prior to run SMC/CP/SDMA resume */
+   amdgpu_ttm_recover_gart(adev);
+
+   /* now we are okay to resume SMC/CP/SDMA */
+   amdgpu_resume_late(adev);




+
+   amdgpu_irq_gpu_reset_resume_helper(adev);
+
+   if (amdgpu_ib_ring_tests(adev))
+   dev_err(adev->dev, "[GPU_RESET] ib ring test failed 
(%d).\n", r);

+
+   /* rellease full contr

Re: [PATCH] drm/amdgpu: clear framebuffer with GPU


Am 08.02.2017 um 05:01 schrieb Edward O'Callaghan:


On 02/08/2017 12:24 PM, Pixel Ding wrote:

CPU is not efficient to do this job. There's a failure caused by this
is that handshaking gets timeout of SRIOV virtual function.

Can you fixup the commit message a little but otherwise,
Reviewed-by: Edward O'Callaghan 


Monk figured out that you need to move the fb init after the IB init 
during device startup.


Otherwise setting this flag here will cause a NULL pointer dereference 
in the SA code.


Assuming Monks patch lands first during the upstream push this one is 
Reviewed-by: Christian König  as well.


Regards,
Christian.




Signed-off-by: Pixel Ding 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 1e735c4..2867f55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -148,7 +148,8 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
ret = amdgpu_gem_object_create(adev, aligned_size, 0,
   AMDGPU_GEM_DOMAIN_VRAM,
   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
+  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+  AMDGPU_GEM_CREATE_VRAM_CLEARED,
   true, &gobj);
if (ret) {
printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
@@ -242,8 +243,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
/* setup helper */
rfbdev->helper.fb = fb;
  
-	memset_io(abo->kptr, 0x0, amdgpu_bo_size(abo));

-
strcpy(info->fix.id, "amdgpudrmfb");
  
  	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);




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[PATCH] drm/amdgpu:fix amdgpu_sa_bo_new error

ib_pool init should prior to fbdev_init, otherwise
there will be error from amdgpu_sa_bo_new
(amdgpu_sa.c:323)

fbdev_init will call ttm_validate which further call
amdgpu_sa_bo_new.

Change-Id: I3a969570d443f61a44f67b0d76b3871ca5c3ea81
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index afcae15..4169bb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1918,14 +1918,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* Get a log2 for easy divisions. */
adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
 
-   amdgpu_fbdev_init(adev);
-
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
goto failed;
}
 
+   amdgpu_fbdev_init(adev);
+
r = amdgpu_ib_ring_tests(adev);
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
-- 
2.7.4

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Re: [PATCH 01/11] drm/amdgpu:use MACRO like other places

On 08/02/17 06:26 PM, Monk Liu wrote:
> 
> + WREG32(temp + i,
> + unique_indices[i] & 0x3);
> + WREG32(data + i,
> + unique_indices[i] >> 20);

Use a single line in both cases (or fix the indentation of the second
lines to align with the opening parens).


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[PATCH 10/11] drm/amdgpu:use clear_ring to clr RB

In resume routine, we need clr RB prior to the
ring test of engine, otherwise some engine hang
duplicated during GPU reset.

Change-Id: Ie28f5aa677074f922e4a1a2eeeb7fe06461d9bdb
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 7bacf3c..37d8422 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -230,7 +230,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
dev_err(adev->dev, "(%d) ring create failed\n", r);
return r;
}
-   memset((void *)ring->ring, 0, ring->ring_size);
+   amdgpu_ring_clear_ring(ring);
}
ring->ptr_mask = (ring->ring_size / 4) - 1;
ring->max_dw = max_dw;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b0612d1..6584173 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4509,6 +4509,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device 
*adev)
}
 
/* start the ring */
+   amdgpu_ring_clear_ring(ring);
gfx_v8_0_cp_gfx_start(adev);
ring->ready = true;
r = amdgpu_ring_test_ring(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 9394ca6..d5206f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -615,6 +615,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
+   amdgpu_ring_clear_ring(ring);
wb_offset = (ring->rptr_offs * 4);
 
mutex_lock(&adev->srbm_mutex);
-- 
2.7.4

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[PATCH 04/11] drm/amdgpu:no kiq for mailbox registers access

Use no kiq version reg access due to:
1) better performance
2) INTR context consideration (some routine in mailbox is in
   INTR context e.g.xgpu_vi_mailbox_rcv_irq)

Change-Id: I383d7ce858a136d7b112180f86e3d632d37b4d1c
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index b8edfe5..7c7420f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -321,12 +321,12 @@ static void xgpu_vi_mailbox_send_ack(struct amdgpu_device 
*adev)
int timeout = VI_MAILBOX_TIMEDOUT;
u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
 
-   reg = RREG32(mmMAILBOX_CONTROL);
+   reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
-   WREG32(mmMAILBOX_CONTROL, reg);
+   WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
 
/*Wait for RCV_MSG_VALID to be 0*/
-   reg = RREG32(mmMAILBOX_CONTROL);
+   reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
while (reg & mask) {
if (timeout <= 0) {
pr_err("RCV_MSG_VALID is not cleared\n");
@@ -335,7 +335,7 @@ static void xgpu_vi_mailbox_send_ack(struct amdgpu_device 
*adev)
mdelay(1);
timeout -=1;
 
-   reg = RREG32(mmMAILBOX_CONTROL);
+   reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
}
 }
 
@@ -343,10 +343,10 @@ static void xgpu_vi_mailbox_set_valid(struct 
amdgpu_device *adev, bool val)
 {
u32 reg;
 
-   reg = RREG32(mmMAILBOX_CONTROL);
+   reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,
TRN_MSG_VALID, val ? 1 : 0);
-   WREG32(mmMAILBOX_CONTROL, reg);
+   WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
 }
 
 static void xgpu_vi_mailbox_trans_msg(struct amdgpu_device *adev,
@@ -354,10 +354,10 @@ static void xgpu_vi_mailbox_trans_msg(struct 
amdgpu_device *adev,
 {
u32 reg;
 
-   reg = RREG32(mmMAILBOX_MSGBUF_TRN_DW0);
+   reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
MSGBUF_DATA, event);
-   WREG32(mmMAILBOX_MSGBUF_TRN_DW0, reg);
+   WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
 
xgpu_vi_mailbox_set_valid(adev, true);
 }
@@ -368,11 +368,11 @@ static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device 
*adev,
u32 reg;
u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
 
-   reg = RREG32(mmMAILBOX_CONTROL);
+   reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
if (!(reg & mask))
return -ENOENT;
 
-   reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0);
+   reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
if (reg != event)
return -ENOENT;
 
@@ -388,7 +388,7 @@ static int xgpu_vi_poll_ack(struct amdgpu_device *adev)
u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);
u32 reg;
 
-   reg = RREG32(mmMAILBOX_CONTROL);
+   reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
while (!(reg & mask)) {
if (timeout <= 0) {
pr_err("Doesn't get ack from pf.\n");
@@ -398,7 +398,7 @@ static int xgpu_vi_poll_ack(struct amdgpu_device *adev)
msleep(1);
timeout -= 1;
 
-   reg = RREG32(mmMAILBOX_CONTROL);
+   reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
}
 
return r;
@@ -490,11 +490,11 @@ static int xgpu_vi_set_mailbox_ack_irq(struct 
amdgpu_device *adev,
   unsigned type,
   enum amdgpu_interrupt_state state)
 {
-   u32 tmp = RREG32(mmMAILBOX_INT_CNTL);
+   u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
 
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,
(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
-   WREG32(mmMAILBOX_INT_CNTL, tmp);
+   WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
 
return 0;
 }
@@ -519,11 +519,11 @@ static int xgpu_vi_set_mailbox_rcv_irq(struct 
amdgpu_device *adev,
   unsigned type,
   enum amdgpu_interrupt_state state)
 {
-   u32 tmp = RREG32(mmMAILBOX_INT_CNTL);
+   u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
 
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,
(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
-   WREG32(mmMAILBOX_INT_CNTL, tmp);
+   WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
 
return 0;
 }
-- 
2.7.4

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[PATCH 07/11] drm/amdgpu:new field in_resete introduced for gfx

use it to seperate driver load and gpu reset/resume
because gfx IP need different approach for different
hw_init trigger source

Change-Id: I991e0da52ccd197716d279bf9014de46d39acfea
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 74bffca8..acd9970 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -901,6 +901,7 @@ struct amdgpu_gfx {
/* reset mask */
uint32_tgrbm_soft_reset;
uint32_tsrbm_soft_reset;
+   boolin_reset;
 };
 
 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-- 
2.7.4

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[PATCH 02/11] drm/amdgpu:impl RREG32 no kiq version

some registers are PF & VF copy, and we can safely use
mmio method to access them.

and sometime we are forbid to use kiq to access registers
for example in INTR context.

we need a MACRO that always disable KIQ for regs accessing

Change-Id: Ie6dc323dc86829a4a6ceb7073c269b106b534c4a
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 21 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++--
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 402a895..74bffca8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1510,9 +1510,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev);
 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
 
 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
-   bool always_indirect);
+   uint32_t acc_flags);
 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
-   bool always_indirect);
+   uint32_t acc_flags);
 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
 
@@ -1523,11 +1523,18 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device 
*adev);
 /*
  * Registers read & write functions.
  */
-#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
-#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
-#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", 
amdgpu_mm_rreg(adev, (reg), false))
-#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
-#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
+
+#define AMDGPU_REGS_IDX   (1<<0)
+#define AMDGPU_REGS_NO_KIQ(1<<1)
+
+#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
+#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 
AMDGPU_REGS_NO_KIQ)
+
+#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
+#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
+#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", 
amdgpu_mm_rreg(adev, (reg), 0))
+#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
+#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3534089..5215fc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -91,16 +91,16 @@ bool amdgpu_device_is_px(struct drm_device *dev)
  * MMIO register access helper functions.
  */
 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
-   bool always_indirect)
+   uint32_t acc_flags)
 {
uint32_t ret;
 
-   if (amdgpu_sriov_runtime(adev)) {
+   if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
BUG_ON(in_interrupt());
return amdgpu_virt_kiq_rreg(adev, reg);
}
 
-   if ((reg * 4) < adev->rmmio_size && !always_indirect)
+   if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
else {
unsigned long flags;
@@ -115,16 +115,16 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, 
uint32_t reg,
 }
 
 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
-   bool always_indirect)
+   uint32_t acc_flags)
 {
trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 
-   if (amdgpu_sriov_runtime(adev)) {
+   if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
BUG_ON(in_interrupt());
return amdgpu_virt_kiq_wreg(adev, reg, v);
}
 
-   if ((reg * 4) < adev->rmmio_size && !always_indirect)
+   if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
else {
unsigned long flags;
-- 
2.7.4

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[PATCH 09/11] drm/amdgpu:imple ring clear

we can use it clear ring buffer instead of fullfill
0, which is not correct for engine

Change-Id: I89dcd7b6c4de558f9b2860209a2739c7d4af262d
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 0e57b04..3fd4ce8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -186,5 +186,12 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
 unsigned ring_size, struct amdgpu_irq_src *irq_src,
 unsigned irq_type);
 void amdgpu_ring_fini(struct amdgpu_ring *ring);
+static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
+{
+   int i = 0;
+   while (i <= ring->ptr_mask)
+   ring->ring[i++] = ring->funcs->nop;
+
+}
 
 #endif
-- 
2.7.4

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[PATCH 03/11] drm/amdgpu:Refine handshake of mailbox

From: Ken Xue 

Change-Id: If3a7d05824847234759b86563e8052949e171972
Signed-off-by: Ken Xue 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index d2622b6..b8edfe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device 
*adev)
 static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
 {
u32 reg;
+   int timeout = VI_MAILBOX_TIMEDOUT;
+   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
 
reg = RREG32(mmMAILBOX_CONTROL);
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
WREG32(mmMAILBOX_CONTROL, reg);
+
+   /*Wait for RCV_MSG_VALID to be 0*/
+   reg = RREG32(mmMAILBOX_CONTROL);
+   while (reg & mask) {
+   if (timeout <= 0) {
+   pr_err("RCV_MSG_VALID is not cleared\n");
+   break;
+   }
+   mdelay(1);
+   timeout -=1;
+
+   reg = RREG32(mmMAILBOX_CONTROL);
+   }
 }
 
 static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
@@ -351,6 +366,11 @@ static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device 
*adev,
   enum idh_event event)
 {
u32 reg;
+   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
+
+   reg = RREG32(mmMAILBOX_CONTROL);
+   if (!(reg & mask))
+   return -ENOENT;
 
reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0);
if (reg != event)
@@ -419,7 +439,9 @@ static int xgpu_vi_send_access_requests(struct 
amdgpu_device *adev,
xgpu_vi_mailbox_set_valid(adev, false);
 
/* start to check msg if request is idh_req_gpu_init_access */
-   if (request == IDH_REQ_GPU_INIT_ACCESS) {
+   if (request == IDH_REQ_GPU_INIT_ACCESS ||
+   request == IDH_REQ_GPU_FINI_ACCESS ||
+   request == IDH_REQ_GPU_RESET_ACCESS) {
r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
if (r)
return r;
-- 
2.7.4

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[PATCH 11/11] drm/amdgpu:fix kiq_resume routine (V2)

v2:
use in_rest to fix compute ring test failure issue
which occured after FLR/gpu_reset.

we need backup a clean status of MQD which was created in drv load
stage, and use it in resume stage, otherwise KCQ and KIQ all may
faild in ring/ib test.

Change-Id: I41be940454a6638e9a8a05f096601eaa1fbebaab
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 44 ++
 2 files changed, 35 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5215fc5..afcae15 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2410,6 +2410,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, 
bool voluntary)
 
mutex_lock(&adev->virt.lock_reset);
atomic_inc(&adev->gpu_reset_counter);
+   adev->gfx.in_reset = true;
 
/* block TTM */
resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
@@ -2494,6 +2495,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, 
bool voluntary)
dev_info(adev->dev, "GPU reset failed\n");
}
 
+   adev->gfx.in_reset = false;
mutex_unlock(&adev->virt.lock_reset);
return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6584173..1822420 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4877,24 +4877,46 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring 
*ring,
struct amdgpu_kiq *kiq = &adev->gfx.kiq;
uint64_t eop_gpu_addr;
bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
+   int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
 
if (is_kiq) {
eop_gpu_addr = kiq->eop_gpu_addr;
gfx_v8_0_kiq_setting(&kiq->ring);
-   } else
+   } else {
eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
ring->queue * MEC_HPD_SIZE;
+   mqd_idx = ring - &adev->gfx.compute_ring[0];
+   }
 
-   mutex_lock(&adev->srbm_mutex);
-   vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+   if (!adev->gfx.in_reset) {
+   memset((void *)mqd, 0, sizeof(*mqd));
+   mutex_lock(&adev->srbm_mutex);
+   vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+   gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr, ring);
+   if (is_kiq)
+   gfx_v8_0_kiq_init_register(adev, mqd, ring);
+   vi_srbm_select(adev, 0, 0, 0, 0);
+   mutex_unlock(&adev->srbm_mutex);
 
-   gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr, ring);
+   if (adev->gfx.mec.mqd_backup[mqd_idx])
+   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
+   } else { /* for GPU_RESET case */
+   /* reset MQD to a clean status */
+   if (adev->gfx.mec.mqd_backup[mqd_idx])
+   memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(*mqd));
 
-   if (is_kiq)
-   gfx_v8_0_kiq_init_register(adev, mqd, ring);
-
-   vi_srbm_select(adev, 0, 0, 0, 0);
-   mutex_unlock(&adev->srbm_mutex);
+   /* reset ring buffer */
+   ring->wptr = 0;
+   amdgpu_ring_clear_ring(ring);
+
+   if (is_kiq) {
+   mutex_lock(&adev->srbm_mutex);
+   vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+   gfx_v8_0_kiq_init_register(adev, mqd, ring);
+   vi_srbm_select(adev, 0, 0, 0, 0);
+   mutex_unlock(&adev->srbm_mutex);
+   }
+   }
 
if (is_kiq)
gfx_v8_0_kiq_enable(ring);
@@ -4913,9 +4935,9 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
 
ring = &adev->gfx.kiq.ring;
if (!amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr)) {
-   memset((void *)ring->mqd_ptr, 0, sizeof(struct vi_mqd));
r = gfx_v8_0_kiq_init_queue(ring, ring->mqd_ptr, 
ring->mqd_gpu_addr);
amdgpu_bo_kunmap(ring->mqd_obj);
+   ring->mqd_ptr = NULL;
if (r)
return r;
} else {
@@ -4925,9 +4947,9 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
if (!amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr)) {
-   memset((void *)ring->mqd_ptr, 0, sizeof(struct vi_mqd));
r = gfx_v8_0_kiq_init_queue(ring, ring->mqd_ptr, 
ring->mqd_gpu_addr);
amdgpu_bo_kunmap(ring->mqd_obj);
+   ring->mqd_ptr = NULL;

[PATCH 08/11] drm/amdgpu:alloc mqd backup

this is required for restoring the mqds after GPU reset.

Change-Id: I84f821faa657a5d942c33d30f206eb66b579c2f8
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index acd9970..73086d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -781,6 +781,7 @@ struct amdgpu_mec {
u32 num_pipe;
u32 num_mec;
u32 num_queue;
+   struct vi_mqd   *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
 };
 
 struct amdgpu_kiq {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8f545992..b0612d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7309,6 +7309,11 @@ static int gfx_v8_0_compute_mqd_soft_init(struct 
amdgpu_device *adev)
dev_warn(adev->dev, "failed to create ring mqd ob 
(%d)", r);
return r;
}
+
+   /* prepare MQD backup */
+   adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = 
kmalloc(sizeof(struct vi_mqd), GFP_KERNEL);
+   if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
+   dev_warn(adev->dev, "no memory to create MQD 
backup for ring %s\n", ring->name);
}
 
/* create MQD for each KCQ */
@@ -7323,6 +7328,11 @@ static int gfx_v8_0_compute_mqd_soft_init(struct 
amdgpu_device *adev)
dev_warn(adev->dev, "failed to create ring mqd 
ob (%d)", r);
return r;
}
+
+   /* prepare MQD backup */
+   adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct 
vi_mqd), GFP_KERNEL);
+   if (!adev->gfx.mec.mqd_backup[i])
+   dev_warn(adev->dev, "no memory to create MQD 
backup for ring %s\n", ring->name);
}
}
 
-- 
2.7.4

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[PATCH 06/11] drm/amdgpu:RUNTIME flag should clr later

this flag will get cleared by request gpu access

Change-Id: Ie484bb0141420055370e019dcd8c110fb34f8a1b
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 5f156d3..98cbcd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -505,9 +505,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct 
*work)
struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, 
virt);
 
/* wait until RCV_MSG become 3 */
-   if (!xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL))
-   adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
-   else {
+   if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
pr_err("failed to recieve FLR_CMPL\n");
return;
}
-- 
2.7.4

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[PATCH 01/11] drm/amdgpu:use MACRO like other places

Change-Id: Ica8f86577a50d817119de4b4fb95068dc72652a9
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6734e55..8f545992 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4068,10 +4068,10 @@ static int gfx_v8_0_init_save_restore_list(struct 
amdgpu_device *adev)
data = mmRLC_SRM_INDEX_CNTL_DATA_0;
for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
if (unique_indices[i] != 0) {
-   amdgpu_mm_wreg(adev, temp + i,
-   unique_indices[i] & 0x3, false);
-   amdgpu_mm_wreg(adev, data + i,
-   unique_indices[i] >> 20, false);
+   WREG32(temp + i,
+   unique_indices[i] & 0x3);
+   WREG32(data + i,
+   unique_indices[i] >> 20);
}
}
kfree(register_list_format);
-- 
2.7.4

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[PATCH 05/11] drm/amdgpu:use work instead of delay-work