Re: [PATCH 17/35] drivers/gpu: Convert remaining uses of pr_warning to pr_warn

2017-02-17 Thread Edward O'Callaghan 


On 02/18/2017 01:22 AM, Christian König wrote:
> Am 17.02.2017 um 08:11 schrieb Joe Perches:
>> To enable eventual removal of pr_warning
>>
>> This makes pr_warn use consistent for drivers/gpu
>>
>> Prior to this patch, there were 15 uses of pr_warning and
>> 20 uses of pr_warn in drivers/gpu
>>
>> Signed-off-by: Joe Perches 
> 
> Acked-by: Christian König .

Reviewed-by: Edward O'Callaghan 

> 
>> ---
>>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c |  2 +-
>>   drivers/gpu/drm/amd/powerplay/inc/pp_debug.h |  2 +-
>>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c  |  4 ++--
>>   drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c   | 14
>> +++---
>>   drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c |  4 ++--
>>   drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c |  4 ++--
>>   6 files changed, 15 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index b1de9e8ccdbc..83266408634e 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -1535,7 +1535,7 @@ static int smu7_get_evv_voltages(struct pp_hwmgr
>> *hwmgr)
>>   if (vddc >= 2000 || vddc == 0)
>>   return -EINVAL;
>>   } else {
>> -pr_warning("failed to retrieving EVV voltage!\n");
>> +pr_warn("failed to retrieving EVV voltage!\n");
>>   continue;
>>   }
>>   diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> index 072880130cfb..f3f9ebb631a5 100644
>> --- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> @@ -37,7 +37,7 @@
>>   #define PP_ASSERT_WITH_CODE(cond, msg, code)\
>>   do {\
>>   if (!(cond)) {\
>> -pr_warning("%s\n", msg);\
>> +pr_warn("%s\n", msg);\
>>   code;\
>>   }\
>>   } while (0)
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> index 0f7a77b7312e..5450f5ef8e89 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> @@ -2131,7 +2131,7 @@ uint32_t fiji_get_offsetof(uint32_t type,
>> uint32_t member)
>>   return offsetof(SMU73_Discrete_DpmTable,
>> LowSclkInterruptThreshold);
>>   }
>>   }
>> -pr_warning("can't get the offset of type %x member %x\n", type,
>> member);
>> +pr_warn("can't get the offset of type %x member %x\n", type,
>> member);
>>   return 0;
>>   }
>>   @@ -2156,7 +2156,7 @@ uint32_t fiji_get_mac_definition(uint32_t value)
>>   return SMU73_MAX_LEVELS_MVDD;
>>   }
>>   -pr_warning("can't get the mac of %x\n", value);
>> +pr_warn("can't get the mac of %x\n", value);
>>   return 0;
>>   }
>>   diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> index ad82161df831..51adf04ab4b3 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> @@ -122,7 +122,7 @@ static void
>> iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
>>   break;
>>   default:
>>   smu_data->power_tune_defaults = _iceland;
>> -pr_warning("Unknown V.I. Device ID.\n");
>> +pr_warn("Unknown V.I. Device ID.\n");
>>   break;
>>   }
>>   return;
>> @@ -378,7 +378,7 @@ static int
>> iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
>>   return -EINVAL);
>> if (NULL == hwmgr->dyn_state.cac_leakage_table) {
>> -pr_warning("CAC Leakage Table does not exist, using vddc.\n");
>> +pr_warn("CAC Leakage Table does not exist, using vddc.\n");
>>   return 0;
>>   }
>>   @@ -394,7 +394,7 @@ static int
>> iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
>>   *lo =
>> hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc *
>> VOLTAGE_SCALE;
>>   *hi =
>> (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage *
>> VOLTAGE_SCALE);
>>   } else {
>> -pr_warning("Index from SCLK/VDDC Dependency Table
>> exceeds the CAC Leakage Table index, using maximum index from CAC
>> table.\n");
>> +pr_warn("Index from SCLK/VDDC Dependency Table
>> exceeds the CAC Leakage Table index, using maximum index from CAC
>> table.\n");
>>   *lo =
>> hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count
>> - 1].Vddc * VOLTAGE_SCALE;
>>

Re: [PATCH] amdgpu/powerplay: Fixup printk() usage in pp_debug.h

2017-02-17 Thread Edward O'Callaghan 
disregard this, sorry for the noise.

On 02/16/2017 07:42 PM, Edward O'Callaghan wrote:
> We should properly prefix which kernel module this spewed
> from in dmesg for consistency to the user.
> 
> Signed-off-by: Edward O'Callaghan 
> ---
>  drivers/gpu/drm/amd/powerplay/inc/pp_debug.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h 
> b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
> index bfdbec1..e4fad15 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
> @@ -28,12 +28,12 @@
>  #include 
>  #include 
>  
> -#define PP_ASSERT_WITH_CODE(cond, msg, code) \
> - do {\
> - if (!(cond)) {  \
> - printk("%s\n", msg);\
> - code;   \
> - }   \
> +#define PP_ASSERT_WITH_CODE(cond, msg, code) \
> + do {\
> + if (!(cond)) {  \
> + pr_error("amdgpu: %s\n", msg);  \
> + code;   \
> + }   \
>   } while (0)
>  
>  
> 
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Re: [PATCH umr] Add SENSOR for SI/CIK/KV systems.

2017-02-17 Thread Edward O'Callaghan 
Reviewed-by: Edward O'Callaghan 

On 02/18/2017 06:26 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis 
> ---
>  src/app/top.c | 30 ++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/src/app/top.c b/src/app/top.c
> index 92ab8ab854af..c97a0c9d93ab 100644
> --- a/src/app/top.c
> +++ b/src/app/top.c
> @@ -231,6 +231,27 @@ static struct umr_bitfield stat_vi_sensor_bits[] = {
>   { NULL, 0, 0, NULL },
>  };
>  
> +static struct umr_bitfield stat_cik_sensor_bits[] = {
> + { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
> _bitfield_default },
> + { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
> _bitfield_default },
> + { NULL, 0, 0, NULL },
> +};
> +
> +static struct umr_bitfield stat_kaveri_sensor_bits[] = {
> + { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
> _bitfield_default },
> + { NULL, 0, 0, NULL },
> +};
> +
> +static struct umr_bitfield stat_si_sensor_bits[] = {
> + { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
> _bitfield_default },
> + { NULL, 0, 0, NULL },
> +};
> +
>  #define AMDGPU_INFO_NUM_BYTES_MOVED  0x0f
>  #define AMDGPU_INFO_VRAM_USAGE   0x10
>  #define AMDGPU_INFO_GTT_USAGE0x11
> @@ -774,6 +795,15 @@ static void top_build_vi_program(struct umr_asic *asic)
>   } else if (asic->config.gfx.family == 130) {
>   // Volcanic Islands Family
>   ENTRY_SENSOR(i++, "GFX_SCLK", _vi_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
> + } else if (asic->config.gfx.family == 125) {
> + // Fusion
> + ENTRY_SENSOR(i++, "GFX_SCLK", _kaveri_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
> + } else if (asic->config.gfx.family == 120) {
> + // CIK
> + ENTRY_SENSOR(i++, "GFX_SCLK", _cik_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
> + } else if (asic->config.gfx.family == 110) {
> + // SI
> + ENTRY_SENSOR(i++, "GFX_SCLK", _si_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
>   }
>  
>   // More GFX bits
> 



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Re: [PATCH 00/11] remove fb_location programming

2017-02-17 Thread Alex Deucher 
On Fri, Feb 17, 2017 at 3:38 PM, Alex Deucher  wrote:
> Since evergreen, the vbios has programmed the FB_LOCATION to the proper size
> during asic_init, so there is no need to reprogram them in the driver.
> We can safely leave the location as set by the vbios.  This simplifies the
> driver significantly.

Tested this on CI and VI.  Works fine with DAL/DC. With the legacy
display path, VCE fails to initialize (ECPU won't come out of reset).
Any ideas?

Alex

>
> Alex Deucher (11):
>   drm/amdgpu/vce2: fix vce bar programming
>   drm/amdgpu: put gtt at 0 in the internal address space
>   drm/amdgpu/gmc8: use the vram location programmed by the vbios
>   drm/amdgpu/gmc7: use the vram location programmed by the vbios
>   drm/amdgpu/gmc6: use the vram location programmed by the vbios
>   drm/amdgpu/gmc8: drop fb location programming
>   drm/amdgpu/gmc7: drop fb location programming
>   drm/amdgpu/gmc6: drop fb location programming
>   drm/amdgpu: drop set_vga_render_state from display funcs (v2)
>   drm/amdgpu: remove *_mc_access from display funcs (v2)
>   drm/amd/dc/dm: remove redundant display structs
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   4 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   8 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  12 --
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 135 
> +-
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.h|   6 -
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  80 +
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.h|   6 -
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 115 --
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  82 +
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.h |   6 -
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c  |  97 +++-
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  38 ++
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  35 ++
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  34 ++
>  drivers/gpu/drm/amd/amdgpu/vce_v2_0.c |  17 +--
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  75 +---
>  16 files changed, 83 insertions(+), 667 deletions(-)
>
> --
> 2.5.5
>
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[PATCH 08/11] drm/amdgpu/gmc6: drop fb location programming

2017-02-17 Thread Alex Deucher 
No need to do this as the vbios does this for us.  As such
we no longer need to stop the mc during init.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index f2239ce..feafb6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -243,8 +243,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device 
*adev,
 
 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 {
-   struct amdgpu_mode_mc_save save;
-   u32 tmp;
int i, j;
 
/* Initialize HDP */
@@ -257,11 +255,6 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
}
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
-   if (adev->mode_info.num_crtc)
-   amdgpu_display_set_vga_render_state(adev, false);
-
-   gmc_v6_0_mc_stop(adev, );
-
if (gmc_v6_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
@@ -274,13 +267,6 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
   adev->mc.vram_end >> 12);
WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
   adev->vram_scratch.gpu_addr >> 12);
-   tmp = ((adev->mc.vram_end >> 24) & 0x) << 16;
-   tmp |= ((adev->mc.vram_start >> 24) & 0x);
-   WREG32(mmMC_VM_FB_LOCATION, tmp);
-   /* XXX double check these! */
-   WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
-   WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
-   WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFF);
WREG32(mmMC_VM_AGP_BASE, 0);
WREG32(mmMC_VM_AGP_TOP, 0x0FFF);
WREG32(mmMC_VM_AGP_BOT, 0x0FFF);
@@ -288,7 +274,6 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
if (gmc_v6_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
-   gmc_v6_0_mc_resume(adev, );
 }
 
 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
-- 
2.5.5

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[PATCH 07/11] drm/amdgpu/gmc7: drop fb location programming

2017-02-17 Thread Alex Deucher 
No need to do this as the vbios does this for us.  As such
we no longer need to stop the mc during init.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 13 -
 1 file changed, 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index bd94c3d..55a3ca7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -266,7 +266,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device 
*adev,
  */
 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 {
-   struct amdgpu_mode_mc_save save;
u32 tmp;
int i, j;
 
@@ -280,10 +279,6 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
}
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
-   if (adev->mode_info.num_crtc)
-   amdgpu_display_set_vga_render_state(adev, false);
-
-   gmc_v7_0_mc_stop(adev, );
if (gmc_v7_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
@@ -294,20 +289,12 @@ static void gmc_v7_0_mc_program(struct amdgpu_device 
*adev)
   adev->mc.vram_end >> 12);
WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
   adev->vram_scratch.gpu_addr >> 12);
-   tmp = ((adev->mc.vram_end >> 24) & 0x) << 16;
-   tmp |= ((adev->mc.vram_start >> 24) & 0x);
-   WREG32(mmMC_VM_FB_LOCATION, tmp);
-   /* XXX double check these! */
-   WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
-   WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
-   WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFF);
WREG32(mmMC_VM_AGP_BASE, 0);
WREG32(mmMC_VM_AGP_TOP, 0x0FFF);
WREG32(mmMC_VM_AGP_BOT, 0x0FFF);
if (gmc_v7_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
-   gmc_v7_0_mc_resume(adev, );
 
WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | 
BIF_FB_EN__FB_WRITE_EN_MASK);
 
-- 
2.5.5

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[PATCH 10/11] drm/amdgpu: remove *_mc_access from display funcs (v2)

2017-02-17 Thread Alex Deucher 
These are no longer needed now that we use the fb_location
programmed by the vbios.

v2: update DC as well

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   6 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  10 --
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 130 --
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.h|   5 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  75 -
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.h|   5 +-
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  77 -
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.h |   5 +-
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c  |  90 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  18 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  17 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  16 +--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  12 --
 15 files changed, 54 insertions(+), 529 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 458688e..4656b56 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -570,7 +570,6 @@ struct amdgpu_mc {
struct amdgpu_irq_src   vm_fault;
uint32_tvram_type;
uint32_tsrbm_soft_reset;
-   struct amdgpu_mode_mc_save save;
boolprt_warning;
 };
 
@@ -1714,8 +1713,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) 
(adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
 #define amdgpu_display_add_encoder(adev, e, s, c) 
(adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) 
(adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), 
(h), (r))
-#define amdgpu_display_stop_mc_access(adev, s) 
(adev)->mode_info.funcs->stop_mc_access((adev), (s))
-#define amdgpu_display_resume_mc_access(adev, s) 
(adev)->mode_info.funcs->resume_mc_access((adev), (s))
 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) 
(adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) 
(adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
 #define amdgpu_gfx_get_gpu_clock_counter(adev) 
(adev)->gfx.funcs->get_gpu_clock_counter((adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c0679d3..195fde1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2559,12 +2559,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
r = amdgpu_suspend(adev);
 
 retry:
-   /* Disable fb access */
-   if (adev->mode_info.num_crtc) {
-   struct amdgpu_mode_mc_save save;
-   amdgpu_display_stop_mc_access(adev, );
-   amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
-   }
amdgpu_atombios_scratch_regs_save(adev);
r = amdgpu_asic_reset(adev);
amdgpu_atombios_scratch_regs_restore(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 45dc83e..83d4edb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -260,12 +260,6 @@ struct amdgpu_audio {
int num_pins;
 };
 
-struct amdgpu_mode_mc_save {
-   u32 vga_render_control;
-   u32 vga_hdp_control;
-   bool crtc_enabled[AMDGPU_MAX_CRTCS];
-};
-
 struct amdgpu_display_funcs {
/* display watermarks */
void (*bandwidth_update)(struct amdgpu_device *adev);
@@ -301,10 +295,6 @@ struct amdgpu_display_funcs {
  uint16_t connector_object_id,
  struct amdgpu_hpd *hpd,
  struct amdgpu_router *router);
-   void (*stop_mc_access)(struct amdgpu_device *adev,
-  struct amdgpu_mode_mc_save *save);
-   void (*resume_mc_access)(struct amdgpu_device *adev,
-struct amdgpu_mode_mc_save *save);
/* it is used to enter or exit into free sync mode */
int (*notify_freesync)(struct drm_device *dev, void *data,
   struct drm_file *filp);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 3b0daaf..6acdff4 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -484,134 +484,6 @@ bool

[PATCH 03/11] drm/amdgpu/gmc8: use the vram location programmed by the vbios

2017-02-17 Thread Alex Deucher 
This makes mc programming much simpler in future patches.

Since evergreen, the vbios has been programming the fb location
to the proper vram size.  The only reason to reprogram it would
be to change the location.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 6e32f28..d41737a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -334,13 +334,16 @@ static int gmc_v8_0_mc_load_microcode(struct 
amdgpu_device *adev)
 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
   struct amdgpu_mc *mc)
 {
+   u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0x;
+   base <<= 24;
+
if (mc->mc_vram_size > 0xFFC000ULL) {
/* leave room for at least 1024M GTT */
dev_warn(adev->dev, "limiting VRAM\n");
mc->real_vram_size = 0xFFC000ULL;
mc->mc_vram_size = 0xFFC000ULL;
}
-   amdgpu_vram_location(adev, >mc, 0);
+   amdgpu_vram_location(adev, >mc, base);
adev->mc.gtt_base_align = 0;
amdgpu_gtt_location(adev, mc);
 }
-- 
2.5.5

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[PATCH 11/11] drm/amd/dc/dm: remove redundant display structs

2017-02-17 Thread Alex Deucher 
Now that the mc_access functions are gone, we no longer
need separate structs for all the different dce families
in dm.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 60 ++-
 1 file changed, 4 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7b58434..1044a84 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1404,48 +1404,7 @@ static int amdgpu_notify_freesync(struct drm_device 
*dev, void *data,
return r;
 }
 
-#ifdef CONFIG_DRM_AMDGPU_CIK
-static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = {
-   .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-   .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-   .vblank_wait = NULL,
-   .backlight_set_level =
-   dm_set_backlight_level,/* called unconditionally */
-   .backlight_get_level =
-   dm_get_backlight_level,/* called unconditionally */
-   .hpd_sense = NULL,/* called unconditionally */
-   .hpd_set_polarity = NULL, /* called unconditionally */
-   .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-   .page_flip = dm_page_flip, /* called unconditionally */
-   .page_flip_get_scanoutpos =
-   dm_crtc_get_scanoutpos,/* called unconditionally */
-   .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-   .add_connector = NULL, /* VBIOS parsing. DAL does it. */
-   .notify_freesync = amdgpu_notify_freesync,
-};
-#endif
-
-static const struct amdgpu_display_funcs dm_dce_v10_0_display_funcs = {
-   .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-   .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-   .vblank_wait = NULL,
-   .backlight_set_level =
-   dm_set_backlight_level,/* called unconditionally */
-   .backlight_get_level =
-   dm_get_backlight_level,/* called unconditionally */
-   .hpd_sense = NULL,/* called unconditionally */
-   .hpd_set_polarity = NULL, /* called unconditionally */
-   .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-   .page_flip = dm_page_flip, /* called unconditionally */
-   .page_flip_get_scanoutpos =
-   dm_crtc_get_scanoutpos,/* called unconditionally */
-   .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-   .add_connector = NULL, /* VBIOS parsing. DAL does it. */
-   .notify_freesync = amdgpu_notify_freesync,
-
-};
-
-static const struct amdgpu_display_funcs dm_dce_v11_0_display_funcs = {
+static const struct amdgpu_display_funcs dm_display_funcs = {
.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
.vblank_wait = NULL,
@@ -1509,53 +1468,42 @@ static int dm_early_init(void *handle)
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
-#ifdef CONFIG_DRM_AMDGPU_CIK
-   if (adev->mode_info.funcs == NULL)
-   adev->mode_info.funcs = _dce_v8_0_display_funcs;
-#endif
break;
case CHIP_FIJI:
case CHIP_TONGA:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 7;
-   if (adev->mode_info.funcs == NULL)
-   adev->mode_info.funcs = _dce_v10_0_display_funcs;
break;
case CHIP_CARRIZO:
adev->mode_info.num_crtc = 3;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 9;
-   if (adev->mode_info.funcs == NULL)
-   adev->mode_info.funcs = _dce_v11_0_display_funcs;
break;
case CHIP_STONEY:
adev->mode_info.num_crtc = 2;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 9;
-   if (adev->mode_info.funcs == NULL)
-   adev->mode_info.funcs = _dce_v11_0_display_funcs;
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
adev->mode_info.num_dig = 5;
-   if (adev->mode_info.funcs == NULL)
-   adev->mode_info.funcs = _dce_v11_0_display_funcs;
break;
case CHIP_POLARIS10:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
-   if (adev->mode_info.funcs == NULL)
-   adev->mode_info.funcs =

[PATCH 05/11] drm/amdgpu/gmc6: use the vram location programmed by the vbios

2017-02-17 Thread Alex Deucher 
This makes mc programming much simpler in future patches.

Since evergreen, the vbios has been programming the fb location
to the proper vram size.  The only reason to reprogram it would
be to change the location.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 3328428..f2239ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -228,12 +228,15 @@ static int gmc_v6_0_mc_load_microcode(struct 
amdgpu_device *adev)
 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
   struct amdgpu_mc *mc)
 {
+   u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0x;
+   base <<= 24;
+
if (mc->mc_vram_size > 0xFFC000ULL) {
dev_warn(adev->dev, "limiting VRAM\n");
mc->real_vram_size = 0xFFC000ULL;
mc->mc_vram_size = 0xFFC000ULL;
}
-   amdgpu_vram_location(adev, >mc, 0);
+   amdgpu_vram_location(adev, >mc, base);
adev->mc.gtt_base_align = 0;
amdgpu_gtt_location(adev, mc);
 }
-- 
2.5.5

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[PATCH 09/11] drm/amdgpu: drop set_vga_render_state from display funcs (v2)

2017-02-17 Thread Alex Deucher 
Not used.

v2: include DC as well

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  | 2 --
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 5 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.h| 3 ---
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 5 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.h| 3 ---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 5 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.h | 3 ---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c  | 7 ---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
 11 files changed, 6 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 67df5eb..458688e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1702,7 +1702,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), 
(iv))
 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
-#define amdgpu_display_set_vga_render_state(adev, r) 
(adev)->mode_info.funcs->set_vga_render_state((adev), (r))
 #define amdgpu_display_vblank_get_counter(adev, crtc) 
(adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
 #define amdgpu_display_vblank_wait(adev, crtc) 
(adev)->mode_info.funcs->vblank_wait((adev), (crtc))
 #define amdgpu_display_backlight_set_level(adev, e, l) 
(adev)->mode_info.funcs->backlight_set_level((e), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 0740673..45dc83e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -267,8 +267,6 @@ struct amdgpu_mode_mc_save {
 };
 
 struct amdgpu_display_funcs {
-   /* vga render */
-   void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
/* display watermarks */
void (*bandwidth_update)(struct amdgpu_device *adev);
/* get frame count */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index db6e299..3b0daaf 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -612,8 +612,8 @@ void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 }
 
-void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
-   bool render)
+static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
+  bool render)
 {
u32 tmp;
 
@@ -3747,7 +3747,6 @@ static void dce_v10_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
-   .set_vga_render_state = _v10_0_set_vga_render_state,
.bandwidth_update = _v10_0_bandwidth_update,
.vblank_get_counter = _v10_0_vblank_get_counter,
.vblank_wait = _v10_0_vblank_wait,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
index c29c10b1..2ced0eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
@@ -29,9 +29,6 @@ extern const struct amdgpu_ip_block_version 
dce_v10_0_ip_block;
 extern const struct amdgpu_ip_block_version dce_v10_1_ip_block;
 
 void dce_v10_0_disable_dce(struct amdgpu_device *adev);
-
-void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
-   bool render);
 void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
  struct amdgpu_mode_mc_save *save);
 void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 459afac..20d8de8 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -572,8 +572,8 @@ void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 }
 
-void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
-   bool render)
+static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
+  bool render)
 {
u32 tmp;
 
@@ -3816,7 +3816,6 @@ static void dce_v11_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
-   .set_vga_render_state = _v11_0_set_vga_render_state,
.bandwidth_update = _v11_0_bandwidth_update,

[PATCH 04/11] drm/amdgpu/gmc7: use the vram location programmed by the vbios

2017-02-17 Thread Alex Deucher 
This makes mc programming much simpler in future patches.

Since evergreen, the vbios has been programming the fb location
to the proper vram size.  The only reason to reprogram it would
be to change the location.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 4b38d06..bd94c3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -242,13 +242,16 @@ static int gmc_v7_0_mc_load_microcode(struct 
amdgpu_device *adev)
 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
   struct amdgpu_mc *mc)
 {
+   u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0x;
+   base <<= 24;
+
if (mc->mc_vram_size > 0xFFC000ULL) {
/* leave room for at least 1024M GTT */
dev_warn(adev->dev, "limiting VRAM\n");
mc->real_vram_size = 0xFFC000ULL;
mc->mc_vram_size = 0xFFC000ULL;
}
-   amdgpu_vram_location(adev, >mc, 0);
+   amdgpu_vram_location(adev, >mc, base);
adev->mc.gtt_base_align = 0;
amdgpu_gtt_location(adev, mc);
 }
-- 
2.5.5

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[PATCH 06/11] drm/amdgpu/gmc8: drop fb location programming

2017-02-17 Thread Alex Deucher 
No need to do this as the vbios does this for us.  As such
we no longer need to stop the mc during init.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 -
 1 file changed, 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index d41737a..622fed3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -358,7 +358,6 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device 
*adev,
  */
 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 {
-   struct amdgpu_mode_mc_save save;
u32 tmp;
int i, j;
 
@@ -372,10 +371,6 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
}
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
-   if (adev->mode_info.num_crtc)
-   amdgpu_display_set_vga_render_state(adev, false);
-
-   gmc_v8_0_mc_stop(adev, );
if (gmc_v8_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
@@ -386,20 +381,12 @@ static void gmc_v8_0_mc_program(struct amdgpu_device 
*adev)
   adev->mc.vram_end >> 12);
WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
   adev->vram_scratch.gpu_addr >> 12);
-   tmp = ((adev->mc.vram_end >> 24) & 0x) << 16;
-   tmp |= ((adev->mc.vram_start >> 24) & 0x);
-   WREG32(mmMC_VM_FB_LOCATION, tmp);
-   /* XXX double check these! */
-   WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
-   WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
-   WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFF);
WREG32(mmMC_VM_AGP_BASE, 0);
WREG32(mmMC_VM_AGP_TOP, 0x0FFF);
WREG32(mmMC_VM_AGP_BOT, 0x0FFF);
if (gmc_v8_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
-   gmc_v8_0_mc_resume(adev, );
 
WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | 
BIF_FB_EN__FB_WRITE_EN_MASK);
 
-- 
2.5.5

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[PATCH 02/11] drm/amdgpu: put gtt at 0 in the internal address space

2017-02-17 Thread Alex Deucher 
There still seem to be some blocks that make accesses
in the lower part of the address space.  This works around
this.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ee8c4a0..c0679d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -603,7 +603,7 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, struct 
amdgpu_mc *mc)
dev_warn(adev->dev, "limiting GTT\n");
mc->gtt_size = size_bf;
}
-   mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - 
mc->gtt_size;
+   mc->gtt_start = 0;
} else {
if (mc->gtt_size > size_af) {
dev_warn(adev->dev, "limiting GTT\n");
-- 
2.5.5

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[PATCH 01/11] drm/amdgpu/vce2: fix vce bar programming

2017-02-17 Thread Alex Deucher 
Program the VCE BAR and offsets properly.  The current code
was carried over from a limitation from older VCE versions.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 9ea9934..cb0b730f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -167,8 +167,7 @@ static void vce_v2_0_init_cg(struct amdgpu_device *adev)
 
 static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
 {
-   uint64_t addr = adev->vce.gpu_addr;
-   uint32_t size;
+   uint32_t size, offset;
 
WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
@@ -181,19 +180,21 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
WREG32(mmVCE_LMI_VM_CTRL, 0);
 
-   addr += AMDGPU_VCE_FIRMWARE_OFFSET;
+   WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
+
+   offset = AMDGPU_VCE_FIRMWARE_OFFSET;
size = VCE_V2_0_FW_SIZE;
-   WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fff);
+   WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fff);
WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
 
-   addr += size;
+   offset += size;
size = VCE_V2_0_STACK_SIZE;
-   WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fff);
+   WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fff);
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
 
-   addr += size;
+   offset += size;
size = VCE_V2_0_DATA_SIZE;
-   WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fff);
+   WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fff);
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
 
WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
-- 
2.5.5

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[PATCH 00/11] remove fb_location programming

2017-02-17 Thread Alex Deucher 
Since evergreen, the vbios has programmed the FB_LOCATION to the proper size
during asic_init, so there is no need to reprogram them in the driver.
We can safely leave the location as set by the vbios.  This simplifies the
driver significantly.

Alex Deucher (11):
  drm/amdgpu/vce2: fix vce bar programming
  drm/amdgpu: put gtt at 0 in the internal address space
  drm/amdgpu/gmc8: use the vram location programmed by the vbios
  drm/amdgpu/gmc7: use the vram location programmed by the vbios
  drm/amdgpu/gmc6: use the vram location programmed by the vbios
  drm/amdgpu/gmc8: drop fb location programming
  drm/amdgpu/gmc7: drop fb location programming
  drm/amdgpu/gmc6: drop fb location programming
  drm/amdgpu: drop set_vga_render_state from display funcs (v2)
  drm/amdgpu: remove *_mc_access from display funcs (v2)
  drm/amd/dc/dm: remove redundant display structs

 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  12 --
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 135 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.h|   6 -
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  80 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.h|   6 -
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 115 --
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  82 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.h |   6 -
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c  |  97 +++-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  38 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  35 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  34 ++
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c |  17 +--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  75 +---
 16 files changed, 83 insertions(+), 667 deletions(-)

-- 
2.5.5

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[PATCH umr] Add SENSOR for SI/CIK/KV systems.

2017-02-17 Thread Tom St Denis 
Signed-off-by: Tom St Denis 
---
 src/app/top.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/src/app/top.c b/src/app/top.c
index 92ab8ab854af..c97a0c9d93ab 100644
--- a/src/app/top.c
+++ b/src/app/top.c
@@ -231,6 +231,27 @@ static struct umr_bitfield stat_vi_sensor_bits[] = {
{ NULL, 0, 0, NULL },
 };
 
+static struct umr_bitfield stat_cik_sensor_bits[] = {
+   { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
_bitfield_default },
+   { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
_bitfield_default },
+   { "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
_bitfield_default },
+   { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
_bitfield_default },
+   { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_kaveri_sensor_bits[] = {
+   { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
_bitfield_default },
+   { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
_bitfield_default },
+   { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_si_sensor_bits[] = {
+   { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
_bitfield_default },
+   { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
_bitfield_default },
+   { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
_bitfield_default },
+   { NULL, 0, 0, NULL },
+};
+
 #define AMDGPU_INFO_NUM_BYTES_MOVED0x0f
 #define AMDGPU_INFO_VRAM_USAGE 0x10
 #define AMDGPU_INFO_GTT_USAGE  0x11
@@ -774,6 +795,15 @@ static void top_build_vi_program(struct umr_asic *asic)
} else if (asic->config.gfx.family == 130) {
// Volcanic Islands Family
ENTRY_SENSOR(i++, "GFX_SCLK", _vi_sensor_bits[0], 
_options.vi.sensors, "Sensors");
+   } else if (asic->config.gfx.family == 125) {
+   // Fusion
+   ENTRY_SENSOR(i++, "GFX_SCLK", _kaveri_sensor_bits[0], 
_options.vi.sensors, "Sensors");
+   } else if (asic->config.gfx.family == 120) {
+   // CIK
+   ENTRY_SENSOR(i++, "GFX_SCLK", _cik_sensor_bits[0], 
_options.vi.sensors, "Sensors");
+   } else if (asic->config.gfx.family == 110) {
+   // SI
+   ENTRY_SENSOR(i++, "GFX_SCLK", _si_sensor_bits[0], 
_options.vi.sensors, "Sensors");
}
 
// More GFX bits
-- 
2.11.0

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[PATCH 17/35] drivers/gpu: Convert remaining uses of pr_warning to pr_warn

2017-02-17 Thread Joe Perches 
To enable eventual removal of pr_warning

This makes pr_warn use consistent for drivers/gpu

Prior to this patch, there were 15 uses of pr_warning and
20 uses of pr_warn in drivers/gpu

Signed-off-by: Joe Perches 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c |  2 +-
 drivers/gpu/drm/amd/powerplay/inc/pp_debug.h |  2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c  |  4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c   | 14 +++---
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c |  4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c |  4 ++--
 6 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b1de9e8ccdbc..83266408634e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1535,7 +1535,7 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
if (vddc >= 2000 || vddc == 0)
return -EINVAL;
} else {
-   pr_warning("failed to retrieving EVV 
voltage!\n");
+   pr_warn("failed to retrieving EVV 
voltage!\n");
continue;
}
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h 
b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
index 072880130cfb..f3f9ebb631a5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
@@ -37,7 +37,7 @@
 #define PP_ASSERT_WITH_CODE(cond, msg, code)   \
do {\
if (!(cond)) {  \
-   pr_warning("%s\n", msg);\
+   pr_warn("%s\n", msg);   \
code;   \
}   \
} while (0)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index 0f7a77b7312e..5450f5ef8e89 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -2131,7 +2131,7 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
return offsetof(SMU73_Discrete_DpmTable, 
LowSclkInterruptThreshold);
}
}
-   pr_warning("can't get the offset of type %x member %x\n", type, member);
+   pr_warn("can't get the offset of type %x member %x\n", type, member);
return 0;
 }
 
@@ -2156,7 +2156,7 @@ uint32_t fiji_get_mac_definition(uint32_t value)
return SMU73_MAX_LEVELS_MVDD;
}
 
-   pr_warning("can't get the mac of %x\n", value);
+   pr_warn("can't get the mac of %x\n", value);
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index ad82161df831..51adf04ab4b3 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -122,7 +122,7 @@ static void iceland_initialize_power_tune_defaults(struct 
pp_hwmgr *hwmgr)
break;
default:
smu_data->power_tune_defaults = _iceland;
-   pr_warning("Unknown V.I. Device ID.\n");
+   pr_warn("Unknown V.I. Device ID.\n");
break;
}
return;
@@ -378,7 +378,7 @@ static int iceland_get_std_voltage_value_sidd(struct 
pp_hwmgr *hwmgr,
return -EINVAL);
 
if (NULL == hwmgr->dyn_state.cac_leakage_table) {
-   pr_warning("CAC Leakage Table does not exist, using vddc.\n");
+   pr_warn("CAC Leakage Table does not exist, using vddc.\n");
return 0;
}
 
@@ -394,7 +394,7 @@ static int iceland_get_std_voltage_value_sidd(struct 
pp_hwmgr *hwmgr,
*lo = 
hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
*hi = 
(uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * 
VOLTAGE_SCALE);
} else {
-   pr_warning("Index from SCLK/VDDC Dependency 
Table exceeds the CAC Leakage Table index, using maximum index from CAC 
table.\n");
+   pr_warn("Index from SCLK/VDDC Dependency Table 
exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
*lo = 
hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count
 - 1].Vddc * VOLTAGE_SCALE;
*hi =

[PATCH 00/35] treewide trivial patches converting pr_warning to pr_warn

2017-02-17 Thread Joe Perches 
There are ~4300 uses of pr_warn and ~250 uses of the older
pr_warning in the kernel source tree.

Make the use of pr_warn consistent across all kernel files.

This excludes all files in tools/ as there is a separate
define pr_warning for that directory tree and pr_warn is
not used in tools/.

Done with 'sed s/\bpr_warning\b/pr_warn/' and some emacsing.

Miscellanea:

o Coalesce formats and realign arguments

Some files not compiled - no cross-compilers

Joe Perches (35):
  alpha: Convert remaining uses of pr_warning to pr_warn
  ARM: ep93xx: Convert remaining uses of pr_warning to pr_warn
  arm64: Convert remaining uses of pr_warning to pr_warn
  arch/blackfin: Convert remaining uses of pr_warning to pr_warn
  ia64: Convert remaining use of pr_warning to pr_warn
  powerpc: Convert remaining uses of pr_warning to pr_warn
  sh: Convert remaining uses of pr_warning to pr_warn
  sparc: Convert remaining use of pr_warning to pr_warn
  x86: Convert remaining uses of pr_warning to pr_warn
  drivers/acpi: Convert remaining uses of pr_warning to pr_warn
  block/drbd: Convert remaining uses of pr_warning to pr_warn
  gdrom: Convert remaining uses of pr_warning to pr_warn
  drivers/char: Convert remaining use of pr_warning to pr_warn
  clocksource: Convert remaining use of pr_warning to pr_warn
  drivers/crypto: Convert remaining uses of pr_warning to pr_warn
  fmc: Convert remaining use of pr_warning to pr_warn
  drivers/gpu: Convert remaining uses of pr_warning to pr_warn
  drivers/ide: Convert remaining uses of pr_warning to pr_warn
  drivers/input: Convert remaining uses of pr_warning to pr_warn
  drivers/isdn: Convert remaining uses of pr_warning to pr_warn
  drivers/macintosh: Convert remaining uses of pr_warning to pr_warn
  drivers/media: Convert remaining use of pr_warning to pr_warn
  drivers/mfd: Convert remaining uses of pr_warning to pr_warn
  drivers/mtd: Convert remaining uses of pr_warning to pr_warn
  drivers/of: Convert remaining uses of pr_warning to pr_warn
  drivers/oprofile: Convert remaining uses of pr_warning to pr_warn
  drivers/platform: Convert remaining uses of pr_warning to pr_warn
  drivers/rapidio: Convert remaining use of pr_warning to pr_warn
  drivers/scsi: Convert remaining use of pr_warning to pr_warn
  drivers/sh: Convert remaining use of pr_warning to pr_warn
  drivers/tty: Convert remaining uses of pr_warning to pr_warn
  drivers/video: Convert remaining uses of pr_warning to pr_warn
  kernel/trace: Convert remaining uses of pr_warning to pr_warn
  lib: Convert remaining uses of pr_warning to pr_warn
  sound/soc: Convert remaining uses of pr_warning to pr_warn

 arch/alpha/kernel/perf_event.c |  4 +-
 arch/arm/mach-ep93xx/core.c|  4 +-
 arch/arm64/include/asm/syscall.h   |  8 ++--
 arch/arm64/kernel/hw_breakpoint.c  |  8 ++--
 arch/arm64/kernel/smp.c|  4 +-
 arch/blackfin/kernel/nmi.c |  2 +-
 arch/blackfin/kernel/ptrace.c  |  2 +-
 arch/blackfin/mach-bf533/boards/stamp.c|  2 +-
 arch/blackfin/mach-bf537/boards/cm_bf537e.c|  2 +-
 arch/blackfin/mach-bf537/boards/cm_bf537u.c|  2 +-
 arch/blackfin/mach-bf537/boards/stamp.c|  2 +-
 arch/blackfin/mach-bf537/boards/tcm_bf537.c|  2 +-
 arch/blackfin/mach-bf561/boards/cm_bf561.c |  2 +-
 arch/blackfin/mach-bf561/boards/ezkit.c|  2 +-
 arch/blackfin/mm/isram-driver.c|  4 +-
 arch/ia64/kernel/setup.c   |  6 +--
 arch/powerpc/kernel/pci-common.c   |  4 +-
 arch/powerpc/mm/init_64.c  |  5 +--
 arch/powerpc/mm/mem.c  |  3 +-
 arch/powerpc/platforms/512x/mpc512x_shared.c   |  4 +-
 arch/powerpc/platforms/85xx/socrates_fpga_pic.c|  7 ++--
 arch/powerpc/platforms/86xx/mpc86xx_hpcn.c |  2 +-
 arch/powerpc/platforms/pasemi/dma_lib.c|  4 +-
 arch/powerpc/platforms/powernv/opal.c  |  8 ++--
 arch/powerpc/platforms/powernv/pci-ioda.c  | 10 ++---
 arch/powerpc/platforms/ps3/device-init.c   | 14 +++
 arch/powerpc/platforms/ps3/mm.c|  4 +-
 arch/powerpc/platforms/ps3/os-area.c   |  2 +-
 arch/powerpc/platforms/pseries/iommu.c |  8 ++--
 arch/powerpc/platforms/pseries/setup.c |  4 +-
 arch/powerpc/sysdev/fsl_pci.c  |  9 ++---
 arch/powerpc/sysdev/mpic.c | 10 ++---
 arch/powerpc/sysdev/xics/icp-native.c  | 10 ++---
 arch/powerpc/sysdev/xics/ics-opal.c|  4 +-
 arch/powerpc/sysdev/xics/ics-rtas.c|  4 +-
 arch/powerpc/sysdev/xics/xics-common.c |  8 ++--
 arch/sh/boards/mach-sdk7786/nmi.c  |  2 +-
 arch/sh/drivers/pci/fixups-sdk7786.c   |  2 +-
 arch/sh/kernel/io_trapped.c

Re: [PATCH 00/35] treewide trivial patches converting pr_warning to pr_warn

2017-02-17 Thread Geert Uytterhoeven 
Hi Rafael,

On Fri, Feb 17, 2017 at 1:27 PM, Rafael J. Wysocki  wrote:
> On Fri, Feb 17, 2017 at 8:11 AM, Joe Perches  wrote:
>> There are ~4300 uses of pr_warn and ~250 uses of the older
>> pr_warning in the kernel source tree.
>>
>> Make the use of pr_warn consistent across all kernel files.
>>
>> This excludes all files in tools/ as there is a separate
>> define pr_warning for that directory tree and pr_warn is
>> not used in tools/.
>>
>> Done with 'sed s/\bpr_warning\b/pr_warn/' and some emacsing.
>
> Sorry about asking if that has been asked already.
>
> Wouldn't it be slightly less intrusive to simply redefined
> pr_warning() as a synonym for pr_warn()?

That's already the case.

This series cleans up the cruft, so we can catch all users with
"git grep -w pr_warn".

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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Re: [PATCH 00/35] treewide trivial patches converting pr_warning to pr_warn

2017-02-17 Thread Rafael J. Wysocki 
On Fri, Feb 17, 2017 at 8:11 AM, Joe Perches  wrote:
> There are ~4300 uses of pr_warn and ~250 uses of the older
> pr_warning in the kernel source tree.
>
> Make the use of pr_warn consistent across all kernel files.
>
> This excludes all files in tools/ as there is a separate
> define pr_warning for that directory tree and pr_warn is
> not used in tools/.
>
> Done with 'sed s/\bpr_warning\b/pr_warn/' and some emacsing.

Sorry about asking if that has been asked already.

Wouldn't it be slightly less intrusive to simply redefined
pr_warning() as a synonym for pr_warn()?

Thanks,
Rafael
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Re: [PATCH] drm/amdgpu: refuse to reserve io mem for split VRAM buffers

2017-02-17 Thread Nicolai Hähnle 

On 17.02.2017 11:08, Christian König wrote:

Am 17.02.2017 um 00:21 schrieb Nicolai Hähnle:

On 17.02.2017 00:02, Alex Deucher wrote:

On Thu, Feb 16, 2017 at 5:55 PM, Nicolai Hähnle 
wrote:

From: Nicolai Hähnle 

When the fast blit path fails while attempting to move a buffer from
RAM
to VRAM, we fall back to a CPU-based memcpy that cannot handle split
VRAM
buffers. Instead of crashing, simply fail the buffer move.

Ideally, we would teach TTM about split buffers so that the fallback
still
works in this case, but that is quite involved. So for now, apply the
simplest possible fix.

Fixes: 40361bb1704b ("drm/amdgpu: add VRAM manager v2")
Signed-off-by: Nicolai Hähnle 


Possibly fixes this bug report?
https://bugzilla.kernel.org/show_bug.cgi?id=194579


It's related, but I think that report is a false positive. It does
point at code that is not too pretty, though. I've commented on that
bug report as well.

In any case, that overflow should indeed happen whenever the bug
addressed by this patch happens, but (a) this patch doesn't change
that, and (b) I'm pretty sure that the overflow reported by PaX is
benign.


Yes, agree. The bug report is indeed a false positive.

Nicolai what do you think about removing the offset from the BO
structure and only calculate it on demand?


I think it's a good idea. There are lots of uses in other drivers, 
though, so a first step would be adding a helper analogous to 
amdgpu_bo_gpu_offset in ttm_bo_api.h.




We may still have other bugs with split BOs, though.


Yeah, agree as well. I was also considering disabling that feature by
default for the moment if it helps with your corruption bug.


Good point, I'll give that a try as well.

Cheers,
Nicolai
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Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info

2017-02-17 Thread Christian König 

Am 17.02.2017 um 06:02 schrieb Zhang, Jerry:

Hi Christian,

Thanks for specifying it.

Please check my update in another mail if getting the correct info as you 
mentioned.


Just make sure that the default value is zero, this way you keep backward
compatible with older kernel interfaces.

I have checked all gfx from 6 to 8. By default they are 1. Just 2 APUs(gfxv8) 
are 0.


In this case you might want to bump the driver minor number as well to 
indicate validity of that field.


See we can extend the structures by adding new fields to the end, but 
old kernels will not set those fields (so they stay zero cleared).


Not sure what the UMD is expecting here.

Regards,
Christian.



Regards,
Jerry (Junwei Zhang)

Linux Base Graphics
SRDC Software Development
_



-Original Message-
From: Christian König [mailto:deathsim...@vodafone.de]
Sent: Thursday, February 16, 2017 17:37
To: Zhang, Jerry; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info

Am 16.02.2017 um 10:24 schrieb Zhang, Jerry:

-Original Message-
From: Christian König [mailto:deathsim...@vodafone.de]
Sent: Thursday, February 16, 2017 17:12
To: Zhang, Jerry; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu
info

Am 16.02.2017 um 03:53 schrieb Junwei Zhang:

Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a
Signed-off-by: Junwei Zhang 

Complete NAK on this. The drm_amdgpu_capability structure is specific
to the pro driver.

Thanks to reminder it.
I neglect it.


The Vulkan stack on the other hand is supposed to work on the open
stack as well.

So please but that into the drm_amdgpu_info_device structure and the
new field in the amdgpu_gca_config structure (you might as well want
to rename the amdgpu_gca_config structure).

So you mean add the feature or config structure in amdgpu_device directly

from now on.

Right?

No, just forget about the config or feature structure. Add gfx features to
amdgpu_gca_config.


Could you explain the meaning about gca?

I just think that the naming isn't the best, something like amdgpu_gfx_config
would probably be better.


BTW,
1) in the future we may add more feature/config in the same structure, but

may not for gfx.

Stop, that is really bad design. The features/config should be kept on a per IP
basis.

So gfx config/features should only be grouped together with gfx features. Don't
mix features from different block inside the kernel module.

The IOCTL interface is a different story, here we have the
drm_amdgpu_info_device structure for information about the whole GPU as
well as individual structures about each IP block (like firmware versions 
etc...).

For the current case adding that to drm_amdgpu_info_device sounds like the
right approach to me.


2) Shall we add a version to control these features? UMD could know the

features status according to the version.

No, the size of the drm_amdgpu_info_device structure is already version
controlled.

Just make sure that the default value is zero, this way you keep backward
compatible with older kernel interfaces.

Regards,
Christian.


Regards,
Christian.


---
drivers/gpu/drm/amd/amdgpu/amdgpu.h |  6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 ++
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  6 ++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 14 ++
include/uapi/drm/amdgpu_drm.h   |  1 +
6 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1ad3f08..cdc2b2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs {
void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t
simd,

uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);

};

+struct amdgpu_gfx_cap {
+   uint32_t gc_double_offchip_lds_buf; };
+
struct amdgpu_gfx {
struct mutexgpu_clock_mutex;
struct amdgpu_gca_configconfig;
@@ -911,6 +915,8 @@ struct amdgpu_gfx {
/* reset mask */
uint32_tgrbm_soft_reset;
uint32_tsrbm_soft_reset;
+
+   struct amdgpu_gfx_cap   cap;
};

int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm
*vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7f59608..e7aa382 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device
*dev,

void *data, struct drm_file

cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG;
cap.direct_gma_size = amdgpu_direct_gma_size;
}
+

Re: [PATCH v2 1/1] drm/amdgpu: export gfx config by gpu info (v2)

2017-02-17 Thread Christian König 

Am 17.02.2017 um 06:05 schrieb Junwei Zhang:

v2: move the config struct to drm_amdgpu_info_device

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  7 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  1 +
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 ++
  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  6 ++
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 16 +++-
  include/uapi/drm/amdgpu_drm.h   |  2 ++
  6 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7f1421f..9204545 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -873,6 +873,10 @@ struct amdgpu_gfx_funcs {
void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
  };
  
+struct amdgpu_gfx_config {

+   uint32_t double_offchip_lds_buf;
+};
+


Any specific reason why we can't add that to the existing 
amdgpu_gca_config structure?


Apart from that the patch looks good to me.

Regards,
Christian.


  struct amdgpu_gfx {
struct mutexgpu_clock_mutex;
struct amdgpu_gca_configconfig;
@@ -916,6 +920,9 @@ struct amdgpu_gfx {
uint32_tgrbm_soft_reset;
uint32_tsrbm_soft_reset;
boolin_reset;
+
+   /* gfx config */
+   struct amdgpu_gfx_configgc;
  };
  
  int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 6b9bf0e..922ae3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -545,6 +545,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
dev_info.vram_type = adev->mc.vram_type;
dev_info.vram_bit_width = adev->mc.vram_width;
dev_info.vce_harvest_config = adev->vce.harvest_config;
+   dev_info.gc_double_offchip_lds_buf = 
adev->gfx.gc.double_offchip_lds_buf;
  
  		return copy_to_user(out, _info,

min((size_t)size, sizeof(dev_info))) ? 
-EFAULT : 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 782190d..b758283 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1579,6 +1579,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device 
*adev)
mutex_unlock(>grbm_idx_mutex);
  }
  
+static void gfx_v6_0_config_init(struct amdgpu_device *adev)

+{
+   adev->gfx.gc.double_offchip_lds_buf = 1;
+}
+
  static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
  {
u32 gb_addr_config = 0;
@@ -1736,6 +1741,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
gfx_v6_0_setup_spi(adev);
  
  	gfx_v6_0_get_cu_info(adev);

+   gfx_v6_0_config_init(adev);
  
  	WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |

   (0x2b << 
CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 8e07a50..f0f0512 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct 
amdgpu_device *adev)
mutex_unlock(>srbm_mutex);
  }
  
+static void gfx_v7_0_config_init(struct amdgpu_device *adev)

+{
+   adev->gfx.gc.double_offchip_lds_buf = 1;
+}
+
  /**
   * gfx_v7_0_gpu_init - setup the 3D engine
   *
@@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
  
  	gfx_v7_0_setup_rb(adev);

gfx_v7_0_get_cu_info(adev);
+   gfx_v7_0_config_init(adev);
  
  	/* set HW defaults for 3D engine */

WREG32(mmCP_MEQ_THRESHOLDS,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index fdce3de..0b700b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3846,6 +3846,19 @@ static void gfx_v8_0_init_compute_vmid(struct 
amdgpu_device *adev)
mutex_unlock(>srbm_mutex);
  }
  
+static void gfx_v8_0_config_init(struct amdgpu_device *adev)

+{
+   switch (adev->asic_type) {
+   default:
+   adev->gfx.gc.double_offchip_lds_buf = 1;
+   break;
+   case CHIP_CARRIZO:
+   case CHIP_STONEY:
+   adev->gfx.gc.double_offchip_lds_buf = 0;
+   break;
+   }
+}
+
  static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
  {
u32 tmp, sh_static_mem_cfg;
@@ -3859,6 +3872,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)

Re: [PATCH] drm/amdgpu: refuse to reserve io mem for split VRAM buffers

2017-02-17 Thread Christian König 

Am 17.02.2017 um 00:21 schrieb Nicolai Hähnle:

On 17.02.2017 00:02, Alex Deucher wrote:
On Thu, Feb 16, 2017 at 5:55 PM, Nicolai Hähnle  
wrote:

From: Nicolai Hähnle 

When the fast blit path fails while attempting to move a buffer from 
RAM
to VRAM, we fall back to a CPU-based memcpy that cannot handle split 
VRAM

buffers. Instead of crashing, simply fail the buffer move.

Ideally, we would teach TTM about split buffers so that the fallback 
still

works in this case, but that is quite involved. So for now, apply the
simplest possible fix.

Fixes: 40361bb1704b ("drm/amdgpu: add VRAM manager v2")
Signed-off-by: Nicolai Hähnle 


Possibly fixes this bug report?
https://bugzilla.kernel.org/show_bug.cgi?id=194579


It's related, but I think that report is a false positive. It does 
point at code that is not too pretty, though. I've commented on that 
bug report as well.


In any case, that overflow should indeed happen whenever the bug 
addressed by this patch happens, but (a) this patch doesn't change 
that, and (b) I'm pretty sure that the overflow reported by PaX is 
benign.


Yes, agree. The bug report is indeed a false positive.

Nicolai what do you think about removing the offset from the BO 
structure and only calculate it on demand?




We may still have other bugs with split BOs, though.


Yeah, agree as well. I was also considering disabling that feature by 
default for the moment if it helps with your corruption bug.


Regards,
Christian.



Cheers,
Nicolai



Alex


--
I ran into this bug during testing. Unfortunately it does not fix the
memory corruption bug that I mentioned elsewhere... oh well.
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index 8d6a68f..f8b578d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -529,6 +529,9 @@ static int amdgpu_ttm_io_mem_reserve(struct 
ttm_bo_device *bdev, struct ttm_mem_

case TTM_PL_TT:
break;
case TTM_PL_VRAM:
+   if (mem->start == AMDGPU_BO_INVALID_OFFSET)
+   return -EINVAL;
+
mem->bus.offset = mem->start << PAGE_SHIFT;
/* check if it's visible */
if ((mem->bus.offset + mem->bus.size) > 
adev->mc.visible_vram_size)

--
2.9.3

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