RE: [PATCH 00/11] remove fb_location programming

2017-02-21 Thread Zhang, Jerry 
> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, February 21, 2017 22:38
> To: Zhang, Jerry
> Cc: amd-gfx list; Deucher, Alexander
> Subject: Re: [PATCH 00/11] remove fb_location programming
> 
> On Tue, Feb 21, 2017 at 1:47 AM, Zhang, Jerry  wrote:
> > Hi Alex,
> >
> > The series of patch is Reviewed-by: Junwei Zhang 
> >
> >> Tested this on CI and VI.  Works fine with DAL/DC. With the legacy
> >> display path, VCE fails to initialize (ECPU won't come out of reset).
> >> Any ideas?
> >
> > Did you met the issue in VI?
> 
> Yes.
> 
> > It looks that you're missing vce v3.0 changes for mc_resume.
> > Please confirm it.
> 
> What changes did you have in mind?  The changes for vce2.0 are not necessary
> for vce3.0 since it was programmed properly from the beginning as far as I
> understand it.

Hi Alex,

I thought vce3.0 had similar issue about BAR programming.
After checking, only vce2.0 needs this change indeed.
Sorry for misleading.

> 
> Alex
> 
> >
> > Regards,
> > Jerry (Junwei Zhang)
> >
> > Linux Base Graphics
> > SRDC Software Development
> > _
> >
> >
> >> -Original Message-
> >> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On
> >> Behalf Of Alex Deucher
> >> Sent: Saturday, February 18, 2017 7:08
> >> To: amd-gfx list
> >> Cc: Deucher, Alexander
> >> Subject: Re: [PATCH 00/11] remove fb_location programming
> >>
> >> On Fri, Feb 17, 2017 at 3:38 PM, Alex Deucher 
> wrote:
> >> > Since evergreen, the vbios has programmed the FB_LOCATION to the
> >> > proper size during asic_init, so there is no need to reprogram them in 
> >> > the
> driver.
> >> > We can safely leave the location as set by the vbios.  This
> >> > simplifies the driver significantly.
> >>
> >> Tested this on CI and VI.  Works fine with DAL/DC. With the legacy
> >> display path, VCE fails to initialize (ECPU won't come out of reset).
> >> Any ideas?
> >>
> >> Alex
> >>
> >> >
> >> > Alex Deucher (11):
> >> >   drm/amdgpu/vce2: fix vce bar programming
> >> >   drm/amdgpu: put gtt at 0 in the internal address space
> >> >   drm/amdgpu/gmc8: use the vram location programmed by the vbios
> >> >   drm/amdgpu/gmc7: use the vram location programmed by the vbios
> >> >   drm/amdgpu/gmc6: use the vram location programmed by the vbios
> >> >   drm/amdgpu/gmc8: drop fb location programming
> >> >   drm/amdgpu/gmc7: drop fb location programming
> >> >   drm/amdgpu/gmc6: drop fb location programming
> >> >   drm/amdgpu: drop set_vga_render_state from display funcs (v2)
> >> >   drm/amdgpu: remove *_mc_access from display funcs (v2)
> >> >   drm/amd/dc/dm: remove redundant display structs
> >> >
> >> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   4 -
> >> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   8 +-
> >> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  12 --
> >> >  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 135 
> >> > +-
> >> >  drivers/gpu/drm/amd/amdgpu/dce_v10_0.h|   6 -
> >> >  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  80 +
> >> >  drivers/gpu/drm/amd/amdgpu/dce_v11_0.h|   6 -
> >> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 115 
> >> > --
> >> >  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  82 +
> >> >  drivers/gpu/drm/amd/amdgpu/dce_v8_0.h |   6 -
> >> >  drivers/gpu/drm/amd/amdgpu/dce_virtual.c  |  97 +++-
> >> >  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  38 ++
> >> >  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  35 ++
> >> >  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  34 ++
> >> >  drivers/gpu/drm/amd/amdgpu/vce_v2_0.c |  17 +--
> >> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  75
> >> > +---
> >> >  16 files changed, 83 insertions(+), 667 deletions(-)
> >> >
> >> > --
> >> > 2.5.5
> >> >
> >> ___
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH v2] drm/amdgpu: add DP audio support for si dce6 (v2)

2017-02-21 Thread Xiaojie Yuan 
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names

Signed-off-by: Xiaojie Yuan 
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 457 +++--
 .../drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h |   2 +
 2 files changed, 423 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 94877cb..cb5137c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -118,14 +118,27 @@ static const struct {
 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
 u32 block_offset, u32 reg)
 {
-   DRM_INFO(": dce_v6_0_audio_endpt_rreg no impl\n");
-   return 0;
+   unsigned long flags;
+   u32 r;
+
+   spin_lock_irqsave(>audio_endpt_idx_lock, flags);
+   WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
+   r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
+   spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
+
+   return r;
 }
 
 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
  u32 block_offset, u32 reg, u32 v)
 {
-   DRM_INFO(": dce_v6_0_audio_endpt_wreg no impl\n");
+   unsigned long flags;
+
+   spin_lock_irqsave(>audio_endpt_idx_lock, flags);
+   WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
+   reg | 
AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
+   WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
+   spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
 }
 
 static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
@@ -1231,17 +1244,17 @@ static void dce_v6_0_bandwidth_update(struct 
amdgpu_device *adev)
dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], 
lb_size, num_heads);
}
 }
-/*
+
 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
 {
int i;
-   u32 offset, tmp;
+   u32 tmp;
 
for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
-   offset = adev->mode_info.audio.pin[i].offset;
-   tmp = RREG32_AUDIO_ENDPT(offset,
- 
AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
-   if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) 
== 1)
+   tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
+   
ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
+   if (REG_GET_FIELD(tmp, 
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
+   PORT_CONNECTIVITY))
adev->mode_info.audio.pin[i].connected = false;
else
adev->mode_info.audio.pin[i].connected = true;
@@ -1263,45 +1276,206 @@ static struct amdgpu_audio_pin 
*dce_v6_0_audio_get_pin(struct amdgpu_device *ade
return NULL;
 }
 
-static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
+static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
 {
struct amdgpu_device *adev = encoder->dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
-   u32 offset;
 
if (!dig || !dig->afmt || !dig->afmt->pin)
return;
 
-   offset = dig->afmt->offset;
-
-   WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
-  AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
-
+   WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
+  REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
+dig->afmt->pin->id));
 }
 
 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
struct drm_display_mode *mode)
 {
-   DRM_INFO(": dce_v6_0_audio_write_latency_fields---no imp!\n");
+   struct amdgpu_device *adev = encoder->dev->dev_private;
+   struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+   struct drm_connector *connector;
+   struct amdgpu_connector *amdgpu_connector = NULL;
+   int interlace = 0;
+   u32 tmp;
+
+   list_for_each_entry(connector, 
>dev->mode_config.connector_list, head) {
+   if (connector->encoder == encoder) {
+   amdgpu_connector = to_amdgpu_connector(connector);
+   break;
+   }
+   }
+
+   if (!amdgpu_connector) {
+   DRM_ERROR("Couldn't find encoder's connector\n");
+   return;
+   }
+
+   if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+

[PATCH v3] drm/amdgpu: add DP audio support for si dce6 (v3)

2017-02-21 Thread Xiaojie Yuan 
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names
v3: fix num_pins for tahiti, pitcairn, verde and oland

Signed-off-by: Xiaojie Yuan 
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 467 +++--
 .../drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h |   2 +
 2 files changed, 433 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 94877cb..7c11ed8 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -118,14 +118,27 @@ static const struct {
 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
 u32 block_offset, u32 reg)
 {
-   DRM_INFO(": dce_v6_0_audio_endpt_rreg no impl\n");
-   return 0;
+   unsigned long flags;
+   u32 r;
+
+   spin_lock_irqsave(>audio_endpt_idx_lock, flags);
+   WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
+   r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
+   spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
+
+   return r;
 }
 
 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
  u32 block_offset, u32 reg, u32 v)
 {
-   DRM_INFO(": dce_v6_0_audio_endpt_wreg no impl\n");
+   unsigned long flags;
+
+   spin_lock_irqsave(>audio_endpt_idx_lock, flags);
+   WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
+   reg | 
AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
+   WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
+   spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
 }
 
 static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
@@ -1231,17 +1244,17 @@ static void dce_v6_0_bandwidth_update(struct 
amdgpu_device *adev)
dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], 
lb_size, num_heads);
}
 }
-/*
+
 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
 {
int i;
-   u32 offset, tmp;
+   u32 tmp;
 
for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
-   offset = adev->mode_info.audio.pin[i].offset;
-   tmp = RREG32_AUDIO_ENDPT(offset,
- 
AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
-   if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) 
== 1)
+   tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
+   
ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
+   if (REG_GET_FIELD(tmp, 
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
+   PORT_CONNECTIVITY))
adev->mode_info.audio.pin[i].connected = false;
else
adev->mode_info.audio.pin[i].connected = true;
@@ -1263,45 +1276,206 @@ static struct amdgpu_audio_pin 
*dce_v6_0_audio_get_pin(struct amdgpu_device *ade
return NULL;
 }
 
-static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
+static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
 {
struct amdgpu_device *adev = encoder->dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
-   u32 offset;
 
if (!dig || !dig->afmt || !dig->afmt->pin)
return;
 
-   offset = dig->afmt->offset;
-
-   WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
-  AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
-
+   WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
+  REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
+dig->afmt->pin->id));
 }
 
 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
struct drm_display_mode *mode)
 {
-   DRM_INFO(": dce_v6_0_audio_write_latency_fields---no imp!\n");
+   struct amdgpu_device *adev = encoder->dev->dev_private;
+   struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+   struct drm_connector *connector;
+   struct amdgpu_connector *amdgpu_connector = NULL;
+   int interlace = 0;
+   u32 tmp;
+
+   list_for_each_entry(connector, 
>dev->mode_config.connector_list, head) {
+   if (connector->encoder == encoder) {
+   amdgpu_connector = to_amdgpu_connector(connector);
+   break;
+   }
+   }
+
+   if (!amdgpu_connector) {
+   DRM_ERROR("Couldn't find encoder's connector\n");
+   return;
+   }
+
+   if

RE: [PATCH] drm/amdgpu: bump driver version for new lds buffer query

2017-02-21 Thread Zhang, Jerry 
Hi Alex,

Thanks for your work.
I have pushed the patch...

Regards,
Jerry (Junwei Zhang)

Linux Base Graphics
SRDC Software Development
_


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Alex Deucher
> Sent: Wednesday, February 22, 2017 6:34
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu: bump driver version for new lds buffer query
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 72c33b9..0dd0e2d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -60,9 +60,10 @@
>   * - 3.8.0 - Add support raster config init in the kernel
>   * - 3.9.0 - Add support for memory query info about VRAM and GTT.
>   * - 3.10.0 - Add support for sensor query info (clocks, temp, etc).
> + * - 3.11.0 - Add query for double offchip LDS buffers
>   */
>  #define KMS_DRIVER_MAJOR 3
> -#define KMS_DRIVER_MINOR 10
> +#define KMS_DRIVER_MINOR 11
>  #define KMS_DRIVER_PATCHLEVEL0
> 
>  int amdgpu_vram_limit = 0;
> --
> 2.5.5
> 
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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RE: [PATCH v3 1/1] drm/amdgpu: export gfx config double offchip LDS buffers (v3)

2017-02-21 Thread Zhang, Jerry 
> -Original Message-
> From: Deucher, Alexander
> Sent: Tuesday, February 21, 2017 22:48
> To: Zhang, Jerry; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jerry
> Subject: RE: [PATCH v3 1/1] drm/amdgpu: export gfx config double offchip LDS
> buffers (v3)
> 
> > -Original Message-
> > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Junwei Zhang
> > Sent: Sunday, February 19, 2017 9:51 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Zhang, Jerry
> > Subject: [PATCH v3 1/1] drm/amdgpu: export gfx config double offchip
> > LDS buffers (v3)
> >
> > v2: move the config struct to drm_amdgpu_info_device
> > v3: move the config feature to amdgpu_gca_config
> >
> > Signed-off-by: Junwei Zhang 
> 
> Should bump the drm version as well in amdgpu_drv.c.  With that fixed:
> Reviewed-by: Alex Deucher 

Sorry, I have pushed the patch.
Then prepare another patch to bump the version.

> 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  3 +++
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
> >  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 ++
> >  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  6 ++
> >  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 16 +++-
> >  include/uapi/drm/amdgpu_drm.h   |  2 ++
> >  6 files changed, 34 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 7f1421f..9c552a9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -856,6 +856,9 @@ struct amdgpu_gca_config {
> > uint32_t macrotile_mode_array[16];
> >
> > struct amdgpu_rb_config
> > rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
> > +
> > +   /* gfx configure feature */
> > +   uint32_t double_offchip_lds_buf;
> >  };
> >
> >  struct amdgpu_cu_info {
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index 6b9bf0e..bcc13907d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -545,6 +545,8 @@ static int amdgpu_info_ioctl(struct drm_device
> > *dev, void *data, struct drm_file
> > dev_info.vram_type = adev->mc.vram_type;
> > dev_info.vram_bit_width = adev->mc.vram_width;
> > dev_info.vce_harvest_config = adev->vce.harvest_config;
> > +   dev_info.gc_double_offchip_lds_buf =
> > +   adev->gfx.config.double_offchip_lds_buf;
> >
> > return copy_to_user(out, _info,
> > min((size_t)size, sizeof(dev_info))) ? - 
> > EFAULT :
> 0; diff
> > --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> > index 782190d..138e15a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> > @@ -1579,6 +1579,11 @@ static void gfx_v6_0_setup_spi(struct
> > amdgpu_device *adev)
> > mutex_unlock(>grbm_idx_mutex);
> >  }
> >
> > +static void gfx_v6_0_config_init(struct amdgpu_device *adev) {
> > +   adev->gfx.config.double_offchip_lds_buf = 1; }
> > +
> >  static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)  {
> > u32 gb_addr_config = 0;
> > @@ -1736,6 +1741,7 @@ static void gfx_v6_0_gpu_init(struct
> > amdgpu_device *adev)
> > gfx_v6_0_setup_spi(adev);
> >
> > gfx_v6_0_get_cu_info(adev);
> > +   gfx_v6_0_config_init(adev);
> >
> > WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 <<
> > CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
> >(0x2b <<
> > CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> > index 8e07a50..6e7b273 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> > @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct
> > amdgpu_device *adev)
> > mutex_unlock(>srbm_mutex);
> >  }
> >
> > +static void gfx_v7_0_config_init(struct amdgpu_device *adev) {
> > +   adev->gfx.config.double_offchip_lds_buf = 1; }
> > +
> >  /**
> >   * gfx_v7_0_gpu_init - setup the 3D engine
> >   *
> > @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct
> > amdgpu_device *adev)
> >
> > gfx_v7_0_setup_rb(adev);
> > gfx_v7_0_get_cu_info(adev);
> > +   gfx_v7_0_config_init(adev);
> >
> > /* set HW defaults for 3D engine */
> > WREG32(mmCP_MEQ_THRESHOLDS,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index fdce3de..1533693 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -3846,6 +3846,19 @@ static void gfx_v8_0_init_compute_vmid(struct
> > amdgpu_device *adev)
> > mutex_unlock(>srbm_mutex);
> >  }
> >
> > +static void gfx_v8_0_config_init(struct amdgpu_device

[PATCH] drm/amdgpu: bump driver version for new lds buffer query

2017-02-21 Thread Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 72c33b9..0dd0e2d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -60,9 +60,10 @@
  * - 3.8.0 - Add support raster config init in the kernel
  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
  * - 3.10.0 - Add support for sensor query info (clocks, temp, etc).
+ * - 3.11.0 - Add query for double offchip LDS buffers
  */
 #define KMS_DRIVER_MAJOR   3
-#define KMS_DRIVER_MINOR   10
+#define KMS_DRIVER_MINOR   11
 #define KMS_DRIVER_PATCHLEVEL  0
 
 int amdgpu_vram_limit = 0;
-- 
2.5.5

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Re: [PATCH xf86-video-ati 3/3] present: Wait for screen pixmap BO idle before setting modes for unflip

2017-02-21 Thread Alex Deucher 
On Tue, Feb 21, 2017 at 4:03 AM, Michel Dänzer  wrote:
> From: Michel Dänzer 
>
> To make sure the screen pixmap contents are up to date when it starts
> being scanned out.
>
> Signed-off-by: Michel Dänzer 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  src/radeon_present.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/radeon_present.c b/src/radeon_present.c
> index b36e29b19..1b0ddcb82 100644
> --- a/src/radeon_present.c
> +++ b/src/radeon_present.c
> @@ -404,6 +404,8 @@ modeset:
>  old_fb_id = info->drmmode.fb_id;
>  info->drmmode.fb_id = 0;
>
> +radeon_cs_flush_indirect(scrn);
> +radeon_bo_wait(info->front_bo);
>  for (i = 0; i < config->num_crtc; i++) {
> xf86CrtcPtr crtc = config->crtc[i];
> drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
> --
> 2.11.0
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH v2 xf86-video-ati 3/3] Allow toggling TearFree at runtime via output property

2017-02-21 Thread Alex Deucher 
On Tue, Feb 21, 2017 at 3:17 AM, Michel Dänzer  wrote:
> From: Michel Dänzer 
>
> Option "TearFree" now sets the default value of the output property.
> See the manpage update for details.
>
> TearFree is now enabled by default for outputs using rotation or other
> RandR transforms, and for RandR 1.4 slave outputs.
>
> Signed-off-by: Michel Dänzer 

Series is:
Reviewed-by: Alex Deucher 

> ---
>
> v2: Fix build against xserver 1.10
>
>  man/radeon.man|  15 +++--
>  src/drmmode_display.c | 161 
> +-
>  src/drmmode_display.h |   2 +
>  src/radeon.h  |   2 +-
>  src/radeon_dri2.c |  35 ---
>  src/radeon_kms.c  |  43 +-
>  6 files changed, 216 insertions(+), 42 deletions(-)
>
> diff --git a/man/radeon.man b/man/radeon.man
> index 8990ae21d..5301dd7f0 100644
> --- a/man/radeon.man
> +++ b/man/radeon.man
> @@ -281,10 +281,17 @@ Enable DRI2 page flipping.  The default is
>  Pageflipping is supported on all radeon hardware.
>  .TP
>  .BI "Option \*qTearFree\*q \*q" boolean \*q
> -Enable tearing prevention using the hardware page flipping mechanism. 
> Requires allocating two
> -separate scanout buffers for each CRTC. Enabling this option currently 
> disables Option
> -\*qEnablePageFlip\*q. The default is
> -.B off.
> +Set the default value of the per-output 'TearFree' property, which controls
> +tearing prevention using the hardware page flipping mechanism. TearFree is
> +on for any CRTC associated with one or more outputs with TearFree on. Two
> +separate scanout buffers need to be allocated for each CRTC with TearFree
> +on. While TearFree is on for any CRTC, it currently prevents clients from 
> using
> +DRI page flipping. If this option is set, the default value of the property 
> is
> +'on' or 'off' accordingly. If this option isn't set, the default value of the
> +property is
> +.B auto,
> +which means that TearFree is on for outputs with rotation or other RandR
> +transforms, and for RandR 1.4 slave outputs, otherwise off.
>  .TP
>  .BI "Option \*qAccelMethod\*q \*q" "string" \*q
>  Chooses between available acceleration architectures.  Valid values are
> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
> index fcac1562b..5b0236da4 100644
> --- a/src/drmmode_display.c
> +++ b/src/drmmode_display.c
> @@ -670,6 +670,34 @@ drmmode_can_use_hw_cursor(xf86CrtcPtr crtc)
> return TRUE;
>  }
>
> +static void
> +drmmode_crtc_update_tear_free(xf86CrtcPtr crtc)
> +{
> +   RADEONInfoPtr info = RADEONPTR(crtc->scrn);
> +   xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
> +   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
> +   int i;
> +
> +   drmmode_crtc->tear_free = FALSE;
> +
> +   for (i = 0; i < xf86_config->num_output; i++) {
> +   xf86OutputPtr output = xf86_config->output[i];
> +   drmmode_output_private_ptr drmmode_output = 
> output->driver_private;
> +
> +   if (output->crtc != crtc)
> +   continue;
> +
> +   if (drmmode_output->tear_free == 1 ||
> +   (drmmode_output->tear_free == 2 &&
> +(radeon_is_gpu_screen(crtc->scrn->pScreen) ||
> + info->shadow_primary ||
> + crtc->transformPresent || crtc->rotation != 
> RR_Rotate_0))) {
> +   drmmode_crtc->tear_free = TRUE;
> +   return;
> +   }
> +   }
> +}
> +
>  #if XF86_CRTC_VERSION >= 4
>
>  static Bool
> @@ -683,10 +711,11 @@ drmmode_handle_transform(xf86CrtcPtr crtc)
> else
> crtc->driverIsPerformingTransform = XF86DriverTransformNone;
>  #else
> +   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
> RADEONInfoPtr info = RADEONPTR(crtc->scrn);
>
> crtc->driverIsPerformingTransform = crtc->transformPresent ||
> -   (info->tear_free && crtc->rotation != RR_Rotate_0);
> +   (drmmode_crtc->tear_free && crtc->rotation != RR_Rotate_0);
>  #endif
>
> ret = xf86CrtcRotate(crtc);
> @@ -706,24 +735,87 @@ drmmode_handle_transform(xf86CrtcPtr crtc)
>
>  #endif
>
> +#ifdef RADEON_PIXMAP_SHARING
> +
>  static void
> +drmmode_crtc_prime_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode,
> + unsigned scanout_id, int *fb_id, int *x,
> + int *y)
> +{
> +   ScrnInfoPtr scrn = crtc->scrn;
> +   ScreenPtr screen = scrn->pScreen;
> +   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
> +
> +   if (drmmode_crtc->tear_free &&
> +   !drmmode_crtc->scanout[1].pixmap) {
> +   RegionPtr region;
> +   BoxPtr box;
> +
> +   drmmode_crtc_scanout_create(crtc, _crtc->scanout[1],
> +

RE: [PATCH] drm/amdgpu: add HDMI audio support for si dce6

2017-02-21 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Xiaojie Yuan
> Sent: Tuesday, February 21, 2017 5:40 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yuan, Xiaojie
> Subject: [PATCH] drm/amdgpu: add HDMI audio support for si dce6
> 
> Signed-off-by: Xiaojie Yuan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130
> +++---
>  1 file changed, 121 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index c940bec..1398db6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1531,12 +1531,58 @@ static void dce_v6_0_audio_fini(struct
> amdgpu_device *adev)
>   adev->mode_info.audio.enabled = false;
>  }
> 
> -/*
> -static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder,
> uint32_t clock)
> +static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
>  {
> - DRM_INFO(": dce_v6_0_afmt_update_ACR---no imp!\n");
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_encoder *amdgpu_encoder =
> to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
> >enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt-
> >offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL,
> HDMI_NULL_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL,
> HDMI_GC_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL,
> HDMI_GC_CONT, 1);
> + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset,
> tmp);
> +}
> +
> +static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
> +uint32_t clock, int bpc)
> +{
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
> + struct amdgpu_encoder *amdgpu_encoder =
> to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
> >enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt-
> >offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL,
> HDMI_ACR_AUTO_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL,
> HDMI_ACR_SOURCE,
> + bpc > 8 ? 0 : 1);
> + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset,
> tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32,
> acr.cts_32khz);
> + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32,
> acr.n_32khz);
> + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44,
> acr.cts_44_1khz);
> + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44,
> acr.n_44_1khz);
> + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48,
> acr.cts_48khz);
> + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48,
> acr.n_48khz);
> + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
>  }
> -*/
> 
>  static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder
> *encoder,
>  struct drm_display_mode *mode)
> @@ -1585,6 +1631,7 @@ static void dce_v6_0_audio_set_dto(struct
> drm_encoder *encoder, u32 clock)
>   struct drm_device *dev = encoder->dev;
>   struct amdgpu_device *adev = dev->dev_private;
>   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder-
> >crtc);
> + int em =
> amdgpu_atombios_encoder_get_encoder_mode(encoder);
>   u32 tmp;
> 
>   /*
> @@ -1596,10 +1643,21 @@ static void dce_v6_0_audio_set_dto(struct
> drm_encoder *encoder, u32 clock)
>   tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
>   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
>   DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc-
> >crtc_id);
> - tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> DCCG_AUDIO_DTO_SEL, 1);
> + if (em == ATOM_ENCODER_MODE_HDMI) {
> + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> + DCCG_AUDIO_DTO_SEL, 0);
> + } else if (ENCODER_MODE_IS_DP(em)) {
> + tmp = REG_SET_FIELD(tmp,

Re: [PATCH] drm/amdgpu: add DP audio support for si dce6

2017-02-21 Thread Alex Deucher 
On Tue, Feb 21, 2017 at 10:21 AM, Deucher, Alexander
 wrote:
>> -Original Message-
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Xiaojie Yuan
>> Sent: Monday, February 20, 2017 5:16 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Yuan, Xiaojie
>> Subject: [PATCH] drm/amdgpu: add DP audio support for si dce6
>>
>> Signed-off-by: Xiaojie Yuan 
>> ---
>>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 457
>> +++--
>>  .../drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h |   2 +
>>  2 files changed, 425 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> index 94877cb..ec2f122 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> @@ -118,14 +118,31 @@ static const struct {
>>  static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
>>u32 block_offset, u32 reg)
>>  {
>> - DRM_INFO(": dce_v6_0_audio_endpt_rreg no impl\n");
>> - return 0;
>> + unsigned long flags;
>> + u32 r;
>> +
>> + spin_lock_irqsave(>audio_endpt_idx_lock, flags);
>> + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
>> reg);
>> + r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA +
>> block_offset);
>> + spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
>> +
>> + return r;
>>  }
>>
>>  static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
>> u32 block_offset, u32 reg, u32 v)
>>  {
>> - DRM_INFO(": dce_v6_0_audio_endpt_wreg no impl\n");
>> + unsigned long flags;
>> + u32 tmp;
>> +
>> + spin_lock_irqsave(>audio_endpt_idx_lock, flags);
>> + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_ENDPOINT_INDEX,
>> + AZALIA_ENDPOINT_REG_INDEX, reg);
>> + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_ENDPOINT_INDEX,
>> + AZALIA_ENDPOINT_REG_WRITE_EN, 1);
>> + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
>> tmp);
>> + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset,
>> v);
>> + spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
>>  }
>>
>>  static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
>> @@ -1231,17 +1248,17 @@ static void dce_v6_0_bandwidth_update(struct
>> amdgpu_device *adev)
>>   dce_v6_0_program_watermarks(adev, adev-
>> >mode_info.crtcs[i+1], lb_size, num_heads);
>>   }
>>  }
>> -/*
>> +
>>  static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device
>> *adev)
>>  {
>>   int i;
>> - u32 offset, tmp;
>> + u32 tmp;
>>
>>   for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
>> - offset = adev->mode_info.audio.pin[i].offset;
>> - tmp = RREG32_AUDIO_ENDPT(offset,
>> -
>> AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
>> - if (((tmp & PORT_CONNECTIVITY_MASK) >>
>> PORT_CONNECTIVITY_SHIFT) == 1)
>> + tmp = RREG32_AUDIO_ENDPT(adev-
>> >mode_info.audio.pin[i].offset,
>> +
>>   ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_
>> DEFAULT);
>> + if (REG_GET_FIELD(tmp,
>> AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
>> + PORT_CONNECTIVITY))
>>   adev->mode_info.audio.pin[i].connected = false;
>>   else
>>   adev->mode_info.audio.pin[i].connected = true;
>> @@ -1268,40 +1285,201 @@ static void
>> dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
>>   struct amdgpu_device *adev = encoder->dev->dev_private;
>>   struct amdgpu_encoder *amdgpu_encoder =
>> to_amdgpu_encoder(encoder);
>>   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
>> >enc_priv;
>> - u32 offset;
>>
>>   if (!dig || !dig->afmt || !dig->afmt->pin)
>>   return;
>>
>> - offset = dig->afmt->offset;
>> -
>> - WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
>> -AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
>> -
>> + WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
>> +REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL,
>> AFMT_AUDIO_SRC_SELECT,
>> +  dig->afmt->pin->id));
>>  }
>>
>>  static void dce_v6_0_audio_write_latency_fields(struct drm_encoder
>> *encoder,
>>   struct drm_display_mode
>> *mode)
>>  {
>> - DRM_INFO(": dce_v6_0_audio_write_latency_fields---no
>> imp!\n");
>> + struct amdgpu_device *adev = encoder->dev->dev_private;
>> + struct amdgpu_encoder *amdgpu_encoder =
>> to_amdgpu_encoder(encoder);
>> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
>> >enc_priv;
>> + struct drm_connector *connector;
>> + struct amdgpu_connector *amdgpu_connector = NULL;
>> + int interlace = 0;
>> + u32 tmp;
>>

RE: [PATCH] drm/amdgpu: add DP audio support for si dce6

2017-02-21 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Xiaojie Yuan
> Sent: Monday, February 20, 2017 5:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yuan, Xiaojie
> Subject: [PATCH] drm/amdgpu: add DP audio support for si dce6
> 
> Signed-off-by: Xiaojie Yuan 
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 457
> +++--
>  .../drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h |   2 +
>  2 files changed, 425 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 94877cb..ec2f122 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -118,14 +118,31 @@ static const struct {
>  static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
>u32 block_offset, u32 reg)
>  {
> - DRM_INFO(": dce_v6_0_audio_endpt_rreg no impl\n");
> - return 0;
> + unsigned long flags;
> + u32 r;
> +
> + spin_lock_irqsave(>audio_endpt_idx_lock, flags);
> + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
> reg);
> + r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA +
> block_offset);
> + spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
> +
> + return r;
>  }
> 
>  static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
> u32 block_offset, u32 reg, u32 v)
>  {
> - DRM_INFO(": dce_v6_0_audio_endpt_wreg no impl\n");
> + unsigned long flags;
> + u32 tmp;
> +
> + spin_lock_irqsave(>audio_endpt_idx_lock, flags);
> + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_ENDPOINT_INDEX,
> + AZALIA_ENDPOINT_REG_INDEX, reg);
> + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_ENDPOINT_INDEX,
> + AZALIA_ENDPOINT_REG_WRITE_EN, 1);
> + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
> tmp);
> + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset,
> v);
> + spin_unlock_irqrestore(>audio_endpt_idx_lock, flags);
>  }
> 
>  static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
> @@ -1231,17 +1248,17 @@ static void dce_v6_0_bandwidth_update(struct
> amdgpu_device *adev)
>   dce_v6_0_program_watermarks(adev, adev-
> >mode_info.crtcs[i+1], lb_size, num_heads);
>   }
>  }
> -/*
> +
>  static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device
> *adev)
>  {
>   int i;
> - u32 offset, tmp;
> + u32 tmp;
> 
>   for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
> - offset = adev->mode_info.audio.pin[i].offset;
> - tmp = RREG32_AUDIO_ENDPT(offset,
> -
> AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
> - if (((tmp & PORT_CONNECTIVITY_MASK) >>
> PORT_CONNECTIVITY_SHIFT) == 1)
> + tmp = RREG32_AUDIO_ENDPT(adev-
> >mode_info.audio.pin[i].offset,
> +
>   ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_
> DEFAULT);
> + if (REG_GET_FIELD(tmp,
> AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
> + PORT_CONNECTIVITY))
>   adev->mode_info.audio.pin[i].connected = false;
>   else
>   adev->mode_info.audio.pin[i].connected = true;
> @@ -1268,40 +1285,201 @@ static void
> dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
>   struct amdgpu_device *adev = encoder->dev->dev_private;
>   struct amdgpu_encoder *amdgpu_encoder =
> to_amdgpu_encoder(encoder);
>   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
> >enc_priv;
> - u32 offset;
> 
>   if (!dig || !dig->afmt || !dig->afmt->pin)
>   return;
> 
> - offset = dig->afmt->offset;
> -
> - WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
> -AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
> -
> + WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
> +REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL,
> AFMT_AUDIO_SRC_SELECT,
> +  dig->afmt->pin->id));
>  }
> 
>  static void dce_v6_0_audio_write_latency_fields(struct drm_encoder
> *encoder,
>   struct drm_display_mode
> *mode)
>  {
> - DRM_INFO(": dce_v6_0_audio_write_latency_fields---no
> imp!\n");
> + struct amdgpu_device *adev = encoder->dev->dev_private;
> + struct amdgpu_encoder *amdgpu_encoder =
> to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
> >enc_priv;
> + struct drm_connector *connector;
> + struct amdgpu_connector *amdgpu_connector = NULL;
> + int interlace = 0;
> + u32 tmp;
> +
> + list_for_each_entry(connector, >dev-
> >mode_config.connector_list, head) {
> + if (connector->encoder == encoder) {
> + amdgpu_connector =
>

RE: [PATCH v3 1/1] drm/amdgpu: export gfx config double offchip LDS buffers (v3)

2017-02-21 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Junwei Zhang
> Sent: Sunday, February 19, 2017 9:51 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jerry
> Subject: [PATCH v3 1/1] drm/amdgpu: export gfx config double offchip LDS
> buffers (v3)
> 
> v2: move the config struct to drm_amdgpu_info_device
> v3: move the config feature to amdgpu_gca_config
> 
> Signed-off-by: Junwei Zhang 

Should bump the drm version as well in amdgpu_drv.c.  With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  3 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  6 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 16 +++-
>  include/uapi/drm/amdgpu_drm.h   |  2 ++
>  6 files changed, 34 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 7f1421f..9c552a9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -856,6 +856,9 @@ struct amdgpu_gca_config {
>   uint32_t macrotile_mode_array[16];
> 
>   struct amdgpu_rb_config
> rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
> +
> + /* gfx configure feature */
> + uint32_t double_offchip_lds_buf;
>  };
> 
>  struct amdgpu_cu_info {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 6b9bf0e..bcc13907d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -545,6 +545,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
> void *data, struct drm_file
>   dev_info.vram_type = adev->mc.vram_type;
>   dev_info.vram_bit_width = adev->mc.vram_width;
>   dev_info.vce_harvest_config = adev->vce.harvest_config;
> + dev_info.gc_double_offchip_lds_buf =
> + adev->gfx.config.double_offchip_lds_buf;
> 
>   return copy_to_user(out, _info,
>   min((size_t)size, sizeof(dev_info))) ? -
> EFAULT : 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 782190d..138e15a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1579,6 +1579,11 @@ static void gfx_v6_0_setup_spi(struct
> amdgpu_device *adev)
>   mutex_unlock(>grbm_idx_mutex);
>  }
> 
> +static void gfx_v6_0_config_init(struct amdgpu_device *adev)
> +{
> + adev->gfx.config.double_offchip_lds_buf = 1;
> +}
> +
>  static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>  {
>   u32 gb_addr_config = 0;
> @@ -1736,6 +1741,7 @@ static void gfx_v6_0_gpu_init(struct
> amdgpu_device *adev)
>   gfx_v6_0_setup_spi(adev);
> 
>   gfx_v6_0_get_cu_info(adev);
> + gfx_v6_0_config_init(adev);
> 
>   WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 <<
> CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
>  (0x2b <<
> CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 8e07a50..6e7b273 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct
> amdgpu_device *adev)
>   mutex_unlock(>srbm_mutex);
>  }
> 
> +static void gfx_v7_0_config_init(struct amdgpu_device *adev)
> +{
> + adev->gfx.config.double_offchip_lds_buf = 1;
> +}
> +
>  /**
>   * gfx_v7_0_gpu_init - setup the 3D engine
>   *
> @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct
> amdgpu_device *adev)
> 
>   gfx_v7_0_setup_rb(adev);
>   gfx_v7_0_get_cu_info(adev);
> + gfx_v7_0_config_init(adev);
> 
>   /* set HW defaults for 3D engine */
>   WREG32(mmCP_MEQ_THRESHOLDS,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index fdce3de..1533693 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3846,6 +3846,19 @@ static void gfx_v8_0_init_compute_vmid(struct
> amdgpu_device *adev)
>   mutex_unlock(>srbm_mutex);
>  }
> 
> +static void gfx_v8_0_config_init(struct amdgpu_device *adev)
> +{
> + switch (adev->asic_type) {
> + default:
> + adev->gfx.config.double_offchip_lds_buf = 1;
> + break;
> + case CHIP_CARRIZO:
> + case CHIP_STONEY:
> + adev->gfx.config.double_offchip_lds_buf = 0;
> + break;
> + }
> +}
> +
>  static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
>  {
>   u32 tmp, sh_static_mem_cfg;
> @@ -3859,6 +3872,7 @@ static void gfx_v8_0_gpu_init(struct
> amdgpu_device *adev)
>

Re: [PATCH 00/11] remove fb_location programming

2017-02-21 Thread Alex Deucher 
On Tue, Feb 21, 2017 at 1:47 AM, Zhang, Jerry  wrote:
> Hi Alex,
>
> The series of patch is Reviewed-by: Junwei Zhang 
>
>> Tested this on CI and VI.  Works fine with DAL/DC. With the legacy display 
>> path,
>> VCE fails to initialize (ECPU won't come out of reset).
>> Any ideas?
>
> Did you met the issue in VI?

Yes.

> It looks that you're missing vce v3.0 changes for mc_resume.
> Please confirm it.

What changes did you have in mind?  The changes for vce2.0 are not
necessary for vce3.0 since it was programmed properly from the
beginning as far as I understand it.

Alex

>
> Regards,
> Jerry (Junwei Zhang)
>
> Linux Base Graphics
> SRDC Software Development
> _
>
>
>> -Original Message-
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
>> Alex Deucher
>> Sent: Saturday, February 18, 2017 7:08
>> To: amd-gfx list
>> Cc: Deucher, Alexander
>> Subject: Re: [PATCH 00/11] remove fb_location programming
>>
>> On Fri, Feb 17, 2017 at 3:38 PM, Alex Deucher  wrote:
>> > Since evergreen, the vbios has programmed the FB_LOCATION to the
>> > proper size during asic_init, so there is no need to reprogram them in the 
>> > driver.
>> > We can safely leave the location as set by the vbios.  This simplifies
>> > the driver significantly.
>>
>> Tested this on CI and VI.  Works fine with DAL/DC. With the legacy display 
>> path,
>> VCE fails to initialize (ECPU won't come out of reset).
>> Any ideas?
>>
>> Alex
>>
>> >
>> > Alex Deucher (11):
>> >   drm/amdgpu/vce2: fix vce bar programming
>> >   drm/amdgpu: put gtt at 0 in the internal address space
>> >   drm/amdgpu/gmc8: use the vram location programmed by the vbios
>> >   drm/amdgpu/gmc7: use the vram location programmed by the vbios
>> >   drm/amdgpu/gmc6: use the vram location programmed by the vbios
>> >   drm/amdgpu/gmc8: drop fb location programming
>> >   drm/amdgpu/gmc7: drop fb location programming
>> >   drm/amdgpu/gmc6: drop fb location programming
>> >   drm/amdgpu: drop set_vga_render_state from display funcs (v2)
>> >   drm/amdgpu: remove *_mc_access from display funcs (v2)
>> >   drm/amd/dc/dm: remove redundant display structs
>> >
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   4 -
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   8 +-
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  12 --
>> >  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 135 
>> > +-
>> >  drivers/gpu/drm/amd/amdgpu/dce_v10_0.h|   6 -
>> >  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  80 +
>> >  drivers/gpu/drm/amd/amdgpu/dce_v11_0.h|   6 -
>> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 115 --
>> >  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  82 +
>> >  drivers/gpu/drm/amd/amdgpu/dce_v8_0.h |   6 -
>> >  drivers/gpu/drm/amd/amdgpu/dce_virtual.c  |  97 +++-
>> >  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  38 ++
>> >  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  35 ++
>> >  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  34 ++
>> >  drivers/gpu/drm/amd/amdgpu/vce_v2_0.c |  17 +--
>> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  75 +---
>> >  16 files changed, 83 insertions(+), 667 deletions(-)
>> >
>> > --
>> > 2.5.5
>> >
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: add HDMI audio support for si dce6

2017-02-21 Thread Christian König 
Not much of an issue, but when sending out a second version of a patch 
we usually put a v2 on the subject line to indicate that.


Additional to that the patch also needs at least a little bit of commit 
message.


With that fixed it is Acked-by: Christian König .

Regards,
Christian.

Am 21.02.2017 um 13:08 schrieb Edward O'Callaghan:

Reviewed-by: Edward O'Callaghan 

On 02/21/2017 09:39 PM, Xiaojie Yuan wrote:

Signed-off-by: Xiaojie Yuan 
---
  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130 +++---
  1 file changed, 121 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index c940bec..1398db6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1531,12 +1531,58 @@ static void dce_v6_0_audio_fini(struct amdgpu_device 
*adev)
adev->mode_info.audio.enabled = false;
  }
  
-/*

-static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t 
clock)
+static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
  {
-   DRM_INFO(": dce_v6_0_afmt_update_ACR---no imp!\n");
+   struct drm_device *dev = encoder->dev;
+   struct amdgpu_device *adev = dev->dev_private;
+   struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+   u32 tmp;
+
+   tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
+   tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
+   tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
+   WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
+}
+
+static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
+  uint32_t clock, int bpc)
+{
+   struct drm_device *dev = encoder->dev;
+   struct amdgpu_device *adev = dev->dev_private;
+   struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
+   struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+   u32 tmp;
+
+   tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 
1);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
+   bpc > 8 ? 0 : 1);
+   WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
+
+   tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
+   WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
+   tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
+   WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
+
+   tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, 
acr.cts_44_1khz);
+   WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
+   tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
+   WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
+
+   tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
+   WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
+   tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
+   WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
  }
-*/
  
  static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,

   struct drm_display_mode *mode)
@@ -1585,6 +1631,7 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
*encoder, u32 clock)
struct drm_device *dev = encoder->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
+   int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
u32 tmp;
  
  	/*

@@ -1596,10 +1643,21 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
*encoder, u32 clock)
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
-   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 1);
+   if (em == ATOM_ENCODER_MODE_HDMI) {
+   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
+   DCCG_AUDIO_DTO_SEL, 0);
+   } else if (ENCODER_MODE_IS_DP(em)) {
+   tmp =

Re: [PATCH] drm/amdgpu: add HDMI audio support for si dce6

2017-02-21 Thread Edward O'Callaghan 
Reviewed-by: Edward O'Callaghan 

On 02/21/2017 09:39 PM, Xiaojie Yuan wrote:
> Signed-off-by: Xiaojie Yuan 
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130 
> +++---
>  1 file changed, 121 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index c940bec..1398db6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1531,12 +1531,58 @@ static void dce_v6_0_audio_fini(struct amdgpu_device 
> *adev)
>   adev->mode_info.audio.enabled = false;
>  }
>  
> -/*
> -static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t 
> clock)
> +static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
>  {
> - DRM_INFO(": dce_v6_0_afmt_update_ACR---no imp!\n");
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
> + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
> +}
> +
> +static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
> +uint32_t clock, int bpc)
> +{
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
> + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 
> 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
> + bpc > 8 ? 0 : 1);
> + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
> + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
> + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, 
> acr.cts_44_1khz);
> + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
> + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
> + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
> + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
>  }
> -*/
>  
>  static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
>  struct drm_display_mode *mode)
> @@ -1585,6 +1631,7 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
> *encoder, u32 clock)
>   struct drm_device *dev = encoder->dev;
>   struct amdgpu_device *adev = dev->dev_private;
>   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
> + int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
>   u32 tmp;
>  
>   /*
> @@ -1596,10 +1643,21 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
> *encoder, u32 clock)
>   tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
>   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
>   DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
> - tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 1);
> + if (em == ATOM_ENCODER_MODE_HDMI) {
> + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> + DCCG_AUDIO_DTO_SEL, 0);
> + } else if (ENCODER_MODE_IS_DP(em)) {
> + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> + DCCG_AUDIO_DTO_SEL, 1);
> + }
>   WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
> - WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
> - WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
> + if (em == ATOM_ENCODER_MODE_HDMI) {
> +

Re: [PATCH] drm/amdgpu: refuse to reserve io mem for split VRAM buffers

2017-02-21 Thread Nicolai Hähnle 

On 17.02.2017 11:08, Christian König wrote:

Am 17.02.2017 um 00:21 schrieb Nicolai Hähnle:

We may still have other bugs with split BOs, though.


Yeah, agree as well. I was also considering disabling that feature by
default for the moment if it helps with your corruption bug.


The corruption still occurs with amdgpu.vram_page_split = -1, unfortunately.

Cheers,
Nicolai
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RE: [PATCH v2] amdgpu: export gfx double offchip LDS buffers by dev info

2017-02-21 Thread Zhang, Jerry 
> -Original Message-
> From: Christian König [mailto:deathsim...@vodafone.de]
> Sent: Tuesday, February 21, 2017 17:23
> To: Zhang, Jerry; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2] amdgpu: export gfx double offchip LDS buffers by dev
> info
> 
> Am 21.02.2017 um 03:19 schrieb Junwei Zhang:
> > Signed-off-by: Junwei Zhang 
> 
> Reviewed-by: Christian König .
> 
> But wait before pushing it upstream for the kernel change to land upstream as
> well.

Sure, thanks.

> 
> Regards,
> Christian.
> 
> > ---
> >   include/drm/amdgpu_drm.h | 2 ++
> >   1 file changed, 2 insertions(+)
> >
> > diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index
> > 9c3bd18..85bb701 100644
> > --- a/include/drm/amdgpu_drm.h
> > +++ b/include/drm/amdgpu_drm.h
> > @@ -767,6 +767,8 @@ struct drm_amdgpu_info_device {
> > uint32_t vram_bit_width;
> > /* vce harvesting instance */
> > uint32_t vce_harvest_config;
> > +   /* gfx double offchip LDS buffers */
> > +   uint32_t gc_double_offchip_lds_buf;
> >   };
> >
> >   struct drm_amdgpu_info_hw_ip {
> 

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Re: [PATCH v2] amdgpu: export gfx double offchip LDS buffers by dev info

2017-02-21 Thread Christian König 

Am 21.02.2017 um 03:19 schrieb Junwei Zhang:

Signed-off-by: Junwei Zhang 


Reviewed-by: Christian König .

But wait before pushing it upstream for the kernel change to land 
upstream as well.


Regards,
Christian.


---
  include/drm/amdgpu_drm.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 9c3bd18..85bb701 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -767,6 +767,8 @@ struct drm_amdgpu_info_device {
uint32_t vram_bit_width;
/* vce harvesting instance */
uint32_t vce_harvest_config;
+   /* gfx double offchip LDS buffers */
+   uint32_t gc_double_offchip_lds_buf;
  };
  
  struct drm_amdgpu_info_hw_ip {



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Re: [PATCH] drm/amdgpu: rename amdgpu_gca_config to amdgpu_gfx_config

2017-02-21 Thread Christian König 

Am 21.02.2017 um 03:35 schrieb Junwei Zhang:

Signed-off-by: Junwei Zhang 


Reviewed-by: Christian König .


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e2d583c..d0c0009 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -827,7 +827,7 @@ struct amdgpu_rb_config {
uint32_t raster_config_1;
  };
  
-struct amdgpu_gca_config {

+struct amdgpu_gfx_config {
unsigned max_shader_engines;
unsigned max_tile_pipes;
unsigned max_cu_per_sh;
@@ -879,7 +879,7 @@ struct amdgpu_gfx_funcs {
  
  struct amdgpu_gfx {

struct mutexgpu_clock_mutex;
-   struct amdgpu_gca_configconfig;
+   struct amdgpu_gfx_configconfig;
struct amdgpu_rlc   rlc;
struct amdgpu_mec   mec;
struct amdgpu_kiq   kiq;



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[PATCH xf86-video-ati 2/3] present: Only call drmModeRmFB after setting modes for unflip

2017-02-21 Thread Michel Dänzer 
From: Michel Dänzer 

Fixes display intermittently blanking when a modeset is used for unflip.

Signed-off-by: Michel Dänzer 
---
 src/radeon_present.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/radeon_present.c b/src/radeon_present.c
index 29800fec0..b36e29b19 100644
--- a/src/radeon_present.c
+++ b/src/radeon_present.c
@@ -371,6 +371,7 @@ radeon_present_unflip(ScreenPtr screen, uint64_t event_id)
 struct radeon_present_vblank_event *event;
 PixmapPtr pixmap = screen->GetScreenPixmap(screen);
 uint32_t handle;
+int old_fb_id;
 int i;
 
 if (!radeon_present_check_unflip(scrn))
@@ -400,7 +401,7 @@ modeset:
 /* info->drmmode.fb_id still points to the FB for the last flipped BO.
  * Clear it, drmmode_set_mode_major will re-create it
  */
-drmModeRmFB(info->drmmode.fd, info->drmmode.fb_id);
+old_fb_id = info->drmmode.fb_id;
 info->drmmode.fb_id = 0;
 
 for (i = 0; i < config->num_crtc; i++) {
@@ -417,6 +418,7 @@ modeset:
drmmode_crtc->need_modeset = TRUE;
 }
 
+drmModeRmFB(info->drmmode.fd, old_fb_id);
 present_event_notify(event_id, 0, 0);
 
 info->drmmode.present_flipping = FALSE;
-- 
2.11.0

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[PATCH xf86-video-ati 1/3] Use drmmode_crtc_scanout_free in drmmode_fini

2017-02-21 Thread Michel Dänzer 
From: Michel Dänzer 

We were leaking drmmode_crtc->scanout_damage, which caused trouble on
server reset. Fixes server reset with active separate scanout pixmaps.

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 5b0236da4..fd22a19ba 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -2618,13 +2618,8 @@ void drmmode_fini(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
 #endif
}
 
-   for (c = 0; c < config->num_crtc; c++) {
-   xf86CrtcPtr crtc = config->crtc[c];
-   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
-
-   drmmode_crtc_scanout_destroy(>drmmode, 
_crtc->scanout[0]);
-   drmmode_crtc_scanout_destroy(>drmmode, 
_crtc->scanout[1]);
-   }
+   for (c = 0; c < config->num_crtc; c++)
+   drmmode_crtc_scanout_free(config->crtc[c]->driver_private);
 }
 
 
-- 
2.11.0

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[PATCH xf86-video-ati 3/3] present: Wait for screen pixmap BO idle before setting modes for unflip

2017-02-21 Thread Michel Dänzer 
From: Michel Dänzer 

To make sure the screen pixmap contents are up to date when it starts
being scanned out.

Signed-off-by: Michel Dänzer 
---
 src/radeon_present.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/radeon_present.c b/src/radeon_present.c
index b36e29b19..1b0ddcb82 100644
--- a/src/radeon_present.c
+++ b/src/radeon_present.c
@@ -404,6 +404,8 @@ modeset:
 old_fb_id = info->drmmode.fb_id;
 info->drmmode.fb_id = 0;
 
+radeon_cs_flush_indirect(scrn);
+radeon_bo_wait(info->front_bo);
 for (i = 0; i < config->num_crtc; i++) {
xf86CrtcPtr crtc = config->crtc[i];
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
-- 
2.11.0

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[PATCH xf86-video-ati 0/3] Misc fixes

2017-02-21 Thread Michel Dänzer 
From: Michel Dänzer 

Miscellaneous fixes for minor problems I stumbled across while working
on the previous series.

Michel Dänzer (3):
  Use drmmode_crtc_scanout_free in drmmode_fini
  present: Only call drmModeRmFB after setting modes for unflip
  present: Wait for screen pixmap BO idle before setting modes for
unflip

 src/drmmode_display.c | 9 ++---
 src/radeon_present.c  | 6 +-
 2 files changed, 7 insertions(+), 8 deletions(-)

-- 
2.11.0

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[PATCH v2 xf86-video-ati 3/3] Allow toggling TearFree at runtime via output property

2017-02-21 Thread Michel Dänzer 
From: Michel Dänzer 

Option "TearFree" now sets the default value of the output property.
See the manpage update for details.

TearFree is now enabled by default for outputs using rotation or other
RandR transforms, and for RandR 1.4 slave outputs.

Signed-off-by: Michel Dänzer 
---

v2: Fix build against xserver 1.10

 man/radeon.man|  15 +++--
 src/drmmode_display.c | 161 +-
 src/drmmode_display.h |   2 +
 src/radeon.h  |   2 +-
 src/radeon_dri2.c |  35 ---
 src/radeon_kms.c  |  43 +-
 6 files changed, 216 insertions(+), 42 deletions(-)

diff --git a/man/radeon.man b/man/radeon.man
index 8990ae21d..5301dd7f0 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -281,10 +281,17 @@ Enable DRI2 page flipping.  The default is
 Pageflipping is supported on all radeon hardware.
 .TP
 .BI "Option \*qTearFree\*q \*q" boolean \*q
-Enable tearing prevention using the hardware page flipping mechanism. Requires 
allocating two
-separate scanout buffers for each CRTC. Enabling this option currently 
disables Option
-\*qEnablePageFlip\*q. The default is
-.B off.
+Set the default value of the per-output 'TearFree' property, which controls
+tearing prevention using the hardware page flipping mechanism. TearFree is
+on for any CRTC associated with one or more outputs with TearFree on. Two
+separate scanout buffers need to be allocated for each CRTC with TearFree
+on. While TearFree is on for any CRTC, it currently prevents clients from using
+DRI page flipping. If this option is set, the default value of the property is
+'on' or 'off' accordingly. If this option isn't set, the default value of the
+property is
+.B auto,
+which means that TearFree is on for outputs with rotation or other RandR
+transforms, and for RandR 1.4 slave outputs, otherwise off.
 .TP
 .BI "Option \*qAccelMethod\*q \*q" "string" \*q
 Chooses between available acceleration architectures.  Valid values are
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index fcac1562b..5b0236da4 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -670,6 +670,34 @@ drmmode_can_use_hw_cursor(xf86CrtcPtr crtc)
return TRUE;
 }
 
+static void
+drmmode_crtc_update_tear_free(xf86CrtcPtr crtc)
+{
+   RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+   xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
+   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+   int i;
+
+   drmmode_crtc->tear_free = FALSE;
+
+   for (i = 0; i < xf86_config->num_output; i++) {
+   xf86OutputPtr output = xf86_config->output[i];
+   drmmode_output_private_ptr drmmode_output = 
output->driver_private;
+
+   if (output->crtc != crtc)
+   continue;
+
+   if (drmmode_output->tear_free == 1 ||
+   (drmmode_output->tear_free == 2 &&
+(radeon_is_gpu_screen(crtc->scrn->pScreen) ||
+ info->shadow_primary ||
+ crtc->transformPresent || crtc->rotation != 
RR_Rotate_0))) {
+   drmmode_crtc->tear_free = TRUE;
+   return;
+   }
+   }
+}
+
 #if XF86_CRTC_VERSION >= 4
 
 static Bool
@@ -683,10 +711,11 @@ drmmode_handle_transform(xf86CrtcPtr crtc)
else
crtc->driverIsPerformingTransform = XF86DriverTransformNone;
 #else
+   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
 
crtc->driverIsPerformingTransform = crtc->transformPresent ||
-   (info->tear_free && crtc->rotation != RR_Rotate_0);
+   (drmmode_crtc->tear_free && crtc->rotation != RR_Rotate_0);
 #endif
 
ret = xf86CrtcRotate(crtc);
@@ -706,24 +735,87 @@ drmmode_handle_transform(xf86CrtcPtr crtc)
 
 #endif
 
+#ifdef RADEON_PIXMAP_SHARING
+
 static void
+drmmode_crtc_prime_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode,
+ unsigned scanout_id, int *fb_id, int *x,
+ int *y)
+{
+   ScrnInfoPtr scrn = crtc->scrn;
+   ScreenPtr screen = scrn->pScreen;
+   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+   if (drmmode_crtc->tear_free &&
+   !drmmode_crtc->scanout[1].pixmap) {
+   RegionPtr region;
+   BoxPtr box;
+
+   drmmode_crtc_scanout_create(crtc, _crtc->scanout[1],
+   mode->HDisplay,
+   mode->VDisplay);
+   region = _crtc->scanout_last_region;
+   RegionUninit(region);
+   region->data = NULL;
+   box = RegionExtents(region);
+   box->x1 = crtc->x;
+   box->y1 = crtc->y;
+   box->x2 = crtc->x + mode->HDisplay;
+