Re: [PATCH v2 2/2] drm/amdgpu: export test ring debugfs interface

[Huang Rui]

On Thu, May 11, 2017 at 02:41:56PM +0800, Christian König wrote:
> Am 11.05.2017 um 07:42 schrieb Huang Rui:
> > Signed-off-by: Huang Rui 
> > ---
> >
> > V1 -> V2:
> > - park the scheduler thread for each ring to avoid conflict with commands
> from
> >active apps.
> >
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50
> --
> >   1 file changed, 48 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> > b/drivers/gpu/drm/amd
> /amdgpu/amdgpu_device.c
> > index 19ac196..04a63b5 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -3643,14 +3643,60 @@ static int amdgpu_debugfs_test_ib(struct seq_file 
> > *m,
> void *data)
> >return 0;
> >   }
> >  
> > +static int amdgpu_ring_tests(struct amdgpu_device *adev)
> > +{
> > + unsigned i;
> > + int r = 0;
> > +
> > + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
> > + struct amdgpu_ring *ring = adev->rings[i];
> > +
> > + if (!ring || !ring->ready || !ring->sched.thread)
> > + continue;
> > +
> > + /* hold on the scheduler */
> > + kthread_park(ring->sched.thread);
> > +
> > + r = amdgpu_ring_test_ring(ring);
> > + if (r) {
> > + ring->ready = false;
> 
> Don't mess with the ready flag here.
> 
> > + DRM_ERROR("amdgpu: failed to test ring %d (%d).\n",
> > +   i, r);
> > + }
> > +
> > + /* go on the scheduler */
> > + kthread_unpark(ring->sched.thread);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static int amdgpu_debugfs_test_ring(struct seq_file *m, void *data)
> > +{
> > + struct drm_info_node *node = (struct drm_info_node *) m->private;
> > + struct drm_device *dev = node->minor->dev;
> > + struct amdgpu_device *adev = dev->dev_private;
> > + int r = 0;
> > +
> > + seq_printf(m, "run ring test:\n");
> > + r = amdgpu_ring_tests(adev);
> 
> Why a separate function for this?
> 

I think it might be re-used by other side in future.

> Additional to that I agree with Dave that when we have the IB test the
> ring test is not necessary any more.
> 
> We just do this on boot/resume separately to be able to narrow down
> problems faster when we see in the logs that one fails but the other
> succeeds.
> 

Yeah, you know, we only want to expose ib test orignally. When I write that
codes, I found the ring tests are also able to re-use the debugfs list. :)

Is there anything that might break the ring at runtime? If not, I can drop
this patch.

Thanks,
Rui
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 01/11] drm/ttm: cleanup coding style in ttm_bo_api.h

[Michel Dänzer]

On 10/05/17 08:43 PM, Christian König wrote:
> Ping, could anybody take a look at this set?

For the series:

Reviewed-by: Michel Dänzer 


Might be worth converting e.g. ttm_bo_move_ttm to a context parameter as
well?

Also, I wonder if the two booleans couldn't be converted to enums or
something, so that one wouldn't always need to look up the struct
ttm_operation_ctx definition to know what they mean.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH xf86-video-ati] Remove unused struct members from drmmode_display.h

[Michel Dänzer]

From: Michel Dänzer 

(Ported from amdgpu commit 462ac3341e5bfbded9086d3d9043821d19352b3e)

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 1 -
 src/drmmode_display.h | 2 --
 2 files changed, 3 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index e2899cf50..d0ecfa855 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -2540,7 +2540,6 @@ Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr 
drmmode, int cpp)
xf86CrtcConfigInit(pScrn, &drmmode_xf86crtc_config_funcs);
 
drmmode->scrn = pScrn;
-   drmmode->cpp = cpp;
mode_res = drmModeGetResources(drmmode->fd);
if (!mode_res)
return FALSE;
diff --git a/src/drmmode_display.h b/src/drmmode_display.h
index df2c4b7bb..db68054a7 100644
--- a/src/drmmode_display.h
+++ b/src/drmmode_display.h
@@ -41,8 +41,6 @@
 
 typedef struct {
   int fd;
-  drmModeFBPtr mode_fb;
-  int cpp;
   struct radeon_bo_manager *bufmgr;
   ScrnInfoPtr scrn;
 #ifdef HAVE_LIBUDEV
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: fix NULL pointer panic of emit_gds_switch

[Chunming Zhou]

[  338.384770] BUG: unable to handle kernel NULL pointer dereference at 
  (null)
[  338.384817] IP: [<  (null)>]   (null)
[  338.384843] PGD 0

[  338.384865] Oops: 0010 [#1] SMP
[  338.384881] Modules linked in: amdgpu(OE) ttm(OE) drm_kms_helper(E) drm(E) 
i2c_algo_bit(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E) sysimgblt(E) 
rpcsec_gss_krb5(E) nfsv4(E) nfs(E) fscache(E) snd_hda_codec_realtek(E) 
snd_hda_codec_generic(E) snd_hda_codec_hdmi(E) snd_hda_intel(E) 
snd_hda_codec(E) eeepc_wmi(E) joydev(E) asus_wmi(E) sparse_keymap(E) video(E) 
snd_hda_core(E) snd_hwdep(E) snd_pcm(E) snd_seq_midi(E) snd_seq_midi_event(E) 
snd_rawmidi(E) snd_seq(E) snd_seq_device(E) snd_timer(E) snd(E) soundcore(E) 
kvm(E) irqbypass(E) crct10dif_pclmul(E) crc32_pclmul(E) ghash_clmulni_intel(E) 
aesni_intel(E) aes_x86_64(E) lrw(E) shpchp(E) gf128mul(E) glue_helper(E) 
8250_dw(E) ablk_helper(E) i2c_piix4(E) cryptd(E) serio_raw(E) 
i2c_designware_platform(E) mac_hid(E) i2c_designware_core(E) nfsd(E) 
auth_rpcgss(E)
[  338.385293]  nfs_acl(E) lockd(E) grace(E) sunrpc(E) parport_pc(E) ppdev(E) 
lp(E) parport(E) autofs4(E) hid_generic(E) usbhid(E) hid(E) psmouse(E) r8169(E) 
ahci(E) mii(E) libahci(E) wmi(E)
[  338.385395] CPU: 10 PID: 1477 Comm: sdma0 Tainted: G   OE   
4.9.0-custom #4
[  338.385432] Hardware name: System manufacturer System Product Name/PRIME 
B350-PLUS, BIOS 0606 04/06/2017
[  338.385477] task: 88020924 task.stack: c90001bd4000
[  338.385505] RIP: 0010:[<>]  [<  (null)>]   
(null)
[  338.385543] RSP: 0018:c90001bd7d40  EFLAGS: 00010202
[  338.385568] RAX: a072c280 RBX: 8801d420f400 RCX: 4000
[  338.385602] RDX:  RSI: 0005 RDI: 880212376018
[  338.385635] RBP: c90001bd7da8 R08:  R09: 4000
[  338.385669] R10:  R11: 0002 R12: 88021237
[  338.385702] R13: 880212370e90 R14: 880212376018 R15: 0001
[  338.385738] FS:  () GS:88021ee8() 
knlGS:
[  338.385776] CS:  0010 DS:  ES:  CR0: 80050033
[  338.385803] CR2:  CR3: 000212352000 CR4: 003406e0
[  338.385834] Stack:
[  338.385843]  a05d2313  c9004000 
811818d3
[  338.385879]  0018 880212370a18 01ffc900 
8801bc5f2e00
[  338.385915]  8801d420f400 880212376018  
0001
[  338.385950] Call Trace:
[  338.385993]  [] ? amdgpu_vm_flush+0x283/0x400 [amdgpu]
[  338.386025]  [] ? printk+0x4d/0x4f
[  338.386074]  [] amdgpu_ib_schedule+0x4a6/0x4d0 [amdgpu]
[  338.386140]  [] amdgpu_job_run+0x64/0x180 [amdgpu]
[  338.386203]  [] amd_sched_main+0x2e9/0x4a0 [amdgpu]
[  338.386232]  [] ? prepare_to_wait_event+0x110/0x110
[  338.386295]  [] ? amd_sched_select_entity+0xe0/0xe0 
[amdgpu]
[  338.386327]  [] kthread+0xd3/0xf0
[  338.386349]  [] ? kthread_park+0x60/0x60
[  338.386376]  [] ret_from_fork+0x25/0x30
[  338.386401] Code:  Bad RIP value.
[  338.386420] RIP  [<  (null)>]   (null)
[  338.386443]  RSP 
[  338.386458] CR2: 
[  338.398508] ---[ end trace 4c66fcdc74b9a0a2 ]---

Change-Id: I0867463a9ec13d0f16b7f95bcca218cd42c3e867
Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 84aba1a..bca1fb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -783,7 +783,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job)
mutex_unlock(&id_mgr->lock);
}
 
-   if (gds_switch_needed) {
+   if (ring->funcs->emit_gds_switch && gds_switch_needed) {
id->gds_base = job->gds_base;
id->gds_size = job->gds_size;
id->gws_base = job->gws_base;
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: fix NULL pointer panic of emit_gds_switch

[Christian König]

Am 11.05.2017 um 12:27 schrieb Chunming Zhou:

[  338.384770] BUG: unable to handle kernel NULL pointer dereference at 
  (null)
[  338.384817] IP: [<  (null)>]   (null)
[  338.384843] PGD 0

[  338.384865] Oops: 0010 [#1] SMP
[  338.384881] Modules linked in: amdgpu(OE) ttm(OE) drm_kms_helper(E) drm(E) 
i2c_algo_bit(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E) sysimgblt(E) 
rpcsec_gss_krb5(E) nfsv4(E) nfs(E) fscache(E) snd_hda_codec_realtek(E) 
snd_hda_codec_generic(E) snd_hda_codec_hdmi(E) snd_hda_intel(E) 
snd_hda_codec(E) eeepc_wmi(E) joydev(E) asus_wmi(E) sparse_keymap(E) video(E) 
snd_hda_core(E) snd_hwdep(E) snd_pcm(E) snd_seq_midi(E) snd_seq_midi_event(E) 
snd_rawmidi(E) snd_seq(E) snd_seq_device(E) snd_timer(E) snd(E) soundcore(E) 
kvm(E) irqbypass(E) crct10dif_pclmul(E) crc32_pclmul(E) ghash_clmulni_intel(E) 
aesni_intel(E) aes_x86_64(E) lrw(E) shpchp(E) gf128mul(E) glue_helper(E) 
8250_dw(E) ablk_helper(E) i2c_piix4(E) cryptd(E) serio_raw(E) 
i2c_designware_platform(E) mac_hid(E) i2c_designware_core(E) nfsd(E) 
auth_rpcgss(E)
[  338.385293]  nfs_acl(E) lockd(E) grace(E) sunrpc(E) parport_pc(E) ppdev(E) 
lp(E) parport(E) autofs4(E) hid_generic(E) usbhid(E) hid(E) psmouse(E) r8169(E) 
ahci(E) mii(E) libahci(E) wmi(E)
[  338.385395] CPU: 10 PID: 1477 Comm: sdma0 Tainted: G   OE   
4.9.0-custom #4
[  338.385432] Hardware name: System manufacturer System Product Name/PRIME 
B350-PLUS, BIOS 0606 04/06/2017
[  338.385477] task: 88020924 task.stack: c90001bd4000
[  338.385505] RIP: 0010:[<>]  [<  (null)>]   
(null)
[  338.385543] RSP: 0018:c90001bd7d40  EFLAGS: 00010202
[  338.385568] RAX: a072c280 RBX: 8801d420f400 RCX: 4000
[  338.385602] RDX:  RSI: 0005 RDI: 880212376018
[  338.385635] RBP: c90001bd7da8 R08:  R09: 4000
[  338.385669] R10:  R11: 0002 R12: 88021237
[  338.385702] R13: 880212370e90 R14: 880212376018 R15: 0001
[  338.385738] FS:  () GS:88021ee8() 
knlGS:
[  338.385776] CS:  0010 DS:  ES:  CR0: 80050033
[  338.385803] CR2:  CR3: 000212352000 CR4: 003406e0
[  338.385834] Stack:
[  338.385843]  a05d2313  c9004000 
811818d3
[  338.385879]  0018 880212370a18 01ffc900 
8801bc5f2e00
[  338.385915]  8801d420f400 880212376018  
0001
[  338.385950] Call Trace:
[  338.385993]  [] ? amdgpu_vm_flush+0x283/0x400 [amdgpu]
[  338.386025]  [] ? printk+0x4d/0x4f
[  338.386074]  [] amdgpu_ib_schedule+0x4a6/0x4d0 [amdgpu]
[  338.386140]  [] amdgpu_job_run+0x64/0x180 [amdgpu]
[  338.386203]  [] amd_sched_main+0x2e9/0x4a0 [amdgpu]
[  338.386232]  [] ? prepare_to_wait_event+0x110/0x110
[  338.386295]  [] ? amd_sched_select_entity+0xe0/0xe0 
[amdgpu]
[  338.386327]  [] kthread+0xd3/0xf0
[  338.386349]  [] ? kthread_park+0x60/0x60
[  338.386376]  [] ret_from_fork+0x25/0x30
[  338.386401] Code:  Bad RIP value.
[  338.386420] RIP  [<  (null)>]   (null)
[  338.386443]  RSP 
[  338.386458] CR2: 
[  338.398508] ---[ end trace 4c66fcdc74b9a0a2 ]---

Change-Id: I0867463a9ec13d0f16b7f95bcca218cd42c3e867
Signed-off-by: Chunming Zhou 


Shorten the commit message a bit, with that fixed the patch is 
Reviewed-by: Christian König 



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 84aba1a..bca1fb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -783,7 +783,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job)
mutex_unlock(&id_mgr->lock);
}
  
-	if (gds_switch_needed) {

+   if (ring->funcs->emit_gds_switch && gds_switch_needed) {
id->gds_base = job->gds_base;
id->gds_size = job->gds_size;
id->gws_base = job->gws_base;



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH xf86-video-ati] Remove unused struct members from drmmode_display.h

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Thursday, May 11, 2017 6:03 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-ati] Remove unused struct members from
> drmmode_display.h
> 
> From: Michel Dänzer 
> 
> (Ported from amdgpu commit
> 462ac3341e5bfbded9086d3d9043821d19352b3e)
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  src/drmmode_display.c | 1 -
>  src/drmmode_display.h | 2 --
>  2 files changed, 3 deletions(-)
> 
> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
> index e2899cf50..d0ecfa855 100644
> --- a/src/drmmode_display.c
> +++ b/src/drmmode_display.c
> @@ -2540,7 +2540,6 @@ Bool drmmode_pre_init(ScrnInfoPtr pScrn,
> drmmode_ptr drmmode, int cpp)
>   xf86CrtcConfigInit(pScrn, &drmmode_xf86crtc_config_funcs);
> 
>   drmmode->scrn = pScrn;
> - drmmode->cpp = cpp;
>   mode_res = drmModeGetResources(drmmode->fd);
>   if (!mode_res)
>   return FALSE;
> diff --git a/src/drmmode_display.h b/src/drmmode_display.h
> index df2c4b7bb..db68054a7 100644
> --- a/src/drmmode_display.h
> +++ b/src/drmmode_display.h
> @@ -41,8 +41,6 @@
> 
>  typedef struct {
>int fd;
> -  drmModeFBPtr mode_fb;
> -  int cpp;
>struct radeon_bo_manager *bufmgr;
>ScrnInfoPtr scrn;
>  #ifdef HAVE_LIBUDEV
> --
> 2.11.0
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: fix NULL pointer panic of emit_gds_switch

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Chunming Zhou
> Sent: Thursday, May 11, 2017 6:28 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou, David(ChunMing)
> Subject: [PATCH] drm/amdgpu: fix NULL pointer panic of emit_gds_switch
> 
> [  338.384770] BUG: unable to handle kernel NULL pointer dereference at
> (null)
> [  338.384817] IP: [<  (null)>]   (null)
> [  338.384843] PGD 0
> 
> [  338.384865] Oops: 0010 [#1] SMP
> [  338.384881] Modules linked in: amdgpu(OE) ttm(OE) drm_kms_helper(E)
> drm(E) i2c_algo_bit(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E)
> sysimgblt(E) rpcsec_gss_krb5(E) nfsv4(E) nfs(E) fscache(E)
> snd_hda_codec_realtek(E) snd_hda_codec_generic(E)
> snd_hda_codec_hdmi(E) snd_hda_intel(E) snd_hda_codec(E) eeepc_wmi(E)
> joydev(E) asus_wmi(E) sparse_keymap(E) video(E) snd_hda_core(E)
> snd_hwdep(E) snd_pcm(E) snd_seq_midi(E) snd_seq_midi_event(E)
> snd_rawmidi(E) snd_seq(E) snd_seq_device(E) snd_timer(E) snd(E)
> soundcore(E) kvm(E) irqbypass(E) crct10dif_pclmul(E) crc32_pclmul(E)
> ghash_clmulni_intel(E) aesni_intel(E) aes_x86_64(E) lrw(E) shpchp(E)
> gf128mul(E) glue_helper(E) 8250_dw(E) ablk_helper(E) i2c_piix4(E) cryptd(E)
> serio_raw(E) i2c_designware_platform(E) mac_hid(E)
> i2c_designware_core(E) nfsd(E) auth_rpcgss(E)
> [  338.385293]  nfs_acl(E) lockd(E) grace(E) sunrpc(E) parport_pc(E) ppdev(E)
> lp(E) parport(E) autofs4(E) hid_generic(E) usbhid(E) hid(E) psmouse(E)
> r8169(E) ahci(E) mii(E) libahci(E) wmi(E)
> [  338.385395] CPU: 10 PID: 1477 Comm: sdma0 Tainted: G   OE   4.9.0-
> custom #4
> [  338.385432] Hardware name: System manufacturer System Product
> Name/PRIME B350-PLUS, BIOS 0606 04/06/2017
> [  338.385477] task: 88020924 task.stack: c90001bd4000
> [  338.385505] RIP: 0010:[<>]  [<  (null)>]   
> (null)
> [  338.385543] RSP: 0018:c90001bd7d40  EFLAGS: 00010202
> [  338.385568] RAX: a072c280 RBX: 8801d420f400 RCX:
> 4000
> [  338.385602] RDX:  RSI: 0005 RDI:
> 880212376018
> [  338.385635] RBP: c90001bd7da8 R08:  R09:
> 4000
> [  338.385669] R10:  R11: 0002 R12:
> 88021237
> [  338.385702] R13: 880212370e90 R14: 880212376018 R15:
> 0001
> [  338.385738] FS:  () GS:88021ee8()
> knlGS:
> [  338.385776] CS:  0010 DS:  ES:  CR0: 80050033
> [  338.385803] CR2:  CR3: 000212352000 CR4:
> 003406e0
> [  338.385834] Stack:
> [  338.385843]  a05d2313  c9004000
> 811818d3
> [  338.385879]  0018 880212370a18 01ffc900
> 8801bc5f2e00
> [  338.385915]  8801d420f400 880212376018 
> 0001
> [  338.385950] Call Trace:
> [  338.385993]  [] ? amdgpu_vm_flush+0x283/0x400
> [amdgpu]
> [  338.386025]  [] ? printk+0x4d/0x4f
> [  338.386074]  [] amdgpu_ib_schedule+0x4a6/0x4d0
> [amdgpu]
> [  338.386140]  [] amdgpu_job_run+0x64/0x180 [amdgpu]
> [  338.386203]  [] amd_sched_main+0x2e9/0x4a0
> [amdgpu]
> [  338.386232]  [] ? prepare_to_wait_event+0x110/0x110
> [  338.386295]  [] ? amd_sched_select_entity+0xe0/0xe0
> [amdgpu]
> [  338.386327]  [] kthread+0xd3/0xf0
> [  338.386349]  [] ? kthread_park+0x60/0x60
> [  338.386376]  [] ret_from_fork+0x25/0x30
> [  338.386401] Code:  Bad RIP value.
> [  338.386420] RIP  [<  (null)>]   (null)
> [  338.386443]  RSP 
> [  338.386458] CR2: 
> [  338.398508] ---[ end trace 4c66fcdc74b9a0a2 ]---
> 
> Change-Id: I0867463a9ec13d0f16b7f95bcca218cd42c3e867
> Signed-off-by: Chunming Zhou 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 84aba1a..bca1fb5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -783,7 +783,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
> struct amdgpu_job *job)
>   mutex_unlock(&id_mgr->lock);
>   }
> 
> - if (gds_switch_needed) {
> + if (ring->funcs->emit_gds_switch && gds_switch_needed) {
>   id->gds_base = job->gds_base;
>   id->gds_size = job->gds_size;
>   id->gws_base = job->gws_base;
> --
> 1.9.1
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: cleanup VM manager init/fini

[Christian König]

From: Christian König 

VM is mandatory for all hw amdgpu supports. So remove the leftovers
to make it optionally.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  3 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  2 -
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 59 
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 82 -
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 82 -
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 80 
 6 files changed, 78 insertions(+), 230 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 6778ea5..c8b037a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -571,9 +571,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
uint64_t va_flags;
int r = 0;
 
-   if (!adev->vm_manager.enabled)
-   return -ENOTTY;
-
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
dev_err(&dev->pdev->dev,
"va_address 0x%lX is in reserved area 0x%X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 27546df..afe9073 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -173,8 +173,6 @@ struct amdgpu_vm_manager {
uint32_tblock_size;
/* vram base address for page table entry  */
u64 vram_base_offset;
-   /* is vm enabled? */
-   boolenabled;
/* vm pte handling */
const struct amdgpu_vm_pte_funcs*vm_pte_funcs;
struct amdgpu_ring  *vm_pte_rings[AMDGPU_MAX_RINGS];
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index d860939..1e6263a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -614,33 +614,6 @@ static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
amdgpu_gart_fini(adev);
 }
 
-static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
-{
-   /*
-* number of VMs
-* VMID 0 is reserved for System
-* amdgpu graphics/compute will use VMIDs 1-7
-* amdkfd will use VMIDs 8-15
-*/
-   adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
-   adev->vm_manager.num_level = 1;
-   amdgpu_vm_manager_init(adev);
-
-   /* base offset of vram pages */
-   if (adev->flags & AMD_IS_APU) {
-   u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
-   tmp <<= 22;
-   adev->vm_manager.vram_base_offset = tmp;
-   } else
-   adev->vm_manager.vram_base_offset = 0;
-
-   return 0;
-}
-
-static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
-{
-}
-
 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 u32 status, u32 addr, u32 mc_client)
 {
@@ -887,26 +860,34 @@ static int gmc_v6_0_sw_init(void *handle)
if (r)
return r;
 
-   if (!adev->vm_manager.enabled) {
-   r = gmc_v6_0_vm_init(adev);
-   if (r) {
-   dev_err(adev->dev, "vm manager initialization failed 
(%d).\n", r);
-   return r;
-   }
-   adev->vm_manager.enabled = true;
+   /*
+* number of VMs
+* VMID 0 is reserved for System
+* amdgpu graphics/compute will use VMIDs 1-7
+* amdkfd will use VMIDs 8-15
+*/
+   adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
+   adev->vm_manager.num_level = 1;
+   amdgpu_vm_manager_init(adev);
+
+   /* base offset of vram pages */
+   if (adev->flags & AMD_IS_APU) {
+   u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
+
+   tmp <<= 22;
+   adev->vm_manager.vram_base_offset = tmp;
+   } else {
+   adev->vm_manager.vram_base_offset = 0;
}
 
-   return r;
+   return 0;
 }
 
 static int gmc_v6_0_sw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-   if (adev->vm_manager.enabled) {
-   gmc_v6_0_vm_fini(adev);
-   adev->vm_manager.enabled = false;
-   }
+   amdgpu_vm_manager_fini(adev);
gmc_v6_0_gart_fini(adev);
amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 2750e5c..967505b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -724,55 +724,6 @@ static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
amdgpu_gart_fini(adev);
 }
 
-/*
- * vm
- * VMID 0 is the physical GPU addresses 

RE: [PATCH] drm/amdgpu: cleanup VM manager init/fini

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Thursday, May 11, 2017 10:22 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: cleanup VM manager init/fini
> 
> From: Christian König 
> 
> VM is mandatory for all hw amdgpu supports. So remove the leftovers
> to make it optionally.
> 
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  3 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  2 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 59 
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 82 ---
> --
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 82 ---
> --
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 80 ---
> -
>  6 files changed, 78 insertions(+), 230 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 6778ea5..c8b037a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -571,9 +571,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
> void *data,
>   uint64_t va_flags;
>   int r = 0;
> 
> - if (!adev->vm_manager.enabled)
> - return -ENOTTY;
> -
>   if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
>   dev_err(&dev->pdev->dev,
>   "va_address 0x%lX is in reserved area 0x%X\n",
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 27546df..afe9073 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -173,8 +173,6 @@ struct amdgpu_vm_manager {
>   uint32_tblock_size;
>   /* vram base address for page table entry  */
>   u64 vram_base_offset;
> - /* is vm enabled? */
> - boolenabled;
>   /* vm pte handling */
>   const struct amdgpu_vm_pte_funcs*vm_pte_funcs;
>   struct amdgpu_ring
> *vm_pte_rings[AMDGPU_MAX_RINGS];
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index d860939..1e6263a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -614,33 +614,6 @@ static void gmc_v6_0_gart_fini(struct
> amdgpu_device *adev)
>   amdgpu_gart_fini(adev);
>  }
> 
> -static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
> -{
> - /*
> -  * number of VMs
> -  * VMID 0 is reserved for System
> -  * amdgpu graphics/compute will use VMIDs 1-7
> -  * amdkfd will use VMIDs 8-15
> -  */
> - adev->vm_manager.id_mgr[0].num_ids =
> AMDGPU_NUM_OF_VMIDS;
> - adev->vm_manager.num_level = 1;
> - amdgpu_vm_manager_init(adev);
> -
> - /* base offset of vram pages */
> - if (adev->flags & AMD_IS_APU) {
> - u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
> - tmp <<= 22;
> - adev->vm_manager.vram_base_offset = tmp;
> - } else
> - adev->vm_manager.vram_base_offset = 0;
> -
> - return 0;
> -}
> -
> -static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
> -{
> -}
> -
>  static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
>u32 status, u32 addr, u32 mc_client)
>  {
> @@ -887,26 +860,34 @@ static int gmc_v6_0_sw_init(void *handle)
>   if (r)
>   return r;
> 
> - if (!adev->vm_manager.enabled) {
> - r = gmc_v6_0_vm_init(adev);
> - if (r) {
> - dev_err(adev->dev, "vm manager initialization failed
> (%d).\n", r);
> - return r;
> - }
> - adev->vm_manager.enabled = true;
> + /*
> +  * number of VMs
> +  * VMID 0 is reserved for System
> +  * amdgpu graphics/compute will use VMIDs 1-7
> +  * amdkfd will use VMIDs 8-15
> +  */
> + adev->vm_manager.id_mgr[0].num_ids =
> AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.num_level = 1;
> + amdgpu_vm_manager_init(adev);
> +
> + /* base offset of vram pages */
> + if (adev->flags & AMD_IS_APU) {
> + u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
> +
> + tmp <<= 22;
> + adev->vm_manager.vram_base_offset = tmp;
> + } else {
> + adev->vm_manager.vram_base_offset = 0;
>   }
> 
> - return r;
> + return 0;
>  }
> 
>  static int gmc_v6_0_sw_fini(void *handle)
>  {
>   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> - if (adev->vm_manager.enabled) {
> - gmc_v6_0_vm_fini(adev);
> - adev->vm_manager.enabled = false;
> - }
> + amdgpu_vm_manager_fini(adev);
>   gmc_v6_0_gart_fini(adev);
>   amdgpu_gem_force_release(adev);
>   am

Re: [PATCH v2 2/2] drm/amdgpu: export test ring debugfs interface

[Christian König]

Am 11.05.2017 um 09:35 schrieb Huang Rui:

On Thu, May 11, 2017 at 02:41:56PM +0800, Christian König wrote:

Am 11.05.2017 um 07:42 schrieb Huang Rui:

Signed-off-by: Huang Rui 
---

V1 -> V2:
- park the scheduler thread for each ring to avoid conflict with commands

from

active apps.

---
   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50

--

   1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd

/amdgpu/amdgpu_device.c

index 19ac196..04a63b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3643,14 +3643,60 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m,

void *data)

return 0;
   }
  
+static int amdgpu_ring_tests(struct amdgpu_device *adev)

+{
+ unsigned i;
+ int r = 0;
+
+ for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+ struct amdgpu_ring *ring = adev->rings[i];
+
+ if (!ring || !ring->ready || !ring->sched.thread)
+ continue;
+
+ /* hold on the scheduler */
+ kthread_park(ring->sched.thread);
+
+ r = amdgpu_ring_test_ring(ring);
+ if (r) {
+ ring->ready = false;

Don't mess with the ready flag here.


+ DRM_ERROR("amdgpu: failed to test ring %d (%d).\n",
+   i, r);
+ }
+
+ /* go on the scheduler */
+ kthread_unpark(ring->sched.thread);
+ }
+
+ return r;
+}
+
+static int amdgpu_debugfs_test_ring(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+ int r = 0;
+
+ seq_printf(m, "run ring test:\n");
+ r = amdgpu_ring_tests(adev);

Why a separate function for this?


I think it might be re-used by other side in future.


Well in this case we should create the function when we actually use it 
and not just because a possible use some times in the future.



Additional to that I agree with Dave that when we have the IB test the
ring test is not necessary any more.

We just do this on boot/resume separately to be able to narrow down
problems faster when we see in the logs that one fails but the other
succeeds.


Yeah, you know, we only want to expose ib test orignally. When I write that
codes, I found the ring tests are also able to re-use the debugfs list. :)

Is there anything that might break the ring at runtime? If not, I can drop
this patch.


Yeah, the ring tests messes with the ready flags, so I would rather drop 
this patch.


Christian.



Thanks,
Rui



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 1/1] amdgpu: move asic id table to a separate file

[Li, Samuel]

Good catch!

Sam

From: Yuan, Xiaojie
Sent: Thursday, May 11, 2017 6:51 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] amdgpu: move asic id table to a separate file


Hi Samuel,



Here's an off-by-one error:

+   id = asic_id_table + table_size -1;



should be:

+   id = asic_id_table + table_size;



Regards,

Xiaojie


From: Li, Samuel
Sent: Thursday, May 11, 2017 4:56:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Yuan, Xiaojie; Li, Samuel
Subject: [PATCH 1/1] amdgpu: move asic id table to a separate file

From: Xiaojie Yuan mailto:xiaojie.y...@amd.com>>

Change-Id: I12216da14910f5e2b0970bc1fafc2a20b0ef1ba9
Signed-off-by: Samuel Li mailto:samuel...@amd.com>>
---
 amdgpu/Makefile.am   |   2 +
 amdgpu/Makefile.sources  |   2 +-
 amdgpu/amdgpu_asic_id.c  | 198 +++
 amdgpu/amdgpu_asic_id.h  | 165 ---
 amdgpu/amdgpu_device.c   |  28 +--
 amdgpu/amdgpu_internal.h |  10 +++
 6 files changed, 232 insertions(+), 173 deletions(-)
 create mode 100644 amdgpu/amdgpu_asic_id.c
 delete mode 100644 amdgpu/amdgpu_asic_id.h

diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
index cf7bc1b..ecf9e82 100644
--- a/amdgpu/Makefile.am
+++ b/amdgpu/Makefile.am
@@ -30,6 +30,8 @@ AM_CFLAGS = \
 $(PTHREADSTUBS_CFLAGS) \
 -I$(top_srcdir)/include/drm

+AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${datadir}/libdrm/amdgpu.ids\"
+
 libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
 libdrm_amdgpu_ladir = $(libdir)
 libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined
diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources
index 487b9e0..bc3abaa 100644
--- a/amdgpu/Makefile.sources
+++ b/amdgpu/Makefile.sources
@@ -1,5 +1,5 @@
 LIBDRM_AMDGPU_FILES := \
-   amdgpu_asic_id.h \
+   amdgpu_asic_id.c \
 amdgpu_bo.c \
 amdgpu_cs.c \
 amdgpu_device.c \
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
new file mode 100644
index 000..d50e21a
--- /dev/null
+++ b/amdgpu/amdgpu_asic_id.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
+{
+   char *buf;
+   char *s_did;
+   char *s_rid;
+   char *s_name;
+   char *endptr;
+   int r = 0;
+
+   buf = strdup(line);
+   if (!buf)
+   return -ENOMEM;
+
+   /* ignore empty line and commented line */
+   if (strlen(line) == 0 || line[0] == '#') {
+   r = -EAGAIN;
+   goto out;
+   }
+
+   /* device id */
+   s_did = strtok(buf, ",");
+   if (!s_did) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->did = strtol(s_did, &endptr, 16);
+   if (*endptr) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   /* revision id */
+   s_rid = strtok(NULL, ",");
+   if (!s_rid) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->rid = strtol(s_rid, &endptr, 16);
+   if (*endptr) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   /* marketing name */
+   s_name = strtok(NULL, ",");
+   if (!s_name) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->marketing_name = strdup(s_name);
+   if (id->marketing_name == NULL) {
+   r = -EINVAL;
+   goto out;
+   }
+
+out:
+   free(buf);
+
+   return r;
+}
+
+int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_as

Re: [PATCH 1/1] amdgpu: move asic id table to a separate file

[Yuan, Xiaojie]

Hi Samuel,


Here's an off-by-one error:

+   id = asic_id_table + table_size -1;


should be:

+   id = asic_id_table + table_size;


Regards,

Xiaojie


From: Li, Samuel
Sent: Thursday, May 11, 2017 4:56:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Yuan, Xiaojie; Li, Samuel
Subject: [PATCH 1/1] amdgpu: move asic id table to a separate file

From: Xiaojie Yuan 

Change-Id: I12216da14910f5e2b0970bc1fafc2a20b0ef1ba9
Signed-off-by: Samuel Li 
---
 amdgpu/Makefile.am   |   2 +
 amdgpu/Makefile.sources  |   2 +-
 amdgpu/amdgpu_asic_id.c  | 198 +++
 amdgpu/amdgpu_asic_id.h  | 165 ---
 amdgpu/amdgpu_device.c   |  28 +--
 amdgpu/amdgpu_internal.h |  10 +++
 6 files changed, 232 insertions(+), 173 deletions(-)
 create mode 100644 amdgpu/amdgpu_asic_id.c
 delete mode 100644 amdgpu/amdgpu_asic_id.h

diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
index cf7bc1b..ecf9e82 100644
--- a/amdgpu/Makefile.am
+++ b/amdgpu/Makefile.am
@@ -30,6 +30,8 @@ AM_CFLAGS = \
 $(PTHREADSTUBS_CFLAGS) \
 -I$(top_srcdir)/include/drm

+AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${datadir}/libdrm/amdgpu.ids\"
+
 libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
 libdrm_amdgpu_ladir = $(libdir)
 libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined
diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources
index 487b9e0..bc3abaa 100644
--- a/amdgpu/Makefile.sources
+++ b/amdgpu/Makefile.sources
@@ -1,5 +1,5 @@
 LIBDRM_AMDGPU_FILES := \
-   amdgpu_asic_id.h \
+   amdgpu_asic_id.c \
 amdgpu_bo.c \
 amdgpu_cs.c \
 amdgpu_device.c \
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
new file mode 100644
index 000..d50e21a
--- /dev/null
+++ b/amdgpu/amdgpu_asic_id.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright © 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
+{
+   char *buf;
+   char *s_did;
+   char *s_rid;
+   char *s_name;
+   char *endptr;
+   int r = 0;
+
+   buf = strdup(line);
+   if (!buf)
+   return -ENOMEM;
+
+   /* ignore empty line and commented line */
+   if (strlen(line) == 0 || line[0] == '#') {
+   r = -EAGAIN;
+   goto out;
+   }
+
+   /* device id */
+   s_did = strtok(buf, ",");
+   if (!s_did) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->did = strtol(s_did, &endptr, 16);
+   if (*endptr) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   /* revision id */
+   s_rid = strtok(NULL, ",");
+   if (!s_rid) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->rid = strtol(s_rid, &endptr, 16);
+   if (*endptr) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   /* marketing name */
+   s_name = strtok(NULL, ",");
+   if (!s_name) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->marketing_name = strdup(s_name);
+   if (id->marketing_name == NULL) {
+   r = -EINVAL;
+   goto out;
+   }
+
+out:
+   free(buf);
+
+   return r;
+}
+
+int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table)
+{
+   struct amdgpu_asic_id *asic_id_table;
+   struct amdgpu_asic_id *id;
+   FILE *fp;
+   char *line = NULL;
+   size_t len;
+   ssize_t n;
+   int line_num = 1;
+   size_t table_size = 0;
+   size_t table_max_size = 256;
+   int r = 0;

Raven support added to umr

[Tom St Denis]

Hi all,

I've pushed out a large commit which adds raven support to umr.  Since 
it's quite large I've bypassed the list.


The commit can be seen here:

https://cgit.freedesktop.org/amd/umr/commit/?id=6acc89e4ec159de470af1ec1b9f53d4e97c562bb

Cheers,
Tom
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/4] drm/amd/powerplay/smu7: disable mclk switching for high refresh rates

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index d745065..98a1463 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2793,7 +2793,8 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
 
disable_mclk_switching = ((1 < info.display_count) ||
  disable_mclk_switching_for_frame_lock ||
- smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us));
+ smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us) ||
+ (mode_info.refresh_rate > 120));
 
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/4] drm/amdgpu/ci: disable mclk switching for high refresh rates

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 6dc1410..eb5d03b 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -906,6 +906,12 @@ static bool ci_dpm_vblank_too_short(struct amdgpu_device 
*adev)
u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 
300;
 
+   /* disable mclk switching if the refresh is >120Hz, even if the
+* blanking period would allow it
+*/
+   if (amdgpu_dpm_get_vrefresh(adev) > 120)
+   return false;
+
if (vblank_time < switch_limit)
return true;
else
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/4] drm/amd/powerplay/smu7: add vblank check for mclk switching

[Alex Deucher]

Check to make sure the vblank period is long enough to support
mclk switching.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 31 +---
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a74a3db..d745065 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2655,6 +2655,28 @@ static int smu7_get_power_state_size(struct pp_hwmgr 
*hwmgr)
return sizeof(struct smu7_power_state);
 }
 
+static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
+uint32_t vblank_time_us)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   uint32_t switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
+
+   switch (hwmgr->chip_id) {
+   case CHIP_POLARIS10:
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS12:
+   switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
+   break;
+   default:
+   switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
+   break;
+   }
+
+   if (vblank_time_us < switch_limit_us)
+   return true;
+   else
+   return false;
+}
 
 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *request_ps,
@@ -2669,6 +2691,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
bool disable_mclk_switching;
bool disable_mclk_switching_for_frame_lock;
struct cgs_display_info info = {0};
+   struct cgs_mode_info mode_info = {0};
const struct phm_clock_and_voltage_limits *max_limits;
uint32_t i;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -2677,6 +2700,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
int32_t count;
int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
 
+   info.mode_info = &mode_info;
data->battery_state = (PP_StateUILabel_Battery ==
request_ps->classification.ui_label);
 
@@ -2703,8 +2727,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
 
cgs_get_active_displays_info(hwmgr->device, &info);
 
-   /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
-
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
 
@@ -2769,8 +2791,9 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,

PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
 
 
-   disable_mclk_switching = (1 < info.display_count) ||
-   disable_mclk_switching_for_frame_lock;
+   disable_mclk_switching = ((1 < info.display_count) ||
+ disable_mclk_switching_for_frame_lock ||
+ smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us));
 
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/4] drm/radeon/ci: disable mclk switching for high refresh rates

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/ci_dpm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 7ba4508..5ced733 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -776,6 +776,12 @@ bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
u32 vblank_time = r600_dpm_get_vblank_time(rdev);
u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 
+   /* disable mclk switching if the refresh is >120Hz, even if the
+* blanking period would allow it
+*/
+   if (r600_dpm_get_vrefresh(rdev) > 120)
+   return false;
+
if (vblank_time < switch_limit)
return true;
else
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Testing dc-drm-next-atomic-wip

[Ernst Sjöstrand]

Hi,

this is more feedback about how the code works and runs rather than
what you're really looking for, so I thought I'd start a new thread.
:-)

I get the following error when compiling and (obviously) forgetting to
enable the new DC option.
I see the option will be removed, so maybe that doesn't matter?

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c: In function ‘amdgpu_device_init’:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1956:6: error: ‘struct
amdgpu_device’ has no member named ‘dm_state’; did you mean
‘mm_stats’?
  adev->dm_state = kzalloc(sizeof(*adev->dm_state), GFP_KERNEL);
  ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1956:39: error: ‘struct
amdgpu_device’ has no member named ‘dm_state’; did you mean
‘mm_stats’?
  adev->dm_state = kzalloc(sizeof(*adev->dm_state), GFP_KERNEL);
   ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1957:10: error: ‘struct
amdgpu_device’ has no member named ‘dm_state’; did you mean
‘mm_stats’?
  if (adev->dm_state == NULL)
  ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1959:6: error: ‘struct
amdgpu_device’ has no member named ‘dm_state’; did you mean
‘mm_stats’?
  adev->dm_state->dev = adev;
  ^~

Btw, perhaps you should add a dc-wip-something tag under versions in bugzilla?

Regards
//Ernst


2017-05-03 16:13 GMT+02:00 Harry Wentland :
> Hi all,
>
> Over the last few months we (mostly Andrey and myself) have taken and
> addressed some of the feedback received from December's DC RFC. A lot of our
> work so far centers around atomic. We were able to take a whole bunch of the
> areas where we rolled our own solution and use DRM atomic helpers instead.
>
> You can find our most recent drm-next based tree at
> https://cgit.freedesktop.org/~hwentland/linux/log/?h=dc-drm-next-atomic-wip
>
> An outline of the changes with commit hashes from that tree are listed
> below. They aren't necessarily in order but are grouped by functionality.
>
> I would like to solicit input on the changes and the current state of
> amd/display in general.
>
> I'm on IRC every weekday from 9-5 eastern time, sometimes at other hours.
> Feel free to ask questions, discuss, leave comments. Let me know if there's
> anything else I can do to facilitate review.
>
> We know there's more work to be done but would much rather prioritize that
> work based on community feedback than merely our own impressions.
>
> We haven't finished plumbing drm types to the dc types yet, and there are
> still a bunch of other things in progress.  We are not looking to re-hash
> the previous discussion, but rather we'd like some feedback on our work so
> far.
>
> The list of changes (trimmed commit tags):
>
> == Use common helpers for pageflip ==
> 144da239b047 Use pflip prepare and submit parts (v2)
> ff7ac264a9a1 Fix page flip after daniel's acquire_ctx change
>
>
> == implement atomic_get_properties ==
> cf4a84df7189 Fallback on legacy properties in atomic_get_properties
> 01f96706b6ca get_atomic_property missing for drm_connector_funcs
>
>
> == Use common helpers for gamma ==
> 3f547d7098de Use atomic helpers for gamma
>
>
> == Use atomic helpers for commit ==
> 41831f55bd58 Refactor atomic commit implementation. (v2)
> 6c67dd3c5cd5 Refactor headless to use atomic commit.
> eb22ef1ecb16 Remove page_fleep_needed function.
>
>
> == Use atomic helpers for S3 ==
> 5a6ae6f76249 Switch to DRM helpers in s3.
>
>
> == Simmplify mapping between DRM and DC objects ==
> 84a3ee023b9b Remove get_connector_for_link.
> 6d8978a98b40 Remove get_connector_for_sink.
>
>
> == Use DRM EDID read instead of DC ==
> 566969dacfad Fix i2c write flag.
> 527c3699ff3c Refactor edid read.
> 5ac51023d275 Fix missing irq refactor causing potential i2c race
>
>
> == Save DC validate_ctx in atomic_check and use in commit ==
> 8c194d8e4ee9 pull commit_surfaces out of atomic_commit into helper function
> 27eef98b38c8 Return context from validate_context
> ca3ee10e915b Add DM global atomic state
> 8ba1ca856532 Hook dm private state into atomic_check
> 10160455ac6d Add correct retain/release for objs in dm_atomic_state
> 0f1b2e2aecbb Commit validation set from state
> 258e6a91fc61 Add validate_context to atomic_state
> 64f569b5df20 Use validate_context from atomic_check in commit
>
>
> == Start multi-plane implementation ==
> 601ff4e70b7c decouple per-crtc-plane model
> a0b859a0b114 Fix cleanup in amdgpu_dm_initialize_drm_device
> ee02010d7a82 update plane functionalities
> 3b7345fd1abb Allow planes on all crtcs
> d9cf37462156 initialize YUV plane capabilities
> 248f06b2613e Universal cursor plane hook-up.
>
>
> == Minor cleanups ==
> d99bf02cb8fc Rename atomic_commit parameter.
> f15fb9726502 Use amdgpu mode funcs statically
> d3e37fa70643 Remove unused define from amdgpu_dm_types
> 80a38ad58125 Add lock around updating freesync property
> 8c7f16853824 Use new drm_dp_find_vcpi_slots to compute slots
>
> Regards,
> Harry
> ___
> amd-gfx mailing list
> amd-gfx@list

Re: [PATCH 000/117] Raven Support

[Christian König]

Am 10.05.2017 um 21:30 schrieb Deucher, Alexander:

-Original Message-
From: Christian König [mailto:deathsim...@vodafone.de]
Sent: Wednesday, May 10, 2017 3:29 PM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH 000/117] Raven Support

Am 10.05.2017 um 20:45 schrieb Alex Deucher:

This patch set adds support for the new "Raven" APU.

The first 12 patches add support for the new ACP
audio hardware on Raven. Patches 11 and 12 are not
meant for upstream, they are for early hardware testing.
The rest add GPU support.  Patches 17-24 are register
headers (which are relatively large), so I'm not sending
them out.

You can view the whole patch set here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=raven

Patches #1-#13 are Acked-by: Christian König .

Patches #14-#16 are Reviewed-by: Christian König
.

Patches #17-#25 are somehow missing on the mailing lists at the moment.

17-24 are just register headers.  I didn’t send them out because they are too 
big.


Ok, that makes sense. Only had time to skimmed over the set.

Found a few ends which still need some work. For example has anybody 
tested multi level page tables on Raven yet?


But that not blocking so feel free to add an Acked-by: Christian König 
.


Christian.



Alex


Going to take a look at the rest tomorrow.

Christian.


Alex Deucher (12):
drm/amdgpu: add gpu_info firmware (v3)
drm/amdgpu: parse the gpu_info firmware (v4)
drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
drm/amdgpu: add register headers for DCN 1.0
drm/amdgpu: add register headers for GC 9.1
drm/amdgpu: add register headers for MMHUB 9.1
drm/amdgpu: add register headers for MP 10.0
drm/amdgpu: add register headers for NBIO 7.0
drm/amdgpu: add register headers for SDMA 4.1
drm/amdgpu: add register headers for THM 10.0
drm/amdgpu: add register headers for VCN 1.0
drm/amdgpu/raven: power up/down VCN via the SMU (v2)

Andrey Grodzovsky (1):
drm/amd: Add DCN ivsrcids (v2)

Chunming Zhou (17):
drm/amdgpu: add RAVEN family id definition
drm/amdgpu: add Raven ip blocks
drm/amdgpu/soc15: add Raven golden setting
drm/amdgpu: add Raven chip id case for ucode
drm/amdgpu: add module firmware for raven
drm/amdgpu: add gc9.1 golden setting (v2)
drm/amdgpu/gfx9: add chip name for raven when initializing microcode
drm/amdgpu/gfx9: add raven gfx config
drm/amdgpu: add raven case for gmc9 golden setting
drm/amdgpu/gmc9: set mc vm fb offset for raven
drm/amdgpu/gmc9: change fb offset sequence so that used wider
drm/amdgpu: add Raven sdma golden setting and chip id case
drm/amdgpu: add nbio7 support
drm/amdgpu: apply nbio7 for Raven (v3)
drm/amd/powerplay/rv: power up/down sdma via the SMU
drm/amdgpu/powerplay/raven: add smu block and enable powerplay
drm/amdgpu: add RAVEN pci id

Harry Wentland (7):
drm/amdgpu/display: Add calcs code for DCN
drm/amdgpu/display: Add core dc support for DCN
drm/amdgpu/display: Add dml support for DCN
drm/amdgpu/display: Add gpio support for DCN
drm/amdgpu/display: Add i2c/aux support for DCN
drm/amdgpu/display: Add irq support for DCN
drm/amdgpu/display: Enable DCN in DC

Hawking Zhang (13):
drm/amd/amdgpu: fill in raven case in soc15 early init
drm/amdgpu/gfx9: extend rlc fw setup
drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
drm/amdgpu: correct gfx9 csb size
drm/amdgpu/gfx9: add rlc bo init/fini
drm/amdgpu/gfx9: rlc save&restore list programming
drm/amdgpu: init gfx power gating on raven
drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
drm/amdgpu/gfx9: allow updating gfx cgpg state
drm/amdgpu/gfx9: allow updating gfx mgpg state
drm/amdgpu: enable dcn1.0 dc support on raven

Huang Rui (17):
drm/amdgpu/soc15: add clock gating functions for raven
drm/amdgpu: enable soc15 clock gating flags for raven
drm/amdgpu: add gfx clock gating for raven
drm/amdgpu: add raven clock gating and light sleep for mmhub
drm/amdgpu: enable MC MGCG and LS for raven
drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
drm/amdgpu: enable sdma v4 MGCG and LS for raven
drm/amdgpu: init sdma power gating for raven
drm/amdgpu/sdma4: add dynamic power gating for raven
drm/amdgpu: enable sdma power gating for raven
drm/amdgpu: add nbio MGCG for raven
drm/amdgpu: add psp v10 function callback for raven
drm/amdgpu: add psp v10 ip block
drm/amdgpu: register the psp v10 function pointers at psp sw_init
drm/amdgpu/soc15: add psp ip block
drm/amdgpu/vcn: add sw clock gating
drm/amdgpu: enable sw clock gating for vcn

Leo Liu (32):
drm/amdgpu: add initial vcn support and decode tests
drm/amdgpu: add encode tests for vcn
drm/

[PATCH 3/5] drm/amdgpu/gfx9: move SET_RESOURCES into the same command stream

[Alex Deucher]

As the KCQ setup.  This way we only have to wait once for the
entire MEC.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 73 +++
 1 file changed, 14 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7be71fb..9051590 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2478,59 +2478,7 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring 
*ring)
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
 }
 
-static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
-{
-   struct amdgpu_device *adev = ring->adev;
-   uint32_t scratch, tmp = 0;
-   int r, i;
-
-   r = amdgpu_gfx_scratch_get(adev, &scratch);
-   if (r) {
-   DRM_ERROR("Failed to get scratch reg (%d).\n", r);
-   return r;
-   }
-   WREG32(scratch, 0xCAFEDEAD);
-
-   r = amdgpu_ring_alloc(ring, 8);
-   if (r) {
-   DRM_ERROR("Failed to lock KIQ (%d).\n", r);
-   amdgpu_gfx_scratch_free(adev, scratch);
-   return r;
-   }
-   amdgpu_ring_alloc(ring, 11);
-   /* set resources */
-   amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
-   amdgpu_ring_write(ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
- PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 
queue_type:0 (KIQ) */
-   amdgpu_ring_write(ring, 0x00FF);/* queue mask lo */
-   amdgpu_ring_write(ring, 0); /* queue mask hi */
-   amdgpu_ring_write(ring, 0); /* gws mask lo */
-   amdgpu_ring_write(ring, 0); /* gws mask hi */
-   amdgpu_ring_write(ring, 0); /* oac mask */
-   amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */
-   /* write to scratch for completion */
-   amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-   amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
-   amdgpu_ring_write(ring, 0xDEADBEEF);
-   amdgpu_ring_commit(ring);
-
-   for (i = 0; i < adev->usec_timeout; i++) {
-   tmp = RREG32(scratch);
-   if (tmp == 0xDEADBEEF)
-   break;
-   DRM_UDELAY(1);
-   }
-   if (i >= adev->usec_timeout) {
-   DRM_ERROR("KIQ enable failed (scratch(0x%04X)=0x%08X)\n",
- scratch, tmp);
-   r = -EINVAL;
-   }
-   amdgpu_gfx_scratch_free(adev, scratch);
-
-   return r;
-}
-
-static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev)
+static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
 {
struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
uint32_t scratch, tmp = 0;
@@ -2543,13 +2491,23 @@ static int gfx_v9_0_map_queues_enable(struct 
amdgpu_device *adev)
}
WREG32(scratch, 0xCAFEDEAD);
 
-   r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 3);
+   r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
if (r) {
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
amdgpu_gfx_scratch_free(adev, scratch);
return r;
}
 
+   /* set resources */
+   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
+   amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
+ PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 
queue_type:0 (KIQ) */
+   amdgpu_ring_write(kiq_ring, 0x00FF);/* queue mask lo */
+   amdgpu_ring_write(kiq_ring, 0); /* queue mask hi */
+   amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
+   amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
+   amdgpu_ring_write(kiq_ring, 0); /* oac mask */
+   amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
@@ -2836,7 +2794,6 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
struct amdgpu_device *adev = ring->adev;
struct v9_mqd *mqd = ring->mqd_ptr;
int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
-   int r;
 
gfx_v9_0_kiq_setting(ring);
 
@@ -2867,9 +2824,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
mutex_unlock(&adev->srbm_mutex);
}
 
-   r = gfx_v9_0_kiq_enable(ring);
-
-   return r;
+   return 0;
 }
 
 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
@@ -2941,7 +2896,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
goto done;
}
 
-   r = gfx_v9_0_map_queues_enable(adev);
+   r = gfx_v9_0_kiq_kcq_enable(adev);
 done:
return r;
 }
-- 
2.5.5

[PATCH 0/5] GFX9 KIQ

[Alex Deucher]

These are the laste of the gfx9 KIQ patches that haven't landed yet.  Can
someone with gfx9 capable hw test this (vega10 or raven)?  This is needed
to enable powergating on gfx9.

Thanks,

Alex

Alex Deucher (5):
  drm/amdgpu: split gfx_v9_0_kiq_init_queue into two
  drm/amdgpu/gfx9: wait once for all KCQs to be created
  drm/amdgpu/gfx9: move SET_RESOURCES into the same command stream
  drm/amdgpu/gfx9: fix resume of KIQ and KCQs (v2)
  drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring
management. (v4)

 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 488 +-
 1 file changed, 126 insertions(+), 362 deletions(-)

-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/5] drm/amdgpu: split gfx_v9_0_kiq_init_queue into two

[Alex Deucher]

One for KIQ and one for the KCQ. This simplifies the logic and
allows for future optimizations.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 63 +++
 1 file changed, 42 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a1e1b7a..2881e1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2833,25 +2833,18 @@ static int gfx_v9_0_kiq_init_register(struct 
amdgpu_ring *ring)
 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
-   struct amdgpu_kiq *kiq = &adev->gfx.kiq;
struct v9_mqd *mqd = ring->mqd_ptr;
-   bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
int r;
 
-   if (is_kiq) {
-   gfx_v9_0_kiq_setting(&kiq->ring);
-   } else {
-   mqd_idx = ring - &adev->gfx.compute_ring[0];
-   }
+   gfx_v9_0_kiq_setting(ring);
 
if (!adev->gfx.in_reset) {
memset((void *)mqd, 0, sizeof(*mqd));
mutex_lock(&adev->srbm_mutex);
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v9_0_mqd_init(ring);
-   if (is_kiq)
-   gfx_v9_0_kiq_init_register(ring);
+   gfx_v9_0_kiq_init_register(ring);
soc15_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
 
@@ -2866,19 +2859,47 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
ring->wptr = 0;
amdgpu_ring_clear_ring(ring);
 
-   if (is_kiq) {
-   mutex_lock(&adev->srbm_mutex);
-   soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 
0);
-   gfx_v9_0_kiq_init_register(ring);
-   soc15_grbm_select(adev, 0, 0, 0, 0);
-   mutex_unlock(&adev->srbm_mutex);
-   }
+   mutex_lock(&adev->srbm_mutex);
+   soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+   gfx_v9_0_kiq_init_register(ring);
+   soc15_grbm_select(adev, 0, 0, 0, 0);
+   mutex_unlock(&adev->srbm_mutex);
}
 
-   if (is_kiq)
-   r = gfx_v9_0_kiq_enable(ring);
-   else
-   r = gfx_v9_0_map_queue_enable(&kiq->ring, ring);
+   r = gfx_v9_0_kiq_enable(ring);
+
+   return r;
+}
+
+static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+   struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+   struct v9_mqd *mqd = ring->mqd_ptr;
+   int mqd_idx = ring - &adev->gfx.compute_ring[0];
+   int r;
+
+   if (!adev->gfx.in_reset) {
+   memset((void *)mqd, 0, sizeof(*mqd));
+   mutex_lock(&adev->srbm_mutex);
+   soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+   gfx_v9_0_mqd_init(ring);
+   soc15_grbm_select(adev, 0, 0, 0, 0);
+   mutex_unlock(&adev->srbm_mutex);
+
+   if (adev->gfx.mec.mqd_backup[mqd_idx])
+   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
+   } else { /* for GPU_RESET case */
+   /* reset MQD to a clean status */
+   if (adev->gfx.mec.mqd_backup[mqd_idx])
+   memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(*mqd));
+
+   /* reset ring buffer */
+   ring->wptr = 0;
+   amdgpu_ring_clear_ring(ring);
+   }
+
+   r = gfx_v9_0_map_queue_enable(&kiq->ring, ring);
 
return r;
 }
@@ -2914,7 +2935,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
goto done;
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
if (!r) {
-   r = gfx_v9_0_kiq_init_queue(ring);
+   r = gfx_v9_0_kcq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
ring->mqd_ptr = NULL;
}
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] drm/amdgpu/gfx9: fix resume of KIQ and KCQs (v2)

[Alex Deucher]

No need to reset the wptr and clear the rings.  The UNMAP_QUEUES
packet writes the current MQD state back the MQD on suspend,
so there is no need to reset it as well.

v2: fix from gfx8 (Rex)

Ack-by: monk liu 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 28 +++-
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9051590..42390c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2797,18 +2797,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
 
gfx_v9_0_kiq_setting(ring);
 
-   if (!adev->gfx.in_reset) {
-   memset((void *)mqd, 0, sizeof(*mqd));
-   mutex_lock(&adev->srbm_mutex);
-   soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-   gfx_v9_0_mqd_init(ring);
-   gfx_v9_0_kiq_init_register(ring);
-   soc15_grbm_select(adev, 0, 0, 0, 0);
-   mutex_unlock(&adev->srbm_mutex);
-
-   if (adev->gfx.mec.mqd_backup[mqd_idx])
-   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
-   } else { /* for GPU_RESET case */
+   if (adev->gfx.in_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(*mqd));
@@ -2822,6 +2811,17 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
gfx_v9_0_kiq_init_register(ring);
soc15_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
+   } else {
+   memset((void *)mqd, 0, sizeof(*mqd));
+   mutex_lock(&adev->srbm_mutex);
+   soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+   gfx_v9_0_mqd_init(ring);
+   gfx_v9_0_kiq_init_register(ring);
+   soc15_grbm_select(adev, 0, 0, 0, 0);
+   mutex_unlock(&adev->srbm_mutex);
+
+   if (adev->gfx.mec.mqd_backup[mqd_idx])
+   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
}
 
return 0;
@@ -2843,7 +2843,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring 
*ring)
 
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
-   } else { /* for GPU_RESET case */
+   } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(*mqd));
@@ -2851,6 +2851,8 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring 
*ring)
/* reset ring buffer */
ring->wptr = 0;
amdgpu_ring_clear_ring(ring);
+   } else {
+   amdgpu_ring_clear_ring(ring);
}
 
return 0;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/5] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v4)

[Alex Deucher]

KIQ is the Kernel Interface Queue for managing the MEC.  Rather than setting
up rings via direct MMIO of ring registers, the rings are configured via
special packets sent to the KIQ.  The allows the MEC to better manage shared
resources and certain power events. It also reduces the code paths in the
driver to support and is required for MEC powergating.

v2: drop gfx_v9_0_cp_compute_fini() as well
v3: rebase on latest changes derived from gfx8, add unmap queues on
hw_fini
v4: fix copy/paste typo in error message (Rex)

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 374 --
 1 file changed, 81 insertions(+), 293 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 42390c5..5ee7fb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1415,23 +1415,21 @@ static int gfx_v9_0_sw_init(void *handle)
return r;
}
 
-   if (amdgpu_sriov_vf(adev)) {
-   r = gfx_v9_0_kiq_init(adev);
-   if (r) {
-   DRM_ERROR("Failed to init KIQ BOs!\n");
-   return r;
-   }
+   r = gfx_v9_0_kiq_init(adev);
+   if (r) {
+   DRM_ERROR("Failed to init KIQ BOs!\n");
+   return r;
+   }
 
-   kiq = &adev->gfx.kiq;
-   r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
-   if (r)
-   return r;
+   kiq = &adev->gfx.kiq;
+   r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
+   if (r)
+   return r;
 
-   /* create MQD for all compute queues as wel as KIQ for SRIOV 
case */
-   r = gfx_v9_0_compute_mqd_sw_init(adev);
-   if (r)
-   return r;
-   }
+   /* create MQD for all compute queues as wel as KIQ for SRIOV case */
+   r = gfx_v9_0_compute_mqd_sw_init(adev);
+   if (r)
+   return r;
 
/* reserve GDS, GWS and OA resource for gfx */
r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
@@ -1478,11 +1476,9 @@ static int gfx_v9_0_sw_fini(void *handle)
for (i = 0; i < adev->gfx.num_compute_rings; i++)
amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 
-   if (amdgpu_sriov_vf(adev)) {
-   gfx_v9_0_compute_mqd_sw_fini(adev);
-   gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
-   gfx_v9_0_kiq_fini(adev);
-   }
+   gfx_v9_0_compute_mqd_sw_fini(adev);
+   gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
+   gfx_v9_0_kiq_fini(adev);
 
gfx_v9_0_mec_fini(adev);
gfx_v9_0_ngg_fini(adev);
@@ -2375,13 +2371,6 @@ static void gfx_v9_0_cp_compute_enable(struct 
amdgpu_device *adev, bool enable)
udelay(50);
 }
 
-static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
-{
-   gfx_v9_0_cp_compute_enable(adev, true);
-
-   return 0;
-}
-
 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 {
const struct gfx_firmware_header_v1_0 *mec_hdr;
@@ -2424,45 +2413,6 @@ static int gfx_v9_0_cp_compute_load_microcode(struct 
amdgpu_device *adev)
return 0;
 }
 
-static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
-{
-   int i, r;
-
-   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-   struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-
-   if (ring->mqd_obj) {
-   r = amdgpu_bo_reserve(ring->mqd_obj, true);
-   if (unlikely(r != 0))
-   dev_warn(adev->dev, "(%d) reserve MQD bo 
failed\n", r);
-
-   amdgpu_bo_unpin(ring->mqd_obj);
-   amdgpu_bo_unreserve(ring->mqd_obj);
-
-   amdgpu_bo_unref(&ring->mqd_obj);
-   ring->mqd_obj = NULL;
-   }
-   }
-}
-
-static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
-
-static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
-{
-   int i, r;
-   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-   struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-   if (gfx_v9_0_init_queue(ring))
-   dev_warn(adev->dev, "compute queue %d init failed!\n", 
i);
-   }
-
-   r = gfx_v9_0_cp_compute_start(adev);
-   if (r)
-   return r;
-
-   return 0;
-}
-
 /* KIQ functions */
 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
 {
@@ -2553,6 +2503,56 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device 
*adev)
return r;
 }
 
+static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
+{
+   struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
+   uint32_t scratch, tmp = 0;
+   int r, i;
+
+   r = amdgpu_g

[PATCH 2/5] drm/amdgpu/gfx9: wait once for all KCQs to be created

[Alex Deucher]

Rather than waiting for each queue.

Reviewed-by: monk liu 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 60 +--
 1 file changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2881e1c..7be71fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2530,11 +2530,9 @@ static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
return r;
 }
 
-static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
-struct amdgpu_ring *ring)
+static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev)
 {
-   struct amdgpu_device *adev = kiq_ring->adev;
-   uint64_t mqd_addr, wptr_addr;
+   struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
uint32_t scratch, tmp = 0;
int r, i;
 
@@ -2545,33 +2543,36 @@ static int gfx_v9_0_map_queue_enable(struct amdgpu_ring 
*kiq_ring,
}
WREG32(scratch, 0xCAFEDEAD);
 
-   r = amdgpu_ring_alloc(kiq_ring, 10);
+   r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 3);
if (r) {
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
amdgpu_gfx_scratch_free(adev, scratch);
return r;
}
 
-   mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
-   wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-
-   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
-   /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
-   amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
- PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
- PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
- PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
- PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
- PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
- PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: 
normal compute queue */
- PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: 
all_on_one_pipe */
- PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: 
compute */
- PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: 
must be 1 */
-   amdgpu_ring_write(kiq_ring, 
PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
-   amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
-   amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
-   amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
-   amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
+   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+   struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
+   uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
+   uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+
+   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
+   /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
+   amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, 
num_Q: 1 */
+ PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* 
Queue_Sel */
+ PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
+ PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
+ PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
+ PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 
1)) |
+ PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 
/*queue_type: normal compute queue */
+ PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc 
format: all_on_one_pipe */
+ PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* 
engine_sel: compute */
+ PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* 
num_queues: must be 1 */
+   amdgpu_ring_write(kiq_ring, 
PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
+   amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
+   amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
+   amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
+   amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
+   }
/* write to scratch for completion */
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
@@ -2874,10 +2875,8 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
-   struct amdgpu_kiq *kiq = &adev->gfx.kiq;
struct v9_mqd *mqd = ring->mqd_ptr;
i

[PATCH libdrm v2 1/1] amdgpu: move asic id table to a separate file

[Samuel Li]

From: Xiaojie Yuan 

v2: fix an off by one error and leading white spaces

Change-Id: I12216da14910f5e2b0970bc1fafc2a20b0ef1ba9
Reviewed-by: Junwei Zhang 
Signed-off-by: Samuel Li 
---
 amdgpu/Makefile.am   |   2 +
 amdgpu/Makefile.sources  |   2 +-
 amdgpu/amdgpu_asic_id.c  | 198 +++
 amdgpu/amdgpu_asic_id.h  | 165 ---
 amdgpu/amdgpu_device.c   |  28 +--
 amdgpu/amdgpu_internal.h |  10 +++
 6 files changed, 232 insertions(+), 173 deletions(-)
 create mode 100644 amdgpu/amdgpu_asic_id.c
 delete mode 100644 amdgpu/amdgpu_asic_id.h

diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
index cf7bc1b..ecf9e82 100644
--- a/amdgpu/Makefile.am
+++ b/amdgpu/Makefile.am
@@ -30,6 +30,8 @@ AM_CFLAGS = \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
 
+AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${datadir}/libdrm/amdgpu.ids\"
+
 libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
 libdrm_amdgpu_ladir = $(libdir)
 libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined
diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources
index 487b9e0..bc3abaa 100644
--- a/amdgpu/Makefile.sources
+++ b/amdgpu/Makefile.sources
@@ -1,5 +1,5 @@
 LIBDRM_AMDGPU_FILES := \
-   amdgpu_asic_id.h \
+   amdgpu_asic_id.c \
amdgpu_bo.c \
amdgpu_cs.c \
amdgpu_device.c \
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
new file mode 100644
index 000..067f38c
--- /dev/null
+++ b/amdgpu/amdgpu_asic_id.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright © 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
+{
+   char *buf;
+   char *s_did;
+   char *s_rid;
+   char *s_name;
+   char *endptr;
+   int r = 0;
+
+   buf = strdup(line);
+   if (!buf)
+   return -ENOMEM;
+
+   /* ignore empty line and commented line */
+   if (strlen(line) == 0 || line[0] == '#') {
+   r = -EAGAIN;
+   goto out;
+   }
+
+   /* device id */
+   s_did = strtok(buf, ",");
+   if (!s_did) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->did = strtol(s_did, &endptr, 16);
+   if (*endptr) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   /* revision id */
+   s_rid = strtok(NULL, ",");
+   if (!s_rid) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->rid = strtol(s_rid, &endptr, 16);
+   if (*endptr) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   /* marketing name */
+   s_name = strtok(NULL, ",");
+   if (!s_name) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   id->marketing_name = strdup(s_name);
+   if (id->marketing_name == NULL) {
+   r = -EINVAL;
+   goto out;
+   }
+
+out:
+   free(buf);
+
+   return r;
+}
+
+int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table)
+{
+   struct amdgpu_asic_id *asic_id_table;
+   struct amdgpu_asic_id *id;
+   FILE *fp;
+   char *line = NULL;
+   size_t len;
+   ssize_t n;
+   int line_num = 1;
+   size_t table_size = 0;
+   size_t table_max_size = 256;
+   int r = 0;
+
+   fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
+   if (!fp) {
+   fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE,
+   strerror(errno));
+   return -EINVAL;
+   }
+
+   asic_id_table = calloc(table_max_size, sizeof(struct amdgpu_asic_id));
+   if (!asic_id_table) {
+

RE: [PATCH 1/1] amdgpu: move asic id table to a separate file

[Li, Samuel]

Submitted a request to create a new repo on freedesktop. Michel, do you have 
the privilege to create it?
https://bugs.freedesktop.org/show_bug.cgi?id=99589

Sam

-Original Message-
From: Michel Dänzer [mailto:mic...@daenzer.net] 
Sent: Wednesday, May 10, 2017 10:33 PM
To: Li, Samuel 
Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie 
Subject: Re: [PATCH 1/1] amdgpu: move asic id table to a separate file

On 11/05/17 06:10 AM, Li, Samuel wrote:
> Also attach a sample ids file for reference. The names are from 
> marketing, not related to source code and no reviews necessary here:)

Just because it's not source code doesn't mean no review is necessary. :)


> It can be put in directory /usr/share/libdrm.

What is the canonical location where distros or users building upstream libdrm 
can get this file from? There needs to be a good solution for that before this 
can land.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

[Pavel Machek]

On Fri 2017-04-21 14:08:04, Ville Syrjälä wrote:
> On Fri, Apr 21, 2017 at 11:50:18AM +0200, Gerd Hoffmann wrote:
> > On Fr, 2017-04-21 at 12:25 +0300, Ville Syrjälä wrote:
> > > On Fri, Apr 21, 2017 at 09:58:24AM +0200, Gerd Hoffmann wrote:
> > > > While working on graphics support for virtual machines on ppc64 (which
> > > > exists in both little and big endian variants) I've figured the comments
> > > > for various drm fourcc formats in the header file don't match reality.
> > > > 
> > > > Comments says the RGB formats are little endian, but in practice they
> > > > are native endian.  Look at the drm_mode_legacy_fb_format() helper.  It
> > > > maps -- for example -- bpp/depth 32/24 to DRM_FORMAT_XRGB, no matter
> > > > whenever the machine is little endian or big endian.  The users of this
> > > > function (fbdev emulation, DRM_IOCTL_MODE_ADDFB) expect the framebuffer
> > > > is native endian, not little endian.  Most userspace also operates on
> > > > native endian only.
> > > 
> > > I'm not a fan of "native". Native to what? "CPU" or "host" is what I'd
> > > call it.
> > 
> > native == whatever the cpu is using.
> > 
> > I personally find "native" more intuitive, but at the end of the day I
> > don't mind much.  If people prefer "host" over "native" I'll change it.
> 
> "native" to me feels more like "native to the GPU" since these things
> really are tied to the GPU not the CPU. That's also why I went with the
> explicit endianness originally so that the driver could properly declare
> what the GPU supports.

You can easily have more than one GPU in the system. Plus these are
used by cameras / frame grabbers, too. So anything else than CPU
endianness is badly defined.

(And I agree with the rest of the thread -- we should really be
explicit; fourcc should specify what format the image data are in, and
it should be possible to write fourcc + raw data into file and
transfer it between machines.)


Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) 
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


signature.asc
Description: Digital signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 1/1] amdgpu: move asic id table to a separate file

[Li, Samuel]

The bugzilla id is actually here,
https://bugs.freedesktop.org/show_bug.cgi?id=101013


Sam

-Original Message-
From: Li, Samuel 
Sent: Thursday, May 11, 2017 5:13 PM
To: 'Michel Dänzer' 
Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie 
Subject: RE: [PATCH 1/1] amdgpu: move asic id table to a separate file

Submitted a request to create a new repo on freedesktop. Michel, do you have 
the privilege to create it?
https://bugs.freedesktop.org/show_bug.cgi?id=99589

Sam

-Original Message-
From: Michel Dänzer [mailto:mic...@daenzer.net]
Sent: Wednesday, May 10, 2017 10:33 PM
To: Li, Samuel 
Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie 
Subject: Re: [PATCH 1/1] amdgpu: move asic id table to a separate file

On 11/05/17 06:10 AM, Li, Samuel wrote:
> Also attach a sample ids file for reference. The names are from 
> marketing, not related to source code and no reviews necessary here:)

Just because it's not source code doesn't mean no review is necessary. :)


> It can be put in directory /usr/share/libdrm.

What is the canonical location where distros or users building upstream libdrm 
can get this file from? There needs to be a good solution for that before this 
can land.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: properly byteswap gpu_info firmware

[Alex Deucher]

It's stored in LE format.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d95d4c9..8a5bb42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1459,19 +1459,19 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
(const struct gpu_info_firmware_v1_0 *)(fw->data +

le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 
-   adev->gfx.config.max_shader_engines = gpu_info_fw->gc_num_se;
-   adev->gfx.config.max_cu_per_sh = gpu_info_fw->gc_num_cu_per_sh;
-   adev->gfx.config.max_sh_per_se = gpu_info_fw->gc_num_sh_per_se;
-   adev->gfx.config.max_backends_per_se = 
gpu_info_fw->gc_num_rb_per_se;
+   adev->gfx.config.max_shader_engines = 
le32_to_cpu(gpu_info_fw->gc_num_se);
+   adev->gfx.config.max_cu_per_sh = 
le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
+   adev->gfx.config.max_sh_per_se = 
le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
+   adev->gfx.config.max_backends_per_se = 
le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
adev->gfx.config.max_texture_channel_caches =
-   gpu_info_fw->gc_num_tccs;
-   adev->gfx.config.max_gprs = gpu_info_fw->gc_num_gprs;
-   adev->gfx.config.max_gs_threads = 
gpu_info_fw->gc_num_max_gs_thds;
-   adev->gfx.config.gs_vgt_table_depth = 
gpu_info_fw->gc_gs_table_depth;
-   adev->gfx.config.gs_prim_buffer_depth = 
gpu_info_fw->gc_gsprim_buff_depth;
+   le32_to_cpu(gpu_info_fw->gc_num_tccs);
+   adev->gfx.config.max_gprs = 
le32_to_cpu(gpu_info_fw->gc_num_gprs);
+   adev->gfx.config.max_gs_threads = 
le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
+   adev->gfx.config.gs_vgt_table_depth = 
le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
+   adev->gfx.config.gs_prim_buffer_depth = 
le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
adev->gfx.config.double_offchip_lds_buf =
-   gpu_info_fw->gc_double_offchip_lds_buffer;
-   adev->gfx.cu_info.wave_front_size = gpu_info_fw->gc_wave_size;
+   le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
+   adev->gfx.cu_info.wave_front_size = 
le32_to_cpu(gpu_info_fw->gc_wave_size);
break;
}
default:
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/radeon: Unbreak HPD handling for r600+

[Lyude]

We end up reading the interrupt register for HPD5, and then writing it
to HPD6 which on systems without anything using HPD5 results in
permanently disabling hotplug on one of the display outputs after the
first time we acknowledge a hotplug interrupt from the GPU.

This code is really bad. But for now, let's just fix this. I will
hopefully have a large patch series to refactor all of this soon.

Signed-off-by: Lyude 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/radeon/cik.c   | 4 ++--
 drivers/gpu/drm/radeon/evergreen.c | 4 ++--
 drivers/gpu/drm/radeon/r600.c  | 2 +-
 drivers/gpu/drm/radeon/si.c| 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 53710dd..cfc917c 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7401,7 +7401,7 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
@@ -7431,7 +7431,7 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_RX_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index d1b1e0c..c48d19e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4933,7 +4933,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
@@ -4964,7 +4964,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & 
DC_HPD6_RX_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_RX_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0a08517..e06e2d8 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3988,7 +3988,7 @@ static void r600_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.r600.disp_int_cont2 & 
DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 528e5a4..bfeb774 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6330,7 +6330,7 @@ static inline void si_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
@@ -6361,7 +6361,7 @@ static inline void si_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & 
DC_HPD6_RX_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_RX_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
-- 
2.9.3

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 0/5] GFX9 KIQ

[Tom St Denis]

On 11/05/17 02:35 PM, Alex Deucher wrote:

These are the laste of the gfx9 KIQ patches that haven't landed yet.  Can
someone with gfx9 capable hw test this (vega10 or raven)?  This is needed
to enable powergating on gfx9.

Thanks,


If nobody gets to it by morning I'll try it out first thing on my vega10 
though my VBIOS might need updating...


Tom
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/5] drm/syncobj: add sync obj wait interface. (v2)

[Dave Airlie]

From: Dave Airlie 

This interface will allow sync object to be used to back
Vulkan fences. This API is pretty much the vulkan fence waiting
API, and I've ported the code from amdgpu.

v2: accept relative timeout, pass remaining time back
to userspace.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/drm_internal.h |   2 +
 drivers/gpu/drm/drm_ioctl.c|   2 +
 drivers/gpu/drm/drm_syncobj.c  | 139 -
 include/uapi/drm/drm.h |  12 
 4 files changed, 154 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 44ef903..a508ad9 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -156,3 +156,5 @@ int drm_syncobj_handle_to_fd_ioctl(struct drm_device *dev, 
void *data,
   struct drm_file *file_private);
 int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, void *data,
   struct drm_file *file_private);
+int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data,
+  struct drm_file *file_private);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 6da7adc..b142466 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -653,6 +653,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, 
drm_syncobj_fd_to_handle_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl,
+ DRM_UNLOCKED|DRM_RENDER_ALLOW),
 };
 
 #define DRM_CORE_IOCTL_COUNT   ARRAY_SIZE( drm_ioctls )
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 835e987..9a8c690 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -1,5 +1,7 @@
 /*
  * Copyright 2017 Red Hat
+ * Parts ported from amdgpu (fence wait code).
+ * Copyright 2016 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -31,10 +33,13 @@
  * that contain an optional fence. The fence can be updated with a new
  * fence, or be NULL.
  *
+ * syncobj's can be waited upon, where it will wait for the underlying
+ * fence.
+ *
  * syncobj's can be export to fd's and back, these fd's are opaque and
  * have no other use case, except passing the syncobj between processes.
  *
- * TODO: sync_file interactions, waiting
+ * TODO: sync_file interactions.
  *
  * Their primary use-case is to implement Vulkan fences and semaphores.
  *
@@ -383,3 +388,135 @@ drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, 
void *data,
return drm_syncobj_fd_to_handle(file_private, args->fd,
&args->handle);
 }
+
+static int drm_syncobj_wait_all_fences(struct drm_device *dev,
+  struct drm_file *file_private,
+  struct drm_syncobj_wait *wait,
+  uint32_t *handles)
+{
+   uint32_t i;
+   int ret = 0;
+   unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns);
+
+   for (i = 0; i < wait->count_handles; i++) {
+   struct dma_fence *fence;
+
+   ret = drm_syncobj_fence_get(file_private, handles[i],
+   &fence);
+   if (ret)
+   return ret;
+
+   if (!fence)
+   continue;
+
+   ret = dma_fence_wait_timeout(fence, true, timeout);
+
+   dma_fence_put(fence);
+   if (ret < 0)
+   return ret;
+   if (ret == 0)
+   break;
+   timeout = ret;
+   }
+
+   if (ret > 0)
+   wait->timeout_ns = jiffies_to_nsecs(ret);
+   wait->out_status = (ret > 0);
+   wait->first_signaled = 0;
+   return 0;
+}
+
+static int drm_syncobj_wait_any_fence(struct drm_device *dev,
+ struct drm_file *file_private,
+ struct drm_syncobj_wait *wait,
+ uint32_t *handles)
+{
+   unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns);
+   struct dma_fence **array;
+   uint32_t i;
+   int ret;
+   uint32_t first = ~0;
+
+   /* Prepare the fence array */
+   array = kcalloc(wait->count_handles,
+   sizeof(struct dma_fence *), GFP_KERNEL);
+
+   if (array == NULL)
+   return -ENOMEM;
+
+   for (i = 0; i < wait->count_handles; i++) {
+   struct dma_fence *fence;
+
+   ret = drm_syncobj_fence_get(file_private, handles[i],
+   &fe

drm syncobj - can we get some r-b/a-bs?

[Dave Airlie]

Okay I'm not convinced this is going to get any better out of tree,
I've polished what I can, and fixed up the last few comments from people,

I'd like to rebase on drm-misc probably at some point and send a pull
request for it.

This mostly just addresses things around naming that Chris pointed out.

Dave.

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/5] amdgpu: use drm sync objects for shared semaphores (v4)

[Dave Airlie]

From: Dave Airlie 

This creates a new command submission chunk for amdgpu
to add in and out sync objects around the submission.

Sync objects are managed via the drm syncobj ioctls.

The command submission interface is enhanced with two new
chunks, one for syncobj pre submission dependencies,
and one for post submission sync obj signalling,
and just takes a list of handles for each.

This is based on work originally done by David Zhou at AMD,
with input from Christian Konig on what things should look like.

In theory VkFences could be backed with sync objects and
just get passed into the cs as syncobj handles as well.

NOTE: this interface addition needs a version bump to expose
it to userspace.

v1.1: keep file reference on import.
v2: move to using syncobjs
v2.1: change some APIs to just use p pointer.
v3: make more robust against CS failures, we now add the
wait sems but only remove them once the CS job has been
submitted.
v4: rewrite names of API and base on new syncobj code.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 81 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  2 +-
 include/uapi/drm/amdgpu_drm.h   |  6 +++
 3 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index df25b32..e86c832 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
 
@@ -217,6 +218,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void 
*data)
break;
 
case AMDGPU_CHUNK_ID_DEPENDENCIES:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
break;
 
default:
@@ -1008,6 +1011,40 @@ static int amdgpu_process_fence_dep(struct 
amdgpu_cs_parser *p,
return 0;
 }
 
+static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
+uint32_t handle)
+{
+   int r;
+   struct dma_fence *fence;
+   r = drm_syncobj_fence_get(p->filp, handle, &fence);
+   if (r)
+   return r;
+
+   r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
+   dma_fence_put(fence);
+
+   return r;
+}
+
+static int amdgpu_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
+struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   for (i = 0; i < num_deps; ++i) {
+   r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
  struct amdgpu_cs_parser *p)
 {
@@ -1022,12 +1059,54 @@ static int amdgpu_cs_dependencies(struct amdgpu_device 
*adev,
r = amdgpu_process_fence_dep(p, chunk);
if (r)
return r;
+   } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
+   r = amdgpu_process_syncobj_in_dep(p, chunk);
+   if (r)
+   return r;
}
}
 
return 0;
 }
 
+static int amdgpu_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
+ struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   for (i = 0; i < num_deps; ++i) {
+   r = drm_syncobj_replace_fence(p->filp, deps[i].handle,
+ p->fence);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
+static int amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
+{
+   int i, r;
+
+   for (i = 0; i < p->nchunks; ++i) {
+   struct amdgpu_cs_chunk *chunk;
+
+   chunk = &p->chunks[i];
+
+   if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
+   r = amdgpu_process_syncobj_out_dep(p, chunk);
+   if (r)
+   return r;
+   }
+   }
+   return 0;
+}
+
 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
union drm_amdgpu_cs *cs)
 {
@@ -1055,7 +1134,7 @@ static int amdgpu_cs_submit(struct amdgpu

[PATCH 1/5] drm: introduce sync objects (v2)

[Dave Airlie]

From: Dave Airlie 

Sync objects are new toplevel drm object, that contain a
pointer to a fence. This fence can be updated via command
submission ioctls via drivers.

There is also a generic wait obj API modelled on the vulkan
wait API (with code modelled on some amdgpu code).

These objects can be converted to an opaque fd that can be
passes between processes.

v2: rename reference/unreference to put/get (Chris)
fix leaked reference (David Zhou)
drop mutex in favour of cmpxchg (Chris)
document drm_syncobj_fence_get
use ENOENT for syncobj lookup.

Signed-off-by: Dave Airlie 

fixup
---
 Documentation/gpu/drm-internals.rst |   3 +
 Documentation/gpu/drm-mm.rst|   6 +
 drivers/gpu/drm/Makefile|   2 +-
 drivers/gpu/drm/drm_fops.c  |   8 +
 drivers/gpu/drm/drm_internal.h  |  13 ++
 drivers/gpu/drm/drm_ioctl.c |  12 ++
 drivers/gpu/drm/drm_syncobj.c   | 385 
 include/drm/drmP.h  |   5 +
 include/drm/drm_drv.h   |   1 +
 include/drm/drm_syncobj.h   |  87 
 include/uapi/drm/drm.h  |  25 +++
 11 files changed, 546 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_syncobj.c
 create mode 100644 include/drm/drm_syncobj.h

diff --git a/Documentation/gpu/drm-internals.rst 
b/Documentation/gpu/drm-internals.rst
index e35920d..2ea3bce 100644
--- a/Documentation/gpu/drm-internals.rst
+++ b/Documentation/gpu/drm-internals.rst
@@ -98,6 +98,9 @@ DRIVER_ATOMIC
 implement appropriate obj->atomic_get_property() vfuncs for any
 modeset objects with driver specific properties.
 
+DRIVER_SYNCOBJ
+Driver support drm sync objects.
+
 Major, Minor and Patchlevel
 ~~~
 
diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index f5760b1..28aebe8 100644
--- a/Documentation/gpu/drm-mm.rst
+++ b/Documentation/gpu/drm-mm.rst
@@ -483,3 +483,9 @@ DRM Cache Handling
 
 .. kernel-doc:: drivers/gpu/drm/drm_cache.c
:export:
+
+DRM Sync Objects
+===
+
+.. kernel-doc:: drivers/gpu/drm/drm_syncobj.c
+   :export:
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 3ee9579..b5e565c 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -16,7 +16,7 @@ drm-y   :=drm_auth.o drm_bufs.o drm_cache.o \
drm_framebuffer.o drm_connector.o drm_blend.o \
drm_encoder.o drm_mode_object.o drm_property.o \
drm_plane.o drm_color_mgmt.o drm_print.o \
-   drm_dumb_buffers.o drm_mode_config.o
+   drm_dumb_buffers.o drm_mode_config.o drm_syncobj.o
 
 drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
 drm-$(CONFIG_DRM_VM) += drm_vm.o
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index afdf5b1..9a61df2 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -219,6 +219,9 @@ static int drm_open_helper(struct file *filp, struct 
drm_minor *minor)
if (drm_core_check_feature(dev, DRIVER_GEM))
drm_gem_open(dev, priv);
 
+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_open(priv);
+
if (drm_core_check_feature(dev, DRIVER_PRIME))
drm_prime_init_file_private(&priv->prime);
 
@@ -266,6 +269,8 @@ static int drm_open_helper(struct file *filp, struct 
drm_minor *minor)
 out_prime_destroy:
if (drm_core_check_feature(dev, DRIVER_PRIME))
drm_prime_destroy_file_private(&priv->prime);
+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_release(priv);
if (drm_core_check_feature(dev, DRIVER_GEM))
drm_gem_release(dev, priv);
put_pid(priv->pid);
@@ -400,6 +405,9 @@ int drm_release(struct inode *inode, struct file *filp)
drm_property_destroy_user_blobs(dev, file_priv);
}
 
+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_release(file_priv);
+
if (drm_core_check_feature(dev, DRIVER_GEM))
drm_gem_release(dev, file_priv);
 
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index f37388c..44ef903 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -142,4 +142,17 @@ static inline int drm_debugfs_crtc_crc_add(struct drm_crtc 
*crtc)
 {
return 0;
 }
+
 #endif
+
+/* drm_syncobj.c */
+void drm_syncobj_open(struct drm_file *file_private);
+void drm_syncobj_release(struct drm_file *file_private);
+int drm_syncobj_create_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file_private);
+int drm_syncobj_destroy_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_private);
+int drm_syncobj_handle_to_fd_ioctl(struct drm_device *dev, void *data,
+  struct drm_file *file_private);
+int drm_s

[PATCH 4/5] amdgpu/cs: split out fence dependency checking

[Dave Airlie]

From: Dave Airlie 

This just splits out the fence depenency checking into it's
own function to make it easier to add semaphore dependencies.

Reviewed-by: Christian König 
Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 85 +++---
 1 file changed, 47 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 99424cb..df25b32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -963,56 +963,65 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
return 0;
 }
 
-static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- struct amdgpu_cs_parser *p)
+static int amdgpu_process_fence_dep(struct amdgpu_cs_parser *p,
+   struct amdgpu_cs_chunk *chunk)
 {
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-   int i, j, r;
-
-   for (i = 0; i < p->nchunks; ++i) {
-   struct drm_amdgpu_cs_chunk_dep *deps;
-   struct amdgpu_cs_chunk *chunk;
-   unsigned num_deps;
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_dep *deps;
 
-   chunk = &p->chunks[i];
+   deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_dep);
 
-   if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
-   continue;
+   for (i = 0; i < num_deps; ++i) {
+   struct amdgpu_ring *ring;
+   struct amdgpu_ctx *ctx;
+   struct dma_fence *fence;
 
-   deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
-   num_deps = chunk->length_dw * 4 /
-   sizeof(struct drm_amdgpu_cs_chunk_dep);
+   r = amdgpu_cs_get_ring(p->adev, deps[i].ip_type,
+  deps[i].ip_instance,
+  deps[i].ring, &ring);
+   if (r)
+   return r;
 
-   for (j = 0; j < num_deps; ++j) {
-   struct amdgpu_ring *ring;
-   struct amdgpu_ctx *ctx;
-   struct dma_fence *fence;
+   ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
+   if (ctx == NULL)
+   return -EINVAL;
 
-   r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
-  deps[j].ip_instance,
-  deps[j].ring, &ring);
+   fence = amdgpu_ctx_get_fence(ctx, ring,
+deps[i].handle);
+   if (IS_ERR(fence)) {
+   r = PTR_ERR(fence);
+   amdgpu_ctx_put(ctx);
+   return r;
+   } else if (fence) {
+   r = amdgpu_sync_fence(p->adev, &p->job->sync,
+ fence);
+   dma_fence_put(fence);
+   amdgpu_ctx_put(ctx);
if (r)
return r;
+   }
+   }
+   return 0;
+}
 
-   ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
-   if (ctx == NULL)
-   return -EINVAL;
+static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
+ struct amdgpu_cs_parser *p)
+{
+   int i, r;
 
-   fence = amdgpu_ctx_get_fence(ctx, ring,
-deps[j].handle);
-   if (IS_ERR(fence)) {
-   r = PTR_ERR(fence);
-   amdgpu_ctx_put(ctx);
-   return r;
+   for (i = 0; i < p->nchunks; ++i) {
+   struct amdgpu_cs_chunk *chunk;
 
-   } else if (fence) {
-   r = amdgpu_sync_fence(adev, &p->job->sync,
- fence);
-   dma_fence_put(fence);
-   amdgpu_ctx_put(ctx);
-   if (r)
-   return r;
-   }
+   chunk = &p->chunks[i];
+
+   if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
+   r = amdgpu_process_fence_dep(p, chunk);
+   if (r)
+   return r;
}
}
 
-- 
2.9.3

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/5] drm/syncobj: add sync_file interaction.

[Dave Airlie]

From: Dave Airlie 

This interface allows importing the fence from a sync_file into
an existing drm sync object, or exporting the fence attached to
an existing drm sync object into a new sync file object.

This should only be used to interact with sync files where necessary.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/drm_syncobj.c | 56 +++
 include/uapi/drm/drm.h|  6 +++--
 2 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 9a8c690..69ef20a 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -52,6 +52,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "drm_internal.h"
 #include 
@@ -290,6 +291,48 @@ static int drm_syncobj_fd_to_handle(struct drm_file 
*file_private,
return 0;
 }
 
+int drm_syncobj_import_sync_file_fence(struct drm_file *file_private,
+  int fd, int handle)
+{
+   struct dma_fence *fence = sync_file_get_fence(fd);
+   if (!fence)
+   return -EINVAL;
+
+   return drm_syncobj_replace_fence(file_private, handle, fence);
+}
+
+int drm_syncobj_export_sync_file(struct drm_file *file_private,
+int handle, int *p_fd)
+{
+   int ret;
+   struct dma_fence *fence;
+   struct sync_file *sync_file;
+   int fd = get_unused_fd_flags(O_CLOEXEC);
+
+   if (fd < 0)
+   return fd;
+
+   ret = drm_syncobj_fence_get(file_private, handle, &fence);
+   if (ret)
+   goto err_put_fd;
+
+   sync_file = sync_file_create(fence);
+   if (!sync_file) {
+   ret = -EINVAL;
+   goto err_fence_put;
+   }
+
+   fd_install(fd, sync_file->file);
+
+   dma_fence_put(fence);
+   *p_fd = fd;
+   return 0;
+err_fence_put:
+   dma_fence_put(fence);
+err_put_fd:
+   put_unused_fd(fd);
+   return ret;
+}
 /**
  * drm_syncobj_open - initalizes syncobj file-private structures at devnode 
open time
  * @dev: drm_device which is being opened by userspace
@@ -372,6 +415,12 @@ drm_syncobj_handle_to_fd_ioctl(struct drm_device *dev, 
void *data,
if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ))
return -ENODEV;
 
+   if (args->flags & DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_FENCE_SYNC_FILE)
+   return drm_syncobj_export_sync_file(file_private, args->handle,
+   &args->fd);
+   else if (args->flags)
+   return -EINVAL;
+
return drm_syncobj_handle_to_fd(file_private, args->handle,
&args->fd);
 }
@@ -385,6 +434,13 @@ drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, 
void *data,
if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ))
return -ENODEV;
 
+   if (args->flags & DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE_FENCE)
+   return drm_syncobj_import_sync_file_fence(file_private,
+ args->fd,
+ args->handle);
+   else if (args->flags)
+   return -EINVAL;
+
return drm_syncobj_fd_to_handle(file_private, args->fd,
&args->handle);
 }
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index db9e35e..d0e05f4 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -707,13 +707,15 @@ struct drm_syncobj_destroy {
__u32 pad;
 };
 
+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE_FENCE (1 << 0)
+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_FENCE_SYNC_FILE (1 << 0)
 struct drm_syncobj_handle {
__u32 handle;
/** Flags.. only applicable for handle->fd */
-   __u32 flags;
+   __u32 fd_flags;
 
__s32 fd;
-   __u32 pad;
+   __u32 flags;
 };
 
 /* timeout_ns is relative timeout in nanoseconds */
-- 
2.9.3

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/1] amdgpu: move asic id table to a separate file

[Michel Dänzer]

On 12/05/17 06:13 AM, Li, Samuel wrote:
> Submitted a request to create a new repo on freedesktop.

What's the point of having a separate repository upstream? Can't we just
keep it in the libdrm repository?


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: properly byteswap gpu_info firmware

[Michel Dänzer]

On 12/05/17 08:10 AM, Alex Deucher wrote:
> It's stored in LE format.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22 +++---
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index d95d4c9..8a5bb42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1459,19 +1459,19 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
> amdgpu_device *adev)
>   (const struct gpu_info_firmware_v1_0 *)(fw->data +
>   
> le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>  
> - adev->gfx.config.max_shader_engines = gpu_info_fw->gc_num_se;
> - adev->gfx.config.max_cu_per_sh = gpu_info_fw->gc_num_cu_per_sh;
> - adev->gfx.config.max_sh_per_se = gpu_info_fw->gc_num_sh_per_se;
> - adev->gfx.config.max_backends_per_se = 
> gpu_info_fw->gc_num_rb_per_se;
> + adev->gfx.config.max_shader_engines = 
> le32_to_cpu(gpu_info_fw->gc_num_se);
> + adev->gfx.config.max_cu_per_sh = 
> le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
> + adev->gfx.config.max_sh_per_se = 
> le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
> + adev->gfx.config.max_backends_per_se = 
> le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
>   adev->gfx.config.max_texture_channel_caches =
> - gpu_info_fw->gc_num_tccs;
> - adev->gfx.config.max_gprs = gpu_info_fw->gc_num_gprs;
> - adev->gfx.config.max_gs_threads = 
> gpu_info_fw->gc_num_max_gs_thds;
> - adev->gfx.config.gs_vgt_table_depth = 
> gpu_info_fw->gc_gs_table_depth;
> - adev->gfx.config.gs_prim_buffer_depth = 
> gpu_info_fw->gc_gsprim_buff_depth;
> + le32_to_cpu(gpu_info_fw->gc_num_tccs);
> + adev->gfx.config.max_gprs = 
> le32_to_cpu(gpu_info_fw->gc_num_gprs);
> + adev->gfx.config.max_gs_threads = 
> le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
> + adev->gfx.config.gs_vgt_table_depth = 
> le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
> + adev->gfx.config.gs_prim_buffer_depth = 
> le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
>   adev->gfx.config.double_offchip_lds_buf =
> - gpu_info_fw->gc_double_offchip_lds_buffer;
> - adev->gfx.cu_info.wave_front_size = gpu_info_fw->gc_wave_size;
> + le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
> + adev->gfx.cu_info.wave_front_size = 
> le32_to_cpu(gpu_info_fw->gc_wave_size);
>   break;
>   }
>   default:
> 

Reviewed-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/4] drm/amdgpu: Add vm context module param

[Harish Kasiviswanathan]

Add VM context module param (amdgpu.vm_update_context) that can used to
control how the VM pde/pte are updated for Graphics and Compute.

BIT0 controls Graphics and BIT1 Compute.
 BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU
 BIT1 [= 0] Compute updated by SDMA [= 1] by CPU

By default, only for large BAR system vm_update_context = 2, indicating
that Graphics VMs will be updated via SDMA and Compute VMs will be
updated via CPU. And for all all other systems (by default)
vm_update_context = 0

Signed-off-by: Harish Kasiviswanathan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 29 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  | 16 +++-
 5 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index fadeb55..d927153 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -94,6 +94,7 @@
 extern int amdgpu_vm_block_size;
 extern int amdgpu_vm_fault_stop;
 extern int amdgpu_vm_debug;
+extern int amdgpu_vm_update_context;
 extern int amdgpu_dc;
 extern int amdgpu_sched_jobs;
 extern int amdgpu_sched_hw_submission;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 26fce4d..f07bcae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -93,6 +93,7 @@
 int amdgpu_vm_block_size = -1;
 int amdgpu_vm_fault_stop = 0;
 int amdgpu_vm_debug = 0;
+int amdgpu_vm_update_context = -1;
 int amdgpu_vram_page_split = 1024;
 int amdgpu_exp_hw_support = 0;
 int amdgpu_dc = -1;
@@ -180,6 +181,9 @@
 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = 
enabled)");
 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
 
+MODULE_PARM_DESC(vm_update_context, "VM update using CPU (0 = never (default 
except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for 
LB), 3 = Both");
+module_param_named(vm_update_context, amdgpu_vm_update_context, int, 0444);
+
 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM 
allocations (default 1024, -1 = disable)");
 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d167949..c524053 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -774,7 +774,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct 
drm_file *file_priv)
goto out_suspend;
}
 
-   r = amdgpu_vm_init(adev, &fpriv->vm);
+   r = amdgpu_vm_init(adev, &fpriv->vm,
+  !!(amdgpu_vm_update_context &
+  AMDGPU_VM_USE_CPU_FOR_GFX));
if (r) {
kfree(fpriv);
goto out_suspend;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5d92e73..ff6cf33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -721,6 +721,11 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
return true;
 }
 
+static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
+{
+   return (adev->mc.real_vram_size == adev->mc.visible_vram_size);
+}
+
 /**
  * amdgpu_vm_flush - hardware flush the vm
  *
@@ -2292,10 +2297,12 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, 
uint64_t vm_size)
  *
  * @adev: amdgpu_device pointer
  * @vm: requested vm
+ * @vm_update_mode: FALSE use SDMA, TRUE use CPU to update page tables
  *
  * Init @vm fields.
  */
-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+  bool vm_update_mode)
 {
const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
AMDGPU_VM_PTE_COUNT(adev) * 8);
@@ -2324,6 +2331,10 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm)
if (r)
return r;
 
+   vm->is_vm_update_mode_cpu = vm_update_mode;
+   DRM_DEBUG_DRIVER("VM update mode is %s\n",
+vm->is_vm_update_mode_cpu ? "CPU" : "SDMA");
+
vm->last_dir_update = NULL;
 
r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
@@ -2455,6 +2466,22 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
atomic64_set(&adev->vm_manager.client_counter, 0);
spin_lock_init(&adev->vm_manager.prt_lock);
atomic_set(&adev->vm_manager.num_prt_users, 0);
+
+   /* If not overridden by the user, by default, only in large BAR systems
+* Compute VM tables will be updated by CPU
+*/
+#ifdef CONFIG_X86_64
+   if (amdgpu_vm_update_context == -1) 

Re: [PATCH 000/117] Raven Support

[zhoucm1]

On 2017年05月12日 02:08, Christian König wrote:

Am 10.05.2017 um 21:30 schrieb Deucher, Alexander:

-Original Message-
From: Christian König [mailto:deathsim...@vodafone.de]
Sent: Wednesday, May 10, 2017 3:29 PM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH 000/117] Raven Support

Am 10.05.2017 um 20:45 schrieb Alex Deucher:

This patch set adds support for the new "Raven" APU.

The first 12 patches add support for the new ACP
audio hardware on Raven. Patches 11 and 12 are not
meant for upstream, they are for early hardware testing.
The rest add GPU support.  Patches 17-24 are register
headers (which are relatively large), so I'm not sending
them out.

You can view the whole patch set here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=raven
Patches #1-#13 are Acked-by: Christian König 
.


Patches #14-#16 are Reviewed-by: Christian König
.

Patches #17-#25 are somehow missing on the mailing lists at the moment.
17-24 are just register headers.  I didn’t send them out because they 
are too big.


Ok, that makes sense. Only had time to skimmed over the set.

Found a few ends which still need some work. For example has anybody 
tested multi level page tables on Raven yet?
I've used it for a long time and not found issues, we just need set that 
the levels to 3 after Alex pushes these patches.


Regards,
David Zhou


But that not blocking so feel free to add an Acked-by: Christian König 
.


Christian.



Alex


Going to take a look at the rest tomorrow.

Christian.


Alex Deucher (12):
drm/amdgpu: add gpu_info firmware (v3)
drm/amdgpu: parse the gpu_info firmware (v4)
drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
drm/amdgpu: add register headers for DCN 1.0
drm/amdgpu: add register headers for GC 9.1
drm/amdgpu: add register headers for MMHUB 9.1
drm/amdgpu: add register headers for MP 10.0
drm/amdgpu: add register headers for NBIO 7.0
drm/amdgpu: add register headers for SDMA 4.1
drm/amdgpu: add register headers for THM 10.0
drm/amdgpu: add register headers for VCN 1.0
drm/amdgpu/raven: power up/down VCN via the SMU (v2)

Andrey Grodzovsky (1):
drm/amd: Add DCN ivsrcids (v2)

Chunming Zhou (17):
drm/amdgpu: add RAVEN family id definition
drm/amdgpu: add Raven ip blocks
drm/amdgpu/soc15: add Raven golden setting
drm/amdgpu: add Raven chip id case for ucode
drm/amdgpu: add module firmware for raven
drm/amdgpu: add gc9.1 golden setting (v2)
drm/amdgpu/gfx9: add chip name for raven when initializing 
microcode

drm/amdgpu/gfx9: add raven gfx config
drm/amdgpu: add raven case for gmc9 golden setting
drm/amdgpu/gmc9: set mc vm fb offset for raven
drm/amdgpu/gmc9: change fb offset sequence so that used wider
drm/amdgpu: add Raven sdma golden setting and chip id case
drm/amdgpu: add nbio7 support
drm/amdgpu: apply nbio7 for Raven (v3)
drm/amd/powerplay/rv: power up/down sdma via the SMU
drm/amdgpu/powerplay/raven: add smu block and enable powerplay
drm/amdgpu: add RAVEN pci id

Harry Wentland (7):
drm/amdgpu/display: Add calcs code for DCN
drm/amdgpu/display: Add core dc support for DCN
drm/amdgpu/display: Add dml support for DCN
drm/amdgpu/display: Add gpio support for DCN
drm/amdgpu/display: Add i2c/aux support for DCN
drm/amdgpu/display: Add irq support for DCN
drm/amdgpu/display: Enable DCN in DC

Hawking Zhang (13):
drm/amd/amdgpu: fill in raven case in soc15 early init
drm/amdgpu/gfx9: extend rlc fw setup
drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
drm/amdgpu: correct gfx9 csb size
drm/amdgpu/gfx9: add rlc bo init/fini
drm/amdgpu/gfx9: rlc save&restore list programming
drm/amdgpu: init gfx power gating on raven
drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu 
handshake

drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
drm/amdgpu/gfx9: allow updating gfx cgpg state
drm/amdgpu/gfx9: allow updating gfx mgpg state
drm/amdgpu: enable dcn1.0 dc support on raven

Huang Rui (17):
drm/amdgpu/soc15: add clock gating functions for raven
drm/amdgpu: enable soc15 clock gating flags for raven
drm/amdgpu: add gfx clock gating for raven
drm/amdgpu: add raven clock gating and light sleep for mmhub
drm/amdgpu: enable MC MGCG and LS for raven
drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
drm/amdgpu: enable sdma v4 MGCG and LS for raven
drm/amdgpu: init sdma power gating for raven
drm/amdgpu/sdma4: add dynamic power gating for raven
drm/amdgpu: enable sdma power gating for raven
drm/amdgpu: add nbio MGCG for raven
drm/amdgpu: add psp v10 function callback for raven
drm/amdgpu: add psp v10 ip block
drm/amdgpu: register the psp v10 function pointers at psp sw_init
drm/amdgpu/soc15: add psp ip block
drm/amd

[PATCH 3/4] drm/amdgpu: Support page directory update via CPU

[Harish Kasiviswanathan]

If amdgpu.vm_update_context param is set to use CPU, then Page
Directories will be updated by CPU instead of SDMA

Signed-off-by: Harish Kasiviswanathan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 141 +++--
 1 file changed, 99 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ff6cf33..63f0572 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -271,6 +271,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
*adev,
  uint64_t saddr, uint64_t eaddr,
  unsigned level)
 {
+   u64 flags;
unsigned shift = (adev->vm_manager.num_level - level) *
adev->vm_manager.block_size;
unsigned pt_idx, from, to;
@@ -299,6 +300,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
*adev,
saddr = saddr & ((1 << shift) - 1);
eaddr = eaddr & ((1 << shift) - 1);
 
+   flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+   AMDGPU_GEM_CREATE_VRAM_CLEARED;
+   if (vm->is_vm_update_mode_cpu)
+   flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   else
+   flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+   AMDGPU_GEM_CREATE_SHADOW);
+
/* walk over the address space and allocate the page tables */
for (pt_idx = from; pt_idx <= to; ++pt_idx) {
struct reservation_object *resv = vm->root.bo->tbo.resv;
@@ -310,10 +319,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
*adev,
 amdgpu_vm_bo_size(adev, level),
 AMDGPU_GPU_PAGE_SIZE, true,
 AMDGPU_GEM_DOMAIN_VRAM,
-AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-AMDGPU_GEM_CREATE_SHADOW |
-AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
-AMDGPU_GEM_CREATE_VRAM_CLEARED,
+flags,
 NULL, resv, &pt);
if (r)
return r;
@@ -953,6 +959,34 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t 
*pages_addr, uint64_t addr)
return result;
 }
 
+/**
+ * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
+ *
+ * @params: see amdgpu_pte_update_params definition
+ * @pe: kmap addr of the page entry
+ * @addr: dst addr to write into pe
+ * @count: number of page entries to update
+ * @incr: increase next addr by incr bytes
+ * @flags: hw access flags
+ */
+static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
+  uint64_t pe, uint64_t addr,
+  unsigned count, uint32_t incr,
+  uint64_t flags)
+{
+   unsigned int i;
+
+   for (i = 0; i < count; i++) {
+   amdgpu_gart_set_pte_pde(params->adev, (void *)pe,
+   i, addr, flags);
+   addr += incr;
+   }
+
+   mb();
+   amdgpu_gart_flush_gpu_tlb(params->adev, 0);
+}
+
+
 /*
  * amdgpu_vm_update_level - update a single level in the hierarchy
  *
@@ -982,34 +1016,49 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
 
if (!parent->entries)
return 0;
-   ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 
-   /* padding, etc. */
-   ndw = 64;
+   memset(¶ms, 0, sizeof(params));
+   params.adev = adev;
+   shadow = parent->bo->shadow;
 
-   /* assume the worst case */
-   ndw += parent->last_entry_used * 6;
+   WARN_ON(vm->is_vm_update_mode_cpu && shadow);
+   if (vm->is_vm_update_mode_cpu && !shadow) {
+   r = amdgpu_bo_kmap(parent->bo, (void **)&pd_addr);
+   if (r)
+   return r;
+   params.func = amdgpu_vm_cpu_set_ptes;
+   } else {
+   if (shadow) {
+   r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
+   if (r)
+   return r;
+   }
+   ring = container_of(vm->entity.sched, struct amdgpu_ring,
+   sched);
 
-   pd_addr = amdgpu_bo_gpu_offset(parent->bo);
+   /* padding, etc. */
+   ndw = 64;
 
-   shadow = parent->bo->shadow;
-   if (shadow) {
-   r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
+   /* assume the worst case */
+   ndw += parent->last_entry_used * 6;
+
+   pd_addr = amdgpu_bo_gpu_offset(parent->bo);
+
+   if (shadow) {
+  

[PATCH 4/4] drm/amdgpu: Support page table update via CPU

[Harish Kasiviswanathan]

Signed-off-by: Harish Kasiviswanathan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 82 +-
 1 file changed, 81 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 63f0572..63b4696 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -79,6 +79,12 @@ struct amdgpu_pte_update_params {
 uint64_t flags);
/* indicate update pt or its shadow */
bool shadow;
+   /* The next two are used during VM update by CPU
+*  DMA addresses to use for mapping
+*  Kernel pointer of PD/PT BO that needs to be updated
+*/
+   dma_addr_t *pages_addr;
+   void *kptr;
 };
 
 /* Helper to disable partial resident texture feature from a fence callback */
@@ -975,10 +981,14 @@ static void amdgpu_vm_cpu_set_ptes(struct 
amdgpu_pte_update_params *params,
   uint64_t flags)
 {
unsigned int i;
+   uint64_t value;
 
for (i = 0; i < count; i++) {
+   value = params->pages_addr ?
+   amdgpu_vm_map_gart(params->pages_addr, addr) :
+   addr;
amdgpu_gart_set_pte_pde(params->adev, (void *)pe,
-   i, addr, flags);
+   i, value, flags);
addr += incr;
}
 
@@ -1211,6 +1221,59 @@ static struct amdgpu_bo *amdgpu_vm_get_pt(struct 
amdgpu_pte_update_params *p,
 }
 
 /**
+ * amdgpu_vm_update_ptes_cpu - Update the page tables in the range
+ *  start - @end using CPU.
+ * See amdgpu_vm_update_ptes for parameter description.
+ *
+ */
+static int amdgpu_vm_update_ptes_cpu(struct amdgpu_pte_update_params *params,
+uint64_t start, uint64_t end,
+uint64_t dst, uint64_t flags)
+{
+   struct amdgpu_device *adev = params->adev;
+   const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
+   void *pe_ptr;
+   uint64_t addr;
+   struct amdgpu_bo *pt;
+   unsigned int nptes;
+   int r;
+
+   /* initialize the variables */
+   addr = start;
+
+   /* walk over the address space and update the page tables */
+   while (addr < end) {
+   pt = amdgpu_vm_get_pt(params, addr);
+   if (!pt) {
+   pr_err("PT not found, aborting update_ptes\n");
+   return -EINVAL;
+   }
+
+   WARN_ON(params->shadow);
+
+   r = amdgpu_bo_kmap(pt, &pe_ptr);
+   if (r)
+   return r;
+
+   pe_ptr += (addr & mask) * 8;
+
+   if ((addr & ~mask) == (end & ~mask))
+   nptes = end - addr;
+   else
+   nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
+
+   params->func(params, (uint64_t)pe_ptr, dst, nptes,
+AMDGPU_GPU_PAGE_SIZE, flags);
+
+   amdgpu_bo_kunmap(pt);
+   addr += nptes;
+   dst += nptes * AMDGPU_GPU_PAGE_SIZE;
+   }
+
+   return 0;
+}
+
+/**
  * amdgpu_vm_update_ptes - make sure that page tables are valid
  *
  * @params: see amdgpu_pte_update_params definition
@@ -1236,6 +1299,10 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
unsigned nptes; /* next number of ptes to be updated */
uint64_t next_pe_start;
 
+   if (params->func == amdgpu_vm_cpu_set_ptes)
+   return amdgpu_vm_update_ptes_cpu(params, start, end,
+dst, flags);
+
/* initialize the variables */
addr = start;
pt = amdgpu_vm_get_pt(params, addr);
@@ -1422,6 +1489,19 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
params.vm = vm;
params.src = src;
 
+   if (vm->is_vm_update_mode_cpu) {
+   /* params.src is used as flag to indicate system Memory */
+   if (pages_addr)
+   params.src = ~0;
+
+   params.func = amdgpu_vm_cpu_set_ptes;
+   params.pages_addr = pages_addr;
+   params.shadow = false;
+   r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
+   if (!r)
+   return r;
+   }
+
ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 
/* sync to everything on unmapping */
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/4] drm/amdgpu: Return EINVAL if no PT BO

[Harish Kasiviswanathan]

This change is also useful for the upcoming changes where page tables
can be updated by CPU.

Change-Id: I07510ed60c94cf1944ee96bb4b16c40ec88ea17c
Signed-off-by: Harish Kasiviswanathan 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 48 +-
 1 file changed, 30 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 3e97004..5d92e73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1165,8 +1165,9 @@ static struct amdgpu_bo *amdgpu_vm_get_pt(struct 
amdgpu_pte_update_params *p,
  * @flags: mapping flags
  *
  * Update the page tables in the range @start - @end.
+ * Returns 0 for success, -EINVAL for failure.
  */
-static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
+static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
  uint64_t start, uint64_t end,
  uint64_t dst, uint64_t flags)
 {
@@ -1184,12 +1185,12 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
pt = amdgpu_vm_get_pt(params, addr);
if (!pt) {
pr_err("PT not found, aborting update_ptes\n");
-   return;
+   return -EINVAL;
}
 
if (params->shadow) {
if (!pt->shadow)
-   return;
+   return 0;
pt = pt->shadow;
}
if ((addr & ~mask) == (end & ~mask))
@@ -1211,12 +1212,12 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
pt = amdgpu_vm_get_pt(params, addr);
if (!pt) {
pr_err("PT not found, aborting update_ptes\n");
-   return;
+   return -EINVAL;
}
 
if (params->shadow) {
if (!pt->shadow)
-   return;
+   return 0;
pt = pt->shadow;
}
 
@@ -1251,6 +1252,8 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
 
params->func(params, cur_pe_start, cur_dst, cur_nptes,
 AMDGPU_GPU_PAGE_SIZE, flags);
+
+   return 0;
 }
 
 /*
@@ -1262,11 +1265,14 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
  * @end: last PTE to handle
  * @dst: addr those PTEs should point to
  * @flags: hw mapping flags
+ * Returns 0 for success, -EINVAL for failure.
  */
-static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params*params,
+static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags)
 {
+   int r;
+
/**
 * The MC L1 TLB supports variable sized pages, based on a fragment
 * field in the PTE. When this field is set to a non-zero value, page
@@ -1295,28 +1301,30 @@ static void amdgpu_vm_frag_ptes(struct 
amdgpu_pte_update_params *params,
 
/* system pages are non continuously */
if (params->src || !(flags & AMDGPU_PTE_VALID) ||
-   (frag_start >= frag_end)) {
-
-   amdgpu_vm_update_ptes(params, start, end, dst, flags);
-   return;
-   }
+   (frag_start >= frag_end))
+   return amdgpu_vm_update_ptes(params, start, end, dst, flags);
 
/* handle the 4K area at the beginning */
if (start != frag_start) {
-   amdgpu_vm_update_ptes(params, start, frag_start,
- dst, flags);
+   r = amdgpu_vm_update_ptes(params, start, frag_start,
+ dst, flags);
+   if (r)
+   return r;
dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
}
 
/* handle the area in the middle */
-   amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
- flags | frag_flags);
+   r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
+ flags | frag_flags);
+   if (r)
+   return r;
 
/* handle the 4K area at the end */
if (frag_end != end) {
dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
-   amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
+   r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
}
+   return r;
 }
 
 /**
@@ -1437,9 +1445,13 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
goto error_free;
 
params.shadow = true;
-   amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
+   r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, add

Re: [PATCH 5/5] amdgpu: use drm sync objects for shared semaphores (v4)

[zhoucm1]

1. generally, functions in amdgpu_cs.c should be with amdgpu_cs_ as prefix.
2. If I'm not wrong to your proposal, SYNCOBJ_IN is to semaphore wait 
while SYNCOBJ_OUT is to semaphore signal. SYNCOBJ_IN/OUT both are based 
on command submission ioctl, that means user space must generate CS when 
using semaphore? but with my understand, they should not be dependent 
with that, they can be used independently, right?


Anything I missed, if yes, pls correct me.

+   case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:

Regards,
David Zhou
On 2017年05月12日 08:34, Dave Airlie wrote:

From: Dave Airlie 

This creates a new command submission chunk for amdgpu
to add in and out sync objects around the submission.

Sync objects are managed via the drm syncobj ioctls.

The command submission interface is enhanced with two new
chunks, one for syncobj pre submission dependencies,
and one for post submission sync obj signalling,
and just takes a list of handles for each.

This is based on work originally done by David Zhou at AMD,
with input from Christian Konig on what things should look like.

In theory VkFences could be backed with sync objects and
just get passed into the cs as syncobj handles as well.

NOTE: this interface addition needs a version bump to expose
it to userspace.

v1.1: keep file reference on import.
v2: move to using syncobjs
v2.1: change some APIs to just use p pointer.
v3: make more robust against CS failures, we now add the
wait sems but only remove them once the CS job has been
submitted.
v4: rewrite names of API and base on new syncobj code.

Signed-off-by: Dave Airlie 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 81 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  2 +-
  include/uapi/drm/amdgpu_drm.h   |  6 +++
  3 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index df25b32..e86c832 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -27,6 +27,7 @@
  #include 
  #include 
  #include 
+#include 
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
  
@@ -217,6 +218,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)

break;
  
  		case AMDGPU_CHUNK_ID_DEPENDENCIES:

+   case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
break;
  
  		default:

@@ -1008,6 +1011,40 @@ static int amdgpu_process_fence_dep(struct 
amdgpu_cs_parser *p,
return 0;
  }
  
+static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,

+uint32_t handle)
+{
+   int r;
+   struct dma_fence *fence;
+   r = drm_syncobj_fence_get(p->filp, handle, &fence);
+   if (r)
+   return r;
+
+   r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
+   dma_fence_put(fence);
+
+   return r;
+}
+
+static int amdgpu_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
+struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   for (i = 0; i < num_deps; ++i) {
+   r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
  static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
  struct amdgpu_cs_parser *p)
  {
@@ -1022,12 +1059,54 @@ static int amdgpu_cs_dependencies(struct amdgpu_device 
*adev,
r = amdgpu_process_fence_dep(p, chunk);
if (r)
return r;
+   } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
+   r = amdgpu_process_syncobj_in_dep(p, chunk);
+   if (r)
+   return r;
}
}
  
  	return 0;

  }
  
+static int amdgpu_process_syncobj_out_dep(struct amdgpu_cs_parser *p,

+ struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   for (i = 0; i < num_deps; ++i) {
+   r = drm_syncobj_replace_fence(p->filp, deps[i].handle,
+ p->fence);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
+static int amdgpu_cs_post_dependencies(struc

Re: [PATCH 5/5] amdgpu: use drm sync objects for shared semaphores (v4)

[Dave Airlie]

On 12 May 2017 at 13:34, zhoucm1  wrote:
> 1. generally, functions in amdgpu_cs.c should be with amdgpu_cs_ as prefix.

Okay I've fixed this and previous patch up locally.

> 2. If I'm not wrong to your proposal, SYNCOBJ_IN is to semaphore wait while
> SYNCOBJ_OUT is to semaphore signal. SYNCOBJ_IN/OUT both are based on command
> submission ioctl, that means user space must generate CS when using
> semaphore?  but with my understand, they should not be dependent with that,
> they can be used independently, right?

Yes in is WAIT and out is signal, however OUT could also be used to
write a syncobj as a fence if needed, hence why I moved away from
semaphore naming.

The only place I can see them being used independently is a possible
signal operation after present, due not being able to pass the
semaphores over dri3 yet. I think I've said this before and Christian
has confirmed that doing anything with semaphores not via the command
submission ioctl is going to be messy as they have to queue jobs in
the scheduler, so if we need to tune the command submission ioctl to
take empty CS or add a flag to just do semaphore operations we should
do so in the future when we have a clear use case for it (and we see
the need to optimise for it).

Dave.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/5] drm: introduce sync objects (v2)

[Andres Rodriguez]

On 2017-05-11 08:34 PM, Dave Airlie wrote:

From: Dave Airlie 

Sync objects are new toplevel drm object, that contain a
pointer to a fence. This fence can be updated via command
submission ioctls via drivers.

There is also a generic wait obj API modelled on the vulkan
wait API (with code modelled on some amdgpu code).

These objects can be converted to an opaque fd that can be
passes between processes.

v2: rename reference/unreference to put/get (Chris)
fix leaked reference (David Zhou)
drop mutex in favour of cmpxchg (Chris)
document drm_syncobj_fence_get
use ENOENT for syncobj lookup.

Signed-off-by: Dave Airlie 

fixup


Seems like a small `git rebase -i` artifact is leftover here.


---
 Documentation/gpu/drm-internals.rst |   3 +
 Documentation/gpu/drm-mm.rst|   6 +
 drivers/gpu/drm/Makefile|   2 +-
 drivers/gpu/drm/drm_fops.c  |   8 +
 drivers/gpu/drm/drm_internal.h  |  13 ++
 drivers/gpu/drm/drm_ioctl.c |  12 ++
 drivers/gpu/drm/drm_syncobj.c   | 385 
 include/drm/drmP.h  |   5 +
 include/drm/drm_drv.h   |   1 +
 include/drm/drm_syncobj.h   |  87 
 include/uapi/drm/drm.h  |  25 +++
 11 files changed, 546 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_syncobj.c
 create mode 100644 include/drm/drm_syncobj.h

diff --git a/Documentation/gpu/drm-internals.rst 
b/Documentation/gpu/drm-internals.rst
index e35920d..2ea3bce 100644
--- a/Documentation/gpu/drm-internals.rst
+++ b/Documentation/gpu/drm-internals.rst
@@ -98,6 +98,9 @@ DRIVER_ATOMIC
 implement appropriate obj->atomic_get_property() vfuncs for any
 modeset objects with driver specific properties.

+DRIVER_SYNCOBJ
+Driver support drm sync objects.
+
 Major, Minor and Patchlevel
 ~~~

diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index f5760b1..28aebe8 100644
--- a/Documentation/gpu/drm-mm.rst
+++ b/Documentation/gpu/drm-mm.rst
@@ -483,3 +483,9 @@ DRM Cache Handling

 .. kernel-doc:: drivers/gpu/drm/drm_cache.c
:export:
+
+DRM Sync Objects
+===
+
+.. kernel-doc:: drivers/gpu/drm/drm_syncobj.c
+   :export:
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 3ee9579..b5e565c 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -16,7 +16,7 @@ drm-y   :=drm_auth.o drm_bufs.o drm_cache.o \
drm_framebuffer.o drm_connector.o drm_blend.o \
drm_encoder.o drm_mode_object.o drm_property.o \
drm_plane.o drm_color_mgmt.o drm_print.o \
-   drm_dumb_buffers.o drm_mode_config.o
+   drm_dumb_buffers.o drm_mode_config.o drm_syncobj.o

 drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
 drm-$(CONFIG_DRM_VM) += drm_vm.o
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index afdf5b1..9a61df2 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -219,6 +219,9 @@ static int drm_open_helper(struct file *filp, struct 
drm_minor *minor)
if (drm_core_check_feature(dev, DRIVER_GEM))
drm_gem_open(dev, priv);

+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_open(priv);
+
if (drm_core_check_feature(dev, DRIVER_PRIME))
drm_prime_init_file_private(&priv->prime);

@@ -266,6 +269,8 @@ static int drm_open_helper(struct file *filp, struct 
drm_minor *minor)
 out_prime_destroy:
if (drm_core_check_feature(dev, DRIVER_PRIME))
drm_prime_destroy_file_private(&priv->prime);
+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_release(priv);
if (drm_core_check_feature(dev, DRIVER_GEM))
drm_gem_release(dev, priv);
put_pid(priv->pid);
@@ -400,6 +405,9 @@ int drm_release(struct inode *inode, struct file *filp)
drm_property_destroy_user_blobs(dev, file_priv);
}

+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_release(file_priv);
+
if (drm_core_check_feature(dev, DRIVER_GEM))
drm_gem_release(dev, file_priv);

diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index f37388c..44ef903 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -142,4 +142,17 @@ static inline int drm_debugfs_crtc_crc_add(struct drm_crtc 
*crtc)
 {
return 0;
 }
+
 #endif
+
+/* drm_syncobj.c */
+void drm_syncobj_open(struct drm_file *file_private);
+void drm_syncobj_release(struct drm_file *file_private);
+int drm_syncobj_create_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file_private);
+int drm_syncobj_destroy_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_private);
+int drm_syncobj_handle_to_fd_ioctl(struct d

Re: [PATCH 5/5] amdgpu: use drm sync objects for shared semaphores (v4)

[Andres Rodriguez]

The series looks ok to me so far, just the minor rebase nit on the first 
patch.


Let me take an look again tomorrow morning since it is 1am and I 
might've missed something.


Regards,
Andres

On 2017-05-11 08:34 PM, Dave Airlie wrote:

From: Dave Airlie 

This creates a new command submission chunk for amdgpu
to add in and out sync objects around the submission.

Sync objects are managed via the drm syncobj ioctls.

The command submission interface is enhanced with two new
chunks, one for syncobj pre submission dependencies,
and one for post submission sync obj signalling,
and just takes a list of handles for each.

This is based on work originally done by David Zhou at AMD,
with input from Christian Konig on what things should look like.

In theory VkFences could be backed with sync objects and
just get passed into the cs as syncobj handles as well.

NOTE: this interface addition needs a version bump to expose
it to userspace.

v1.1: keep file reference on import.
v2: move to using syncobjs
v2.1: change some APIs to just use p pointer.
v3: make more robust against CS failures, we now add the
wait sems but only remove them once the CS job has been
submitted.
v4: rewrite names of API and base on new syncobj code.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 81 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  2 +-
 include/uapi/drm/amdgpu_drm.h   |  6 +++
 3 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index df25b32..e86c832 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "amdgpu.h"
 #include "amdgpu_trace.h"

@@ -217,6 +218,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void 
*data)
break;

case AMDGPU_CHUNK_ID_DEPENDENCIES:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
break;

default:
@@ -1008,6 +1011,40 @@ static int amdgpu_process_fence_dep(struct 
amdgpu_cs_parser *p,
return 0;
 }

+static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
+uint32_t handle)
+{
+   int r;
+   struct dma_fence *fence;
+   r = drm_syncobj_fence_get(p->filp, handle, &fence);
+   if (r)
+   return r;
+
+   r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
+   dma_fence_put(fence);
+
+   return r;
+}
+
+static int amdgpu_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
+struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   for (i = 0; i < num_deps; ++i) {
+   r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
  struct amdgpu_cs_parser *p)
 {
@@ -1022,12 +1059,54 @@ static int amdgpu_cs_dependencies(struct amdgpu_device 
*adev,
r = amdgpu_process_fence_dep(p, chunk);
if (r)
return r;
+   } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
+   r = amdgpu_process_syncobj_in_dep(p, chunk);
+   if (r)
+   return r;
}
}

return 0;
 }

+static int amdgpu_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
+ struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   for (i = 0; i < num_deps; ++i) {
+   r = drm_syncobj_replace_fence(p->filp, deps[i].handle,
+ p->fence);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
+static int amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
+{
+   int i, r;
+
+   for (i = 0; i < p->nchunks; ++i) {
+   struct amdgpu_cs_chunk *chunk;
+
+   chunk = &p->chunks[i];
+
+   if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
+   r = amdgpu_process_syncobj_out_dep(p, chunk);
+   if (r)
+   retu

Re: [PATCH 5/5] amdgpu: use drm sync objects for shared semaphores (v4)

[zhoucm1]

On 2017年05月12日 12:17, Dave Airlie wrote:

On 12 May 2017 at 13:34, zhoucm1  wrote:

1. generally, functions in amdgpu_cs.c should be with amdgpu_cs_ as prefix.

Okay I've fixed this and previous patch up locally.


2. If I'm not wrong to your proposal, SYNCOBJ_IN is to semaphore wait while
SYNCOBJ_OUT is to semaphore signal. SYNCOBJ_IN/OUT both are based on command
submission ioctl, that means user space must generate CS when using
semaphore?  but with my understand, they should not be dependent with that,
they can be used independently, right?

Yes in is WAIT and out is signal, however OUT could also be used to
write a syncobj as a fence if needed, hence why I moved away from
semaphore naming.

The only place I can see them being used independently is a possible
signal operation after present, due not being able to pass the
semaphores over dri3 yet. I think I've said this before and Christian
has confirmed that doing anything with semaphores not via the command
submission ioctl is going to be messy as they have to queue jobs in
the scheduler, so if we need to tune the command submission ioctl to
take empty CS or add a flag to just do semaphore operations we should
do so in the future when we have a clear use case for it (and we see
the need to optimise for it).

I see.
+David Mao and Jacob to aware, they are expert of Vulkan, if they have 
no concern, It's ok.


Regards,
David Zhou


Dave.


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: fix sem list soft lockup issue

[Junwei Zhang]

sem should be delete from the previous sem list
then add to the new sem list.

If adding sem to the list which is same as previous one,
it will cause endless loop when traverses the sem list.

[  264.133878] NMI watchdog: BUG: soft lockup - CPU#5 stuck for 22s!
...
[  264.133928] task: a216ffbfbd00 task.stack: a216f422
[  264.133929] RIP: 0010:[]  []
amdgpu_sem_put+0x13/0x30 [amdgpu]
[  264.133983] RSP: 0018:a216f4223cb0  EFLAGS: 00200286

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index ff20e11..aac43c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -84,8 +84,10 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
 
mutex_lock(&ctx->rings[i].sem_lock);
/* release all the reset inserted SEM here */
-   list_for_each_entry_safe(sem, tmp, &ctx->rings[i].sem_list, 
list)
+   list_for_each_entry_safe(sem, tmp, &ctx->rings[i].sem_list, 
list) {
+   list_del_init(&sem->list);
amdgpu_sem_put(sem);
+   }
 
mutex_unlock(&ctx->rings[i].sem_lock);
mutex_destroy(&ctx->rings[i].sem_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
index 0302ea6..a7149ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
@@ -371,6 +371,7 @@ static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv,
if (r)
goto err;
mutex_lock(&ctx->rings[out_ring->idx].sem_lock);
+   list_del_init(&sem->list);
list_add(&sem->list, &ctx->rings[out_ring->idx].sem_list);
mutex_unlock(&ctx->rings[out_ring->idx].sem_lock);
amdgpu_sem_get(sem);
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: Unbreak HPD handling for r600+

[Christian König]

Am 12.05.2017 um 01:31 schrieb Lyude:

We end up reading the interrupt register for HPD5, and then writing it
to HPD6 which on systems without anything using HPD5 results in
permanently disabling hotplug on one of the display outputs after the
first time we acknowledge a hotplug interrupt from the GPU.

This code is really bad. But for now, let's just fix this. I will
hopefully have a large patch series to refactor all of this soon.

Signed-off-by: Lyude 
Cc: sta...@vger.kernel.org


Really nice catch! And yes I agree the copy&pasted code in HPD handling 
always scared me as well.


Patch is Reviewed-by: Christian König .

Christian.


---
  drivers/gpu/drm/radeon/cik.c   | 4 ++--
  drivers/gpu/drm/radeon/evergreen.c | 4 ++--
  drivers/gpu/drm/radeon/r600.c  | 2 +-
  drivers/gpu/drm/radeon/si.c| 4 ++--
  4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 53710dd..cfc917c 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7401,7 +7401,7 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
@@ -7431,7 +7431,7 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_RX_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index d1b1e0c..c48d19e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4933,7 +4933,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
@@ -4964,7 +4964,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & 
DC_HPD6_RX_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_RX_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0a08517..e06e2d8 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3988,7 +3988,7 @@ static void r600_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.r600.disp_int_cont2 & 
DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 528e5a4..bfeb774 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6330,7 +6330,7 @@ static inline void si_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}
@@ -6361,7 +6361,7 @@ static inline void si_irq_ack(struct radeon_device *rdev)
WREG32(DC_HPD5_INT_CONTROL, tmp);
}
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & 
DC_HPD6_RX_INTERRUPT) {
-   tmp = RREG32(DC_HPD5_INT_CONTROL);
+   tmp = RREG32(DC_HPD6_INT_CONTROL);
tmp |= DC_HPDx_RX_INT_ACK;
WREG32(DC_HPD6_INT_CONTROL, tmp);
}



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: fix sem list soft lockup issue

[Zhou, David(ChunMing)]

This is internal only patch, please send to internal mail list.

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
Junwei Zhang
Sent: Friday, May 12, 2017 2:54 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jerry 
Subject: [PATCH] drm/amdgpu: fix sem list soft lockup issue

sem should be delete from the previous sem list then add to the new sem list.

If adding sem to the list which is same as previous one, it will cause endless 
loop when traverses the sem list.

[  264.133878] NMI watchdog: BUG: soft lockup - CPU#5 stuck for 22s!
...
[  264.133928] task: a216ffbfbd00 task.stack: a216f422 [  
264.133929] RIP: 0010:[]  []
amdgpu_sem_put+0x13/0x30 [amdgpu]
[  264.133983] RSP: 0018:a216f4223cb0  EFLAGS: 00200286

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +++-  
drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index ff20e11..aac43c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -84,8 +84,10 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
 
mutex_lock(&ctx->rings[i].sem_lock);
/* release all the reset inserted SEM here */
-   list_for_each_entry_safe(sem, tmp, &ctx->rings[i].sem_list, 
list)
+   list_for_each_entry_safe(sem, tmp, &ctx->rings[i].sem_list, 
list) {
+   list_del_init(&sem->list);
amdgpu_sem_put(sem);
+   }
 
mutex_unlock(&ctx->rings[i].sem_lock);
mutex_destroy(&ctx->rings[i].sem_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
index 0302ea6..a7149ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
@@ -371,6 +371,7 @@ static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv,
if (r)
goto err;
mutex_lock(&ctx->rings[out_ring->idx].sem_lock);
+   list_del_init(&sem->list);
list_add(&sem->list, &ctx->rings[out_ring->idx].sem_list);
mutex_unlock(&ctx->rings[out_ring->idx].sem_lock);
amdgpu_sem_get(sem);
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx