Re: [PATCH 2/3] drm/amdgpu: add psp ecc support

2017-07-30 Thread Huang Rui 
On Fri, Jul 28, 2017 at 05:11:18PM +0800, Junwei Zhang wrote:
> Signed-off-by: Junwei Zhang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 ++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 22 ++
>  2 files changed, 36 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 1aa41af..b04cc80 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -256,6 +256,10 @@ static int psp_hw_start(struct psp_context *psp)
>  {
>   int ret;
>  
> + ret = psp_bootloader_set_ecc_mode(psp);
> + if (ret)
> + return ret;
> +
>   ret = psp_bootloader_load_sysdrv(psp);
>   if (ret)
>   return ret;
> @@ -365,9 +369,16 @@ static int psp_load_fw(struct amdgpu_device *adev)
>   if (ret)
>   goto failed_mem;
>  
> - ret = psp_hw_start(psp);
> - if (ret)
> - goto failed_mem;
> + if (psp_bootloader_is_sos_running(psp) &&
> + psp->config.ecc_mode != PSP_ECC_MODE__NONE) {

It need set a default value to config psp->ecc_mode, otherwise, it is
always "0" in this implementation.

> + if (psp_ring_create(psp, PSP_RING_TYPE__KM))
> + goto failed_mem;
> + if (psp_tmr_load(psp))
> + goto failed_mem;
> + } else {
> + if (psp_hw_start(psp))
> + goto failed_mem;
> + }
>  
>   ret = psp_np_fw_load(psp);
>   if (ret)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 3776186..8ec9194 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -63,6 +63,19 @@ enum psp_bootloader_command_list
>   PSP_BL__DEFAULT_ECC = 0x30003,
>  };
>  
> +enum psp_ecc_mode
> +{
> + PSP_ECC_MODE__NONE = 0,
> + PSP_ECC_MODE__OFF = 1,
> + PSP_ECC_MODE__ON = 2,
> + PSP_ECC_MODE__PARTIALON = 3,
> +};
> +
> +struct psp_config
> +{
> + enum psp_ecc_mode   ecc_mode;
> +};
> +
>  struct psp_context
>  {
>   struct amdgpu_device*adev;
> @@ -70,6 +83,8 @@ struct psp_context
>   struct psp_gfx_cmd_resp *cmd;
>  
>   int (*init_microcode)(struct psp_context *psp);
> + int (*bootloader_set_ecc_mode)(struct psp_context *psp);
> + bool (*bootloader_is_sos_running)(struct psp_context *psp);
>   int (*bootloader_load_sysdrv)(struct psp_context *psp);
>   int (*bootloader_load_sos)(struct psp_context *psp);
>   int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
> @@ -123,6 +138,9 @@ struct psp_context
>   struct amdgpu_bo*cmd_buf_bo;
>   uint64_tcmd_buf_mc_addr;
>   struct psp_gfx_cmd_resp *cmd_buf_mem;
> +
> + /* psp config */
> + struct psp_config   config;

At current, we don't need a psp_config wrapper here. Use "enum ecc_mode"
directly to make code more simple.

>  };
>  
>  struct amdgpu_psp_funcs {
> @@ -140,6 +158,10 @@ struct amdgpu_psp_funcs {
>   (psp)->compare_sram_data((psp), (ucode), (type))
>  #define psp_init_microcode(psp) \
>   ((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
> +#define psp_bootloader_set_ecc_mode(psp) \
> + ((psp)->bootloader_set_ecc_mode ? 
> (psp)->bootloader_set_ecc_mode((psp)) : 0)
> +#define psp_bootloader_is_sos_running(psp) \
> + ((psp)->bootloader_is_sos_running ? 
> (psp)->bootloader_is_sos_running((psp)) : 0)
>  #define psp_bootloader_load_sysdrv(psp) \
>   ((psp)->bootloader_load_sysdrv ? 
> (psp)->bootloader_load_sysdrv((psp)) : 0)
>  #define psp_bootloader_load_sos(psp) \
> -- 
> 1.9.1
> 
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Re: [PATCH 1/3] drm/amdgpu: add psp bootloader command list

2017-07-30 Thread Huang Rui 
On Fri, Jul 28, 2017 at 05:11:17PM +0800, Junwei Zhang wrote:
> Signed-off-by: Junwei Zhang 
> ---

Reviewed-by: Huang Rui 

>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 10 ++
>  drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   |  4 ++--
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 538fa9d..3776186 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -53,6 +53,16 @@ struct psp_ring
>   uint32_tring_size;
>  };
>  
> +enum psp_bootloader_command_list
> +{
> + PSP_BL__LOAD_SYSDRV = 0x1,
> + PSP_BL__LOAD_SOSDRV = 0x2,
> + PSP_BL__NO_ECC  = 0x3,
> + PSP_BL__PARTIAL_ECC = 0x30001,
> + PSP_BL__FULL_ECC= 0x30002,
> + PSP_BL__DEFAULT_ECC = 0x30003,
> +};
> +
>  struct psp_context
>  {
>   struct amdgpu_device*adev;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
> b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 2718e86..f93a66e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -190,7 +190,7 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context 
> *psp)
>   /* Provide the sys driver to bootrom */
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>  (uint32_t)(psp->fw_pri_mc_addr >> 20));
> - psp_gfxdrv_command_reg = 1 << 16;
> + psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
>  psp_gfxdrv_command_reg);
>  
> @@ -231,7 +231,7 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
>   /* Provide the PSP secure OS to bootrom */
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>  (uint32_t)(psp->fw_pri_mc_addr >> 20));
> - psp_gfxdrv_command_reg = 2 << 16;
> + psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
>  psp_gfxdrv_command_reg);
>  
> -- 
> 1.9.1
> 
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Re: [PATCH 1/3] drm/amdgpu: only move VM BOs in the LRU during validation v2

2017-07-30 Thread zhoucm1 

The series is Acked-by: Chunming Zhou 


On 2017年07月29日 19:32, Christian König wrote:

From: Christian König 

This should save us a bunch of command submission overhead.

v2: move the LRU move to the right place to avoid the move for the root BO
 and handle the shadow BOs as well. This turned out to be a bug fix because
 the move needs to happen before the kmap.

Signed-off-by: Christian König 
Reviewed-by: Felix Kuehling  (v1)
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 15 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 58 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  2 --
  3 files changed, 16 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index cd5c08a..7fb4baa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -669,10 +669,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
}
  
  error_validate:

-   if (r) {
-   amdgpu_vm_move_pt_bos_in_lru(p->adev, >vm);
+   if (r)
ttm_eu_backoff_reservation(>ticket, >validated);
-   }
  
  error_free_pages:
  
@@ -720,21 +718,18 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)

   * If error is set than unvalidate buffer, otherwise just free memory
   * used by parsing context.
   **/
-static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, 
bool backoff)
+static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
+ bool backoff)
  {
-   struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
unsigned i;
  
-	if (!error) {

-   amdgpu_vm_move_pt_bos_in_lru(parser->adev, >vm);
-
+   if (!error)
ttm_eu_fence_buffer_objects(>ticket,
>validated,
parser->fence);
-   } else if (backoff) {
+   else if (backoff)
ttm_eu_backoff_reservation(>ticket,
   >validated);
-   }
dma_fence_put(parser->fence);
  
  	if (parser->ctx)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a1d4294..a375135 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -159,7 +159,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
   */
  static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
int (*validate)(void *, struct amdgpu_bo *),
-   void *param, bool use_cpu_for_update)
+   void *param, bool use_cpu_for_update,
+   struct ttm_bo_global *glob)
  {
unsigned i;
int r;
@@ -183,12 +184,18 @@ static int amdgpu_vm_validate_level(struct amdgpu_vm_pt 
*parent,
if (r)
return r;
  
+		spin_lock(>lru_lock);

+   ttm_bo_move_to_lru_tail(>bo->tbo);
+   if (entry->bo->shadow)
+   ttm_bo_move_to_lru_tail(>bo->shadow->tbo);
+   spin_unlock(>lru_lock);
+
/*
 * Recurse into the sub directory. This is harmless because we
 * have only a maximum of 5 layers.
 */
r = amdgpu_vm_validate_level(entry, validate, param,
-use_cpu_for_update);
+use_cpu_for_update, glob);
if (r)
return r;
}
@@ -220,54 +227,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
return 0;
  
  	return amdgpu_vm_validate_level(>root, validate, param,

-   vm->use_cpu_for_update);
+   vm->use_cpu_for_update,
+   adev->mman.bdev.glob);
  }
  
  /**

- * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail
- *
- * @adev: amdgpu device instance
- * @vm: vm providing the BOs
- *
- * Move the PT BOs to the tail of the LRU.
- */
-static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent)
-{
-   unsigned i;
-
-   if (!parent->entries)
-   return;
-
-   for (i = 0; i <= parent->last_entry_used; ++i) {
-   struct amdgpu_vm_pt *entry = >entries[i];
-
-   if (!entry->bo)
-   continue;
-
-   ttm_bo_move_to_lru_tail(>bo->tbo);
-   amdgpu_vm_move_level_in_lru(entry);
-   }
-}
-
-/**
- * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
- *
- * @adev: amdgpu device instance
- * @vm: vm providing

Re: [PATCH] drm/amdgpu: Fix undue fallthroughs in golden registers initialization

2017-07-30 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Sun, Jul 30, 2017 at 10:18 AM, Jean Delvare  wrote:

> As I was staring at the si_init_golden_registers code, I noticed that
> the Pitcairn initialization silently falls through the Cape Verde
> initialization, and the Oland initialization falls through the Hainan
> initialization. However there is no comment stating that this is
> intentional, and the radeon driver doesn't have any such fallthrough,
> so I suspect this is not supposed to happen.
>
> Signed-off-by: Jean Delvare 
> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
> Cc: Ken Wang 
> Cc: Alex Deucher 
> Cc: "Marek Olšák" 
> Cc: "Christian König" 
> Cc: Flora Cui 
> ---
> If the fallthroughs are really supposed to happen, comments should be
> added that say so. Surprisingly it doesn't seem to make any
> difference on my Oland card.
>
>  drivers/gpu/drm/amd/amdgpu/si.c |2 ++
>  1 file changed, 2 insertions(+)
>
> --- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/si.c 2017-07-30
> 09:25:46.891083334 +0200
> +++ linux-4.12/drivers/gpu/drm/amd/amdgpu/si.c  2017-07-30
> 09:45:24.350188642 +0200
> @@ -1385,6 +1385,7 @@ static void si_init_golden_registers(str
> amdgpu_program_register_sequence(adev,
>  pitcairn_mgcg_cgcg_init,
>  (const
> u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
> +   break;
> case CHIP_VERDE:
> amdgpu_program_register_sequence(adev,
>  verde_golden_registers,
> @@ -1409,6 +1410,7 @@ static void si_init_golden_registers(str
> amdgpu_program_register_sequence(adev,
>  oland_mgcg_cgcg_init,
>  (const
> u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
> +   break;
> case CHIP_HAINAN:
> amdgpu_program_register_sequence(adev,
>  hainan_golden_registers,
>
>
> --
> Jean Delvare
> SUSE L3 Support
>
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[PATCH] drm/amdgpu: Fix dce_v6_0_disable_dce warning

2017-07-30 Thread Jean Delvare 
Include a missing header to get rid of the following warning:

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c:521:6: warning: no previous prototype for 
'dce_v6_0_disable_dce' [-Wmissing-prototypes]
 void dce_v6_0_disable_dce(struct amdgpu_device *adev)
  ^

Signed-off-by: Jean Delvare 
Cc: Alex Deucher 
Cc: "Christian König" 
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |1 +
 1 file changed, 1 insertion(+)

--- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   2017-07-30 
13:19:50.546603215 +0200
+++ linux-4.12/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c2017-07-30 
13:21:20.083704388 +0200
@@ -42,6 +42,7 @@
 #include "dce/dce_6_0_d.h"
 #include "dce/dce_6_0_sh_mask.h"
 #include "gca/gfx_7_2_enum.h"
+#include "dce_v6_0.h"
 #include "si_enums.h"
 
 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);


-- 
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[PATCH] drm/amdgpu: Fix undue fallthroughs in golden registers initialization

2017-07-30 Thread Jean Delvare 
As I was staring at the si_init_golden_registers code, I noticed that
the Pitcairn initialization silently falls through the Cape Verde
initialization, and the Oland initialization falls through the Hainan
initialization. However there is no comment stating that this is
intentional, and the radeon driver doesn't have any such fallthrough,
so I suspect this is not supposed to happen.

Signed-off-by: Jean Delvare 
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang 
Cc: Alex Deucher 
Cc: "Marek Olšák" 
Cc: "Christian König" 
Cc: Flora Cui 
---
If the fallthroughs are really supposed to happen, comments should be
added that say so. Surprisingly it doesn't seem to make any
difference on my Oland card.

 drivers/gpu/drm/amd/amdgpu/si.c |2 ++
 1 file changed, 2 insertions(+)

--- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/si.c 2017-07-30 
09:25:46.891083334 +0200
+++ linux-4.12/drivers/gpu/drm/amd/amdgpu/si.c  2017-07-30 09:45:24.350188642 
+0200
@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(str
amdgpu_program_register_sequence(adev,
 pitcairn_mgcg_cgcg_init,
 (const 
u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+   break;
case CHIP_VERDE:
amdgpu_program_register_sequence(adev,
 verde_golden_registers,
@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(str
amdgpu_program_register_sequence(adev,
 oland_mgcg_cgcg_init,
 (const 
u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
+   break;
case CHIP_HAINAN:
amdgpu_program_register_sequence(adev,
 hainan_golden_registers,


-- 
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[PATCH] drm/radeon: Make radeon_atif_handler static

2017-07-30 Thread Jean Delvare 
There are no external users of function radeon_atif_handler so it can
be static.

Signed-off-by: Jean Delvare 
Cc: Alex Deucher 
Cc: "Christian König" 
---
 drivers/gpu/drm/radeon/radeon_acpi.c |2 +-
 drivers/gpu/drm/radeon/radeon_acpi.h |3 ---
 2 files changed, 1 insertion(+), 4 deletions(-)

--- linux-4.12.orig/drivers/gpu/drm/radeon/radeon_acpi.c2017-07-03 
01:07:02.0 +0200
+++ linux-4.12/drivers/gpu/drm/radeon/radeon_acpi.c 2017-07-30 
12:58:19.074282660 +0200
@@ -351,7 +351,7 @@ static int radeon_atif_get_sbios_request
  * handles it.
  * Returns NOTIFY code
  */
-int radeon_atif_handler(struct radeon_device *rdev,
+static int radeon_atif_handler(struct radeon_device *rdev,
struct acpi_bus_event *event)
 {
struct radeon_atif *atif = >atif;
--- linux-4.12.orig/drivers/gpu/drm/radeon/radeon_acpi.h2017-07-03 
01:07:02.0 +0200
+++ linux-4.12/drivers/gpu/drm/radeon/radeon_acpi.h 2017-07-30 
12:57:41.427802420 +0200
@@ -27,9 +27,6 @@
 struct radeon_device;
 struct acpi_bus_event;
 
-int radeon_atif_handler(struct radeon_device *rdev,
-   struct acpi_bus_event *event);
-
 /* AMD hw uses four ACPI control methods:
  * 1. ATIF
  * ARG0: (ACPI_INTEGER) function code


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[PATCH] drm/amdgpu: Make amdgpu_atif_handler static

2017-07-30 Thread Jean Delvare 
There are no external users of function amdgpu_atif_handler so it can
be static.

Signed-off-by: Jean Delvare 
Cc: Alex Deucher 
Cc: "Christian König" 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c2017-07-30 
13:06:19.949418618 +0200
+++ linux-4.12/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 2017-07-30 
13:07:14.949120591 +0200
@@ -289,7 +289,7 @@ static int amdgpu_atif_get_sbios_request
  * handles it.
  * Returns NOTIFY code
  */
-int amdgpu_atif_handler(struct amdgpu_device *adev,
+static int amdgpu_atif_handler(struct amdgpu_device *adev,
struct acpi_bus_event *event)
 {
struct amdgpu_atif *atif = >atif;


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[PATCH] drm/amdgpu: Fix amdgpu_pm_acpi_event_handler warning

2017-07-30 Thread Jean Delvare 
Include a missing header to get rid of the following warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:65:6: warning: no previous prototype for 
‘amdgpu_pm_acpi_event_handler’ [-Wmissing-prototypes]
 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  ^

Signed-off-by: Jean Delvare 
Cc: Alex Deucher 
Cc: "Christian König" 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h   |1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

--- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c2017-07-30 
13:18:54.991917627 +0200
+++ linux-4.12/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 2017-07-30 
13:26:16.786365654 +0200
@@ -30,10 +30,10 @@
 #include 
 #include 
 #include "amdgpu.h"
+#include "amdgpu_pm.h"
 #include "amd_acpi.h"
 #include "atom.h"
 
-extern void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
 /* Call the ATIF method
  */
 /**
--- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h  2017-07-30 
13:18:54.991917627 +0200
+++ linux-4.12/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h   2017-07-30 
13:26:16.787365666 +0200
@@ -30,6 +30,7 @@ struct cg_flag_name
const char *name;
 };
 
+void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
 void amdgpu_pm_print_power_states(struct amdgpu_device *adev);


-- 
Jean Delvare
SUSE L3 Support
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[PATCH 3/3] drm/amdgpu: fix Vega10 HW config for 2MB pages

2017-07-30 Thread Christian König 
From: Christian König 

Those values weren't correct. This should result in quite some speedup.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 408723e..6c8040e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -144,8 +144,8 @@ static void gfxhub_v1_0_init_cache_regs(struct 
amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
 
tmp = mmVM_L2_CNTL3_DEFAULT;
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
 
tmp = mmVM_L2_CNTL4_DEFAULT;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index ad8def3..74cb647 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -158,8 +158,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device 
*adev)
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 
tmp = mmVM_L2_CNTL3_DEFAULT;
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 
tmp = mmVM_L2_CNTL4_DEFAULT;
-- 
2.7.4

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[PATCH 2/3] drm/amdgpu: only bind VM shadows after validation v2

2017-07-30 Thread Christian König 
From: Christian König 

No need to do this on every CS.

v2: remove all other bind, reorder code

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 --
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a375135..0308bb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -165,6 +165,14 @@ static int amdgpu_vm_validate_level(struct amdgpu_vm_pt 
*parent,
unsigned i;
int r;
 
+   if (parent->bo->shadow) {
+   struct amdgpu_bo *shadow = parent->bo->shadow;
+
+   r = amdgpu_ttm_bind(>tbo, >tbo.mem);
+   if (r)
+   return r;
+   }
+
if (use_cpu_for_update) {
r = amdgpu_bo_kmap(parent->bo, NULL);
if (r)
@@ -1030,11 +1038,6 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
 
params.func = amdgpu_vm_cpu_set_ptes;
} else {
-   if (shadow) {
-   r = amdgpu_ttm_bind(>tbo, >tbo.mem);
-   if (r)
-   return r;
-   }
ring = container_of(vm->entity.sched, struct amdgpu_ring,
sched);
 
@@ -1070,15 +1073,6 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
if (bo == NULL)
continue;
 
-   if (bo->shadow) {
-   struct amdgpu_bo *pt_shadow = bo->shadow;
-
-   r = amdgpu_ttm_bind(_shadow->tbo,
-   _shadow->tbo.mem);
-   if (r)
-   return r;
-   }
-
pt = amdgpu_bo_gpu_offset(bo);
pt = amdgpu_gart_get_vm_pde(adev, pt);
if (parent->entries[pt_idx].addr == pt ||
-- 
2.7.4

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Re: [PATCH 1/4] drm/amdgpu/sdma4: set wptr shadow atomically (v2)

2017-07-30 Thread Christian König 

Am 28.07.2017 um 22:34 schrieb Alex Deucher:

No functional change until wptr polling uses this
location (future patch).

v2: use WRITE_ONCE

Cc: Frank Min 
Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index bca5d8e..660704d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -293,6 +293,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
  
  	DRM_DEBUG("Setting write pointer\n");

if (ring->use_doorbell) {
+   u64 *wb = (u64 *)>wb.wb[ring->wptr_offs];
+
DRM_DEBUG("Using doorbell -- "
"wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x "
@@ -301,8 +303,7 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
lower_32_bits(ring->wptr << 2),
upper_32_bits(ring->wptr << 2));
/* XXX check if swapping is necessary on BE */
-   adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
-   adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 
2);
+   WRITE_ONCE(*wb, (ring->wptr << 2));
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
ring->doorbell_index, ring->wptr << 2);
  



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