Re: [PATCH] drm/amdgpu: fix amdgpu_vm_handle_moved as well
+if (bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv) {
When we expand mapping fence, we will sync all moved update and clear
here, instead of moved update in amdgpu_vm_bo_update in previous patch.
Yeah, turned out this patch actually didn't worked as expected because
the bo_va->last_pt_update fence could be stale and old and replaces the
new and fresh fence in vm->last_update resulting in VM faults.
I've send a V2 of that patch yesterday which fixes this (and is quite a
bit cleaner in general).
Please take a look at that one instead.
Thanks,
Christian.
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Re: [PATCH] drm/amdgpu: fix amdgpu_vm_handle_moved as well v2
Reviewed-by: Chunming Zhou , but one commit inline...
On 2017年09月11日 22:55, Christian König wrote:
From: Christian König
There is no guarantee that the last BO_VA actually needed an update.
Additional to that all command submissions must wait for moved BOs to
be cleared, not just the first one.
v2: Don't overwrite any newer fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 24 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +--
3 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 4681dcc..b59749d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -805,7 +805,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser
*p)
}
- r = amdgpu_vm_handle_moved(adev, vm, &p->job->sync);
+ r = amdgpu_vm_handle_moved(adev, vm);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5042f09..6b95ba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1742,7 +1742,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
dma_addr_t *pages_addr = NULL;
struct ttm_mem_reg *mem;
struct drm_mm_node *nodes;
- struct dma_fence *exclusive;
+ struct dma_fence *exclusive, **last_update;
uint64_t flags;
int r;
@@ -1768,6 +1768,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
else
flags = 0x0;
+ if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
+ last_update = &vm->last_update;
+ else
+ last_update = &bo_va->last_pt_update;
I still prefer to move this out of bo_update and place to where calling
amdgpu_vm_bo_update, this way, we will know we're syncing which fence of
which path explicitly.
+
if (!clear && bo_va->base.moved) {
bo_va->base.moved = false;
list_splice_init(&bo_va->valids, &bo_va->invalids);
@@ -1779,7 +1784,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
list_for_each_entry(mapping, &bo_va->invalids, list) {
r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
mapping, flags, nodes,
- &bo_va->last_pt_update);
+ last_update);
if (r)
return r;
}
@@ -1802,12 +1807,6 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
trace_amdgpu_vm_bo_mapping(mapping);
}
- if (bo_va->base.bo &&
- bo_va->base.bo->tbo.resv == vm->root.base.bo->tbo.resv) {
- dma_fence_put(vm->last_update);
- vm->last_update = dma_fence_get(bo_va->last_pt_update);
- }
-
return 0;
}
@@ -2005,15 +2004,15 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
* PTs have to be reserved!
*/
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct amdgpu_sync *sync)
+ struct amdgpu_vm *vm)
{
- struct amdgpu_bo_va *bo_va = NULL;
bool clear;
int r = 0;
spin_lock(&vm->status_lock);
while (!list_empty(&vm->moved)) {
+ struct amdgpu_bo_va *bo_va;
+
bo_va = list_first_entry(&vm->moved,
struct amdgpu_bo_va, base.vm_status);
spin_unlock(&vm->status_lock);
@@ -2029,9 +2028,6 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
}
spin_unlock(&vm->status_lock);
- if (bo_va)
- r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
-
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index cb6a622..48c58ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -250,8 +250,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
struct dma_fence **fence);
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct amdgpu_sync *sync);
+ struct amdgpu_vm *vm);
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
bool clear);
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[PATCH 1/5] drm/amdgpu: fix cgs alignment handling
From: Christian König This always allocated on PAGE_SIZE alignment. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index d450a96..8b5fa22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -121,7 +121,7 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, placement.busy_placement = &place; placement.num_busy_placement = 1; - ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE, + ret = amdgpu_bo_create_restricted(adev, size, align, true, domain, flags, NULL, &placement, NULL, 0, &obj); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 5/5] drm/amdgpu: simplify pinning into visible VRAM
From: Christian König
Just set the CPU access required flag when we pin it.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 8a8add3..bc9f162 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -632,7 +632,6 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo)
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- unsigned lpfn;
int r, i;
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
@@ -656,18 +655,12 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64
*gpu_addr)
}
bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ /* force to pin into visible video ram */
+ if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
+ bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
amdgpu_ttm_placement_from_domain(bo, domain);
- for (i = 0; i < bo->placement.num_placement; i++) {
- /* force to pin into visible video ram */
- if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
- !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
- lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
- if (!bo->placements[i].lpfn ||
- (lpfn && lpfn < bo->placements[i].lpfn))
- bo->placements[i].lpfn = lpfn;
- }
+ for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- }
r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
if (unlikely(r)) {
--
2.7.4
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[PATCH 4/5] drm/amdgpu: cleanup amdgpu_bo_pin_restricted
From: Christian König
Nobody is using the min/max interface any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 39 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 ---
2 files changed, 6 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 726a662..8a8add3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -629,20 +629,15 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo)
*bo = NULL;
}
-int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
-u64 min_offset, u64 max_offset,
-u64 *gpu_addr)
+int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ unsigned lpfn;
int r, i;
- unsigned fpfn, lpfn;
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
return -EPERM;
- if (WARN_ON_ONCE(min_offset > max_offset))
- return -EINVAL;
-
/* A shared bo cannot be migrated to VRAM */
if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
return -EINVAL;
@@ -657,12 +652,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32
domain,
if (gpu_addr)
*gpu_addr = amdgpu_bo_gpu_offset(bo);
- if (max_offset != 0) {
- u64 domain_start =
bo->tbo.bdev->man[mem_type].gpu_offset;
- WARN_ON_ONCE(max_offset <
-(amdgpu_bo_gpu_offset(bo) - domain_start));
- }
-
return 0;
}
@@ -671,23 +660,12 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32
domain,
for (i = 0; i < bo->placement.num_placement; i++) {
/* force to pin into visible video ram */
if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
- !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
- (!max_offset || max_offset >
-adev->mc.visible_vram_size)) {
- if (WARN_ON_ONCE(min_offset >
-adev->mc.visible_vram_size))
- return -EINVAL;
- fpfn = min_offset >> PAGE_SHIFT;
+ !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
- } else {
- fpfn = min_offset >> PAGE_SHIFT;
- lpfn = max_offset >> PAGE_SHIFT;
+ if (!bo->placements[i].lpfn ||
+ (lpfn && lpfn < bo->placements[i].lpfn))
+ bo->placements[i].lpfn = lpfn;
}
- if (fpfn > bo->placements[i].fpfn)
- bo->placements[i].fpfn = fpfn;
- if (!bo->placements[i].lpfn ||
- (lpfn && lpfn < bo->placements[i].lpfn))
- bo->placements[i].lpfn = lpfn;
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
}
@@ -718,11 +696,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32
domain,
return r;
}
-int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
-{
- return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
-}
-
int amdgpu_bo_unpin(struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 39b6bf6..4b2c042 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -211,9 +211,6 @@ void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
void amdgpu_bo_unref(struct amdgpu_bo **bo);
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
-int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
-u64 min_offset, u64 max_offset,
-u64 *gpu_addr);
int amdgpu_bo_unpin(struct amdgpu_bo *bo);
int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
int amdgpu_bo_init(struct amdgpu_device *adev);
--
2.7.4
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[PATCH 2/5] drm/amd: remove min/max addr handling from cgs
From: Christian König
Nobody is actually using this and it causes a bunch of unused and buggy code.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 48 ++-
drivers/gpu/drm/amd/include/cgs_common.h | 7 ++--
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 2 +-
3 files changed, 6 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 8b5fa22..53d1591 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -45,7 +45,6 @@ struct amdgpu_cgs_device {
static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
enum cgs_gpu_mem_type type,
uint64_t size, uint64_t align,
- uint64_t min_offset, uint64_t max_offset,
cgs_handle_t *handle)
{
CGS_FUNC_ADEV;
@@ -53,13 +52,6 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device
*cgs_device,
int ret = 0;
uint32_t domain = 0;
struct amdgpu_bo *obj;
- struct ttm_placement placement;
- struct ttm_place place;
-
- if (min_offset > max_offset) {
- BUG_ON(1);
- return -EINVAL;
- }
/* fail if the alignment is not a power of 2 */
if (((align != 1) && (align & (align - 1)))
@@ -73,41 +65,19 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device
*cgs_device,
flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
- if (max_offset > adev->mc.real_vram_size)
- return -EINVAL;
- place.fpfn = min_offset >> PAGE_SHIFT;
- place.lpfn = max_offset >> PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
- TTM_PL_FLAG_VRAM;
break;
case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
- if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
- place.fpfn =
- max(min_offset, adev->mc.visible_vram_size) >>
PAGE_SHIFT;
- place.lpfn =
- min(max_offset, adev->mc.real_vram_size) >>
PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
- TTM_PL_FLAG_VRAM;
- }
-
break;
case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
domain = AMDGPU_GEM_DOMAIN_GTT;
- place.fpfn = min_offset >> PAGE_SHIFT;
- place.lpfn = max_offset >> PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
break;
case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
domain = AMDGPU_GEM_DOMAIN_GTT;
- place.fpfn = min_offset >> PAGE_SHIFT;
- place.lpfn = max_offset >> PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
- TTM_PL_FLAG_UNCACHED;
break;
default:
return -EINVAL;
@@ -116,15 +86,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device
*cgs_device,
*handle = 0;
- placement.placement = &place;
- placement.num_placement = 1;
- placement.busy_placement = &place;
- placement.num_busy_placement = 1;
-
- ret = amdgpu_bo_create_restricted(adev, size, align,
- true, domain, flags,
- NULL, &placement, NULL,
- 0, &obj);
+ ret = amdgpu_bo_create(adev, size, align, true, domain, flags,
+ NULL, NULL, 0, &obj);
if (ret) {
DRM_ERROR("(%d) bo create failed\n", ret);
return ret;
@@ -155,19 +118,14 @@ static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device
*cgs_device, cgs_handle_t h
uint64_t *mcaddr)
{
int r;
- u64 min_offset, max_offset;
struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
WARN_ON_ONCE(obj->placement.num_placement > 1);
- min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
- max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
-
r = amdgpu_bo_reserve(obj, true);
if (unlikely(r != 0))
return r;
- r = amdgpu_bo_pin_restricted(obj, obj->preferred_domains,
-min_offset, max_offset
[PATCH 3/5] drm/amdgpu: fix and cleanup amdgpu_bo_create
From: Christian König
Fix USWC handling by cleaning up the function and removing
quite a bit of unused code.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 83 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ---
2 files changed, 23 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 52d0109..726a662 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -64,11 +64,12 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo)
return false;
}
-static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
- struct ttm_placement *placement,
- struct ttm_place *places,
- u32 domain, u64 flags)
+void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
+ struct ttm_placement *placement = &abo->placement;
+ struct ttm_place *places = abo->placements;
+ u64 flags = abo->flags;
u32 c = 0;
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
@@ -151,27 +152,6 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device
*adev,
placement->busy_placement = places;
}
-void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
-{
- struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
-
- amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements,
- domain, abo->flags);
-}
-
-static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
- struct ttm_placement *placement)
-{
- BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
-
- memcpy(bo->placements, placement->placement,
- placement->num_placement * sizeof(struct ttm_place));
- bo->placement.num_placement = placement->num_placement;
- bo->placement.num_busy_placement = placement->num_busy_placement;
- bo->placement.placement = bo->placements;
- bo->placement.busy_placement = bo->placements;
-}
-
/**
* amdgpu_bo_create_reserved - create reserved BO for kernel use
*
@@ -303,14 +283,13 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64
*gpu_addr,
*cpu_addr = NULL;
}
-int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
- unsigned long size, int byte_align,
- bool kernel, u32 domain, u64 flags,
- struct sg_table *sg,
- struct ttm_placement *placement,
- struct reservation_object *resv,
- uint64_t init_value,
- struct amdgpu_bo **bo_ptr)
+static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ unsigned long size, int byte_align,
+ bool kernel, u32 domain, u64 flags,
+ struct sg_table *sg,
+ struct reservation_object *resv,
+ uint64_t init_value,
+ struct amdgpu_bo **bo_ptr)
{
struct amdgpu_bo *bo;
enum ttm_bo_type type;
@@ -384,10 +363,11 @@ int amdgpu_bo_create_restricted(struct amdgpu_device
*adev,
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
#endif
- amdgpu_fill_placement_to_bo(bo, placement);
- /* Kernel allocation are uninterruptible */
+ bo->tbo.bdev = &adev->mman.bdev;
+ amdgpu_ttm_placement_from_domain(bo, domain);
initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
+ /* Kernel allocation are uninterruptible */
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
&bo->placement, page_align, !kernel, NULL,
acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
@@ -442,27 +422,17 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device
*adev,
unsigned long size, int byte_align,
struct amdgpu_bo *bo)
{
- struct ttm_placement placement = {0};
- struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
int r;
if (bo->shadow)
return 0;
- memset(&placements, 0, sizeof(placements));
- amdgpu_ttm_placement_init(adev, &placement, placements,
- AMDGPU_GEM_DOMAIN_GTT,
- AMDGPU_GEM_CREATE_CPU_GTT_USWC |
- AMDGPU_GEM_CREATE_SHADOW);
-
- r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
- AMDGPU_GEM_D
RE: [PATCH] iommu/amd: flush IOTLB for specific domains only (v3)
Hi Daniel, >-Original Message- >From: Daniel Drake [mailto:dr...@endlessm.com] >Sent: Tuesday, September 12, 2017 12:20 PM >To: Nath, Arindam >Cc: Joerg Roedel ; Lendacky, Thomas >; io...@lists.linux-foundation.org; amd- >g...@lists.freedesktop.org; Deucher, Alexander >; Bridgman, John >; Suthikulpanit, Suravee >; li...@endlessm.com; Craig Stein >; mic...@daenzer.net; Kuehling, Felix >; sta...@vger.kernel.org >Subject: Re: [PATCH] iommu/amd: flush IOTLB for specific domains only (v3) > >Hi, > >On Tue, May 30, 2017 at 3:38 PM, Nath, Arindam >wrote: >>>-Original Message- >>>From: Joerg Roedel [mailto:j...@8bytes.org] >>>Sent: Monday, May 29, 2017 8:09 PM >>>To: Nath, Arindam ; Lendacky, Thomas >>> >>>Cc: io...@lists.linux-foundation.org; amd-gfx@lists.freedesktop.org; >>>Deucher, Alexander ; Bridgman, John >>>; dr...@endlessm.com; Suthikulpanit, >Suravee >>>; li...@endlessm.com; Craig Stein >>>; mic...@daenzer.net; Kuehling, Felix >>>; sta...@vger.kernel.org >>>Subject: Re: [PATCH] iommu/amd: flush IOTLB for specific domains only >(v3) >>> >>>Hi Arindam, >>> >>>I met Tom Lendacky last week in Nuremberg last week and he told me he is >>>working on the same area of the code that this patch is for. His reason >>>for touching this code was to solve some locking problems. Maybe you two >>>can work together on a joint approach to improve this? >> >> Sure Joerg, I will work with Tom. > >What was the end result here? I see that the code has been reworked in >4.13 so your original patch no longer applies. Is the reworked version >also expected to solve the original issue? Yes, if the reworked patch resolves the issue, my patch won't be required anymore. Thanks, Arindam > >Thanks >Daniel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/5] ***[WIP] introduce syncfile as fence reuturn ***
*** BLURB HERE *** Chunming Zhou (5): drm/amdgpu: introduce sync file for CS returning fence drm/amdgpu: add syncfile chunk support drm/amdgpu: add syncfile support to wait ioctl drm/amdgpu: add syncfile fence support to wait_any/all ioctl drm/amdgpu: expand mapping ioctl to return fence to UMD by using syncfile drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 90 - drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 24 +++-- include/uapi/drm/amdgpu_drm.h | 13 - 3 files changed, 96 insertions(+), 31 deletions(-) -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/5] drm/amdgpu: introduce sync file for CS returning fence
Change-Id: If32e17d8fbdf1e158a34eca3de8687a8fc30f797
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 +++
include/uapi/drm/amdgpu_drm.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index be01199..3b049a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -25,6 +25,7 @@
*Jerome Glisse
*/
#include
+#include
#include
#include
#include "amdgpu.h"
@@ -1043,6 +1044,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
struct amdgpu_ring *ring = p->job->ring;
struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
struct amdgpu_job *job;
+ int fd;
+ struct sync_file *sync_file;
int r;
job = p->job;
@@ -1057,6 +1060,14 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
job->owner = p->filp;
job->fence_ctx = entity->fence_context;
p->fence = dma_fence_get(&job->base.s_fence->finished);
+ sync_file = sync_file_create(p->fence);
+ if (!sync_file) {
+ amdgpu_job_free(job);
+ return -ENOMEM;
+ }
+ fd = get_unused_fd_flags(O_CLOEXEC);
+ fd_install(fd, sync_file->file);
+ cs->out.fence_fd = fd;
cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
job->uf_sequence = cs->out.handle;
amdgpu_job_free_resources(job);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 016f7be..d0cd4f0 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -530,6 +530,8 @@ struct drm_amdgpu_cs_in {
};
struct drm_amdgpu_cs_out {
+ int32_t fence_fd;
+ int32_t _pad;
__u64 handle;
};
--
1.9.1
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[PATCH 3/5] drm/amdgpu: add syncfile support to wait ioctl
Change-Id: I79155cef5ee798899cd51a88825512cbf0d8ad82
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 +-
include/uapi/drm/amdgpu_drm.h | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d048802..6c0ea9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1178,6 +1178,14 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void
*data,
if (amdgpu_kms_vram_lost(adev, fpriv))
return -ENODEV;
+ if (wait->in.sf_fd > 0) {
+ struct dma_fence *fence = sync_file_get_fence(wait->in.sf_fd);
+
+ WARN_ONCE(fence, "get fence failed from syncfile fd!");
+ r = kcl_fence_wait_timeout(fence, true, timeout);
+ dma_fence_put(fence);
+ goto out;
+ }
ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
if (ctx == NULL)
return -EINVAL;
@@ -1202,7 +1210,7 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void
*data,
amdgpu_ctx_put(ctx);
if (r < 0)
return r;
-
+out:
memset(wait, 0, sizeof(*wait));
wait->out.status = (r == 0);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 19b4fea..ce110d9 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -399,6 +399,8 @@ struct drm_amdgpu_wait_cs_in {
__u32 ip_instance;
__u32 ring;
__u32 ctx_id;
+ int32_t sf_fd;
+ int32_t _pad;
};
struct drm_amdgpu_wait_cs_out {
--
1.9.1
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[PATCH 5/5] drm/amdgpu: expand mapping ioctl to return fence to UMD by using syncfile
Change-Id: I88e56d34ec5e90fe8001e73d52e893a38938361e
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 24 +++-
include/uapi/drm/amdgpu_drm.h | 4 +++-
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 973c0f0..bf37279 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -27,6 +27,7 @@
*/
#include
#include
+#include
#include
#include
#include "amdgpu.h"
@@ -693,7 +694,8 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device
*adev,
struct amdgpu_vm *vm,
struct amdgpu_bo_va *bo_va,
struct list_head *list,
- uint32_t operation)
+ uint32_t operation,
+ int *sf_fd)
{
int r;
@@ -709,9 +711,18 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device
*adev,
goto error;
if (operation == AMDGPU_VA_OP_MAP ||
- operation == AMDGPU_VA_OP_REPLACE)
- r = amdgpu_vm_bo_update(adev, bo_va, false);
+ operation == AMDGPU_VA_OP_REPLACE) {
+ int fd;
+ struct sync_file *sync_file;
+ r = amdgpu_vm_bo_update(adev, bo_va, false);
+ sync_file = sync_file_create(bo_va->last_pt_update);
+ if (!sync_file)
+ goto error;
+ fd = get_unused_fd_flags(O_CLOEXEC);
+ fd_install(fd, sync_file->file);
+ *sf_fd = fd;
+ }
error:
if (r && r != -ERESTARTSYS)
DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
@@ -737,6 +748,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
+ int sf_fd;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@@ -839,9 +851,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
default:
break;
}
- if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
+ if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) {
amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
- args->operation);
+ args->operation, &sf_fd);
+ args->sf_fd = sf_fd;
+ }
error_backoff:
ttm_eu_backoff_reservation(&ticket, &list);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index cf3fb62..6b97d33 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -487,7 +487,9 @@ struct drm_amdgpu_gem_op {
struct drm_amdgpu_gem_va {
/** GEM object handle */
__u32 handle;
- __u32 _pad;
+ /** sf_fd is an OUTPUT from syncfile, it's present to mapping completion
+*/
+ int32_t sf_fd;
/** AMDGPU_VA_OP_* */
__u32 operation;
/** AMDGPU_VM_PAGE_* */
--
1.9.1
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[PATCH 2/5] drm/amdgpu: add syncfile chunk support
Change-Id: I9a9e8d474c2f31e71bdf9841a518fa48b3e5c33b
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 63 +-
include/uapi/drm/amdgpu_drm.h | 3 ++
2 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 3b049a4..d048802 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -155,6 +155,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, void *data)
break;
case AMDGPU_CHUNK_ID_DEPENDENCIES:
+ case AMDGPU_CHUNK_ID_SYNCFILE:
break;
default:
@@ -983,34 +984,47 @@ static int amdgpu_cs_process_fence_dep(struct
amdgpu_cs_parser *p,
sizeof(struct drm_amdgpu_cs_chunk_dep);
for (i = 0; i < num_deps; ++i) {
- struct amdgpu_ring *ring;
- struct amdgpu_ctx *ctx;
- struct dma_fence *fence;
+ if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
+ struct amdgpu_ring *ring;
+ struct amdgpu_ctx *ctx;
+ struct dma_fence *fence;
- ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
- if (ctx == NULL)
- return -EINVAL;
+ ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
+ if (ctx == NULL)
+ return -EINVAL;
- r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
-deps[i].ip_type,
-deps[i].ip_instance,
-deps[i].ring, &ring);
- if (r) {
- amdgpu_ctx_put(ctx);
- return r;
- }
+ r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
+ deps[i].ip_type,
+ deps[i].ip_instance,
+ deps[i].ring, &ring);
+ if (r) {
+ amdgpu_ctx_put(ctx);
+ return r;
+ }
- fence = amdgpu_ctx_get_fence(ctx, ring,
-deps[i].handle);
- if (IS_ERR(fence)) {
- r = PTR_ERR(fence);
- amdgpu_ctx_put(ctx);
- return r;
- } else if (fence) {
+ fence = amdgpu_ctx_get_fence(ctx, ring,
+ deps[i].handle);
+ if (IS_ERR(fence)) {
+ r = PTR_ERR(fence);
+ amdgpu_ctx_put(ctx);
+ return r;
+ } else if (fence) {
+ r = amdgpu_sync_fence(p->adev, &p->job->sync,
+ fence);
+ dma_fence_put(fence);
+ amdgpu_ctx_put(ctx);
+ if (r)
+ return r;
+ }
+ } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCFILE) {
+ struct dma_fence *fence;
+
+ WARN_ONCE(deps[i].sf_fd < 0,
+ "invalid syncfile fd handle!");
+ fence = sync_file_get_fence(deps[i].sf_fd);
r = amdgpu_sync_fence(p->adev, &p->job->sync,
- fence);
+ fence);
dma_fence_put(fence);
- amdgpu_ctx_put(ctx);
if (r)
return r;
}
@@ -1028,7 +1042,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device
*adev,
chunk = &p->chunks[i];
- if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
+ if ((chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) ||
+ (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCFILE)) {
r = amdgpu_cs_process_fence_dep(p, chunk);
if (r)
return r;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index d0cd4f0..19b4fea 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -511,6 +511,7 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_IB 0x01
#define AMDGPU_CHUNK_ID_FENCE 0x02
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
+#define AMDGPU_CHUNK_ID_SYNCFILE
[PATCH 4/5] drm/amdgpu: add syncfile fence support to wait_any/all ioctl
Change-Id: Ibe77f213560846ec12901e366129d9368750b7ba
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++
include/uapi/drm/amdgpu_drm.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 6c0ea9a..a2fbdaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1233,6 +1233,12 @@ static struct dma_fence *amdgpu_cs_get_fence(struct
amdgpu_device *adev,
struct dma_fence *fence;
int r;
+ if (user->sf_fd > 0) {
+ struct dma_fence *fence = sync_file_get_fence(user->sf_fd);
+
+ WARN_ONCE(fence, "get fence failed from syncfile fd!");
+ return fence;
+ }
ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
if (ctx == NULL)
return ERR_PTR(-EINVAL);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index ce110d9..cf3fb62 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -419,6 +419,8 @@ struct drm_amdgpu_fence {
__u32 ip_instance;
__u32 ring;
__u64 seq_no;
+ int32_t sf_fd;
+ int32_t _pad;
};
struct drm_amdgpu_wait_fences_in {
--
1.9.1
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Re: [PATCH 0/5] ***[WIP] introduce syncfile as fence reuturn ***
NAK for the CS part (but I think that was just as prove of concept anyway). Dave's sync object implementation is already done for this, the problem is that isn't merged yet into amd-staging-4.12 (but should be in 4-13). The VM part looks similar to what I had in mind, but we should base this on Dave's sync_obj stuff as well. Regards, Christian. Am 12.09.2017 um 12:23 schrieb Chunming Zhou: *** BLURB HERE *** Chunming Zhou (5): drm/amdgpu: introduce sync file for CS returning fence drm/amdgpu: add syncfile chunk support drm/amdgpu: add syncfile support to wait ioctl drm/amdgpu: add syncfile fence support to wait_any/all ioctl drm/amdgpu: expand mapping ioctl to return fence to UMD by using syncfile drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 90 - drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 24 +++-- include/uapi/drm/amdgpu_drm.h | 13 - 3 files changed, 96 insertions(+), 31 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: improve PRT syncing
From: Christian König
Just clean that up a bit more.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b59749d..db5dbd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -760,11 +760,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser
*p)
if (r)
return r;
- r = amdgpu_sync_fence(adev, &p->job->sync,
- fpriv->prt_va->last_pt_update);
- if (r)
- return r;
-
if (amdgpu_sriov_vf(adev)) {
struct dma_fence *f;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6b95ba6..2f577da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1768,7 +1768,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
else
flags = 0x0;
- if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
+ if (clear || !bo || bo->tbo.resv == vm->root.base.bo->tbo.resv)
last_update = &vm->last_update;
else
last_update = &bo_va->last_pt_update;
--
2.7.4
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write to GRBM_GFX_INDEX without lock
In the file smu7_powertune.c we have
int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
{
int result;
uint32_t num_se = 0;
uint32_t count, value, value2;
struct cgs_system_info sys_info = {0};
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (result == 0)
num_se = sys_info.value;
if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
PP_CAP(PHM_PlatformCaps_DBRamping) ||
PP_CAP(PHM_PlatformCaps_TDRamping) ||
PP_CAP(PHM_PlatformCaps_TCPRamping)) {
cgs_enter_safe_mode(hwmgr->device, true);
value = 0;
value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
for (count = 0; count < num_se; count++) {
value =
SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK
|
SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK
| (count <<
SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT);
cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX,
value);
The call to "enter safe mode" doesn't hold the lock which means that
this could in theory occur while other things are going on. Granted
this function is likely called during init it should have a lock no?
Cheers,
Tom
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Re: [PATCH] drm/amd/display: Don't leak dc_stream_state.
On 2017-09-08 11:41 AM, Darren Salt wrote:
> Noticed while playing “Valley”, which was causing some 8MB of leakage per
> second. kmemleak listed many entries looking like this:
>
> unreferenced object 0x8802c2951800 (size 1024):
> comm "Xorg", pid 2982, jiffies 4297410155 (age 392.787s)
> hex dump (first 32 bytes):
> 00 50 f9 0c 04 88 ff ff 98 08 00 00 00 00 00 00 .P..
> 80 07 00 00 00 00 00 00 58 00 00 00 2c 00 00 00 X...,...
> backtrace:
> [] create_object+0x13c/0x261
> [] kmemleak_alloc+0x20/0x3c
> [] slab_post_alloc_hook+0x42/0x52
> [] kmem_cache_alloc+0x67/0x76
> [] dc_create_stream_for_sink+0x24/0x1cf
> [] create_stream_for_sink+0x6f/0x295
> [] dm_update_crtcs_state+0xa6/0x268
> [] amdgpu_dm_atomic_check+0x9a/0x314
> [] drm_atomic_check_only+0x17a/0x42d
> [] drm_atomic_commit+0x13/0x4b
> [] drm_atomic_connector_commit_dpms+0xcb/0xe8
> [] drm_mode_obj_set_property_ioctl+0xe6/0x1e3
> [] drm_mode_connector_property_set_ioctl+0x2b/0x2d
> [] drm_ioctl_kernel+0x64/0x9d
> [] drm_ioctl+0x230/0x316
> [] amdgpu_drm_ioctl+0x4b/0x7d
Please leave a Signed-off-by tag (see part 10 of
https://www.kernel.org/doc/html/v4.11/process/submitting-patches.html).
Otherwise the patch looks good. Please resend with the Signed-off-by.
Looks like we'd have the same problem with the break statements. This
wouldn't be as noticeable since they are error conditions.
Thanks,
Harry
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 32c75867eaa7..394fc3c03362 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4525,7 +4525,7 @@ static int dm_update_crtcs_state(
>
>
> if (!drm_atomic_crtc_needs_modeset(crtc_state))
> - continue;
> + goto free_new_stream_continue;
>
> DRM_DEBUG_KMS(
> "amdgpu_crtc id:%d crtc_state_flags: enable:%d,
> active:%d, "
> @@ -4543,7 +4543,7 @@ static int dm_update_crtcs_state(
> if (!enable) {
>
> if (!old_acrtc_state->stream)
> - continue;
> + goto free_new_stream_continue;
>
> DRM_DEBUG_KMS("Disabling DRM crtc: %d\n",
> crtc->base.id);
> @@ -4565,7 +4565,7 @@ static int dm_update_crtcs_state(
> } else {/* Add stream for any updated/enabled CRTC */
>
> if (modereset_required(crtc_state))
> - continue;
> + goto free_new_stream_continue;
>
> if (modeset_required(crtc_state, new_stream,
>old_acrtc_state->stream)) {
> @@ -4590,6 +4590,7 @@ static int dm_update_crtcs_state(
> }
> }
>
> +free_new_stream_continue:
> /* Release extra reference */
> if (new_stream)
>dc_stream_release(new_stream);
>
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[PATCH 4/6] drm/amd/powerplay: Remove unneeded return from pp_smu7_thermal_fini()
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index 064166b48d1f..6867363f561d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -572,5 +572,4 @@ void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr)
{
phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
phm_destroy_table(hwmgr, &(hwmgr->start_thermal_controller));
- return;
}
--
2.12.0
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[PATCH 3/6] drm/amd/powerplay: Make use of PP_CAP in smu7_thermal.c
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index 0c822ef7d907..064166b48d1f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -150,13 +150,11 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr
*hwmgr)
{
int result;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
+ if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0,
FAN_CONTROL_FUZZY);
result = smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_StartFanControl);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_FanSpeedInTableIsRPM))
+ if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM);
@@ -207,8 +205,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr
*hwmgr,
if (speed > 100)
speed = 100;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
@@ -239,8 +236,7 @@ int smu7_fan_ctrl_reset_fan_speed_to_default(struct
pp_hwmgr *hwmgr)
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl)) {
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
result = smu7_fan_ctrl_set_static_mode(hwmgr,
FDO_PWM_MODE_STATIC);
if (!result)
result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
@@ -268,8 +264,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
uint32_t speed)
(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
return 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
crystal_clock_freq = smu7_get_xclk(hwmgr);
@@ -429,8 +424,7 @@ static int tf_smu7_thermal_start_smc_fan_control(struct
pp_hwmgr *hwmgr,
* this function was included in the table.
* Make sure that we still think controlling the fan is OK.
*/
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl)) {
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
smu7_fan_ctrl_start_smc_fan_control(hwmgr);
smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
--
2.12.0
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[PATCH 2/6] drm/amd/powerplay: Tidy up smu7_fan_ctrl_get_fan_speed_rpm()
Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c index a491f1201fda..0c822ef7d907 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c @@ -86,8 +86,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) uint32_t crystal_clock_freq; if (hwmgr->thermal_controller.fanInfo.bNoFan || - (hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution == 0)) + !hwmgr->thermal_controller.fanInfo. ucTachometerPulsesPerRevolution) return -ENODEV; tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, -- 2.12.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/6] drm/amd/powerplay: Tidy up smu7_fan_ctrl_get_fan_speed_info()
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index baddb569a8b8..a491f1201fda 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -37,9 +37,8 @@ int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
fan_speed_info->min_percent = 0;
fan_speed_info->max_percent = 100;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
-
hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
+ if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
+ hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
fan_speed_info->supports_rpm_read = true;
fan_speed_info->supports_rpm_write = true;
fan_speed_info->min_rpm =
hwmgr->thermal_controller.fanInfo.ulMinRPM;
@@ -581,4 +580,4 @@ void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr)
phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
phm_destroy_table(hwmgr, &(hwmgr->start_thermal_controller));
return;
-}
\ No newline at end of file
+}
--
2.12.0
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[PATCH 5/6] drm/amd/powerplay: Make use of PP_CAP in smu7_powertune.c
Signed-off-by: Tom St Denis
---
.../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 42 ++
1 file changed, 18 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 1dc31aa72781..9b4189cd0851 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -636,7 +636,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const
bool enable)
else
didt_block = DIDTBlock_Info;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping) ? en : 0;
+ block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0;
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT,
ixDIDT_SQ_CTRL0);
data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
@@ -645,7 +645,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const
bool enable)
didt_block &= ~SQ_Enable_MASK;
didt_block |= block_en << SQ_Enable_SHIFT;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping) ? en : 0;
+ block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0;
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT,
ixDIDT_DB_CTRL0);
data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
@@ -654,7 +654,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const
bool enable)
didt_block &= ~DB_Enable_MASK;
didt_block |= block_en << DB_Enable_SHIFT;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping) ? en : 0;
+ block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0;
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT,
ixDIDT_TD_CTRL0);
data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
data |= ((block_en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) &
DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
@@ -662,7 +662,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const
bool enable)
didt_block &= ~TD_Enable_MASK;
didt_block |= block_en << TD_Enable_SHIFT;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping) ? en : 0;
+ block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0;
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT,
ixDIDT_TCP_CTRL0);
data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
@@ -753,10 +753,10 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
if (result == 0)
num_se = sys_info.value;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
+ PP_CAP(PHM_PlatformCaps_DBRamping) ||
+ PP_CAP(PHM_PlatformCaps_TDRamping) ||
+ PP_CAP(PHM_PlatformCaps_TCPRamping)) {
cgs_enter_safe_mode(hwmgr->device, true);
value = 0;
@@ -808,10 +808,10 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
{
int result;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
+ PP_CAP(PHM_PlatformCaps_DBRamping) ||
+ PP_CAP(PHM_PlatformCaps_TDRamping) ||
+ PP_CAP(PHM_PlatformCaps_TCPRamping)) {
cgs_enter_safe_mode(hwmgr->device, true);
@@ -836,8 +836,7 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
int result = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_CAC)) {
+ if (PP_CAP(PHM_PlatformCaps_CAC)) {
int smc_result;
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
(uint16_t)(PPSMC_MSG_EnableCac));
@@ -854,8 +853,7 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
int result = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_CAC) && data->cac_enabled) {
+ if (PP_CAP(PHM_Platfor
[PATCH 6/6] drm/amd/powerplay: Tidy up smu7_enable_didt()
Signed-off-by: Tom St Denis --- .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 29 ++ 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c index 9b4189cd0851..8c264c195e1a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c @@ -629,7 +629,6 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) uint32_t block_en = 0; int32_t result = 0; uint32_t didt_block; - uint32_t data; if (hwmgr->chip_id == CHIP_POLARIS11) didt_block = Polaris11_DIDTBlock_Info; @@ -637,41 +636,29 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) didt_block = DIDTBlock_Info; block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0; - - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0); - data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data); + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, +DIDT_SQ_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~SQ_Enable_MASK; didt_block |= block_en << SQ_Enable_SHIFT; block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0; - - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0); - data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data); + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, +DIDT_DB_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~DB_Enable_MASK; didt_block |= block_en << DB_Enable_SHIFT; block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0; - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0); - data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data); + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, +DIDT_TD_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~TD_Enable_MASK; didt_block |= block_en << TD_Enable_SHIFT; block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0; - - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0); - data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data); + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, +DIDT_TCP_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~TCP_Enable_MASK; didt_block |= block_en << TCP_Enable_SHIFT; - if (enable) result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block); -- 2.12.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/display: Disable pre-Vega ASICs be default
Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ drivers/gpu/drm/amd/display/Kconfig| 8 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 34671790ce80..8c496a57788f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1995,7 +1995,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_TONGA: case CHIP_FIJI: case CHIP_VEGA10: +#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) return amdgpu_dc != 0; +#endif case CHIP_KABINI: case CHIP_MULLINS: return amdgpu_dc > 0; diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index e91b6e57cf03..4d2816e01bf0 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -3,11 +3,19 @@ menu "Display Engine Configuration" config DRM_AMD_DC bool "AMD DC - Enable new display engine + default y help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and Raven ASICs. +config DRM_AMD_DC_PRE_VEGA + bool "DC support for Polaris and older ASICs" + default n + help + Choose this option to use the new DC driver for Polaris, Carrizo, + Tonga, Bonaire, and Hawaii. + config DRM_AMD_DC_DCN1_0 bool "DCN 1.0 Raven family" depends on DRM_AMD_DC && X86 -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/display: Clean Kconfig formatting
Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/display/Kconfig | 33 - 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 62ea9f600374..e91b6e57cf03 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -2,26 +2,25 @@ menu "Display Engine Configuration" depends on DRM && DRM_AMDGPU config DRM_AMD_DC -bool "AMD DC - Enable new display engine (will be deprecated when the development is done)" -help - Choose this option if you want to use the new display engine - support for AMDGPU. - - Will be deprecated when the DC component is upstream. + bool "AMD DC - Enable new display engine + help + Choose this option if you want to use the new display engine + support for AMDGPU. This adds required support for Vega and + Raven ASICs. config DRM_AMD_DC_DCN1_0 -bool "DCN 1.0 Raven family" -depends on DRM_AMD_DC && X86 -help -Choose this option if you want to have -RV family for display engine + bool "DCN 1.0 Raven family" + depends on DRM_AMD_DC && X86 + help + Choose this option if you want to have + RV family for display engine config DEBUG_KERNEL_DC -bool "Enable kgdb break in DC" -depends on DRM_AMD_DC -help - Choose this option - if you want to hit - kdgb_break in assert. + bool "Enable kgdb break in DC" + depends on DRM_AMD_DC + help + Choose this option + if you want to hit + kdgb_break in assert. endmenu -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 3/5] drm/amdgpu: fix and cleanup amdgpu_bo_create
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, September 12, 2017 5:09 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 3/5] drm/amdgpu: fix and cleanup amdgpu_bo_create
>
> From: Christian König
>
> Fix USWC handling by cleaning up the function and removing
> quite a bit of unused code.
Can you clarify what was broken?
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 83 +
> -
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ---
> 2 files changed, 23 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 52d0109..726a662 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -64,11 +64,12 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct
> ttm_buffer_object *bo)
> return false;
> }
>
> -static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
> - struct ttm_placement *placement,
> - struct ttm_place *places,
> - u32 domain, u64 flags)
> +void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32
> domain)
> {
> + struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
> + struct ttm_placement *placement = &abo->placement;
> + struct ttm_place *places = abo->placements;
> + u64 flags = abo->flags;
> u32 c = 0;
>
> if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
> @@ -151,27 +152,6 @@ static void amdgpu_ttm_placement_init(struct
> amdgpu_device *adev,
> placement->busy_placement = places;
> }
>
> -void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32
> domain)
> -{
> - struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
> -
> - amdgpu_ttm_placement_init(adev, &abo->placement, abo-
> >placements,
> - domain, abo->flags);
> -}
> -
> -static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
> - struct ttm_placement *placement)
> -{
> - BUG_ON(placement->num_placement >
> (AMDGPU_GEM_DOMAIN_MAX + 1));
> -
> - memcpy(bo->placements, placement->placement,
> -placement->num_placement * sizeof(struct ttm_place));
> - bo->placement.num_placement = placement->num_placement;
> - bo->placement.num_busy_placement = placement-
> >num_busy_placement;
> - bo->placement.placement = bo->placements;
> - bo->placement.busy_placement = bo->placements;
> -}
> -
> /**
> * amdgpu_bo_create_reserved - create reserved BO for kernel use
> *
> @@ -303,14 +283,13 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo
> **bo, u64 *gpu_addr,
> *cpu_addr = NULL;
> }
>
> -int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
> - unsigned long size, int byte_align,
> - bool kernel, u32 domain, u64 flags,
> - struct sg_table *sg,
> - struct ttm_placement *placement,
> - struct reservation_object *resv,
> - uint64_t init_value,
> - struct amdgpu_bo **bo_ptr)
> +static int amdgpu_bo_do_create(struct amdgpu_device *adev,
> +unsigned long size, int byte_align,
> +bool kernel, u32 domain, u64 flags,
> +struct sg_table *sg,
> +struct reservation_object *resv,
> +uint64_t init_value,
> +struct amdgpu_bo **bo_ptr)
Still seems like amdgpu_bo_create_restricted is a better name than do_create.
> {
> struct amdgpu_bo *bo;
> enum ttm_bo_type type;
> @@ -384,10 +363,11 @@ int amdgpu_bo_create_restricted(struct
> amdgpu_device *adev,
> bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> #endif
>
> - amdgpu_fill_placement_to_bo(bo, placement);
> - /* Kernel allocation are uninterruptible */
> + bo->tbo.bdev = &adev->mman.bdev;
> + amdgpu_ttm_placement_from_domain(bo, domain);
>
> initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
> + /* Kernel allocation are uninterruptible */
> r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size,
> type,
>&bo->placement, page_align, !kernel, NULL,
>acc_size, sg, resv,
> &amdgpu_ttm_bo_destroy);
> @@ -442,27 +422,17 @@ static int amdgpu_bo_create_shadow(struct
> amdgpu_device *adev,
> unsigned long size, int byte_align,
> struct amdgpu_bo *bo)
> {
> - struct ttm_placement placement = {0};
> - struct ttm_place placements[AMDGPU_GEM_DOM
RE: [PATCH 4/5] drm/amdgpu: cleanup amdgpu_bo_pin_restricted
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, September 12, 2017 5:09 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 4/5] drm/amdgpu: cleanup amdgpu_bo_pin_restricted
>
> From: Christian König
>
> Nobody is using the min/max interface any more.
>
> Signed-off-by: Christian König
I'm not sure it's a good idea to get rid of this. I can see a need to reserve
memory at specific offsets in memory. Specifically I think SR-IOV will be
placing structures in memory to communicate configuration details from the host
to the guest. Also, we should be reserving the vbios scratch area, but we
don't currently.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 39 +--
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 ---
> 2 files changed, 6 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 726a662..8a8add3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -629,20 +629,15 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo)
> *bo = NULL;
> }
>
> -int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
> - u64 min_offset, u64 max_offset,
> - u64 *gpu_addr)
> +int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
> {
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> + unsigned lpfn;
> int r, i;
> - unsigned fpfn, lpfn;
>
> if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
> return -EPERM;
>
> - if (WARN_ON_ONCE(min_offset > max_offset))
> - return -EINVAL;
> -
> /* A shared bo cannot be migrated to VRAM */
> if (bo->prime_shared_count && (domain ==
> AMDGPU_GEM_DOMAIN_VRAM))
> return -EINVAL;
> @@ -657,12 +652,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo
> *bo, u32 domain,
> if (gpu_addr)
> *gpu_addr = amdgpu_bo_gpu_offset(bo);
>
> - if (max_offset != 0) {
> - u64 domain_start = bo->tbo.bdev-
> >man[mem_type].gpu_offset;
> - WARN_ON_ONCE(max_offset <
> - (amdgpu_bo_gpu_offset(bo) -
> domain_start));
> - }
> -
> return 0;
> }
>
> @@ -671,23 +660,12 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo
> *bo, u32 domain,
> for (i = 0; i < bo->placement.num_placement; i++) {
> /* force to pin into visible video ram */
> if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
> - !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
> &&
> - (!max_offset || max_offset >
> - adev->mc.visible_vram_size)) {
> - if (WARN_ON_ONCE(min_offset >
> - adev->mc.visible_vram_size))
> - return -EINVAL;
> - fpfn = min_offset >> PAGE_SHIFT;
> + !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
> {
> lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
> - } else {
> - fpfn = min_offset >> PAGE_SHIFT;
> - lpfn = max_offset >> PAGE_SHIFT;
> + if (!bo->placements[i].lpfn ||
> + (lpfn && lpfn < bo->placements[i].lpfn))
> + bo->placements[i].lpfn = lpfn;
> }
> - if (fpfn > bo->placements[i].fpfn)
> - bo->placements[i].fpfn = fpfn;
> - if (!bo->placements[i].lpfn ||
> - (lpfn && lpfn < bo->placements[i].lpfn))
> - bo->placements[i].lpfn = lpfn;
> bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
> }
>
> @@ -718,11 +696,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo
> *bo, u32 domain,
> return r;
> }
>
> -int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
> -{
> - return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
> -}
> -
> int amdgpu_bo_unpin(struct amdgpu_bo *bo)
> {
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 39b6bf6..4b2c042 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -211,9 +211,6 @@ void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
> struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
> void amdgpu_bo_unref(struct amdgpu_bo **bo);
> int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
> -int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
> - u64 min_offset, u64 max_offse
RE: write to GRBM_GFX_INDEX without lock
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, September 12, 2017 10:18 AM
> To: amd-gfx mailing list
> Subject: write to GRBM_GFX_INDEX without lock
>
> In the file smu7_powertune.c we have
>
> int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
> {
> int result;
> uint32_t num_se = 0;
> uint32_t count, value, value2;
> struct cgs_system_info sys_info = {0};
>
> sys_info.size = sizeof(struct cgs_system_info);
> sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
> result = cgs_query_system_info(hwmgr->device, &sys_info);
>
> if (result == 0)
> num_se = sys_info.value;
>
> if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
> PP_CAP(PHM_PlatformCaps_DBRamping) ||
> PP_CAP(PHM_PlatformCaps_TDRamping) ||
> PP_CAP(PHM_PlatformCaps_TCPRamping)) {
>
> cgs_enter_safe_mode(hwmgr->device, true);
> value = 0;
> value2 = cgs_read_register(hwmgr->device,
> mmGRBM_GFX_INDEX);
> for (count = 0; count < num_se; count++) {
> value =
> SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK
> |
> SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK
> | (count <<
> SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT);
> cgs_write_register(hwmgr->device,
> mmGRBM_GFX_INDEX, value);
>
>
> The call to "enter safe mode" doesn't hold the lock which means that
> this could in theory occur while other things are going on. Granted
> this function is likely called during init it should have a lock no?
Yes, it should. I think there is a cgs function to handle the locking.
Alex
>
> Cheers,
> Tom
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amd/display: Don't leak dc_stream_state.
Noticed while playing “Valley”, which was causing some 8MB of leakage per
second. kmemleak listed many entries looking like this:
unreferenced object 0x8802c2951800 (size 1024):
comm "Xorg", pid 2982, jiffies 4297410155 (age 392.787s)
hex dump (first 32 bytes):
00 50 f9 0c 04 88 ff ff 98 08 00 00 00 00 00 00 .P..
80 07 00 00 00 00 00 00 58 00 00 00 2c 00 00 00 X...,...
backtrace:
[] create_object+0x13c/0x261
[] kmemleak_alloc+0x20/0x3c
[] slab_post_alloc_hook+0x42/0x52
[] kmem_cache_alloc+0x67/0x76
[] dc_create_stream_for_sink+0x24/0x1cf
[] create_stream_for_sink+0x6f/0x295
[] dm_update_crtcs_state+0xa6/0x268
[] amdgpu_dm_atomic_check+0x9a/0x314
[] drm_atomic_check_only+0x17a/0x42d
[] drm_atomic_commit+0x13/0x4b
[] drm_atomic_connector_commit_dpms+0xcb/0xe8
[] drm_mode_obj_set_property_ioctl+0xe6/0x1e3
[] drm_mode_connector_property_set_ioctl+0x2b/0x2d
[] drm_ioctl_kernel+0x64/0x9d
[] drm_ioctl+0x230/0x316
[] amdgpu_drm_ioctl+0x4b/0x7d
v2: also handle break statements.
Signed-off-by: Darren Salt
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 32c75867eaa7..14f1a4bcf2e9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4466,6 +4466,7 @@ static int dm_update_crtcs_state(
int i;
struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+ struct dc_stream_state *new_stream;
int ret = 0;
/*TODO Move this code into dm_crtc_atomic_check once we get rid of
dc_validation_set */
@@ -4473,10 +4474,10 @@ static int dm_update_crtcs_state(
for_each_crtc_in_state(state, crtc, crtc_state, i) {
struct amdgpu_crtc *acrtc = NULL;
struct amdgpu_connector *aconnector = NULL;
- struct dc_stream_state *new_stream = NULL;
struct drm_connector_state *conn_state = NULL;
struct dm_connector_state *dm_conn_state = NULL;
+ new_stream = NULL;
old_acrtc_state = to_dm_crtc_state(crtc->state);
new_acrtc_state = to_dm_crtc_state(crtc_state);
@@ -4525,7 +4526,7 @@ static int dm_update_crtcs_state(
if (!drm_atomic_crtc_needs_modeset(crtc_state))
- continue;
+ goto next_crtc;
DRM_DEBUG_KMS(
"amdgpu_crtc id:%d crtc_state_flags: enable:%d,
active:%d, "
@@ -4543,7 +4544,7 @@ static int dm_update_crtcs_state(
if (!enable) {
if (!old_acrtc_state->stream)
- continue;
+ goto next_crtc;
DRM_DEBUG_KMS("Disabling DRM crtc: %d\n",
crtc->base.id);
@@ -4554,7 +4555,7 @@ static int dm_update_crtcs_state(
dm_state->context,
old_acrtc_state->stream)) {
ret = -EINVAL;
- break;
+ goto fail;
}
dc_stream_release(old_acrtc_state->stream);
@@ -4565,7 +4566,7 @@ static int dm_update_crtcs_state(
} else {/* Add stream for any updated/enabled CRTC */
if (modereset_required(crtc_state))
- continue;
+ goto next_crtc;
if (modeset_required(crtc_state, new_stream,
old_acrtc_state->stream)) {
@@ -4583,19 +4584,25 @@ static int dm_update_crtcs_state(
dm_state->context,
new_acrtc_state->stream)) {
ret = -EINVAL;
- break;
+ goto fail;
}
*lock_and_validation_needed = true;
}
}
+next_crtc:
/* Release extra reference */
if (new_stream)
dc_stream_release(new_stream);
}
return ret;
+
+fail:
+ if (new_stream)
+ dc_stream_release(new_stream);
+ return ret;
}
static int dm_update_planes_state(
--
2.11.0
___
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RE: [PATCH 2/6] drm/amd/powerplay: Tidy up smu7_fan_ctrl_get_fan_speed_rpm()
> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Tuesday, September 12, 2017 10:47 AM > To: amd-gfx@lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH 2/6] drm/amd/powerplay: Tidy up > smu7_fan_ctrl_get_fan_speed_rpm() > > Signed-off-by: Tom St Denis > --- > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c > index a491f1201fda..0c822ef7d907 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c > @@ -86,8 +86,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct > pp_hwmgr *hwmgr, uint32_t *speed) > uint32_t crystal_clock_freq; > > if (hwmgr->thermal_controller.fanInfo.bNoFan || > - (hwmgr->thermal_controller.fanInfo. > - ucTachometerPulsesPerRevolution == 0)) > + !hwmgr->thermal_controller.fanInfo. > ucTachometerPulsesPerRevolution) Can you fix the whitespace here? Alex > return -ENODEV; > > tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, > CGS_IND_REG__SMC, > -- > 2.12.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 6/6] drm/amd/powerplay: Tidy up smu7_enable_didt()
> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Tuesday, September 12, 2017 10:47 AM > To: amd-gfx@lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH 6/6] drm/amd/powerplay: Tidy up smu7_enable_didt() > > Signed-off-by: Tom St Denis Patches 1,3-6: Reviewed-by: Alex Deucher With the whitespace fixed on patch 2: Reviewed-by: Alex Deucher > --- > .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 29 ++-- > -- > 1 file changed, 8 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c > index 9b4189cd0851..8c264c195e1a 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c > @@ -629,7 +629,6 @@ static int smu7_enable_didt(struct pp_hwmgr > *hwmgr, const bool enable) > uint32_t block_en = 0; > int32_t result = 0; > uint32_t didt_block; > - uint32_t data; > > if (hwmgr->chip_id == CHIP_POLARIS11) > didt_block = Polaris11_DIDTBlock_Info; > @@ -637,41 +636,29 @@ static int smu7_enable_didt(struct pp_hwmgr > *hwmgr, const bool enable) > didt_block = DIDTBlock_Info; > > block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0; > - > - data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0); > - data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; > - data |= ((block_en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & > DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK); > - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, > ixDIDT_SQ_CTRL0, data); > + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, > + DIDT_SQ_CTRL0, DIDT_CTRL_EN, block_en); > didt_block &= ~SQ_Enable_MASK; > didt_block |= block_en << SQ_Enable_SHIFT; > > block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0; > - > - data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0); > - data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; > - data |= ((block_en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & > DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK); > - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, > ixDIDT_DB_CTRL0, data); > + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, > + DIDT_DB_CTRL0, DIDT_CTRL_EN, block_en); > didt_block &= ~DB_Enable_MASK; > didt_block |= block_en << DB_Enable_SHIFT; > > block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0; > - data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0); > - data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; > - data |= ((block_en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & > DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK); > - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, > ixDIDT_TD_CTRL0, data); > + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, > + DIDT_TD_CTRL0, DIDT_CTRL_EN, block_en); > didt_block &= ~TD_Enable_MASK; > didt_block |= block_en << TD_Enable_SHIFT; > > block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0; > - > - data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0); > - data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; > - data |= ((block_en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & > DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK); > - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, > ixDIDT_TCP_CTRL0, data); > + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, > + DIDT_TCP_CTRL0, DIDT_CTRL_EN, block_en); > didt_block &= ~TCP_Enable_MASK; > didt_block |= block_en << TCP_Enable_SHIFT; > > - > if (enable) > result = smum_send_msg_to_smc_with_parameter(hwmgr- > >smumgr, PPSMC_MSG_Didt_Block_Function, didt_block); > > -- > 2.12.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/2] drm/amd/display: Clean Kconfig formatting
> -Original Message- > From: Harry Wentland [mailto:harry.wentl...@amd.com] > Sent: Tuesday, September 12, 2017 10:58 AM > To: amd-gfx@lists.freedesktop.org > Cc: airl...@gmail.com; Deucher, Alexander; dan...@ffwll.ch; Wentland, > Harry > Subject: [PATCH 1/2] drm/amd/display: Clean Kconfig formatting > > Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/display/Kconfig | 33 --- > -- > 1 file changed, 16 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/Kconfig > b/drivers/gpu/drm/amd/display/Kconfig > index 62ea9f600374..e91b6e57cf03 100644 > --- a/drivers/gpu/drm/amd/display/Kconfig > +++ b/drivers/gpu/drm/amd/display/Kconfig > @@ -2,26 +2,25 @@ menu "Display Engine Configuration" > depends on DRM && DRM_AMDGPU > > config DRM_AMD_DC > -bool "AMD DC - Enable new display engine (will be deprecated when > the development is done)" > -help > - Choose this option if you want to use the new display engine > - support for AMDGPU. > - > - Will be deprecated when the DC component is upstream. > + bool "AMD DC - Enable new display engine > + help > + Choose this option if you want to use the new display engine > + support for AMDGPU. This adds required support for Vega and > + Raven ASICs. > > config DRM_AMD_DC_DCN1_0 > -bool "DCN 1.0 Raven family" > -depends on DRM_AMD_DC && X86 > -help > -Choose this option if you want to have > -RV family for display engine > + bool "DCN 1.0 Raven family" > + depends on DRM_AMD_DC && X86 > + help > + Choose this option if you want to have > + RV family for display engine > > config DEBUG_KERNEL_DC > -bool "Enable kgdb break in DC" > -depends on DRM_AMD_DC > -help > - Choose this option > - if you want to hit > - kdgb_break in assert. > + bool "Enable kgdb break in DC" > + depends on DRM_AMD_DC > + help > + Choose this option > + if you want to hit > + kdgb_break in assert. > > endmenu > -- > 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/2] drm/amd/display: Disable pre-Vega ASICs be default
> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Harry Wentland > Sent: Tuesday, September 12, 2017 10:58 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander; Wentland, Harry; airl...@gmail.com; > dan...@ffwll.ch > Subject: [PATCH 2/2] drm/amd/display: Disable pre-Vega ASICs be default > > Signed-off-by: Harry Wentland > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ > drivers/gpu/drm/amd/display/Kconfig| 8 > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 34671790ce80..8c496a57788f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1995,7 +1995,9 @@ bool amdgpu_device_asic_has_dc_support(enum > amd_asic_type asic_type) > case CHIP_TONGA: > case CHIP_FIJI: > case CHIP_VEGA10: > +#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) > return amdgpu_dc != 0; > +#endif > case CHIP_KABINI: > case CHIP_MULLINS: > return amdgpu_dc > 0; > diff --git a/drivers/gpu/drm/amd/display/Kconfig > b/drivers/gpu/drm/amd/display/Kconfig > index e91b6e57cf03..4d2816e01bf0 100644 > --- a/drivers/gpu/drm/amd/display/Kconfig > +++ b/drivers/gpu/drm/amd/display/Kconfig > @@ -3,11 +3,19 @@ menu "Display Engine Configuration" > > config DRM_AMD_DC > bool "AMD DC - Enable new display engine > + default y > help > Choose this option if you want to use the new display engine > support for AMDGPU. This adds required support for Vega and > Raven ASICs. > > +config DRM_AMD_DC_PRE_VEGA > + bool "DC support for Polaris and older ASICs" > + default n > + help > + Choose this option to use the new DC driver for Polaris, Carrizo, > + Tonga, Bonaire, and Hawaii. I'd suggest changing the wording of this option to say something like: "Choose this option to enable the new DC support for older asics by default." So it's clear this just changes the default behavior, the user can still use DC via module parameter. Alex > + > config DRM_AMD_DC_DCN1_0 > bool "DCN 1.0 Raven family" > depends on DRM_AMD_DC && X86 > -- > 2.11.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerplay: lock grbm_gfx index when changing instance
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 8c264c195e1a..0f75af33e581 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -746,6 +746,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
PP_CAP(PHM_PlatformCaps_TCPRamping)) {
cgs_enter_safe_mode(hwmgr->device, true);
+ cgs_lock_grbm_idx(hwmgr->device, true);
value = 0;
value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
for (count = 0; count < num_se; count++) {
@@ -785,6 +786,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((0 == result),
"Failed to enable DPM DIDT.", return
result);
}
+ cgs_lock_grbm_idx(hwmgr->device, false);
cgs_enter_safe_mode(hwmgr->device, false);
}
--
2.12.0
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RE: [PATCH] drm/amd/powerplay: lock grbm_gfx index when changing instance
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, September 12, 2017 12:35 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH] drm/amd/powerplay: lock grbm_gfx index when changing
> instance
>
> Signed-off-by: Tom St Denis
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> index 8c264c195e1a..0f75af33e581 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> @@ -746,6 +746,7 @@ int smu7_enable_didt_config(struct pp_hwmgr
> *hwmgr)
> PP_CAP(PHM_PlatformCaps_TCPRamping)) {
>
> cgs_enter_safe_mode(hwmgr->device, true);
> + cgs_lock_grbm_idx(hwmgr->device, true);
> value = 0;
> value2 = cgs_read_register(hwmgr->device,
> mmGRBM_GFX_INDEX);
> for (count = 0; count < num_se; count++) {
> @@ -785,6 +786,7 @@ int smu7_enable_didt_config(struct pp_hwmgr
> *hwmgr)
> PP_ASSERT_WITH_CODE((0 == result),
> "Failed to enable DPM DIDT.", return
> result);
> }
> + cgs_lock_grbm_idx(hwmgr->device, false);
> cgs_enter_safe_mode(hwmgr->device, false);
> }
>
> --
> 2.12.0
>
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[PATCH libdrm] amdgpu: print error messages when amdgpu_device_initialize is failing
From: Marek Olšák
---
amdgpu/amdgpu_device.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index 9a238d9..2b31c45 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -184,42 +184,47 @@ int amdgpu_device_initialize(int fd,
uint32_t accel_working = 0;
uint64_t start, max;
*device_handle = NULL;
pthread_mutex_lock(&fd_mutex);
if (!fd_tab)
fd_tab = util_hash_table_create(fd_hash, fd_compare);
r = amdgpu_get_auth(fd, &flag_auth);
if (r) {
+ fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
+ __func__, r);
pthread_mutex_unlock(&fd_mutex);
return r;
}
dev = util_hash_table_get(fd_tab, UINT_TO_PTR(fd));
if (dev) {
r = amdgpu_get_auth(dev->fd, &flag_authexist);
if (r) {
+ fprintf(stderr, "%s: amdgpu_get_auth (2) failed (%i)\n",
+ __func__, r);
pthread_mutex_unlock(&fd_mutex);
return r;
}
if ((flag_auth) && (!flag_authexist)) {
dev->flink_fd = dup(fd);
}
*major_version = dev->major_version;
*minor_version = dev->minor_version;
amdgpu_device_reference(device_handle, dev);
pthread_mutex_unlock(&fd_mutex);
return 0;
}
dev = calloc(1, sizeof(struct amdgpu_device));
if (!dev) {
+ fprintf(stderr, "%s: calloc failed\n", __func__);
pthread_mutex_unlock(&fd_mutex);
return -ENOMEM;
}
dev->fd = -1;
dev->flink_fd = -1;
atomic_set(&dev->refcount, 1);
version = drmGetVersion(fd);
@@ -241,41 +246,49 @@ int amdgpu_device_initialize(int fd,
dev->minor_version = version->version_minor;
drmFreeVersion(version);
dev->bo_flink_names = util_hash_table_create(handle_hash,
handle_compare);
dev->bo_handles = util_hash_table_create(handle_hash, handle_compare);
pthread_mutex_init(&dev->bo_table_mutex, NULL);
/* Check if acceleration is working. */
r = amdgpu_query_info(dev, AMDGPU_INFO_ACCEL_WORKING, 4,
&accel_working);
- if (r)
+ if (r) {
+ fprintf(stderr, "%s: amdgpu_query_info(ACCEL_WORKING) failed
(%i)\n",
+ __func__, r);
goto cleanup;
+ }
if (!accel_working) {
+ fprintf(stderr, "%s: AMDGPU_INFO_ACCEL_WORKING = 0\n",
__func__);
r = -EBADF;
goto cleanup;
}
r = amdgpu_query_gpu_info_init(dev);
- if (r)
+ if (r) {
+ fprintf(stderr, "%s: amdgpu_query_gpu_info_init failed\n",
__func__);
goto cleanup;
+ }
amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset,
dev->dev_info.virtual_address_max,
dev->dev_info.virtual_address_alignment);
max = MIN2(dev->dev_info.virtual_address_max, 0x);
start = amdgpu_vamgr_find_va(&dev->vamgr,
max - dev->dev_info.virtual_address_offset,
dev->dev_info.virtual_address_alignment,
0);
- if (start > 0x)
+ if (start > 0x) {
+ fprintf(stderr, "%s: amdgpu_vamgr_find_va failed\n", __func__);
goto free_va; /* shouldn't get here */
+ }
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
dev->dev_info.virtual_address_alignment);
r = amdgpu_parse_asic_ids(&dev->asic_ids);
if (r) {
fprintf(stderr, "%s: Cannot parse ASIC IDs, 0x%x.",
__func__, r);
}
--
2.7.4
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Re: [PATCH libdrm] amdgpu: print error messages when amdgpu_device_initialize is failing
On Tue, Sep 12, 2017 at 1:39 PM, Marek Olšák wrote:
> From: Marek Olšák
>
Reviewed-by: Alex Deucher
> ---
> amdgpu/amdgpu_device.c | 19 ---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
> index 9a238d9..2b31c45 100644
> --- a/amdgpu/amdgpu_device.c
> +++ b/amdgpu/amdgpu_device.c
> @@ -184,42 +184,47 @@ int amdgpu_device_initialize(int fd,
> uint32_t accel_working = 0;
> uint64_t start, max;
>
> *device_handle = NULL;
>
> pthread_mutex_lock(&fd_mutex);
> if (!fd_tab)
> fd_tab = util_hash_table_create(fd_hash, fd_compare);
> r = amdgpu_get_auth(fd, &flag_auth);
> if (r) {
> + fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
> + __func__, r);
> pthread_mutex_unlock(&fd_mutex);
> return r;
> }
> dev = util_hash_table_get(fd_tab, UINT_TO_PTR(fd));
> if (dev) {
> r = amdgpu_get_auth(dev->fd, &flag_authexist);
> if (r) {
> + fprintf(stderr, "%s: amdgpu_get_auth (2) failed
> (%i)\n",
> + __func__, r);
> pthread_mutex_unlock(&fd_mutex);
> return r;
> }
> if ((flag_auth) && (!flag_authexist)) {
> dev->flink_fd = dup(fd);
> }
> *major_version = dev->major_version;
> *minor_version = dev->minor_version;
> amdgpu_device_reference(device_handle, dev);
> pthread_mutex_unlock(&fd_mutex);
> return 0;
> }
>
> dev = calloc(1, sizeof(struct amdgpu_device));
> if (!dev) {
> + fprintf(stderr, "%s: calloc failed\n", __func__);
> pthread_mutex_unlock(&fd_mutex);
> return -ENOMEM;
> }
>
> dev->fd = -1;
> dev->flink_fd = -1;
>
> atomic_set(&dev->refcount, 1);
>
> version = drmGetVersion(fd);
> @@ -241,41 +246,49 @@ int amdgpu_device_initialize(int fd,
> dev->minor_version = version->version_minor;
> drmFreeVersion(version);
>
> dev->bo_flink_names = util_hash_table_create(handle_hash,
> handle_compare);
> dev->bo_handles = util_hash_table_create(handle_hash, handle_compare);
> pthread_mutex_init(&dev->bo_table_mutex, NULL);
>
> /* Check if acceleration is working. */
> r = amdgpu_query_info(dev, AMDGPU_INFO_ACCEL_WORKING, 4,
> &accel_working);
> - if (r)
> + if (r) {
> + fprintf(stderr, "%s: amdgpu_query_info(ACCEL_WORKING) failed
> (%i)\n",
> + __func__, r);
> goto cleanup;
> + }
> if (!accel_working) {
> + fprintf(stderr, "%s: AMDGPU_INFO_ACCEL_WORKING = 0\n",
> __func__);
> r = -EBADF;
> goto cleanup;
> }
>
> r = amdgpu_query_gpu_info_init(dev);
> - if (r)
> + if (r) {
> + fprintf(stderr, "%s: amdgpu_query_gpu_info_init failed\n",
> __func__);
> goto cleanup;
> + }
>
> amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset,
> dev->dev_info.virtual_address_max,
> dev->dev_info.virtual_address_alignment);
>
> max = MIN2(dev->dev_info.virtual_address_max, 0x);
> start = amdgpu_vamgr_find_va(&dev->vamgr,
> max -
> dev->dev_info.virtual_address_offset,
> dev->dev_info.virtual_address_alignment,
> 0);
> - if (start > 0x)
> + if (start > 0x) {
> + fprintf(stderr, "%s: amdgpu_vamgr_find_va failed\n",
> __func__);
> goto free_va; /* shouldn't get here */
> + }
>
> amdgpu_vamgr_init(&dev->vamgr_32, start, max,
> dev->dev_info.virtual_address_alignment);
>
> r = amdgpu_parse_asic_ids(&dev->asic_ids);
> if (r) {
> fprintf(stderr, "%s: Cannot parse ASIC IDs, 0x%x.",
> __func__, r);
> }
>
> --
> 2.7.4
>
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Re: [PATCH 1/5] drm/amdgpu: fix cgs alignment handling
On Tue, Sep 12, 2017 at 5:08 AM, Christian König wrote: > From: Christian König > > This always allocated on PAGE_SIZE alignment. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c > index d450a96..8b5fa22 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c > @@ -121,7 +121,7 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device > *cgs_device, > placement.busy_placement = &place; > placement.num_busy_placement = 1; > > - ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE, > + ret = amdgpu_bo_create_restricted(adev, size, align, > true, domain, flags, > NULL, &placement, NULL, > 0, &obj); > -- > 2.7.4 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/5] drm/amdgpu: fix and cleanup amdgpu_bo_create
Am 12.09.2017 um 17:55 schrieb Deucher, Alexander:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Christian König
Sent: Tuesday, September 12, 2017 5:09 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 3/5] drm/amdgpu: fix and cleanup amdgpu_bo_create
From: Christian König
Fix USWC handling by cleaning up the function and removing
quite a bit of unused code.
Can you clarify what was broken?
We adjusted the BO flags for USWC handling, but those never took effect
because the placement was passed in instead of generated inside this
function.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 83 +
-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ---
2 files changed, 23 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 52d0109..726a662 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -64,11 +64,12 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct
ttm_buffer_object *bo)
return false;
}
-static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
- struct ttm_placement *placement,
- struct ttm_place *places,
- u32 domain, u64 flags)
+void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32
domain)
{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
+ struct ttm_placement *placement = &abo->placement;
+ struct ttm_place *places = abo->placements;
+ u64 flags = abo->flags;
u32 c = 0;
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
@@ -151,27 +152,6 @@ static void amdgpu_ttm_placement_init(struct
amdgpu_device *adev,
placement->busy_placement = places;
}
-void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32
domain)
-{
- struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
-
- amdgpu_ttm_placement_init(adev, &abo->placement, abo-
placements,
- domain, abo->flags);
-}
-
-static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
- struct ttm_placement *placement)
-{
- BUG_ON(placement->num_placement >
(AMDGPU_GEM_DOMAIN_MAX + 1));
-
- memcpy(bo->placements, placement->placement,
- placement->num_placement * sizeof(struct ttm_place));
- bo->placement.num_placement = placement->num_placement;
- bo->placement.num_busy_placement = placement-
num_busy_placement;
- bo->placement.placement = bo->placements;
- bo->placement.busy_placement = bo->placements;
-}
-
/**
* amdgpu_bo_create_reserved - create reserved BO for kernel use
*
@@ -303,14 +283,13 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo
**bo, u64 *gpu_addr,
*cpu_addr = NULL;
}
-int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
- unsigned long size, int byte_align,
- bool kernel, u32 domain, u64 flags,
- struct sg_table *sg,
- struct ttm_placement *placement,
- struct reservation_object *resv,
- uint64_t init_value,
- struct amdgpu_bo **bo_ptr)
+static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ unsigned long size, int byte_align,
+ bool kernel, u32 domain, u64 flags,
+ struct sg_table *sg,
+ struct reservation_object *resv,
+ uint64_t init_value,
+ struct amdgpu_bo **bo_ptr)
Still seems like amdgpu_bo_create_restricted is a better name than do_create.
How about amdgpu_bo_create_impl ?
Point is the function isn't restricted in any way any more.
Christian.
{
struct amdgpu_bo *bo;
enum ttm_bo_type type;
@@ -384,10 +363,11 @@ int amdgpu_bo_create_restricted(struct
amdgpu_device *adev,
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
#endif
- amdgpu_fill_placement_to_bo(bo, placement);
- /* Kernel allocation are uninterruptible */
+ bo->tbo.bdev = &adev->mman.bdev;
+ amdgpu_ttm_placement_from_domain(bo, domain);
initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
+ /* Kernel allocation are uninterruptible */
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size,
type,
&bo->placement, page_align, !kernel, NULL,
acc_size, sg, resv,
&amdgpu_ttm_bo_destroy);
@@ -442,27 +422,17 @@ static int amdgpu_bo_create_shadow(struct
amdgpu_device *adev,
Re: [PATCH 3/5] drm/amdgpu: fix and cleanup amdgpu_bo_create
On Tue, Sep 12, 2017 at 2:35 PM, Christian König
wrote:
> Am 12.09.2017 um 17:55 schrieb Deucher, Alexander:
>>>
>>> -Original Message-
>>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>>> Of Christian König
>>> Sent: Tuesday, September 12, 2017 5:09 AM
>>> To: amd-gfx@lists.freedesktop.org
>>> Subject: [PATCH 3/5] drm/amdgpu: fix and cleanup amdgpu_bo_create
>>>
>>> From: Christian König
>>>
>>> Fix USWC handling by cleaning up the function and removing
>>> quite a bit of unused code.
>>
>> Can you clarify what was broken?
>
>
> We adjusted the BO flags for USWC handling, but those never took effect
> because the placement was passed in instead of generated inside this
> function.
Ah, yes, I see now. Can you add that to the commit message?
>
>
>>
>>> Signed-off-by: Christian König
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 83 +
>>> -
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ---
>>> 2 files changed, 23 insertions(+), 68 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> index 52d0109..726a662 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> @@ -64,11 +64,12 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct
>>> ttm_buffer_object *bo)
>>> return false;
>>> }
>>>
>>> -static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
>>> - struct ttm_placement *placement,
>>> - struct ttm_place *places,
>>> - u32 domain, u64 flags)
>>> +void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32
>>> domain)
>>> {
>>> + struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
>>> + struct ttm_placement *placement = &abo->placement;
>>> + struct ttm_place *places = abo->placements;
>>> + u64 flags = abo->flags;
>>> u32 c = 0;
>>>
>>> if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
>>> @@ -151,27 +152,6 @@ static void amdgpu_ttm_placement_init(struct
>>> amdgpu_device *adev,
>>> placement->busy_placement = places;
>>> }
>>>
>>> -void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32
>>> domain)
>>> -{
>>> - struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
>>> -
>>> - amdgpu_ttm_placement_init(adev, &abo->placement, abo-
placements,
>>>
>>> - domain, abo->flags);
>>> -}
>>> -
>>> -static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
>>> - struct ttm_placement *placement)
>>> -{
>>> - BUG_ON(placement->num_placement >
>>> (AMDGPU_GEM_DOMAIN_MAX + 1));
>>> -
>>> - memcpy(bo->placements, placement->placement,
>>> - placement->num_placement * sizeof(struct ttm_place));
>>> - bo->placement.num_placement = placement->num_placement;
>>> - bo->placement.num_busy_placement = placement-
num_busy_placement;
>>>
>>> - bo->placement.placement = bo->placements;
>>> - bo->placement.busy_placement = bo->placements;
>>> -}
>>> -
>>> /**
>>>* amdgpu_bo_create_reserved - create reserved BO for kernel use
>>>*
>>> @@ -303,14 +283,13 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo
>>> **bo, u64 *gpu_addr,
>>> *cpu_addr = NULL;
>>> }
>>>
>>> -int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
>>> - unsigned long size, int byte_align,
>>> - bool kernel, u32 domain, u64 flags,
>>> - struct sg_table *sg,
>>> - struct ttm_placement *placement,
>>> - struct reservation_object *resv,
>>> - uint64_t init_value,
>>> - struct amdgpu_bo **bo_ptr)
>>> +static int amdgpu_bo_do_create(struct amdgpu_device *adev,
>>> + unsigned long size, int byte_align,
>>> + bool kernel, u32 domain, u64 flags,
>>> + struct sg_table *sg,
>>> + struct reservation_object *resv,
>>> + uint64_t init_value,
>>> + struct amdgpu_bo **bo_ptr)
>>
>> Still seems like amdgpu_bo_create_restricted is a better name than
>> do_create.
>
>
> How about amdgpu_bo_create_impl ?
>
> Point is the function isn't restricted in any way any more.
Sorry, I was mixing this up with the pinning code in my head.
Objection withdrawn. With the updated description, patch is:
Reviewed-by: Alex Deucher
Alex
>
> Christian.
>
>
>>
>>> {
>>> struct amdgpu_bo *bo;
>>> enum ttm_bo_type type;
>>> @@ -384,10 +363,11 @@ int amdgpu_bo_create_restricted(struct
>>> amdgpu_device *adev,
>>>
Re: [PATCH 0/8] Retry page fault handling for Vega10
On 2017-09-12 01:48 AM, Oded Gabbay wrote: > +John, > > If Alex is fine with it then I'm fine with it as well, as long as this > is a temporary solution until some point where you have some > convergence between your internal code and the upstream one. Agreed. I want to converge those branches as soon as possible. > And of course if you have amdkfd only changes then that can be > upstreamed through me directly. Yes. > > Having said that, if you/John/Alex think that this is a more permanent > solution, then maybe a better plan is to first unify the drivers (as > was discussed many times) before starting to upstream changes. If the > 90% of the changes are in both drivers, then there is really no point > of keeping amdkfd as a separate driver. If we unify the drivers first, it would further diverge the branches. That would be counter-productive in my opinion. I'd rather get the branches to converge first and then unify the drivers so we don't have to do it twice. Regards, Felix > > Oded ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amd/display: Don't leak dc_stream_state.
On 2017-09-12 12:10 PM, Darren Salt wrote:
> Noticed while playing “Valley”, which was causing some 8MB of leakage per
> second. kmemleak listed many entries looking like this:
>
> unreferenced object 0x8802c2951800 (size 1024):
> comm "Xorg", pid 2982, jiffies 4297410155 (age 392.787s)
> hex dump (first 32 bytes):
> 00 50 f9 0c 04 88 ff ff 98 08 00 00 00 00 00 00 .P..
> 80 07 00 00 00 00 00 00 58 00 00 00 2c 00 00 00 X...,...
> backtrace:
> [] create_object+0x13c/0x261
> [] kmemleak_alloc+0x20/0x3c
> [] slab_post_alloc_hook+0x42/0x52
> [] kmem_cache_alloc+0x67/0x76
> [] dc_create_stream_for_sink+0x24/0x1cf
> [] create_stream_for_sink+0x6f/0x295
> [] dm_update_crtcs_state+0xa6/0x268
> [] amdgpu_dm_atomic_check+0x9a/0x314
> [] drm_atomic_check_only+0x17a/0x42d
> [] drm_atomic_commit+0x13/0x4b
> [] drm_atomic_connector_commit_dpms+0xcb/0xe8
> [] drm_mode_obj_set_property_ioctl+0xe6/0x1e3
> [] drm_mode_connector_property_set_ioctl+0x2b/0x2d
> [] drm_ioctl_kernel+0x64/0x9d
> [] drm_ioctl+0x230/0x316
> [] amdgpu_drm_ioctl+0x4b/0x7d
>
> v2: also handle break statements.
>
Thanks for the patch. We really should've caught that earlier.
Reviewed-by: Harry Wentland
Harry
> Signed-off-by: Darren Salt
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +--
> 1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 32c75867eaa7..14f1a4bcf2e9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4466,6 +4466,7 @@ static int dm_update_crtcs_state(
> int i;
> struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
> struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
> + struct dc_stream_state *new_stream;
> int ret = 0;
>
> /*TODO Move this code into dm_crtc_atomic_check once we get rid of
> dc_validation_set */
> @@ -4473,10 +4474,10 @@ static int dm_update_crtcs_state(
> for_each_crtc_in_state(state, crtc, crtc_state, i) {
> struct amdgpu_crtc *acrtc = NULL;
> struct amdgpu_connector *aconnector = NULL;
> - struct dc_stream_state *new_stream = NULL;
> struct drm_connector_state *conn_state = NULL;
> struct dm_connector_state *dm_conn_state = NULL;
>
> + new_stream = NULL;
>
> old_acrtc_state = to_dm_crtc_state(crtc->state);
> new_acrtc_state = to_dm_crtc_state(crtc_state);
> @@ -4525,7 +4526,7 @@ static int dm_update_crtcs_state(
>
>
> if (!drm_atomic_crtc_needs_modeset(crtc_state))
> - continue;
> + goto next_crtc;
>
> DRM_DEBUG_KMS(
> "amdgpu_crtc id:%d crtc_state_flags: enable:%d,
> active:%d, "
> @@ -4543,7 +4544,7 @@ static int dm_update_crtcs_state(
> if (!enable) {
>
> if (!old_acrtc_state->stream)
> - continue;
> + goto next_crtc;
>
> DRM_DEBUG_KMS("Disabling DRM crtc: %d\n",
> crtc->base.id);
> @@ -4554,7 +4555,7 @@ static int dm_update_crtcs_state(
> dm_state->context,
> old_acrtc_state->stream)) {
> ret = -EINVAL;
> - break;
> + goto fail;
> }
>
> dc_stream_release(old_acrtc_state->stream);
> @@ -4565,7 +4566,7 @@ static int dm_update_crtcs_state(
> } else {/* Add stream for any updated/enabled CRTC */
>
> if (modereset_required(crtc_state))
> - continue;
> + goto next_crtc;
>
> if (modeset_required(crtc_state, new_stream,
>old_acrtc_state->stream)) {
> @@ -4583,19 +4584,25 @@ static int dm_update_crtcs_state(
> dm_state->context,
> new_acrtc_state->stream)) {
> ret = -EINVAL;
> - break;
> + goto fail;
> }
>
> *lock_and_validation_needed = true;
> }
> }
>
> +next_crtc:
> /* Release extra reference */
> if (new_stream)
>dc_stream_release(new_stream);
> }
[PATCH 3/3] drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_file
From: Marek Olšák
for being able to convert an amdgpu fence into one of the handles.
Mesa will use this.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 61 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
include/uapi/drm/amdgpu_drm.h | 16 +
5 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b5c8b90..c15fa93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1308,6 +1308,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
*data,
int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file
*filp);
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 7cb8a59..6dd719c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -25,6 +25,7 @@
*Jerome Glisse
*/
#include
+#include
#include
#include
#include
@@ -1311,6 +1312,66 @@ static struct dma_fence *amdgpu_cs_get_fence(struct
amdgpu_device *adev,
return fence;
}
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ struct amdgpu_device *adev = dev->dev_private;
+ struct amdgpu_fpriv *fpriv = filp->driver_priv;
+ union drm_amdgpu_fence_to_handle *info = data;
+ struct dma_fence *fence;
+ struct drm_syncobj *syncobj;
+ struct sync_file *sync_file;
+ int fd, r;
+
+ if (amdgpu_kms_vram_lost(adev, fpriv))
+ return -ENODEV;
+
+ fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
+ if (IS_ERR(fence))
+ return PTR_ERR(fence);
+
+ switch (info->in.what) {
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
+ r = drm_syncobj_create(&syncobj, 0, fence);
+ dma_fence_put(fence);
+ if (r)
+ return r;
+ r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
+ drm_syncobj_put(syncobj);
+ return r;
+
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
+ r = drm_syncobj_create(&syncobj, 0, fence);
+ dma_fence_put(fence);
+ if (r)
+ return r;
+ r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
+ drm_syncobj_put(syncobj);
+ return r;
+
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
+ fd = get_unused_fd_flags(O_CLOEXEC);
+ if (fd < 0) {
+ dma_fence_put(fence);
+ return fd;
+ }
+
+ sync_file = sync_file_create(fence);
+ dma_fence_put(fence);
+ if (!sync_file) {
+ put_unused_fd(fd);
+ return -ENOMEM;
+ }
+
+ fd_install(fd, sync_file->file);
+ info->out.handle = fd;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
/**
* amdgpu_cs_wait_all_fence - wait on all fences to signal
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d01aca6..1e38411 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -70,9 +70,10 @@
* - 3.18.0 - Export gpu always on cu bitmap
* - 3.19.0 - Add support for UVD MJPEG decode
* - 3.20.0 - Add support for local BOs
+ * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
*/
#define KMS_DRIVER_MAJOR 3
-#define KMS_DRIVER_MINOR 20
+#define KMS_DRIVER_MINOR 21
#define KMS_DRIVER_PATCHLEVEL 0
int amdgpu_vram_limit = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d31777b..b09d315 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1021,6 +1021,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_D
[PATCH 2/3] drm/syncobj: add a new helper drm_syncobj_get_fd
From: Marek Olšák
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/drm_syncobj.c | 33 +++--
include/drm/drm_syncobj.h | 1 +
2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 0bb1741..62adc7a 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -386,33 +386,38 @@ static int drm_syncobj_alloc_file(struct drm_syncobj
*syncobj)
return 0;
}
-static int drm_syncobj_handle_to_fd(struct drm_file *file_private,
- u32 handle, int *p_fd)
+int drm_syncobj_get_fd(struct drm_syncobj *syncobj, int *p_fd)
{
- struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle);
int ret;
int fd;
- if (!syncobj)
- return -EINVAL;
-
fd = get_unused_fd_flags(O_CLOEXEC);
- if (fd < 0) {
- drm_syncobj_put(syncobj);
+ if (fd < 0)
return fd;
- }
if (!syncobj->file) {
ret = drm_syncobj_alloc_file(syncobj);
- if (ret)
- goto out_put_fd;
+ if (ret) {
+ put_unused_fd(fd);
+ return ret;
+ }
}
fd_install(fd, syncobj->file);
- drm_syncobj_put(syncobj);
*p_fd = fd;
return 0;
-out_put_fd:
- put_unused_fd(fd);
+}
+EXPORT_SYMBOL(drm_syncobj_get_fd);
+
+static int drm_syncobj_handle_to_fd(struct drm_file *file_private,
+ u32 handle, int *p_fd)
+{
+ struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle);
+ int ret;
+
+ if (!syncobj)
+ return -EINVAL;
+
+ ret = drm_syncobj_get_fd(syncobj, p_fd);
drm_syncobj_put(syncobj);
return ret;
}
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index e7f0035..43e2f38 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -140,5 +140,6 @@ int drm_syncobj_create(struct drm_syncobj **out_syncobj,
uint32_t flags,
struct dma_fence *fence);
int drm_syncobj_get_handle(struct drm_file *file_private,
struct drm_syncobj *syncobj, u32 *handle);
+int drm_syncobj_get_fd(struct drm_syncobj *syncobj, int *p_fd);
#endif
--
2.7.4
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/3] drm/syncobj: extract two helpers from drm_syncobj_create
From: Marek Olšák
For amdgpu.
drm_syncobj_create is renamed to drm_syncobj_create_as_handle, and new
helpers drm_syncobj_create and drm_syncobj_get_handle are added.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/drm_syncobj.c | 49 +++
include/drm/drm_syncobj.h | 4
2 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 0422b8c..0bb1741 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -262,8 +262,14 @@ void drm_syncobj_free(struct kref *kref)
}
EXPORT_SYMBOL(drm_syncobj_free);
-static int drm_syncobj_create(struct drm_file *file_private,
- u32 *handle, uint32_t flags)
+/**
+ * drm_syncobj_create - create a new syncobj
+ * @out_syncobj: returned syncobj
+ * @flags: DRM_SYNCOBJ_* flags
+ * @fence: if non-NULL, the syncobj will represent this fence
+ */
+int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
+ struct dma_fence *fence)
{
int ret;
struct drm_syncobj *syncobj;
@@ -284,6 +290,25 @@ static int drm_syncobj_create(struct drm_file
*file_private,
}
}
+ if (fence)
+ drm_syncobj_replace_fence(syncobj, fence);
+
+ *out_syncobj = syncobj;
+ return 0;
+}
+EXPORT_SYMBOL(drm_syncobj_create);
+
+/**
+ * drm_syncobj_get_handle - get a handle from a syncobj
+ */
+int drm_syncobj_get_handle(struct drm_file *file_private,
+ struct drm_syncobj *syncobj, u32 *handle)
+{
+ int ret;
+
+ /* take a reference to put in the idr */
+ drm_syncobj_get(syncobj);
+
idr_preload(GFP_KERNEL);
spin_lock(&file_private->syncobj_table_lock);
ret = idr_alloc(&file_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT);
@@ -299,6 +324,22 @@ static int drm_syncobj_create(struct drm_file
*file_private,
*handle = ret;
return 0;
}
+EXPORT_SYMBOL(drm_syncobj_get_handle);
+
+static int drm_syncobj_create_as_handle(struct drm_file *file_private,
+ u32 *handle, uint32_t flags)
+{
+ int ret;
+ struct drm_syncobj *syncobj;
+
+ ret = drm_syncobj_create(&syncobj, flags, NULL);
+ if (ret)
+ return ret;
+
+ ret = drm_syncobj_get_handle(file_private, syncobj, handle);
+ drm_syncobj_put(syncobj);
+ return ret;
+}
static int drm_syncobj_destroy(struct drm_file *file_private,
u32 handle)
@@ -522,8 +563,8 @@ drm_syncobj_create_ioctl(struct drm_device *dev, void *data,
if (args->flags & ~DRM_SYNCOBJ_CREATE_SIGNALED)
return -EINVAL;
- return drm_syncobj_create(file_private,
- &args->handle, args->flags);
+ return drm_syncobj_create_as_handle(file_private,
+ &args->handle, args->flags);
}
int
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index c00fee5..e7f0035 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -136,5 +136,9 @@ int drm_syncobj_find_fence(struct drm_file *file_private,
u32 handle,
struct dma_fence **fence);
void drm_syncobj_free(struct kref *kref);
+int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
+ struct dma_fence *fence);
+int drm_syncobj_get_handle(struct drm_file *file_private,
+ struct drm_syncobj *syncobj, u32 *handle);
#endif
--
2.7.4
___
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[PATCH libdrm 1/4] amdgpu: add sync_file import and export functions
From: Marek Olšák
---
amdgpu/amdgpu.h| 30 ++
amdgpu/amdgpu_cs.c | 20
2 files changed, 50 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 238b1aa..b44b9b6 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1383,6 +1383,36 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
uint32_t *syncobj);
/**
+ * Export kernel sync object to a sync_file.
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj- \c [in] sync object handle
+ * \param sync_file_fd - \c [out] sync_file file descriptor.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *sync_file_fd);
+
+/**
+ * Import kernel sync object from a sync_file.
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj- \c [in] sync object handle
+ * \param sync_file_fd - \c [in] sync_file file descriptor.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int sync_file_fd);
+
+/**
* Submit raw command submission to kernel
*
* \param dev - \c [in] device handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index dfba875..4a05536 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -635,6 +635,26 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
}
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *sync_file_fd)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int sync_file_fd)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
amdgpu_context_handle context,
amdgpu_bo_list_handle bo_list_handle,
--
2.7.4
___
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[PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper
From: Marek Olšák
---
include/drm/drm.h | 24
xf86drm.c | 22 ++
xf86drm.h | 3 +++
3 files changed, 49 insertions(+)
diff --git a/include/drm/drm.h b/include/drm/drm.h
index bf3674a..4da1667 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -694,6 +694,7 @@ struct drm_prime_handle {
struct drm_syncobj_create {
__u32 handle;
+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
__u32 flags;
};
@@ -712,6 +713,24 @@ struct drm_syncobj_handle {
__u32 pad;
};
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+struct drm_syncobj_wait {
+ __u64 handles;
+ /* absolute timeout */
+ __s64 timeout_nsec;
+ __u32 count_handles;
+ __u32 flags;
+ __u32 first_signaled; /* only valid when not waiting all */
+ __u32 pad;
+};
+
+struct drm_syncobj_array {
+ __u64 handles;
+ __u32 count_handles;
+ __u32 pad;
+};
+
#if defined(__cplusplus)
}
#endif
@@ -834,6 +853,9 @@ extern "C" {
#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct
drm_syncobj_destroy)
#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct
drm_syncobj_handle)
#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct
drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
+#define DRM_IOCTL_SYNCOBJ_RESETDRM_IOWR(0xC4, struct
drm_syncobj_array)
+#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
/**
* Device specific ioctls should only be in their respective headers
@@ -876,6 +898,7 @@ struct drm_event_vblank {
};
/* typedef area */
+#ifndef __KERNEL__
typedef struct drm_clip_rect drm_clip_rect_t;
typedef struct drm_drawable_info drm_drawable_info_t;
typedef struct drm_tex_region drm_tex_region_t;
@@ -917,6 +940,7 @@ typedef struct drm_agp_binding drm_agp_binding_t;
typedef struct drm_agp_info drm_agp_info_t;
typedef struct drm_scatter_gather drm_scatter_gather_t;
typedef struct drm_set_version drm_set_version_t;
+#endif
#if defined(__cplusplus)
}
diff --git a/xf86drm.c b/xf86drm.c
index 6ea0112..8a32717 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4225,3 +4225,25 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle,
int *sync_file_fd)
*sync_file_fd = args.fd;
return 0;
}
+
+int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
+{
+ struct drm_syncobj_wait args;
+ int ret;
+
+ memclear(args);
+ args.handles = (intptr_t)handles;
+ args.timeout_nsec = timeout_nsec;
+ args.count_handles = num_handles;
+ args.flags = flags;
+
+ ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args);
+ if (ret < 0)
+ return ret;
+
+ if (first_signaled)
+ *first_signaled = args.first_signaled;
+ return ret;
+}
diff --git a/xf86drm.h b/xf86drm.h
index 2855a3e..ea650ef 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -860,6 +860,9 @@ extern int drmSyncobjFDToHandle(int fd, int obj_fd,
uint32_t *handle);
extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd);
extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int
*sync_file_fd);
+extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled);
#if defined(__cplusplus)
}
--
2.7.4
___
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[PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle
From: Marek Olšák
---
amdgpu/amdgpu.h | 14 ++
amdgpu/amdgpu_cs.c | 22 ++
include/drm/amdgpu_drm.h | 21 +
3 files changed, 57 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 979acfc..23cde10 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1433,6 +1433,20 @@ int
amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
int sync_file_fd);
/**
+ * Export an amdgpu fence as a handle (syncobj or fd).
+ *
+ * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}
+ * \param out_handle returned handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ */
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle);
+
+/**
* Submit raw command submission to kernel
*
* \param dev - \c [in] device handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 2cde7bf..9577d5c 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -713,3 +713,25 @@ void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence
*fence,
dep->ctx_id = fence->context->id;
dep->handle = fence->fence;
}
+
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle)
+{
+ union drm_amdgpu_fence_to_handle fth = {0};
+ int r;
+
+ fth.in.fence.ctx_id = fence->context->id;
+ fth.in.fence.ip_type = fence->ip_type;
+ fth.in.fence.ip_instance = fence->ip_instance;
+ fth.in.fence.ring = fence->ring;
+ fth.in.fence.seq_no = fence->fence;
+ fth.in.what = what;
+
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE,
+ &fth, sizeof(fth));
+ if (r == 0)
+ *out_handle = fth.out.handle;
+ return r;
+}
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d9aa4a3..00f1b81 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -52,6 +52,7 @@ extern "C" {
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
#define DRM_AMDGPU_VM 0x13
+#define DRM_AMDGPU_FENCE_TO_HANDLE 0x15
#define DRM_IOCTL_AMDGPU_GEM_CREATEDRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -67,6 +68,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
#define DRM_IOCTL_AMDGPU_VMDRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_VM, union drm_amdgpu_vm)
+#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -87,6 +89,8 @@ extern "C" {
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
+/* Flag that BO is always valid in this VM */
+#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -513,6 +517,20 @@ struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD2
+
+union drm_amdgpu_fence_to_handle {
+ struct {
+ struct drm_amdgpu_fence fence;
+ __u32 what;
+ } in;
+ struct {
+ __u32 handle;
+ } out;
+};
+
struct drm_amdgpu_cs_chunk_data {
union {
struct drm_amdgpu_cs_chunk_ib ib_data;
@@ -764,6 +782,7 @@ struct drm_amdgpu_info_device {
__u64 max_memory_clock;
/* cu information */
__u32 cu_active_number;
+ /* NOTE: cu_ao_mask is INVALID, DON'T use it */
__u32 cu_ao_mask;
__u32 cu_bitmap[4][4];
/** Render backend pipe mask. One render backend is CB+DB. */
@@ -818,6 +837,8 @@ struct drm_amdgpu_info_device {
/* max gs wavefront per vgt*/
__u32 max_gs_waves_per_vgt;
__u32 _pad1;
+ /* always on cu bitmap */
+ __u32 cu_ao_bitmap[4][4];
};
struct drm_amdgpu_info_hw_ip {
--
2.7.4
___
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https://lists
[PATCH libdrm 3/4] amdgpu: add amdgpu_cs_syncobj_wait
From: Marek Olšák
---
amdgpu/amdgpu.h| 20
amdgpu/amdgpu_cs.c | 12
2 files changed, 32 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index b44b9b6..979acfc 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1354,6 +1354,26 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
uint32_t syncobj);
/**
+ * Wait for one or all sync objects to signal.
+ *
+ * \param dev- \c [in] self-explanatory
+ * \param handles - \c [in] array of sync object handles
+ * \param num_handles - \c [in] self-explanatory
+ * \param timeout_nsec - \c [in] self-explanatory
+ * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
+ * \param first_signaled - \c [in] self-explanatory
+ *
+ * \return 0 on success\n
+ * -ETIME - Timeout
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+ uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled);
+
+/**
* Export kernel sync object to shareable fd.
*
* \param dev - \c [in] device handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 4a05536..2cde7bf 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -615,6 +615,18 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
return drmSyncobjDestroy(dev->fd, handle);
}
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+ uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjWait(dev->fd, handles, num_handles, timeout_nsec,
+ flags, first_signaled);
+}
+
int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
uint32_t handle,
int *shared_fd)
--
2.7.4
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[PATCH v2] drm/amd/display: Disable pre-Vega ASICs by default
v2: Clarify help text for pre-vega config Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ drivers/gpu/drm/amd/display/Kconfig| 9 + 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 34671790ce80..8c496a57788f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1995,7 +1995,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_TONGA: case CHIP_FIJI: case CHIP_VEGA10: +#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) return amdgpu_dc != 0; +#endif case CHIP_KABINI: case CHIP_MULLINS: return amdgpu_dc > 0; diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index e91b6e57cf03..239a477310af 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -3,11 +3,20 @@ menu "Display Engine Configuration" config DRM_AMD_DC bool "AMD DC - Enable new display engine + default y help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and Raven ASICs. +config DRM_AMD_DC_PRE_VEGA + bool "DC support for Polaris and older ASICs" + default n + help + Choose this option to enable the new DC support for older asics + by default. This includes Polaris, Carrizo, Tonga, Bonaire, + and Hawaii. + config DRM_AMD_DC_DCN1_0 bool "DCN 1.0 Raven family" depends on DRM_AMD_DC && X86 -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/8] drm/amdkfd: Separate doorbell allocation from PASID
PASID management is moving into KGD. Limiting the PASID range to the
number of doorbell pages is no longer practical.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 -
drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 50 +--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 10 +++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6
4 files changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 61fff25..5df12b2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -168,13 +168,6 @@ static bool device_iommu_pasid_init(struct kfd_dev *kfd)
pasid_limit = min_t(unsigned int,
(unsigned int)(1 << kfd->device_info->max_pasid_bits),
iommu_info.max_pasids);
- /*
-* last pasid is used for kernel queues doorbells
-* in the future the last pasid might be used for a kernel thread.
-*/
- pasid_limit = min_t(unsigned int,
- pasid_limit,
- kfd->doorbell_process_limit - 1);
err = amd_iommu_init_device(kfd->pdev, pasid_limit);
if (err < 0) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
index acf4d2a..feb76c2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
@@ -24,16 +24,15 @@
#include
#include
#include
+#include
/*
- * This extension supports a kernel level doorbells management for
- * the kernel queues.
- * Basically the last doorbells page is devoted to kernel queues
- * and that's assures that any user process won't get access to the
- * kernel doorbells page
+ * This extension supports a kernel level doorbells management for the
+ * kernel queues using the first doorbell page reserved for the kernel.
*/
-#define KERNEL_DOORBELL_PASID 1
+static DEFINE_IDA(doorbell_ida);
+static unsigned int max_doorbell_slices;
#define KFD_SIZE_OF_DOORBELL_IN_BYTES 4
/*
@@ -84,13 +83,16 @@ int kfd_doorbell_init(struct kfd_dev *kfd)
(doorbell_aperture_size - doorbell_start_offset) /
doorbell_process_allocation();
else
- doorbell_process_limit = 0;
+ return -ENOSPC;
+
+ if (!max_doorbell_slices ||
+ doorbell_process_limit < max_doorbell_slices)
+ max_doorbell_slices = doorbell_process_limit;
kfd->doorbell_base = kfd->shared_resources.doorbell_physical_address +
doorbell_start_offset;
kfd->doorbell_id_offset = doorbell_start_offset / sizeof(u32);
- kfd->doorbell_process_limit = doorbell_process_limit - 1;
kfd->doorbell_kernel_ptr = ioremap(kfd->doorbell_base,
doorbell_process_allocation());
@@ -185,11 +187,10 @@ u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
return NULL;
/*
-* Calculating the kernel doorbell offset using "faked" kernel
-* pasid that allocated for kernel queues only
+* Calculating the kernel doorbell offset using the first
+* doorbell page.
*/
- *doorbell_off = KERNEL_DOORBELL_PASID * (doorbell_process_allocation() /
- sizeof(u32)) + inx;
+ *doorbell_off = kfd->doorbell_id_offset + inx;
pr_debug("Get kernel queue doorbell\n"
" doorbell offset == 0x%08X\n"
@@ -228,11 +229,12 @@ unsigned int kfd_queue_id_to_doorbell(struct kfd_dev *kfd,
{
/*
* doorbell_id_offset accounts for doorbells taken by KGD.
-* pasid * doorbell_process_allocation/sizeof(u32) adjusts
-* to the process's doorbells
+* index * doorbell_process_allocation/sizeof(u32) adjusts to
+* the process's doorbells.
*/
return kfd->doorbell_id_offset +
- process->pasid * (doorbell_process_allocation()/sizeof(u32)) +
+ process->doorbell_index
+ * doorbell_process_allocation() / sizeof(u32) +
queue_id;
}
@@ -250,5 +252,21 @@ phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
struct kfd_process *process)
{
return dev->doorbell_base +
- process->pasid * doorbell_process_allocation();
+ process->doorbell_index * doorbell_process_allocation();
+}
+
+int kfd_alloc_process_doorbells(struct kfd_process *process)
+{
+ int r = ida_simple_get(&doorbell_ida, 1, max_doorbell_slices,
+ GFP_KERNEL);
+ if (r > 0)
+ process->doorbell_index = r;
+
+ return r;
+}
+
+void kfd_free_process_doorbells(st
[PATCH 5/8] drm/amdkfd: Use PASID manager from KGD
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_module.c | 6 ---
drivers/gpu/drm/amd/amdkfd/kfd_pasid.c | 90 ++---
2 files changed, 38 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 0d73bea..6c5a9ca 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -103,10 +103,6 @@ static int __init kfd_module_init(void)
return -1;
}
- err = kfd_pasid_init();
- if (err < 0)
- return err;
-
err = kfd_chardev_init();
if (err < 0)
goto err_ioctl;
@@ -126,7 +122,6 @@ static int __init kfd_module_init(void)
err_topology:
kfd_chardev_exit();
err_ioctl:
- kfd_pasid_exit();
return err;
}
@@ -137,7 +132,6 @@ static void __exit kfd_module_exit(void)
kfd_process_destroy_wq();
kfd_topology_shutdown();
kfd_chardev_exit();
- kfd_pasid_exit();
dev_info(kfd_device, "Removed module\n");
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
index 1e06de0..d6a7961 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
@@ -20,78 +20,64 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include
#include
#include "kfd_priv.h"
-static unsigned long *pasid_bitmap;
-static unsigned int pasid_limit;
-static DEFINE_MUTEX(pasid_mutex);
-
-int kfd_pasid_init(void)
-{
- pasid_limit = KFD_MAX_NUM_OF_PROCESSES;
-
- pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long),
- GFP_KERNEL);
- if (!pasid_bitmap)
- return -ENOMEM;
-
- set_bit(0, pasid_bitmap); /* PASID 0 is reserved. */
-
- return 0;
-}
-
-void kfd_pasid_exit(void)
-{
- kfree(pasid_bitmap);
-}
+static unsigned int pasid_bits = 16;
+static const struct kfd2kgd_calls *kfd2kgd;
bool kfd_set_pasid_limit(unsigned int new_limit)
{
- if (new_limit < pasid_limit) {
- bool ok;
-
- mutex_lock(&pasid_mutex);
-
- /* ensure that no pasids >= new_limit are in-use */
- ok = (find_next_bit(pasid_bitmap, pasid_limit, new_limit) ==
- pasid_limit);
- if (ok)
- pasid_limit = new_limit;
-
- mutex_unlock(&pasid_mutex);
-
- return ok;
+ if (new_limit < 2)
+ return false;
+
+ if (new_limit < (1U << pasid_bits)) {
+ if (kfd2kgd)
+ /* We've already allocated user PASIDs, too late to
+* change the limit
+*/
+ return false;
+
+ while (new_limit < (1U << pasid_bits))
+ pasid_bits--;
}
return true;
}
-inline unsigned int kfd_get_pasid_limit(void)
+unsigned int kfd_get_pasid_limit(void)
{
- return pasid_limit;
+ return 1U << pasid_bits;
}
unsigned int kfd_pasid_alloc(void)
{
- unsigned int found;
-
- mutex_lock(&pasid_mutex);
-
- found = find_first_zero_bit(pasid_bitmap, pasid_limit);
- if (found == pasid_limit)
- found = 0;
- else
- set_bit(found, pasid_bitmap);
+ int r;
+
+ /* Find the first best KFD device for calling KGD */
+ if (!kfd2kgd) {
+ struct kfd_dev *dev = NULL;
+ unsigned int i = 0;
+
+ while ((dev = kfd_topology_enum_kfd_devices(i)) != NULL) {
+ if (dev && dev->kfd2kgd) {
+ kfd2kgd = dev->kfd2kgd;
+ break;
+ }
+ i++;
+ }
+
+ if (!kfd2kgd)
+ return false;
+ }
- mutex_unlock(&pasid_mutex);
+ r = kfd2kgd->alloc_pasid(pasid_bits);
- return found;
+ return r > 0 ? r : 0;
}
void kfd_pasid_free(unsigned int pasid)
{
- if (!WARN_ON(pasid == 0 || pasid >= pasid_limit))
- clear_bit(pasid, pasid_bitmap);
+ if (kfd2kgd)
+ kfd2kgd->free_pasid(pasid);
}
--
2.7.4
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/8] drm/amdgpu: Fix error handling in amdgpu_vm_init
Make sure vm->root.bo is not left reserved if amdgpu_bo_kmap fails. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 64baa31..87858f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2619,9 +2619,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, goto error_free_root; r = amdgpu_bo_kmap(vm->root.base.bo, NULL); + amdgpu_bo_unreserve(vm->root.base.bo); if (r) goto error_free_root; - amdgpu_bo_unreserve(vm->root.base.bo); } return 0; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/8] drm/amdgpu: Add prescreening stage in IH processing
To filter out high-frequency interrupts that can be safely ignored.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 ++
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 14 ++
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 14 ++
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 14 ++
drivers/gpu/drm/amd/amdgpu/si_ih.c | 14 ++
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 14 ++
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 14 ++
8 files changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c2ff78c..7f17bf5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -336,6 +336,7 @@ struct amdgpu_gart_funcs {
struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
u32 (*get_wptr)(struct amdgpu_device *adev);
+ bool (*prescreen_iv)(struct amdgpu_device *adev);
void (*decode_iv)(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry);
void (*set_rptr)(struct amdgpu_device *adev);
@@ -1761,6 +1762,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
+#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev),
(iv))
#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
#define amdgpu_display_vblank_get_counter(adev, crtc)
(adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 3ab4c65..c834a40 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -169,6 +169,12 @@ int amdgpu_ih_process(struct amdgpu_device *adev)
while (adev->irq.ih.rptr != wptr) {
u32 ring_index = adev->irq.ih.rptr >> 2;
+ /* Prescreening of high-frequency interrupts */
+ if (!amdgpu_ih_prescreen_iv(adev)) {
+ adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
+ continue;
+ }
+
/* Before dispatching irq to IP blocks, send it to amdkfd */
amdgpu_amdkfd_interrupt(adev,
(const void *) &adev->irq.ih.ring[ring_index]);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index b891843..07d3d89 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -228,6 +228,19 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
* [127:96] - reserved
*/
+/**
+ * cik_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool cik_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ /* Process all interrupts */
+ return true;
+}
+
/**
* cik_ih_decode_iv - decode an interrupt vector
*
@@ -433,6 +446,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
static const struct amdgpu_ih_funcs cik_ih_funcs = {
.get_wptr = cik_ih_get_wptr,
+ .prescreen_iv = cik_ih_prescreen_iv,
.decode_iv = cik_ih_decode_iv,
.set_rptr = cik_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 0c1209c..b6cdf4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -208,6 +208,19 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
}
/**
+ * cz_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool cz_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ /* Process all interrupts */
+ return true;
+}
+
+/**
* cz_ih_decode_iv - decode an interrupt vector
*
* @adev: amdgpu_device pointer
@@ -414,6 +427,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
static const struct amdgpu_ih_funcs cz_ih_funcs = {
.get_wptr = cz_ih_get_wptr,
+ .prescreen_iv = cz_ih_prescreen_iv,
.decode_iv = cz_ih_decode_iv,
.set_rptr = cz_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 7a0ea27..65ed6d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -208,6 +208,19 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
}
/**
+ * iceland_ih_prescreen_iv - prescreen an interrupt vect
[PATCH 3/8] drm/radeon: Add PASID manager for KFD
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/radeon/radeon_kfd.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c
b/drivers/gpu/drm/radeon/radeon_kfd.c
index f6578c9..a2ac8ac 100644
--- a/drivers/gpu/drm/radeon/radeon_kfd.c
+++ b/drivers/gpu/drm/radeon/radeon_kfd.c
@@ -58,6 +58,10 @@ static uint64_t get_vmem_size(struct kgd_dev *kgd);
static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
+
+static int alloc_pasid(unsigned int bits);
+static void free_pasid(unsigned int pasid);
+
static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
/*
@@ -112,6 +116,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
.get_vmem_size = get_vmem_size,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
+ .alloc_pasid = alloc_pasid,
+ .free_pasid = free_pasid,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
.init_pipeline = kgd_init_pipeline,
@@ -341,6 +347,31 @@ static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev
*kgd)
return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
}
+/*
+ * PASID manager
+ */
+static DEFINE_IDA(pasid_ida);
+
+int alloc_pasid(unsigned int bits)
+{
+ int pasid = -EINVAL;
+
+ for (bits = min(bits, 31U); bits > 0; bits--) {
+ pasid = ida_simple_get(&pasid_ida,
+ 1U << (bits - 1), 1U << bits,
+ GFP_KERNEL);
+ if (pasid != -ENOSPC)
+ break;
+ }
+
+ return pasid;
+}
+
+void free_pasid(unsigned int pasid)
+{
+ ida_simple_remove(&pasid_ida, pasid);
+}
+
static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
{
return (struct radeon_device *)kgd;
--
2.7.4
___
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[PATCH 8/8] drm/amdgpu: Track pending retry faults in IH and VM (v2)
IH tracks pending retry faults in a hash table for fast lookup in
interrupt context. Each VM has a short FIFO of pending VM faults for
processing in a bottom half.
The IH prescreening stage adds retry faults and filters out repeated
retry interrupts to minimize the impact of interrupt storms.
It's the VM's responsibility remove pending faults once they are
handled. For now this is only done when the VM is destroyed.
v2:
- Made the hash table smaller and the FIFO longer. I never want the
FIFO to fill up, because that would make prescreen take longer.
128 pending page faults should be enough to keep migrations busy.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/Kconfig| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 76 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 12 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 7 +++
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 78 +-
6 files changed, 180 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 1989c27..7fb8492 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -184,6 +184,7 @@ config DRM_AMDGPU
select BACKLIGHT_CLASS_DEVICE
select BACKLIGHT_LCD_SUPPORT
select INTERVAL_TREE
+ select CHASH
help
Choose this option if you have a recent AMD Radeon graphics card.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index c834a40..f5f27e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -196,3 +196,79 @@ int amdgpu_ih_process(struct amdgpu_device *adev)
return IRQ_HANDLED;
}
+
+/**
+ * amdgpu_ih_add_fault - Add a page fault record
+ *
+ * @adev: amdgpu device pointer
+ * @key: 64-bit encoding of PASID and address
+ *
+ * This should be called when a retry page fault interrupt is
+ * received. If this is a new page fault, it will be added to a hash
+ * table. The return value indicates whether this is a new fault, or
+ * a fault that was already known and is already being handled.
+ *
+ * If there are too many pending page faults, this will fail. Retry
+ * interrupts should be ignored in this case until there is enough
+ * free space.
+ *
+ * Returns 0 if the fault was added, 1 if the fault was already known,
+ * -ENOSPC if there are too many pending faults.
+ */
+int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key)
+{
+ unsigned long flags;
+ int r = -ENOSPC;
+
+ if (WARN_ON_ONCE(!adev->irq.ih.faults))
+ /* Should be allocated in _ih_sw_init on GPUs that
+* support retry faults and require retry filtering.
+*/
+ return r;
+
+ spin_lock_irqsave(&adev->irq.ih.faults->lock, flags);
+
+ /* Only let the hash table fill up to 50% for best performance */
+ if (adev->irq.ih.faults->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1)))
+ goto unlock_out;
+
+ r = chash_table_copy_in(&adev->irq.ih.faults->hash, key, NULL);
+ if (!r)
+ adev->irq.ih.faults->count++;
+
+ /* chash_table_copy_in should never fail unless we're losing count */
+ WARN_ON_ONCE(r < 0);
+
+unlock_out:
+ spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags);
+ return r;
+}
+
+/**
+ * amdgpu_ih_clear_fault - Remove a page fault record
+ *
+ * @adev: amdgpu device pointer
+ * @key: 64-bit encoding of PASID and address
+ *
+ * This should be called when a page fault has been handled. Any
+ * future interrupt with this key will be processed as a new
+ * page fault.
+ */
+void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key)
+{
+ unsigned long flags;
+ int r;
+
+ if (!adev->irq.ih.faults)
+ return;
+
+ spin_lock_irqsave(&adev->irq.ih.faults->lock, flags);
+
+ r = chash_table_remove(&adev->irq.ih.faults->hash, key, NULL);
+ if (!WARN_ON_ONCE(r < 0)) {
+ adev->irq.ih.faults->count--;
+ WARN_ON_ONCE(adev->irq.ih.faults->count < 0);
+ }
+
+ spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 3de8e74..ada89358 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -24,6 +24,8 @@
#ifndef __AMDGPU_IH_H__
#define __AMDGPU_IH_H__
+#include
+
struct amdgpu_device;
/*
* vega10+ IH clients
@@ -69,6 +71,13 @@ enum amdgpu_ih_clientid
#define AMDGPU_IH_CLIENTID_LEGACY 0
+#define AMDGPU_PAGEFAULT_HASH_BITS 8
+struct amdgpu_retryfault_hashtable {
+ DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
+ spinlock_t lock;
+ int count;
+};
+
/*
* R6xx+ IH ring
*/
@@ -87,6 +96,7 @@ struct amdgpu_ih_ring
[PATCH 0/8] Retry page fault handling for Vega10
Rebased on adeucher/amd-staging-4.13 and tested on Vega10 (graphics) and Kaveri (KFD). Meaningful graphics tests with retry faults enabled will only be possible after PASID support is added to amdgpu_cs. The chash table was moved to drivers/gpu/drm/amd/lib for now but is ready to move to lib if needed. I have not got any feedback on LKLM and I don't want that to hold up the patch series. TODO: * Finish upstreaming KFD * Allocate PASIDs for graphics contexts * Setup VMID-PASID mapping during graphics command submission * Confirm that graphics page faults have the correct PASID in the IV Felix Kuehling (8): drm/amdgpu: Fix error handling in amdgpu_vm_init drm/amdgpu: Add PASID management drm/radeon: Add PASID manager for KFD drm/amdkfd: Separate doorbell allocation from PASID drm/amdkfd: Use PASID manager from KGD drm/amdgpu: Add prescreening stage in IH processing drm/amd: Closed hash table with low overhead drm/amdgpu: Track pending retry faults in IH and VM (v2) drivers/gpu/drm/Kconfig | 3 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c| 82 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h| 12 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 84 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 21 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 14 + drivers/gpu/drm/amd/amdgpu/cz_ih.c| 14 + drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 14 + drivers/gpu/drm/amd/amdgpu/si_ih.c| 14 + drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 14 + drivers/gpu/drm/amd/amdgpu/vega10_ih.c| 90 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 - drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 50 +- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 6 - drivers/gpu/drm/amd/amdkfd/kfd_pasid.c| 90 ++-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 10 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 + drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 6 + drivers/gpu/drm/amd/include/linux/chash.h | 358 + drivers/gpu/drm/amd/lib/Kconfig | 27 + drivers/gpu/drm/amd/lib/Makefile | 11 + drivers/gpu/drm/amd/lib/chash.c | 622 ++ drivers/gpu/drm/radeon/radeon_kfd.c | 31 ++ 28 files changed, 1504 insertions(+), 91 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/linux/chash.h create mode 100644 drivers/gpu/drm/amd/lib/Kconfig create mode 100644 drivers/gpu/drm/amd/lib/Makefile create mode 100644 drivers/gpu/drm/amd/lib/chash.c -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/8] drm/amdgpu: Add PASID management
Allows assigning a PASID to a VM for identifying VMs involved in page
faults. The global PASID manager is also exported in the KFD
interface so that AMDGPU and KFD can share the PASID space.
PASIDs of different sizes can be requested. On APUs, the PASID size
is deterined by the capabilities of the IOMMU. So KFD must be able
to allocate PASIDs in a smaller range.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 75 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 14 -
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 6 ++
6 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index b9dbbf9..dc7e25c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -169,6 +169,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
.get_vmem_size = get_vmem_size,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
+ .alloc_pasid = amdgpu_vm_alloc_pasid,
+ .free_pasid = amdgpu_vm_free_pasid,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
.init_pipeline = kgd_init_pipeline,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 309f241..c678c69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -128,6 +128,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
.get_vmem_size = get_vmem_size,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
+ .alloc_pasid = amdgpu_vm_alloc_pasid,
+ .free_pasid = amdgpu_vm_free_pasid,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
.init_pipeline = kgd_init_pipeline,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d31777b..7045eec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -825,7 +825,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
}
r = amdgpu_vm_init(adev, &fpriv->vm,
- AMDGPU_VM_CONTEXT_GFX);
+ AMDGPU_VM_CONTEXT_GFX, 0);
if (r) {
kfree(fpriv);
goto out_suspend;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 87858f6..bdb9fe8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -27,12 +27,59 @@
*/
#include
#include
+#include
#include
#include
#include "amdgpu.h"
#include "amdgpu_trace.h"
/*
+ * PASID manager
+ *
+ * PASIDs are global address space identifiers that can be shared
+ * between the GPU, an IOMMU and the driver. VMs on different devices
+ * may use the same PASID if they share the same address
+ * space. Therefore PASIDs are allocated using a global IDA. VMs are
+ * looked up from the PASID per amdgpu_device.
+ */
+static DEFINE_IDA(amdgpu_vm_pasid_ida);
+
+/**
+ * amdgpu_vm_alloc_pasid - Allocate a PASID
+ * @bits: Maximum width of the PASID in bits, must be at least 1
+ *
+ * Allocates a PASID of the given width while keeping smaller PASIDs
+ * available if possible.
+ *
+ * Returns a positive integer on success. Returns %-EINVAL if bits==0.
+ * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
+ * memory allocation failure.
+ */
+int amdgpu_vm_alloc_pasid(unsigned int bits)
+{
+ int pasid = -EINVAL;
+
+ for (bits = min(bits, 31U); bits > 0; bits--) {
+ pasid = ida_simple_get(&amdgpu_vm_pasid_ida,
+ 1U << (bits - 1), 1U << bits,
+ GFP_KERNEL);
+ if (pasid != -ENOSPC)
+ break;
+ }
+
+ return pasid;
+}
+
+/**
+ * amdgpu_vm_free_pasid - Free a PASID
+ * @pasid: PASID to free
+ */
+void amdgpu_vm_free_pasid(unsigned int pasid)
+{
+ ida_simple_remove(&amdgpu_vm_pasid_ida, pasid);
+}
+
+/*
* GPUVM
* GPUVM is similar to the legacy gart on older asics, however
* rather than there being a single global gart table
@@ -2543,7 +2590,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev,
uint64_t vm_size, uint32_
* Init @vm fields.
*/
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- int vm_context)
+
[PATCH 7/8] drm/amd: Closed hash table with low overhead
This adds a statically sized closed hash table implementation with
low memory and CPU overhead. The API is inspired by kfifo.
Storing, retrieving and deleting data does not involve any dynamic
memory management, which makes it ideal for use in interrupt context.
Static memory usage per entry comprises a 32 or 64 bit hash key, two
bits for occupancy tracking and the value size stored in the table.
No list heads or pointers are needed. Therefore this data structure
should be quite cache-friendly, too.
It uses linear probing and lazy deletion. During lookups free space
is reclaimed and entries relocated to speed up future lookups.
Signed-off-by: Felix Kuehling
Acked-by: Christian König
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/amd/include/linux/chash.h | 358 +
drivers/gpu/drm/amd/lib/Kconfig | 27 ++
drivers/gpu/drm/amd/lib/Makefile | 11 +
drivers/gpu/drm/amd/lib/chash.c | 622 ++
6 files changed, 1021 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/linux/chash.h
create mode 100644 drivers/gpu/drm/amd/lib/Kconfig
create mode 100644 drivers/gpu/drm/amd/lib/Makefile
create mode 100644 drivers/gpu/drm/amd/lib/chash.c
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 83cb2a8..1989c27 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -191,6 +191,8 @@ config DRM_AMDGPU
source "drivers/gpu/drm/amd/amdgpu/Kconfig"
+source "drivers/gpu/drm/amd/lib/Kconfig"
+
source "drivers/gpu/drm/nouveau/Kconfig"
source "drivers/gpu/drm/i915/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 24a066e..74683b7 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_DRM_ARM) += arm/
obj-$(CONFIG_DRM_TTM) += ttm/
obj-$(CONFIG_DRM_TDFX) += tdfx/
obj-$(CONFIG_DRM_R128) += r128/
+obj-y += amd/lib/
obj-$(CONFIG_HSA_AMD) += amd/amdkfd/
obj-$(CONFIG_DRM_RADEON)+= radeon/
obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
diff --git a/drivers/gpu/drm/amd/include/linux/chash.h
b/drivers/gpu/drm/amd/include/linux/chash.h
new file mode 100644
index 000..c89b92b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/linux/chash.h
@@ -0,0 +1,358 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _LINUX_CHASH_H
+#define _LINUX_CHASH_H
+
+#include
+#include
+#include
+#include
+
+struct __chash_table {
+ u8 bits;
+ u8 key_size;
+ unsigned int value_size;
+ u32 size_mask;
+ unsigned long *occup_bitmap, *valid_bitmap;
+ union {
+ u32 *keys32;
+ u64 *keys64;
+ };
+ u8 *values;
+
+#ifdef CONFIG_CHASH_STATS
+ u64 hits, hits_steps, hits_time_ns;
+ u64 miss, miss_steps, miss_time_ns;
+ u64 relocs, reloc_dist;
+#endif
+};
+
+#define __CHASH_BITMAP_SIZE(bits) \
+ (((1 << (bits)) + BITS_PER_LONG - 1) / BITS_PER_LONG)
+#define __CHASH_ARRAY_SIZE(bits, size) \
+ size) << (bits)) + sizeof(long) - 1) / sizeof(long))
+
+#define __CHASH_DATA_SIZE(bits, key_size, value_size) \
+ (__CHASH_BITMAP_SIZE(bits) * 2 +\
+__CHASH_ARRAY_SIZE(bits, key_size) + \
+__CHASH_ARRAY_SIZE(bits, value_size))
+
+#define STRUCT_CHASH_TABLE(bits, key_size, value_size) \
+ struct {\
+ struct __chash_table table; \
+ unsigned long data \
+ [__CHASH_DATA_SIZE(bits, key_size, value_size)];\
+ }
+
+/**
+ * struct chash_table - Dynamically allocated closed hash table
+ *
+ * Use th
Re: [PATCH v2] drm/amd/display: Disable pre-Vega ASICs by default
Add Fiji to the help text? Regards //Ernst 2017-09-12 22:46 GMT+02:00 Harry Wentland : > v2: Clarify help text for pre-vega config > > Signed-off-by: Harry Wentland > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ > drivers/gpu/drm/amd/display/Kconfig| 9 + > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 34671790ce80..8c496a57788f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1995,7 +1995,9 @@ bool amdgpu_device_asic_has_dc_support(enum > amd_asic_type asic_type) > case CHIP_TONGA: > case CHIP_FIJI: > case CHIP_VEGA10: > +#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) > return amdgpu_dc != 0; > +#endif > case CHIP_KABINI: > case CHIP_MULLINS: > return amdgpu_dc > 0; > diff --git a/drivers/gpu/drm/amd/display/Kconfig > b/drivers/gpu/drm/amd/display/Kconfig > index e91b6e57cf03..239a477310af 100644 > --- a/drivers/gpu/drm/amd/display/Kconfig > +++ b/drivers/gpu/drm/amd/display/Kconfig > @@ -3,11 +3,20 @@ menu "Display Engine Configuration" > > config DRM_AMD_DC > bool "AMD DC - Enable new display engine > + default y > help > Choose this option if you want to use the new display engine > support for AMDGPU. This adds required support for Vega and > Raven ASICs. > > +config DRM_AMD_DC_PRE_VEGA > + bool "DC support for Polaris and older ASICs" > + default n > + help > + Choose this option to enable the new DC support for older asics > + by default. This includes Polaris, Carrizo, Tonga, Bonaire, > + and Hawaii. > + > config DRM_AMD_DC_DCN1_0 > bool "DCN 1.0 Raven family" > depends on DRM_AMD_DC && X86 > -- > 2.11.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amd/display: Disable pre-Vega ASICs by default
On Tue, Sep 12, 2017 at 8:30 PM, Ernst Sjöstrand wrote: > Add Fiji to the help text? Maybe just say DCE8, 10, 11. Alex > > Regards > //Ernst > > 2017-09-12 22:46 GMT+02:00 Harry Wentland : >> v2: Clarify help text for pre-vega config >> >> Signed-off-by: Harry Wentland >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ >> drivers/gpu/drm/amd/display/Kconfig| 9 + >> 2 files changed, 11 insertions(+) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> index 34671790ce80..8c496a57788f 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> @@ -1995,7 +1995,9 @@ bool amdgpu_device_asic_has_dc_support(enum >> amd_asic_type asic_type) >> case CHIP_TONGA: >> case CHIP_FIJI: >> case CHIP_VEGA10: >> +#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) >> return amdgpu_dc != 0; >> +#endif >> case CHIP_KABINI: >> case CHIP_MULLINS: >> return amdgpu_dc > 0; >> diff --git a/drivers/gpu/drm/amd/display/Kconfig >> b/drivers/gpu/drm/amd/display/Kconfig >> index e91b6e57cf03..239a477310af 100644 >> --- a/drivers/gpu/drm/amd/display/Kconfig >> +++ b/drivers/gpu/drm/amd/display/Kconfig >> @@ -3,11 +3,20 @@ menu "Display Engine Configuration" >> >> config DRM_AMD_DC >> bool "AMD DC - Enable new display engine >> + default y >> help >> Choose this option if you want to use the new display engine >> support for AMDGPU. This adds required support for Vega and >> Raven ASICs. >> >> +config DRM_AMD_DC_PRE_VEGA >> + bool "DC support for Polaris and older ASICs" >> + default n >> + help >> + Choose this option to enable the new DC support for older asics >> + by default. This includes Polaris, Carrizo, Tonga, Bonaire, >> + and Hawaii. >> + >> config DRM_AMD_DC_DCN1_0 >> bool "DCN 1.0 Raven family" >> depends on DRM_AMD_DC && X86 >> -- >> 2.11.0 >> >> ___ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/5] ***[WIP] introduce syncfile as fence reuturn ***
On 2017年09月12日 19:00, Christian König wrote: NAK for the CS part (but I think that was just as prove of concept anyway). Dave's sync object implementation is already done for this, the problem is that isn't merged yet into amd-staging-4.12 (but should be in 4-13). Yeah, I already realized it before, if only vm part, I agree syncobj can satisfy the synchronization between SDMA and other engine. But from your old dependency perspective, we also should cover wait_ioctl and wait_any/all_ioctl, which should also can wait fence from syncfile, so it makes sense that cs_ioctl and va_ioctl return syncfile fd to UMD. Compared with only retuning fence seq number, UMD can be convenience to pass fd to any where it needs to sync and as dependency or to semaphore, and they don't need to construct ip_type/ip_instance/ctx_id/ring any more, even the caching fences in ctx becomes no meanless if don't consider compatibility. Regards, David Zhou The VM part looks similar to what I had in mind, but we should base this on Dave's sync_obj stuff as well. Regards, Christian. Am 12.09.2017 um 12:23 schrieb Chunming Zhou: *** BLURB HERE *** Chunming Zhou (5): drm/amdgpu: introduce sync file for CS returning fence drm/amdgpu: add syncfile chunk support drm/amdgpu: add syncfile support to wait ioctl drm/amdgpu: add syncfile fence support to wait_any/all ioctl drm/amdgpu: expand mapping ioctl to return fence to UMD by using syncfile drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 90 - drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 24 +++-- include/uapi/drm/amdgpu_drm.h | 13 - 3 files changed, 96 insertions(+), 31 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: improve PRT syncing
Could you stop the clean for syncing? and wait we turn back performance
first?
Since you merge too kinds of fence to vm->last_update, we will be
difficult to optimize which fence can remove.
Regards,
David Zhou
On 2017年09月12日 20:06, Christian König wrote:
From: Christian König
Just clean that up a bit more.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b59749d..db5dbd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -760,11 +760,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser
*p)
if (r)
return r;
- r = amdgpu_sync_fence(adev, &p->job->sync,
- fpriv->prt_va->last_pt_update);
- if (r)
- return r;
-
if (amdgpu_sriov_vf(adev)) {
struct dma_fence *f;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6b95ba6..2f577da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1768,7 +1768,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
else
flags = 0x0;
- if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
+ if (clear || !bo || bo->tbo.resv == vm->root.base.bo->tbo.resv)
last_update = &vm->last_update;
else
last_update = &bo_va->last_pt_update;
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH xf86-video-amdgpu] Clarify when TearFree is automatically enabled.
--- man/amdgpu.man | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/man/amdgpu.man b/man/amdgpu.man index c38defe..0d9dd93 100644 --- a/man/amdgpu.man +++ b/man/amdgpu.man @@ -80,8 +80,8 @@ separate scanout buffers need to be allocated for each CRTC with TearFree on. If this option is set, the default value of the property is 'on' or 'off' accordingly. If this option isn't set, the default value of the property is .B auto, -which means that TearFree is on for outputs with rotation or other RandR -transforms, and for RandR 1.4 slave outputs, otherwise off. +which means that TearFree is on for rotated outputs, outputs with RandR +transforms applied and for RandR 1.4 slave outputs, otherwise off. .TP .BI "Option \*qAccelMethod\*q \*q" string \*q Setting this option to -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 4/5] drm/amdgpu: cleanup amdgpu_bo_pin_restricted
On 2017年09月12日 23:59, Deucher, Alexander wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Christian König
Sent: Tuesday, September 12, 2017 5:09 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 4/5] drm/amdgpu: cleanup amdgpu_bo_pin_restricted
From: Christian König
Nobody is using the min/max interface any more.
Signed-off-by: Christian König
I'm not sure it's a good idea to get rid of this. I can see a need to reserve
memory at specific offsets in memory. Specifically I think SR-IOV will be
placing structures in memory to communicate configuration details from the host
to the guest. Also, we should be reserving the vbios scratch area, but we
don't currently.
Yes, if our ISP ip is enabled, this reserve memory is must.
David Zhou
Alex
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 39 +--
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 ---
2 files changed, 6 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 726a662..8a8add3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -629,20 +629,15 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo)
*bo = NULL;
}
-int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
-u64 min_offset, u64 max_offset,
-u64 *gpu_addr)
+int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ unsigned lpfn;
int r, i;
- unsigned fpfn, lpfn;
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
return -EPERM;
- if (WARN_ON_ONCE(min_offset > max_offset))
- return -EINVAL;
-
/* A shared bo cannot be migrated to VRAM */
if (bo->prime_shared_count && (domain ==
AMDGPU_GEM_DOMAIN_VRAM))
return -EINVAL;
@@ -657,12 +652,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo
*bo, u32 domain,
if (gpu_addr)
*gpu_addr = amdgpu_bo_gpu_offset(bo);
- if (max_offset != 0) {
- u64 domain_start = bo->tbo.bdev-
man[mem_type].gpu_offset;
- WARN_ON_ONCE(max_offset <
-(amdgpu_bo_gpu_offset(bo) -
domain_start));
- }
-
return 0;
}
@@ -671,23 +660,12 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo
*bo, u32 domain,
for (i = 0; i < bo->placement.num_placement; i++) {
/* force to pin into visible video ram */
if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
- !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
&&
- (!max_offset || max_offset >
-adev->mc.visible_vram_size)) {
- if (WARN_ON_ONCE(min_offset >
-adev->mc.visible_vram_size))
- return -EINVAL;
- fpfn = min_offset >> PAGE_SHIFT;
+ !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
{
lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
- } else {
- fpfn = min_offset >> PAGE_SHIFT;
- lpfn = max_offset >> PAGE_SHIFT;
+ if (!bo->placements[i].lpfn ||
+ (lpfn && lpfn < bo->placements[i].lpfn))
+ bo->placements[i].lpfn = lpfn;
}
- if (fpfn > bo->placements[i].fpfn)
- bo->placements[i].fpfn = fpfn;
- if (!bo->placements[i].lpfn ||
- (lpfn && lpfn < bo->placements[i].lpfn))
- bo->placements[i].lpfn = lpfn;
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
}
@@ -718,11 +696,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo
*bo, u32 domain,
return r;
}
-int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
-{
- return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
-}
-
int amdgpu_bo_unpin(struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 39b6bf6..4b2c042 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -211,9 +211,6 @@ void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
void amdgpu_bo_unref(struct amdgpu_bo **bo);
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
-int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
-u64 min_offset, u64
[pull] amdgpu and ttm drm-next-4.14
Hi Dave, A few fixes for 4.14. Nothing too major. The following changes since commit 7c0059dd832cc686bf0febefdcf8295cdd93007f: Merge branch 'linux-4.14' of git://github.com/skeggsb/linux into drm-next (2017-08-23 05:32:26 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-4.14 for you to fetch changes up to 3d138c14c4174a2c80874a96935c87eee7c82ecf: drm/amdgpu: revert "fix deadlock of reservation between cs and gpu reset v2" (2017-09-12 22:16:31 -0400) Alex Deucher (5): drm/amdgpu/gfx8: fix spelling typo in mqd allocation drm/amdgpu: add automatic per asic settings for gart_size drm/amdgpu: refine default gart size drm/amdgpu: move default gart size setting into gmc modules drm/amdgpu: set sched_hw_submission higher for KIQ (v3) Christian König (6): drm/amdgpu: fix and cleanup shadow handling drm/amdgpu: discard commands of killed processes drm/amdgpu: remove the GART copy hack drm/amdgpu: fix amdgpu_ttm_bind drm/amdgpu: inline amdgpu_ttm_do_bind again drm/amdgpu: revert "fix deadlock of reservation between cs and gpu reset v2" Christophe JAILLET (1): drm/amdgpu: check memory allocation failure Colin Ian King (1): drm/amdgpu: remove duplicate return statement Emily Deng (1): drm/amdgpu/virtual_dce: Virtual display doesn't support disable vblank immediately Evan Quan (2): drm/amd/powerplay: unhalt mec after loading drm/amd/powerplay: ACG frequency added in PPTable Felix Kuehling (1): drm/amdgpu: Fix huge page updates with CPU Monk Liu (2): drm/ttm: fix missing inc bo_count drm/ttm:fix wrong decoding of bo_count Roger He (1): drm/amd/amdgpu: fix BANK_SELECT on Vega10 (v2) drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 12 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c| 14 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 46 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 16 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 76 -- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h| 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 46 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 ++-- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 19 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 22 ++- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 21 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16 - drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 5 +- drivers/gpu/drm/amd/include/vi_structs.h | 4 +- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 11 +++- drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 6 +- drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 3 +- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 23 +-- drivers/gpu/drm/ttm/ttm_bo.c | 4 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 1 + 28 files changed, 236 insertions(+), 160 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/3] drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_file
Hi Marek,
You're doing same things with me, see my "introduce syncfile as fence
reuturn" patch set, which makes things more simple, we just need to
directly return syncfile fd to UMD when CS, then the fence UMD get will
be always syncfile fd, UMD don't need to construct
ip_type/ip_instance/ctx_id/ring any more, which also can pass to
dependency and syncobj as well.
Regards,
David Zhou
On 2017年09月13日 04:42, Marek Olšák wrote:
From: Marek Olšák
for being able to convert an amdgpu fence into one of the handles.
Mesa will use this.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 61 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
include/uapi/drm/amdgpu_drm.h | 16 +
5 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b5c8b90..c15fa93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1308,6 +1308,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
*data,
int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file
*filp);
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file
*filp);
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 7cb8a59..6dd719c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -25,6 +25,7 @@
*Jerome Glisse
*/
#include
+#include
#include
#include
#include
@@ -1311,6 +1312,66 @@ static struct dma_fence *amdgpu_cs_get_fence(struct
amdgpu_device *adev,
return fence;
}
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ struct amdgpu_device *adev = dev->dev_private;
+ struct amdgpu_fpriv *fpriv = filp->driver_priv;
+ union drm_amdgpu_fence_to_handle *info = data;
+ struct dma_fence *fence;
+ struct drm_syncobj *syncobj;
+ struct sync_file *sync_file;
+ int fd, r;
+
+ if (amdgpu_kms_vram_lost(adev, fpriv))
+ return -ENODEV;
+
+ fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
+ if (IS_ERR(fence))
+ return PTR_ERR(fence);
+
+ switch (info->in.what) {
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
+ r = drm_syncobj_create(&syncobj, 0, fence);
+ dma_fence_put(fence);
+ if (r)
+ return r;
+ r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
+ drm_syncobj_put(syncobj);
+ return r;
+
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
+ r = drm_syncobj_create(&syncobj, 0, fence);
+ dma_fence_put(fence);
+ if (r)
+ return r;
+ r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
+ drm_syncobj_put(syncobj);
+ return r;
+
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
+ fd = get_unused_fd_flags(O_CLOEXEC);
+ if (fd < 0) {
+ dma_fence_put(fence);
+ return fd;
+ }
+
+ sync_file = sync_file_create(fence);
+ dma_fence_put(fence);
+ if (!sync_file) {
+ put_unused_fd(fd);
+ return -ENOMEM;
+ }
+
+ fd_install(fd, sync_file->file);
+ info->out.handle = fd;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
/**
* amdgpu_cs_wait_all_fence - wait on all fences to signal
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d01aca6..1e38411 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -70,9 +70,10 @@
* - 3.18.0 - Export gpu always on cu bitmap
* - 3.19.0 - Add support for UVD MJPEG decode
* - 3.20.0 - Add support for local BOs
+ * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
*/
#define KMS_DRIVER_MAJOR 3
-#define KMS_DRIVER_MINOR 20
+#define KMS_DRIVER_MINOR 21
#define KMS_DRIVER_PATCHLEVEL 0
int amdgpu_vram_limit = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d3177
Re: [PATCH 3/3] drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_file
Hi guys,
Mareks IOCTL proposal looks really good to me.
Please note that we already have sync_obj support for the CS IOCTL in
the 4.13 branch and this work is based on top of that.
UMD don't need to construct ip_type/ip_instance/ctx_id/ring
Well the UMD does want to construct ip_type/ip_instance/ctx_id/ring and
use for the simple reason that it allows more flexibility than
sync_obj/sync_file.
Thinking more about this I'm pretty sure we want to do something similar
for VM map/unmap operations as well.
Regards,
Christian.
Am 13.09.2017 um 05:03 schrieb zhoucm1:
Hi Marek,
You're doing same things with me, see my "introduce syncfile as fence
reuturn" patch set, which makes things more simple, we just need to
directly return syncfile fd to UMD when CS, then the fence UMD get
will be always syncfile fd, UMD don't need to construct
ip_type/ip_instance/ctx_id/ring any more, which also can pass to
dependency and syncobj as well.
Regards,
David Zhou
On 2017年09月13日 04:42, Marek Olšák wrote:
From: Marek Olšák
for being able to convert an amdgpu fence into one of the handles.
Mesa will use this.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 61
+
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
include/uapi/drm/amdgpu_drm.h | 16 +
5 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b5c8b90..c15fa93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1308,6 +1308,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
void *data,
int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct
drm_file *filp);
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+struct drm_file *filp);
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct
drm_file *filp);
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 7cb8a59..6dd719c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -25,6 +25,7 @@
*Jerome Glisse
*/
#include
+#include
#include
#include
#include
@@ -1311,6 +1312,66 @@ static struct dma_fence
*amdgpu_cs_get_fence(struct amdgpu_device *adev,
return fence;
}
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void
*data,
+struct drm_file *filp)
+{
+struct amdgpu_device *adev = dev->dev_private;
+struct amdgpu_fpriv *fpriv = filp->driver_priv;
+union drm_amdgpu_fence_to_handle *info = data;
+struct dma_fence *fence;
+struct drm_syncobj *syncobj;
+struct sync_file *sync_file;
+int fd, r;
+
+if (amdgpu_kms_vram_lost(adev, fpriv))
+return -ENODEV;
+
+fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
+if (IS_ERR(fence))
+return PTR_ERR(fence);
+
+switch (info->in.what) {
+case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
+r = drm_syncobj_create(&syncobj, 0, fence);
+dma_fence_put(fence);
+if (r)
+return r;
+r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
+drm_syncobj_put(syncobj);
+return r;
+
+case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
+r = drm_syncobj_create(&syncobj, 0, fence);
+dma_fence_put(fence);
+if (r)
+return r;
+r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
+drm_syncobj_put(syncobj);
+return r;
+
+case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
+fd = get_unused_fd_flags(O_CLOEXEC);
+if (fd < 0) {
+dma_fence_put(fence);
+return fd;
+}
+
+sync_file = sync_file_create(fence);
+dma_fence_put(fence);
+if (!sync_file) {
+put_unused_fd(fd);
+return -ENOMEM;
+}
+
+fd_install(fd, sync_file->file);
+info->out.handle = fd;
+return 0;
+
+default:
+return -EINVAL;
+}
+}
+
/**
* amdgpu_cs_wait_all_fence - wait on all fences to signal
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d01aca6..1e38411 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -70,9 +70,10 @@
* - 3.18.0 - Export gpu always on cu bitmap
* - 3.19.0 - Add support for UVD MJPEG decode
* - 3.20.0 - Add support for local BOs
+ * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
*/
#define KMS_DRIVER_MAJOR3
-
