Re: [PATCH] drm/amd/amdgpu: add vega10/raven mmhub/athub golden settings

[Zhang, Jerry (Junwei)]

On 09/21/2017 10:56 AM, Evan Quan wrote:

Change-Id: I28e9ca38b68234d0325a5b8a01d135649939c0af
Signed-off-by: Evan Quan 

Reviewed-by: Junwei Zhang 


---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 23 +++
  1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 99147f5..6216993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -32,6 +32,8 @@
  #include "vega10/DC/dce_12_0_offset.h"
  #include "vega10/DC/dce_12_0_sh_mask.h"
  #include "vega10/vega10_enum.h"
+#include "vega10/MMHUB/mmhub_1_0_offset.h"
+#include "vega10/ATHUB/athub_1_0_offset.h"

  #include "soc15_common.h"

@@ -71,6 +73,18 @@ static const u32 golden_settings_vega10_hdp[] =
0xf6e, 0x0fff, 0x,
  };

+static const u32 golden_settings_mmhub_1_0_0[] =
+{
+   SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x0007, 0xfe5fe0fa,
+   SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x0030, 
0x5565
+};
+
+static const u32 golden_settings_athub_1_0_0[] =
+{
+   SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0xff00, 0x0800,
+   SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
+};
+
  static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned type,
@@ -665,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct 
amdgpu_device *adev)
  {
switch (adev->asic_type) {
case CHIP_VEGA10:
+   amdgpu_program_register_sequence(adev,
+   golden_settings_mmhub_1_0_0,
+   (const 
u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+   amdgpu_program_register_sequence(adev,
+   golden_settings_athub_1_0_0,
+   (const 
u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
case CHIP_RAVEN:
+   amdgpu_program_register_sequence(adev,
+   golden_settings_athub_1_0_0,
+   (const 
u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
default:
break;


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[PATCH] drm/amdgpu: Fix driver reloading failure

[Xiangliang . Yu]

SRIOV doesn't implement PMC capability of PCIe, so it can't update
power state by reading PMC register.

Currently, amdgpu driver doesn't disable pci device when removing
driver, the enable_cnt of pci device will not be decrease to 0.
When reloading driver, pci_enable_device will do nothing as
enable_cnt is not zero. And power state will not be updated as PMC
is not support.
So current_state of pci device is not D0 state and pci_enable_msi
return fail.

Add pci_disable_device when remmoving driver to fix the issue.

Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 5035305c..f7b3acb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -613,6 +613,8 @@ amdgpu_pci_remove(struct pci_dev *pdev)
 
drm_dev_unregister(dev);
drm_dev_unref(dev);
+   pci_disable_device(pdev);
+   pci_set_drvdata(pdev, NULL);
 }
 
 static void
-- 
2.7.4

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[PATCH] drm/amd/powerplay: refine phm_register_thermal_interrupt interface

[Rex Zhu]

currently, not all asics implement this callback function
so not return error to avoid powerplay initialize failed
in those asices

Change-Id: I492b7ab54eebcc0d84c169edc0d5876c4529c619
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index f31d2cf..623cff9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -210,10 +210,10 @@ int phm_register_thermal_interrupt(struct pp_hwmgr 
*hwmgr, const void *info)
 {
PHM_FUNC_CHECK(hwmgr);
 
-   if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
-   return -EINVAL;
+   if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL)
+   return 
hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
 
-   return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, 
info);
+   return 0;
 }
 
 /**
-- 
1.9.1

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[PATCH] drm/amd/amdgpu: add vega10/raven mmhub/athub golden settings

[Evan Quan]

Change-Id: I28e9ca38b68234d0325a5b8a01d135649939c0af
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 99147f5..6216993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -32,6 +32,8 @@
 #include "vega10/DC/dce_12_0_offset.h"
 #include "vega10/DC/dce_12_0_sh_mask.h"
 #include "vega10/vega10_enum.h"
+#include "vega10/MMHUB/mmhub_1_0_offset.h"
+#include "vega10/ATHUB/athub_1_0_offset.h"
 
 #include "soc15_common.h"
 
@@ -71,6 +73,18 @@ static const u32 golden_settings_vega10_hdp[] =
0xf6e, 0x0fff, 0x,
 };
 
+static const u32 golden_settings_mmhub_1_0_0[] =
+{
+   SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x0007, 0xfe5fe0fa,
+   SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x0030, 
0x5565
+};
+
+static const u32 golden_settings_athub_1_0_0[] =
+{
+   SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0xff00, 0x0800,
+   SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
+};
+
 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned type,
@@ -665,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct 
amdgpu_device *adev)
 {
switch (adev->asic_type) {
case CHIP_VEGA10:
+   amdgpu_program_register_sequence(adev,
+   golden_settings_mmhub_1_0_0,
+   (const 
u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+   amdgpu_program_register_sequence(adev,
+   golden_settings_athub_1_0_0,
+   (const 
u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
case CHIP_RAVEN:
+   amdgpu_program_register_sequence(adev,
+   golden_settings_athub_1_0_0,
+   (const 
u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
default:
break;
-- 
2.7.4

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[PATCH 07/10] drm/amdkfd: Reuse CHIP_* from amdgpu v2

[Felix Kuehling]

From: Yong Zhao 

There are already CHIP_* definitions under amd_shared.h file on amdgpu
side, so KFD should reuse them rather than defining new ones.

Using enum for asic type requires default cases on switch statements
to prevent compiler warnings. WARN on unsupported ASICs. It should never
get there because KFD should not be initialized on unsupported devices.

v2: Replace BUG() with WARN and error return

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c |  4 
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 18 --
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c  |  3 +++
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |  9 +++--
 4 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 87f8742..fe0f0de 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1130,6 +1130,10 @@ struct device_queue_manager 
*device_queue_manager_init(struct kfd_dev *dev)
case CHIP_KAVERI:
device_queue_manager_init_cik(>ops_asic_specific);
break;
+   default:
+   WARN(1, "Unexpected ASIC family %u",
+dev->device_info->asic_family);
+   goto out_free;
}
 
if (!dqm->ops.initialize(dqm))
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index a47ca3c..d7ed10e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -291,14 +291,20 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev 
*dev,
case CHIP_KAVERI:
kernel_queue_init_cik(>ops_asic_specific);
break;
+   default:
+   WARN(1, "Unexpected ASIC family %u",
+dev->device_info->asic_family);
+   goto out_free;
}
 
-   if (!kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE)) {
-   pr_err("Failed to init kernel queue\n");
-   kfree(kq);
-   return NULL;
-   }
-   return kq;
+   if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
+   return kq;
+
+   pr_err("Failed to init kernel queue\n");
+
+out_free:
+   kfree(kq);
+   return NULL;
 }
 
 void kernel_queue_uninit(struct kernel_queue *kq)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index b1ef136..dfd260e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -31,6 +31,9 @@ struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
return mqd_manager_init_cik(type, dev);
case CHIP_CARRIZO:
return mqd_manager_init_vi(type, dev);
+   default:
+   WARN(1, "Unexpected ASIC family %u",
+dev->device_info->asic_family);
}
 
return NULL;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 4d989b9..47eee77 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -33,6 +33,8 @@
 #include 
 #include 
 
+#include "amd_shared.h"
+
 #define KFD_SYSFS_FILE_MODE 0444
 
 #define KFD_MMAP_DOORBELL_MASK 0x8
@@ -112,11 +114,6 @@ enum cache_policy {
cache_policy_noncoherent
 };
 
-enum asic_family_type {
-   CHIP_KAVERI = 0,
-   CHIP_CARRIZO
-};
-
 struct kfd_event_interrupt_class {
bool (*interrupt_isr)(struct kfd_dev *dev,
const uint32_t *ih_ring_entry);
@@ -125,7 +122,7 @@ struct kfd_event_interrupt_class {
 };
 
 struct kfd_device_info {
-   unsigned int asic_family;
+   enum amd_asic_type asic_family;
const struct kfd_event_interrupt_class *event_interrupt_class;
unsigned int max_pasid_bits;
unsigned int max_no_of_hqd;
-- 
2.7.4

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[PATCH 00/10] KFD fixes v2

[Felix Kuehling]

Small self-contained KFD fixes that don't introduce any new
functionality or features. These may be suitable to include in
drm-fixes for 4.14.

v2:
- Rebased on gabbayo/amdkfd-next
- Addressed code review feedback
- Dropped "Set /dev/kfd permissions to 0666 by default"

Felix Kuehling (3):
  drm/amdkfd: Adjust dequeue latencies and timeouts
  drm/amdkfd: Fix incorrect destroy_mqd parameter
  drm/amdkfd: Print event limit messages only once per process

Yong Zhao (7):
  drm/amdkfd: Reorganize kfd resume code
  drm/amdkfd: Fix suspend/resume issue on Carrizo v2
  drm/amdkfd: Rectify the jiffies calculation error with milliseconds v2
  drm/amdkfd: Use VMID bitmap from KGD v2
  drm/amdkfd: Reuse CHIP_* from amdgpu v2
  drm/amdkfd: Drop _nocpsch suffix from shared functions
  drm/amdkfd: Fix kernel-queue wrapping bugs

 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c|   9 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 106 -
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |  62 +---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |   8 +-
 drivers/gpu/drm/amd/amdkfd/kfd_events.c|   5 +-
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c  |  40 +---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c   |   3 +
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c|   2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  37 ---
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   |  97 +++
 .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |   2 +-
 11 files changed, 235 insertions(+), 136 deletions(-)

-- 
2.7.4

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[PATCH 01/10] drm/amdkfd: Reorganize kfd resume code

[Felix Kuehling]

From: Yong Zhao 

The idea is to let kfd init and resume function share the same code path
as much as possible, rather than to have two copies of almost identical
code. That way improves the code readability and maintainability.

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
Reviewed-by: Oded Gabbay 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 78 +
 1 file changed, 40 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 61fff25..cc8af11 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -92,6 +92,8 @@ static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int 
buf_size,
unsigned int chunk_size);
 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
 
+static int kfd_resume(struct kfd_dev *kfd);
+
 static const struct kfd_device_info *lookup_device_info(unsigned short did)
 {
size_t i;
@@ -176,15 +178,8 @@ static bool device_iommu_pasid_init(struct kfd_dev *kfd)
pasid_limit,
kfd->doorbell_process_limit - 1);
 
-   err = amd_iommu_init_device(kfd->pdev, pasid_limit);
-   if (err < 0) {
-   dev_err(kfd_device, "error initializing iommu device\n");
-   return false;
-   }
-
if (!kfd_set_pasid_limit(pasid_limit)) {
dev_err(kfd_device, "error setting pasid limit\n");
-   amd_iommu_free_device(kfd->pdev);
return false;
}
 
@@ -280,29 +275,22 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
goto kfd_interrupt_error;
}
 
-   if (!device_iommu_pasid_init(kfd)) {
-   dev_err(kfd_device,
-   "Error initializing iommuv2 for device %x:%x\n",
-   kfd->pdev->vendor, kfd->pdev->device);
-   goto device_iommu_pasid_error;
-   }
-   amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
-   iommu_pasid_shutdown_callback);
-   amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
-
kfd->dqm = device_queue_manager_init(kfd);
if (!kfd->dqm) {
dev_err(kfd_device, "Error initializing queue manager\n");
goto device_queue_manager_error;
}
 
-   if (kfd->dqm->ops.start(kfd->dqm)) {
+   if (!device_iommu_pasid_init(kfd)) {
dev_err(kfd_device,
-   "Error starting queue manager for device %x:%x\n",
+   "Error initializing iommuv2 for device %x:%x\n",
kfd->pdev->vendor, kfd->pdev->device);
-   goto dqm_start_error;
+   goto device_iommu_pasid_error;
}
 
+   if (kfd_resume(kfd))
+   goto kfd_resume_error;
+
kfd->dbgmgr = NULL;
 
kfd->init_complete = true;
@@ -314,11 +302,10 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 
goto out;
 
-dqm_start_error:
+kfd_resume_error:
+device_iommu_pasid_error:
device_queue_manager_uninit(kfd->dqm);
 device_queue_manager_error:
-   amd_iommu_free_device(kfd->pdev);
-device_iommu_pasid_error:
kfd_interrupt_exit(kfd);
 kfd_interrupt_error:
kfd_topology_remove_device(kfd);
@@ -338,8 +325,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 {
if (kfd->init_complete) {
+   kgd2kfd_suspend(kfd);
device_queue_manager_uninit(kfd->dqm);
-   amd_iommu_free_device(kfd->pdev);
kfd_interrupt_exit(kfd);
kfd_topology_remove_device(kfd);
kfd_doorbell_fini(kfd);
@@ -362,25 +349,40 @@ void kgd2kfd_suspend(struct kfd_dev *kfd)
 
 int kgd2kfd_resume(struct kfd_dev *kfd)
 {
-   unsigned int pasid_limit;
-   int err;
+   if (!kfd->init_complete)
+   return 0;
 
-   pasid_limit = kfd_get_pasid_limit();
+   return kfd_resume(kfd);
 
-   if (kfd->init_complete) {
-   err = amd_iommu_init_device(kfd->pdev, pasid_limit);
-   if (err < 0) {
-   dev_err(kfd_device, "failed to initialize iommu\n");
-   return -ENXIO;
-   }
+}
 
-   amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
-   iommu_pasid_shutdown_callback);
-   amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
-   kfd->dqm->ops.start(kfd->dqm);
+static int kfd_resume(struct kfd_dev *kfd)
+{
+   int err = 0;
+   unsigned int pasid_limit = kfd_get_pasid_limit();
+
+   err = amd_iommu_init_device(kfd->pdev, pasid_limit);
+   if (err)
+   return -ENXIO;
+   

[PATCH 10/10] drm/amdkfd: Print event limit messages only once per process

[Felix Kuehling]

To avoid spamming the log.

Signed-off-by: Felix Kuehling 
Reviewed-by: Oded Gabbay 
---
 drivers/gpu/drm/amd/amdkfd/kfd_events.c | 5 -
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h   | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 5979158..944abfa 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -292,7 +292,10 @@ static int create_signal_event(struct file *devkfd,
struct kfd_event *ev)
 {
if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) {
-   pr_warn("Signal event wasn't created because limit was 
reached\n");
+   if (!p->signal_event_limit_reached) {
+   pr_warn("Signal event wasn't created because limit was 
reached\n");
+   p->signal_event_limit_reached = true;
+   }
return -ENOMEM;
}
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 47eee77..10c0626 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -532,6 +532,7 @@ struct kfd_process {
struct list_head signal_event_pages;
u32 next_nonsignal_event_id;
size_t signal_event_count;
+   bool signal_event_limit_reached;
 };
 
 /**
-- 
2.7.4

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[PATCH 02/10] drm/amdkfd: Fix suspend/resume issue on Carrizo v2

[Felix Kuehling]

From: Yong Zhao 

When we do suspend/resume through "sudo pm-suspend" while there is
HSA activity running, upon resume we will encounter HWS hanging, which
is caused by memory read/write failures. The root cause is that when
suspend, we neglected to unbind pasid from kfd device.

Another major change is that the bind/unbinding is changed to be
performed on a per process basis, instead of whether there are queues
in dqm.

v2:
- free IOMMU device if kfd_bind_processes_to_device fails in kfd_resume
- add comments to kfd_bind/unbind_processes_to/from_device
- minor cleanups

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
Reviewed-by: Oded Gabbay 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 23 +++--
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 13 ---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  | 15 +++-
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 97 ++
 4 files changed, 109 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index cc8af11..092db3a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -191,7 +191,7 @@ static void iommu_pasid_shutdown_callback(struct pci_dev 
*pdev, int pasid)
struct kfd_dev *dev = kfd_device_by_pci_dev(pdev);
 
if (dev)
-   kfd_unbind_process_from_device(dev, pasid);
+   kfd_process_iommu_unbind_callback(dev, pasid);
 }
 
 /*
@@ -339,12 +339,16 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd)
 
 void kgd2kfd_suspend(struct kfd_dev *kfd)
 {
-   if (kfd->init_complete) {
-   kfd->dqm->ops.stop(kfd->dqm);
-   amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL);
-   amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL);
-   amd_iommu_free_device(kfd->pdev);
-   }
+   if (!kfd->init_complete)
+   return;
+
+   kfd->dqm->ops.stop(kfd->dqm);
+
+   kfd_unbind_processes_from_device(kfd);
+
+   amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL);
+   amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL);
+   amd_iommu_free_device(kfd->pdev);
 }
 
 int kgd2kfd_resume(struct kfd_dev *kfd)
@@ -369,6 +373,10 @@ static int kfd_resume(struct kfd_dev *kfd)
amd_iommu_set_invalid_ppr_cb(kfd->pdev,
 iommu_invalid_ppr_cb);
 
+   err = kfd_bind_processes_to_device(kfd);
+   if (err)
+   goto processes_bind_error;
+
err = kfd->dqm->ops.start(kfd->dqm);
if (err) {
dev_err(kfd_device,
@@ -380,6 +388,7 @@ static int kfd_resume(struct kfd_dev *kfd)
return err;
 
 dqm_start_error:
+processes_bind_error:
amd_iommu_free_device(kfd->pdev);
 
return err;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 53a66e8..5db82b8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -670,7 +670,6 @@ static int initialize_cpsch(struct device_queue_manager 
*dqm)
 
 static int start_cpsch(struct device_queue_manager *dqm)
 {
-   struct device_process_node *node;
int retval;
 
retval = 0;
@@ -697,11 +696,6 @@ static int start_cpsch(struct device_queue_manager *dqm)
 
init_interrupts(dqm);
 
-   list_for_each_entry(node, >queues, list)
-   if (node->qpd->pqm->process && dqm->dev)
-   kfd_bind_process_to_device(dqm->dev,
-   node->qpd->pqm->process);
-
execute_queues_cpsch(dqm, true);
 
return 0;
@@ -714,15 +708,8 @@ static int start_cpsch(struct device_queue_manager *dqm)
 
 static int stop_cpsch(struct device_queue_manager *dqm)
 {
-   struct device_process_node *node;
-   struct kfd_process_device *pdd;
-
destroy_queues_cpsch(dqm, true, true);
 
-   list_for_each_entry(node, >queues, list) {
-   pdd = qpd_to_pdd(node->qpd);
-   pdd->bound = false;
-   }
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
pm_uninit(>packets);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index b397ec7..ef582cc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -435,6 +435,13 @@ struct qcm_process_device {
uint32_t sh_hidden_private_base;
 };
 
+
+enum kfd_pdd_bound {
+   PDD_UNBOUND = 0,
+   PDD_BOUND,
+   PDD_BOUND_SUSPENDED,
+};
+
 /* Data that is per-process-per device. */
 struct kfd_process_device {
/*
@@ -459,7 +466,7 @@ struct kfd_process_device {
uint64_t scratch_limit;
 
/* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */
-   bool bound;
+  

[PATCH 08/10] drm/amdkfd: Drop _nocpsch suffix from shared functions

[Felix Kuehling]

From: Yong Zhao 

Several functions in DQM are shared between cpsch and nocpsch code.
Remove the misleading _nocpsch suffix from their names.

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
Reviewed-by: Oded Gabbay 
---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 24 +++---
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index fe0f0de..471b34e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -386,7 +386,7 @@ static int update_queue(struct device_queue_manager *dqm, 
struct queue *q)
return retval;
 }
 
-static struct mqd_manager *get_mqd_manager_nocpsch(
+static struct mqd_manager *get_mqd_manager(
struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
 {
struct mqd_manager *mqd;
@@ -407,7 +407,7 @@ static struct mqd_manager *get_mqd_manager_nocpsch(
return mqd;
 }
 
-static int register_process_nocpsch(struct device_queue_manager *dqm,
+static int register_process(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
 {
struct device_process_node *n;
@@ -431,7 +431,7 @@ static int register_process_nocpsch(struct 
device_queue_manager *dqm,
return retval;
 }
 
-static int unregister_process_nocpsch(struct device_queue_manager *dqm,
+static int unregister_process(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
 {
int retval;
@@ -513,7 +513,7 @@ static int initialize_nocpsch(struct device_queue_manager 
*dqm)
return 0;
 }
 
-static void uninitialize_nocpsch(struct device_queue_manager *dqm)
+static void uninitialize(struct device_queue_manager *dqm)
 {
int i;
 
@@ -1095,10 +1095,10 @@ struct device_queue_manager 
*device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.stop = stop_cpsch;
dqm->ops.destroy_queue = destroy_queue_cpsch;
dqm->ops.update_queue = update_queue;
-   dqm->ops.get_mqd_manager = get_mqd_manager_nocpsch;
-   dqm->ops.register_process = register_process_nocpsch;
-   dqm->ops.unregister_process = unregister_process_nocpsch;
-   dqm->ops.uninitialize = uninitialize_nocpsch;
+   dqm->ops.get_mqd_manager = get_mqd_manager;
+   dqm->ops.register_process = register_process;
+   dqm->ops.unregister_process = unregister_process;
+   dqm->ops.uninitialize = uninitialize;
dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
@@ -1110,11 +1110,11 @@ struct device_queue_manager 
*device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.create_queue = create_queue_nocpsch;
dqm->ops.destroy_queue = destroy_queue_nocpsch;
dqm->ops.update_queue = update_queue;
-   dqm->ops.get_mqd_manager = get_mqd_manager_nocpsch;
-   dqm->ops.register_process = register_process_nocpsch;
-   dqm->ops.unregister_process = unregister_process_nocpsch;
+   dqm->ops.get_mqd_manager = get_mqd_manager;
+   dqm->ops.register_process = register_process;
+   dqm->ops.unregister_process = unregister_process;
dqm->ops.initialize = initialize_nocpsch;
-   dqm->ops.uninitialize = uninitialize_nocpsch;
+   dqm->ops.uninitialize = uninitialize;
dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
break;
default:
-- 
2.7.4

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[PATCH 06/10] drm/amdkfd: Use VMID bitmap from KGD v2

[Felix Kuehling]

From: Yong Zhao 

The hard-coded values related to VMID were removed in KFD, as those
values can be calculated in the KFD initialization function.

v2: remove unnecessary local variable

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
Reviewed-by: Oded Gabbay 
---
 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c|  9 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c|  5 +
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 13 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  4 
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  7 +++
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  2 +-
 6 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
index 0aa021a..7d5635f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
@@ -769,13 +769,8 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, 
struct kfd_process *p)
union GRBM_GFX_INDEX_BITS reg_gfx_index;
struct kfd_process_device *pdd;
struct dbg_wave_control_info wac_info;
-   int temp;
-   int first_vmid_to_scan = 8;
-   int last_vmid_to_scan = 15;
-
-   first_vmid_to_scan = ffs(dev->shared_resources.compute_vmid_bitmap) - 1;
-   temp = dev->shared_resources.compute_vmid_bitmap >> first_vmid_to_scan;
-   last_vmid_to_scan = first_vmid_to_scan + ffz(temp);
+   int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
+   int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
 
reg_sq_cmd.u32All = 0;
status = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 092db3a..9d23362 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -226,6 +226,11 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 
kfd->shared_resources = *gpu_resources;
 
+   kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
+   kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
+   kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
+   - kfd->vm_info.first_vmid_kfd + 1;
+
/* calculate max size of mqds needed for queues */
size = max_num_of_queues_per_device *
kfd->device_info->mqd_size_aligned;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index dd60c6e..87f8742 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -113,11 +113,11 @@ static int allocate_vmid(struct device_queue_manager *dqm,
if (dqm->vmid_bitmap == 0)
return -ENOMEM;
 
-   bit = find_first_bit((unsigned long *)>vmid_bitmap, CIK_VMID_NUM);
+   bit = find_first_bit((unsigned long *)>vmid_bitmap,
+   dqm->dev->vm_info.vmid_num_kfd);
clear_bit(bit, (unsigned long *)>vmid_bitmap);
 
-   /* Kaveri kfd vmid's starts from vmid 8 */
-   allocated_vmid = bit + KFD_VMID_START_OFFSET;
+   allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
pr_debug("vmid allocation %d\n", allocated_vmid);
qpd->vmid = allocated_vmid;
q->properties.vmid = allocated_vmid;
@@ -132,7 +132,7 @@ static void deallocate_vmid(struct device_queue_manager 
*dqm,
struct qcm_process_device *qpd,
struct queue *q)
 {
-   int bit = qpd->vmid - KFD_VMID_START_OFFSET;
+   int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
 
/* Release the vmid mapping */
set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
@@ -507,7 +507,7 @@ static int initialize_nocpsch(struct device_queue_manager 
*dqm)
dqm->allocated_queues[pipe] |= 1 << queue;
}
 
-   dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1;
+   dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
 
return 0;
@@ -613,8 +613,7 @@ static int set_sched_resources(struct device_queue_manager 
*dqm)
int i, mec;
struct scheduling_resources res;
 
-   res.vmid_mask = (1 << VMID_PER_DEVICE) - 1;
-   res.vmid_mask <<= KFD_VMID_START_OFFSET;
+   res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
 
res.queue_mask = 0;
for (i = 0; i < KGD_MAX_QUEUES; ++i) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index 99e2305..60d46ce 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ 

[PATCH 09/10] drm/amdkfd: Fix kernel-queue wrapping bugs

[Felix Kuehling]

From: Yong Zhao 

Avoid intermediate negative numbers when doing calculations with a mix
of signed and unsigned variables where implicit conversions can lead
to unexpected results.

When kernel queue buffer wraps around to 0, we need to check that rptr
won't be overwritten by the new packet.

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index d7ed10e..8b0c064 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -210,6 +210,11 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
uint32_t wptr, rptr;
unsigned int *queue_address;
 
+   /* When rptr == wptr, the buffer is empty.
+* When rptr == wptr + 1, the buffer is full.
+* It is always rptr that advances to the position of wptr, rather than
+* the opposite. So we can only use up to queue_size_dwords - 1 dwords.
+*/
rptr = *kq->rptr_kernel;
wptr = *kq->wptr_kernel;
queue_address = (unsigned int *)kq->pq_kernel_addr;
@@ -219,11 +224,10 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
pr_debug("wptr: %d\n", wptr);
pr_debug("queue_address 0x%p\n", queue_address);
 
-   available_size = (rptr - 1 - wptr + queue_size_dwords) %
+   available_size = (rptr + queue_size_dwords - 1 - wptr) %
queue_size_dwords;
 
-   if (packet_size_in_dwords >= queue_size_dwords ||
-   packet_size_in_dwords >= available_size) {
+   if (packet_size_in_dwords > available_size) {
/*
 * make sure calling functions know
 * acquire_packet_buffer() failed
@@ -233,6 +237,14 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
}
 
if (wptr + packet_size_in_dwords >= queue_size_dwords) {
+   /* make sure after rolling back to position 0, there is
+* still enough space.
+*/
+   if (packet_size_in_dwords >= rptr) {
+   *buffer_ptr = NULL;
+   return -ENOMEM;
+   }
+   /* fill nops, roll back and start at position 0 */
while (wptr > 0) {
queue_address[wptr] = kq->nop_packet;
wptr = (wptr + 1) % queue_size_dwords;
-- 
2.7.4

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[PATCH 03/10] drm/amdkfd: Rectify the jiffies calculation error with milliseconds v2

[Felix Kuehling]

From: Yong Zhao 

The timeout in milliseconds should not be regarded as jiffies. This
commit fixed that.

v2:
- use msecs_to_jiffies
- change timeout_ms parameter to unsigned int to match msecs_to_jiffies

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 +++---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 5db82b8..87961fe 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -835,12 +835,12 @@ static int create_queue_cpsch(struct device_queue_manager 
*dqm, struct queue *q,
 
 int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
unsigned int fence_value,
-   unsigned long timeout)
+   unsigned int timeout_ms)
 {
-   timeout += jiffies;
+   unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
 
while (*fence_addr != fence_value) {
-   if (time_after(jiffies, timeout)) {
+   if (time_after(jiffies, end_jiffies)) {
pr_err("qcm fence wait loop timeout expired\n");
return -ETIME;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index ef582cc..1c341b3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -669,7 +669,7 @@ struct kernel_queue *pqm_get_kernel_queue(struct 
process_queue_manager *pqm,
 
 int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
unsigned int fence_value,
-   unsigned long timeout);
+   unsigned int timeout_ms);
 
 /* Packet Manager */
 
-- 
2.7.4

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[PATCH 04/10] drm/amdkfd: Adjust dequeue latencies and timeouts

[Felix Kuehling]

Adjust latencies and timeouts for dequeueing with HWS and consolidate
them in one place. Make them longer to allow long running waves to
complete without causing a timeout. The timeout is twice as long as the
latency plus some buffer to make sure we don't detect a timeout
prematurely.

Change timeouts for dequeueing HQDs without HWS. KFD_UNMAP_LATENCY is
more consistent with what the HWS does for user queues.

Signed-off-by: Yong Zhao 
Signed-off-by: Felix Kuehling 
Reviewed-by: Oded Gabbay 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 4 +++-
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c   | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ---
 5 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 87961fe..dd60c6e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -323,7 +323,7 @@ static int destroy_queue_nocpsch(struct 
device_queue_manager *dqm,
 
retval = mqd->destroy_mqd(mqd, q->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
-   QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
+   KFD_UNMAP_LATENCY_MS,
q->pipe, q->queue);
 
if (retval)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index faf820a..99e2305 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -29,7 +29,9 @@
 #include "kfd_priv.h"
 #include "kfd_mqd_manager.h"
 
-#define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS   (500)
+#define KFD_UNMAP_LATENCY_MS   (4000)
+#define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS (2 * KFD_UNMAP_LATENCY_MS + 1000)
+
 #define CIK_VMID_NUM   (8)
 #define KFD_VMID_START_OFFSET  (8)
 #define VMID_PER_DEVICECIK_VMID_NUM
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 0649dd4..04379a6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -185,7 +185,7 @@ static void uninitialize(struct kernel_queue *kq)
kq->mqd->destroy_mqd(kq->mqd,
kq->queue->mqd,
false,
-   QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
+   KFD_UNMAP_LATENCY_MS,
kq->queue->pipe,
kq->queue->queue);
else if (kq->queue->properties.type == KFD_QUEUE_TYPE_DIQ)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 1d31260..9eda884 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -376,7 +376,7 @@ int pm_send_set_resources(struct packet_manager *pm,
packet->bitfields2.queue_type =
queue_type__mes_set_resources__hsa_interface_queue_hiq;
packet->bitfields2.vmid_mask = res->vmid_mask;
-   packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY;
+   packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
packet->bitfields7.oac_mask = res->oac_mask;
packet->bitfields8.gds_heap_base = res->gds_heap_base;
packet->bitfields8.gds_heap_size = res->gds_heap_size;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 1c341b3..7adb890 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -673,11 +673,8 @@ int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
 
 /* Packet Manager */
 
-#define KFD_HIQ_TIMEOUT (500)
-
 #define KFD_FENCE_COMPLETED (100)
 #define KFD_FENCE_INIT   (10)
-#define KFD_UNMAP_LATENCY (150)
 
 struct packet_manager {
struct device_queue_manager *dqm;
-- 
2.7.4

___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support

[Christian König]

Am 20.09.2017 um 19:47 schrieb Li, Samuel:

No that isn't correct. Pinning just notes that the BO shouldn't be moved any
more.  It doesn't wait for anything.

It does. The following is from amdgpu_gem_prime_pin(),
91  * Wait for all shared fences to complete before we switch to future
  92  * use of exclusive fence on this prime shared bo.
  93  */
  94 ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, 
false,
  95   MAX_SCHEDULE_TIMEOUT);
  96 if (unlikely(ret < 0)) {
  97 DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret);
  98 amdgpu_bo_unreserve(bo);
  99 return ret;
100 }

Besides, pinning process prepares all the stuff before and after moving 
buffer(ttm_bo_validate, amdgpu_ttm_bind),


No, you misunderstood what this is good for.

The waiting done here is only for the shared fence to switch from 
explicitly to implicitly synchronization for correct interaction with 
the Intel driver.


As soon the the BO is exported that shouldn't wait for anything any more.


I think if a buffer can be moved, it is probably also in a good condition to be 
accessed.


That is complete nonsense.

ttm_bo_validate() is an asynchronous operation to enable GPU access to 
the BO, it isn't related at all to possible CPU access and can actually 
prevent it a number of cases.


amdgpu_ttm_bind() in turn binds the BO to the GART space and isn't 
related to CPU access either.


What you most likely need to do here is to use 
reservation_object_wait_timeout_rcu() to wait for all GPU operations to end.


Regards,
Christian.



Sam


-Original Message-
From: Koenig, Christian
Sent: Wednesday, September 20, 2017 1:38 PM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support

Am 20.09.2017 um 19:34 schrieb Li, Samuel:

If that is what this callback should do then this implementation
would be incorrect. Pinning doesn't wait for any GPU operation to finish.

During pining, it will all the fences to finish. That shall be OK.

No that isn't correct. Pinning just notes that the BO shouldn't be moved any
more.

It doesn't wait for anything.

Christian.


Sam




-Original Message-
From: Koenig, Christian
Sent: Wednesday, September 20, 2017 12:21 PM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap

support

Am 20.09.2017 um 17:44 schrieb Li, Samuel:

What happens when another thread is using amdgpu_dmabuf_ops to

call

begin_cpu_access/end_cpu_access when you are fixing it up again?

Right, that is an issue.

A simple "if (!amdgpu_dmabuf_ops.begin_cpu_access)" should be able

to

deal with that.


I would just completely drop the two callbacks, pinning is not
necessary for CPU access and thinking more about it it actually has
some unwanted side effects.

CPU access needs synchronization anyway, so the two callbacks cannot
be

dropped (other drivers implemented too), so I would like to keep it
there for now.

Wait a second what do you mean with "CPU access needs

synchronization"?

At least i915 makes the memory GPU inaccessible when you start to use
it with the CPU.

If that is what this callback should do then this implementation
would be incorrect. Pinning doesn't wait for any GPU operation to finish.

Regards,
Christian.


Sam



-Original Message-
From: Koenig, Christian
Sent: Wednesday, September 20, 2017 2:58 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap

support

What do you mean "This isn't race free"?

Take a look at the code again:

+dma_buf = drm_gem_prime_export(dev, gobj, flags);
+amdgpu_dmabuf_ops = *(dma_buf->ops);
+amdgpu_dmabuf_ops.begin_cpu_access =

amdgpu_gem_begin_cpu_access;

+amdgpu_dmabuf_ops.end_cpu_access =

amdgpu_gem_end_cpu_access;

+dma_buf->ops = _dmabuf_ops;

What happens when another thread is using amdgpu_dmabuf_ops to

call

begin_cpu_access/end_cpu_access when you are fixing it up again?

I would just completely drop the two callbacks, pinning is not
necessary for CPU access and thinking more about it it actually has
some unwanted side effects.

Regards,
Christian.

Am 19.09.2017 um 23:22 schrieb Samuel Li:

+vma->vm_pgoff = amdgpu_bo_mmap_offset(bo) >>

PAGE_SHIFT;

Maybe better use "vma->vm_pgoff +=

amdgpu_bo_mmap_offset(bo) >>

PAGE_SHIFT;", but I'm not sure.

How other drivers handle this?

This is a good catch. Looks like pgoff is honored during prime
mmap, not a

fake offset here.

+dma_buf->ops = _dmabuf_ops;

This isn't race free and needs to be fixed.
Better add callbacks to drm_prime.c similar to

drm_gem_dmabuf_mmap().

What do you mean "This isn't race free"?

Regards,
Sam



On 2017-09-15 11:05 AM, Christian König wrote:

Am 14.09.2017 um 00:39 schrieb 

Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support

[Christian König]

Am 20.09.2017 um 19:34 schrieb Li, Samuel:

If that is what this callback should do then this implementation would be
incorrect. Pinning doesn't wait for any GPU operation to finish.

During pining, it will all the fences to finish. That shall be OK.


No that isn't correct. Pinning just notes that the BO shouldn't be moved 
any more.


It doesn't wait for anything.

Christian.



Sam




-Original Message-
From: Koenig, Christian
Sent: Wednesday, September 20, 2017 12:21 PM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support

Am 20.09.2017 um 17:44 schrieb Li, Samuel:

What happens when another thread is using amdgpu_dmabuf_ops to call
begin_cpu_access/end_cpu_access when you are fixing it up again?

Right, that is an issue.

A simple "if (!amdgpu_dmabuf_ops.begin_cpu_access)" should be able to
deal with that.


I would just completely drop the two callbacks, pinning is not
necessary for CPU access and thinking more about it it actually has
some unwanted side effects.

CPU access needs synchronization anyway, so the two callbacks cannot be

dropped (other drivers implemented too), so I would like to keep it there for
now.

Wait a second what do you mean with "CPU access needs synchronization"?

At least i915 makes the memory GPU inaccessible when you start to use it
with the CPU.

If that is what this callback should do then this implementation would be
incorrect. Pinning doesn't wait for any GPU operation to finish.

Regards,
Christian.


Sam



-Original Message-
From: Koenig, Christian
Sent: Wednesday, September 20, 2017 2:58 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap

support

What do you mean "This isn't race free"?

Take a look at the code again:

+dma_buf = drm_gem_prime_export(dev, gobj, flags);
+amdgpu_dmabuf_ops = *(dma_buf->ops);
+amdgpu_dmabuf_ops.begin_cpu_access =

amdgpu_gem_begin_cpu_access;

+amdgpu_dmabuf_ops.end_cpu_access =

amdgpu_gem_end_cpu_access;

+dma_buf->ops = _dmabuf_ops;

What happens when another thread is using amdgpu_dmabuf_ops to call
begin_cpu_access/end_cpu_access when you are fixing it up again?

I would just completely drop the two callbacks, pinning is not
necessary for CPU access and thinking more about it it actually has
some unwanted side effects.

Regards,
Christian.

Am 19.09.2017 um 23:22 schrieb Samuel Li:

+vma->vm_pgoff = amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;

Maybe better use "vma->vm_pgoff +=

amdgpu_bo_mmap_offset(bo) >>

PAGE_SHIFT;", but I'm not sure.

How other drivers handle this?

This is a good catch. Looks like pgoff is honored during prime mmap,
not a

fake offset here.

+dma_buf->ops = _dmabuf_ops;

This isn't race free and needs to be fixed.
Better add callbacks to drm_prime.c similar to

drm_gem_dmabuf_mmap().

What do you mean "This isn't race free"?

Regards,
Sam



On 2017-09-15 11:05 AM, Christian König wrote:

Am 14.09.2017 um 00:39 schrieb Samuel Li:

v2: drop hdp invalidate/flush.

Signed-off-by: Samuel Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 77

++-

 3 files changed, 81 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d2aaad7..188b705 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -395,11 +395,14 @@

amdgpu_gem_prime_import_sg_table(struct

drm_device *dev,

 struct dma_buf *amdgpu_gem_prime_export(struct drm_device

*dev,

 struct drm_gem_object *gobj,
 int flags);
+struct drm_gem_object *amdgpu_gem_prime_import(struct

drm_device *dev,

+struct dma_buf *dma_buf);
 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
 struct reservation_object *amdgpu_gem_prime_res_obj(struct

drm_gem_object *);

 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj,

void

*vaddr);
+int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct
+vm_area_struct *vma);
 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
   /* sub-allocation manager, it has to be protected by another lock.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 2cdf844..9b63ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -835,7 +835,7 @@ static struct drm_driver kms_driver = {
 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 .gem_prime_export = 

[PATCH umr] Use ipname.regname format for --lookup

[Tom St Denis]

Since newer asics have IP blocks with the same register we must specify both.

Signed-off-by: Tom St Denis 
---
 doc/umr.1|  2 +-
 src/app/main.c   |  3 ++-
 src/app/umr_lookup.c | 33 -
 3 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/doc/umr.1 b/doc/umr.1
index e865e131fa51..69a2087d1ade 100644
--- a/doc/umr.1
+++ b/doc/umr.1
@@ -31,7 +31,7 @@ List all blocks attached to the asic that has been detected.
 List all registers in an IP block (can use '-O bits' to list bitfields)
 .IP "--lookup, -lu  "
 Look up an MMIO register by address and bitfield decode the value specified 
(with 0x prefix) or by
-register name.
+register name.  The register name string must include the ipname, e.g., 
uvd6.mmUVD_CONTEXT_ID.
 .IP "--write -w  "
 Write a value specified in hex to a register specified with a complete
 register path in the form <
diff --git a/src/app/main.c b/src/app/main.c
index 17c99b4296a4..0a44c4399bb8 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -502,7 +502,8 @@ if (strcmp(argv[i], "--vm-write") && strcmp(argv[i], 
"-vw")) {
 "\n\t--enumerate, -e\n\t\tEnumerate all AMDGPU devices detected.\n"
 "\n\t--list-blocks, -lb\n\t\tList IP blocks discovered for this device.\n"
 "\n\t--list-regs, -lr \n\t\tList registers for a given IP block (can 
use '-O bits' to list bitfields).\n"
-"\n\t--lookup, -lu  \n\t\tLook up bit decoding of 
an MMIO register by address (with 0x prefix) or by register name.\n"
+"\n\t--lookup, -lu  \n\t\tLook up bit decoding of 
an MMIO register by address (with 0x prefix) or by register name."
+   "\n\t\tThe register name string must include the ipname, e.g., 
uvd6.mmUVD_CONTEXT_ID.\n"
 "\n\t--write, -w  \n\t\tWrite a value in hex to a register 
specified as a register path in the"
"\n\t\tform .  For instance 
\"tonga.uvd5.mmUVD_SOFT_RESET\"."
"\n\t\tCan be used multiple times to set multiple registers.  You can"
diff --git a/src/app/umr_lookup.c b/src/app/umr_lookup.c
index d07130ab0dfa..f88d0b6bce77 100644
--- a/src/app/umr_lookup.c
+++ b/src/app/umr_lookup.c
@@ -47,16 +47,31 @@ void umr_lookup(struct umr_asic *asic, char *address, char 
*value)
}
}
} else {
+   char ipname[256], regname[256], *p;
+
+   memset(ipname, 0, sizeof ipname);
+   memset(regname, 0, sizeof regname);
+   p = strstr(address, ".");
+   if (!p) {
+   fprintf(stderr, "[ERROR]: Must specify ipname.regname 
for umr_lookup()\n");
+   return;
+   }
+   memcpy(ipname, address, p - address);
+   strcpy(regname, p + 1);
+
for (i = 0; i < asic->no_blocks; i++)
-   for (j = 0; j < asic->blocks[i]->no_regs; j++)
-   if (asic->blocks[i]->regs[j].type == REG_MMIO &&
-   !strcmp(asic->blocks[i]->regs[j].regname, address)) 
{
-   printf("%s.%s => 0x%08lx\n", 
asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, (unsigned long)num);
-   for (k = 0; k < 
asic->blocks[i]->regs[j].no_bits; k++) {
-   uint32_t v;
-   v = (1UL << 
(asic->blocks[i]->regs[j].bits[k].stop + 1 - 
asic->blocks[i]->regs[j].bits[k].start)) - 1;
-   v &= (num >> 
asic->blocks[i]->regs[j].bits[k].start);
-   
asic->blocks[i]->regs[j].bits[k].bitfield_print(asic, asic->asicname, 
asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, 
asic->blocks[i]->regs[j].bits[k].regname, 
asic->blocks[i]->regs[j].bits[k].start, asic->blocks[i]->regs[j].bits[k].stop, 
v);
+   if (!strcmp(asic->blocks[i]->ipname, ipname)) {
+   for (j = 0; j < asic->blocks[i]->no_regs; j++) {
+   if (asic->blocks[i]->regs[j].type == 
REG_MMIO &&
+   
!strcmp(asic->blocks[i]->regs[j].regname, regname)) {
+   printf("%s.%s => 0x%08lx\n", 
asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, (unsigned long)num);
+   for (k = 0; k < 
asic->blocks[i]->regs[j].no_bits; k++) {
+   uint32_t v;
+   v = (1UL << 
(asic->blocks[i]->regs[j].bits[k].stop + 1 - 
asic->blocks[i]->regs[j].bits[k].start)) - 1;
+   v &= (num >> 
asic->blocks[i]->regs[j].bits[k].start);
+   
asic->blocks[i]->regs[j].bits[k].bitfield_print(asic, asic->asicname, 
asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, 

RE: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support

[Li, Samuel]

> If that is what this callback should do then this implementation would be
> incorrect. Pinning doesn't wait for any GPU operation to finish.

During pining, it will all the fences to finish. That shall be OK.

Sam



> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, September 20, 2017 12:21 PM
> To: Li, Samuel ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support
> 
> Am 20.09.2017 um 17:44 schrieb Li, Samuel:
> >> What happens when another thread is using amdgpu_dmabuf_ops to call
> >> begin_cpu_access/end_cpu_access when you are fixing it up again?
> > Right, that is an issue.
> 
> A simple "if (!amdgpu_dmabuf_ops.begin_cpu_access)" should be able to
> deal with that.
> 
> >
> >> I would just completely drop the two callbacks, pinning is not
> >> necessary for CPU access and thinking more about it it actually has
> >> some unwanted side effects.
> > CPU access needs synchronization anyway, so the two callbacks cannot be
> dropped (other drivers implemented too), so I would like to keep it there for
> now.
> 
> Wait a second what do you mean with "CPU access needs synchronization"?
> 
> At least i915 makes the memory GPU inaccessible when you start to use it
> with the CPU.
> 
> If that is what this callback should do then this implementation would be
> incorrect. Pinning doesn't wait for any GPU operation to finish.
> 
> Regards,
> Christian.
> 
> >
> > Sam
> >
> >
> >> -Original Message-
> >> From: Koenig, Christian
> >> Sent: Wednesday, September 20, 2017 2:58 AM
> >> To: Li, Samuel ; amd-gfx@lists.freedesktop.org
> >> Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap
> support
> >>
> >>> What do you mean "This isn't race free"?
> >> Take a look at the code again:
> >>> +dma_buf = drm_gem_prime_export(dev, gobj, flags);
> >>> +amdgpu_dmabuf_ops = *(dma_buf->ops);
> >>> +amdgpu_dmabuf_ops.begin_cpu_access =
> >> amdgpu_gem_begin_cpu_access;
> >>> +amdgpu_dmabuf_ops.end_cpu_access =
> >> amdgpu_gem_end_cpu_access;
> >>> +dma_buf->ops = _dmabuf_ops;
> >> What happens when another thread is using amdgpu_dmabuf_ops to call
> >> begin_cpu_access/end_cpu_access when you are fixing it up again?
> >>
> >> I would just completely drop the two callbacks, pinning is not
> >> necessary for CPU access and thinking more about it it actually has
> >> some unwanted side effects.
> >>
> >> Regards,
> >> Christian.
> >>
> >> Am 19.09.2017 um 23:22 schrieb Samuel Li:
> > +vma->vm_pgoff = amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
>  Maybe better use "vma->vm_pgoff +=
> amdgpu_bo_mmap_offset(bo) >>
> >> PAGE_SHIFT;", but I'm not sure.
>  How other drivers handle this?
> >>> This is a good catch. Looks like pgoff is honored during prime mmap,
> >>> not a
> >> fake offset here.
> > +dma_buf->ops = _dmabuf_ops;
>  This isn't race free and needs to be fixed.
>  Better add callbacks to drm_prime.c similar to
> >> drm_gem_dmabuf_mmap().
> >>> What do you mean "This isn't race free"?
> >>>
> >>> Regards,
> >>> Sam
> >>>
> >>>
> >>>
> >>> On 2017-09-15 11:05 AM, Christian König wrote:
>  Am 14.09.2017 um 00:39 schrieb Samuel Li:
> > v2: drop hdp invalidate/flush.
> >
> > Signed-off-by: Samuel Li 
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 ++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  3 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 77
> >> ++-
> > 3 files changed, 81 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index d2aaad7..188b705 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -395,11 +395,14 @@
> amdgpu_gem_prime_import_sg_table(struct
> >> drm_device *dev,
> > struct dma_buf *amdgpu_gem_prime_export(struct drm_device
> *dev,
> > struct drm_gem_object *gobj,
> > int flags);
> > +struct drm_gem_object *amdgpu_gem_prime_import(struct
> >> drm_device *dev,
> > +struct dma_buf *dma_buf);
> > int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
> > void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
> > struct reservation_object *amdgpu_gem_prime_res_obj(struct
> >> drm_gem_object *);
> > void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
> > void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj,
> void
> > *vaddr);
> > +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct
> > +vm_area_struct *vma);
> > int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
> >   /* sub-allocation manager, it has to be protected by another lock.
> > diff --git 

RE: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support

[Li, Samuel]

> What happens when another thread is using amdgpu_dmabuf_ops to call
> begin_cpu_access/end_cpu_access when you are fixing it up again?
Right, that is an issue.

> I would just completely drop the two callbacks, pinning is not necessary for
> CPU access and thinking more about it it actually has some unwanted side
> effects.
CPU access needs synchronization anyway, so the two callbacks cannot be dropped 
(other drivers implemented too), so I would like to keep it there for now.

Sam


> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, September 20, 2017 2:58 AM
> To: Li, Samuel ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2 1/1] drm/amdgpu: Add gem_prime_mmap support
> 
> > What do you mean "This isn't race free"?
> 
> Take a look at the code again:
> > +dma_buf = drm_gem_prime_export(dev, gobj, flags);
> > +amdgpu_dmabuf_ops = *(dma_buf->ops);
> > +amdgpu_dmabuf_ops.begin_cpu_access =
> amdgpu_gem_begin_cpu_access;
> > +amdgpu_dmabuf_ops.end_cpu_access =
> amdgpu_gem_end_cpu_access;
> > +dma_buf->ops = _dmabuf_ops;
> 
> What happens when another thread is using amdgpu_dmabuf_ops to call
> begin_cpu_access/end_cpu_access when you are fixing it up again?
> 
> I would just completely drop the two callbacks, pinning is not necessary for
> CPU access and thinking more about it it actually has some unwanted side
> effects.
> 
> Regards,
> Christian.
> 
> Am 19.09.2017 um 23:22 schrieb Samuel Li:
> >>> +vma->vm_pgoff = amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
> >> Maybe better use "vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >>
> PAGE_SHIFT;", but I'm not sure.
> >> How other drivers handle this?
> > This is a good catch. Looks like pgoff is honored during prime mmap, not a
> fake offset here.
> >
> >>> +dma_buf->ops = _dmabuf_ops;
> >> This isn't race free and needs to be fixed.
> >> Better add callbacks to drm_prime.c similar to
> drm_gem_dmabuf_mmap().
> > What do you mean "This isn't race free"?
> >
> > Regards,
> > Sam
> >
> >
> >
> > On 2017-09-15 11:05 AM, Christian König wrote:
> >> Am 14.09.2017 um 00:39 schrieb Samuel Li:
> >>> v2: drop hdp invalidate/flush.
> >>>
> >>> Signed-off-by: Samuel Li 
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 ++
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  3 +-
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 77
> ++-
> >>>3 files changed, 81 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index d2aaad7..188b705 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -395,11 +395,14 @@ amdgpu_gem_prime_import_sg_table(struct
> drm_device *dev,
> >>>struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
> >>>struct drm_gem_object *gobj,
> >>>int flags);
> >>> +struct drm_gem_object *amdgpu_gem_prime_import(struct
> drm_device *dev,
> >>> +struct dma_buf *dma_buf);
> >>>int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
> >>>void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
> >>>struct reservation_object *amdgpu_gem_prime_res_obj(struct
> drm_gem_object *);
> >>>void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
> >>>void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void
> >>> *vaddr);
> >>> +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct
> >>> +vm_area_struct *vma);
> >>>int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
> >>>  /* sub-allocation manager, it has to be protected by another lock.
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> index 2cdf844..9b63ac5 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> @@ -835,7 +835,7 @@ static struct drm_driver kms_driver = {
> >>>.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> >>>.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> >>>.gem_prime_export = amdgpu_gem_prime_export,
> >>> -.gem_prime_import = drm_gem_prime_import,
> >>> +.gem_prime_import = amdgpu_gem_prime_import,
> >>>.gem_prime_pin = amdgpu_gem_prime_pin,
> >>>.gem_prime_unpin = amdgpu_gem_prime_unpin,
> >>>.gem_prime_res_obj = amdgpu_gem_prime_res_obj, @@ -843,6
> >>> +843,7 @@ static struct drm_driver kms_driver = {
> >>>.gem_prime_import_sg_table =
> amdgpu_gem_prime_import_sg_table,
> >>>.gem_prime_vmap = amdgpu_gem_prime_vmap,
> >>>.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
> >>> +.gem_prime_mmap = amdgpu_gem_prime_mmap,
> >>>  .name = DRIVER_NAME,
> >>>.desc = DRIVER_DESC,
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> >>> 

[PATCH] drm/amd: Fix typo

[Felix Kuehling]

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/lib/chash.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/lib/chash.c b/drivers/gpu/drm/amd/lib/chash.c
index e07e6f3..b8e45f3 100644
--- a/drivers/gpu/drm/amd/lib/chash.c
+++ b/drivers/gpu/drm/amd/lib/chash.c
@@ -223,8 +223,8 @@ static int chash_table_check(struct __chash_table *table)
 static void chash_iter_relocate(struct chash_iter dst, struct chash_iter src)
 {
BUG_ON(src.table == dst.table && src.slot == dst.slot);
-   BUG_ON(src.table->key_size != src.table->key_size);
-   BUG_ON(src.table->value_size != src.table->value_size);
+   BUG_ON(src.table->key_size != dst.table->key_size);
+   BUG_ON(src.table->value_size != dst.table->value_size);
 
if (dst.table->key_size == 4)
dst.table->keys32[dst.slot] = src.table->keys32[src.slot];
-- 
2.7.4

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[PATCH 12/18] drm/amd/powerplay: delete PHM_READ_VFPF_INDIRECT_FIELD

[Rex Zhu]

repeated defining in hwmgr.h

Change-Id: Id4fdbdb7df727516d9bdb2ca6c621b97b5ce509f
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h  | 5 -
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c   | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  | 4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 6 +++---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c  | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 4 ++--
 6 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 56d123f..2263b13 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -193,10 +193,5 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
   reg, field)
 
-/*Operations on named fields.*/
-
-#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
-   SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
-   reg, field)
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index 17f3432..4262765 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -188,7 +188,7 @@ static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
 
 bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
 {
-   return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+   return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
&& (0x20100 <= cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, ixSMC_PC_C)));
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 15059078..40bde0d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -108,7 +108,7 @@ static int fiji_start_smu_in_protection_mode(struct 
pp_hwmgr *hwmgr)
SMU_STATUS, SMU_DONE, 0);
 
/* Check pass/failed indicator */
-   if (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_STATUS, SMU_PASS) != 1) {
PP_ASSERT_WITH_CODE(false,
"SMU Firmware start failed!", return -1);
@@ -304,7 +304,7 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
fiji_avfs_event_mgr(hwmgr, false);
 
/* Check if SMU is running in protected mode */
-   if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+   if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) {
result = fiji_start_smu_in_non_protection_mode(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index eefa13b..22b8ecb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -252,7 +252,7 @@ static int polaris10_start_smu_in_protection_mode(struct 
pp_hwmgr *hwmgr)
 
PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, 
SMU_DONE, 0);
 
-   if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_STATUS, SMU_PASS))
PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return 
-1);
 
@@ -316,8 +316,8 @@ static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
/* Only start SMC if SMC RAM is not running */
if (!smu7_is_smc_ram_running(hwmgr)) {
SMU_VFT_INTACT = false;
-   smu_data->protected_mode = (uint8_t) 
(SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, 
SMU_MODE));
-   smu_data->smu7_data.security_hard_key = (uint8_t) 
(SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, 
SMU_SEL));
+   smu_data->protected_mode = (uint8_t) 
(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, 
SMU_MODE));
+   smu_data->smu7_data.security_hard_key = (uint8_t) 
(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, 
SMU_SEL));
 
/* Check if SMU is running in protected mode */
if (smu_data->protected_mode == 0) {
diff --git 

[PATCH 18/18] drm/amd/powerplay: delete dead code in smumgr

[Rex Zhu]

Change-Id: I722ecb827144adf42b149e41595580ca8d4385ae
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 31 --
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 87 ---
 2 files changed, 118 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index cc67d225..dabf82c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -101,23 +101,6 @@ enum SMU_MAC_DEFINITION {
 extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
 
-extern int smum_wait_on_register(struct pp_hwmgr *hwmgr,
-   uint32_t index, uint32_t value, uint32_t mask);
-
-extern int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
-   uint32_t index, uint32_t value, uint32_t mask);
-
-extern int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
-   uint32_t indirect_port, uint32_t index,
-   uint32_t value, uint32_t mask);
-
-
-extern void smum_wait_for_indirect_register_unequal(
-   struct pp_hwmgr *hwmgr,
-   uint32_t indirect_port, uint32_t index,
-   uint32_t value, uint32_t mask);
-
-
 extern int smu_allocate_memory(void *device, uint32_t size,
 enum cgs_gpu_mem_type type,
 uint32_t byte_align, uint64_t *mc_addr,
@@ -147,19 +130,5 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
 
 extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
 
-#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
-
-#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
-
-
-#define SMUM_GET_FIELD(value, reg, field)  \
-   (((value) & SMUM_FIELD_MASK(reg, field))\
-   >> SMUM_FIELD_SHIFT(reg, field))
-
-
-#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
-   SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
-  reg, field)
-
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index d3c12e0..8673884 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -144,93 +144,6 @@ int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr 
*hwmgr,
hwmgr, msg, parameter);
 }
 
-/*
- * Returns once the part of the register indicated by the mask has
- * reached the given value.
- */
-int smum_wait_on_register(struct pp_hwmgr *hwmgr,
-   uint32_t index,
-   uint32_t value, uint32_t mask)
-{
-   uint32_t i;
-   uint32_t cur_value;
-
-   if (hwmgr == NULL || hwmgr->device == NULL)
-   return -EINVAL;
-
-   for (i = 0; i < hwmgr->usec_timeout; i++) {
-   cur_value = cgs_read_register(hwmgr->device, index);
-   if ((cur_value & mask) == (value & mask))
-   break;
-   udelay(1);
-   }
-
-   /* timeout means wrong logic*/
-   if (i == hwmgr->usec_timeout)
-   return -1;
-
-   return 0;
-}
-
-int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
-   uint32_t index,
-   uint32_t value, uint32_t mask)
-{
-   uint32_t i;
-   uint32_t cur_value;
-
-   if (hwmgr == NULL)
-   return -EINVAL;
-
-   for (i = 0; i < hwmgr->usec_timeout; i++) {
-   cur_value = cgs_read_register(hwmgr->device,
-   index);
-   if ((cur_value & mask) != (value & mask))
-   break;
-   udelay(1);
-   }
-
-   /* timeout means wrong logic */
-   if (i == hwmgr->usec_timeout)
-   return -1;
-
-   return 0;
-}
-
-
-/*
- * Returns once the part of the register indicated by the mask
- * has reached the given value.The indirect space is described by
- * giving the memory-mapped index of the indirect index register.
- */
-int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
-   uint32_t indirect_port,
-   uint32_t index,
-   uint32_t value,
-   uint32_t mask)
-{
-   if (hwmgr == NULL || hwmgr->device == NULL)
-   return -EINVAL;
-
-   cgs_write_register(hwmgr->device, indirect_port, index);
-   return smum_wait_on_register(hwmgr, indirect_port + 1,
-

[PATCH 16/18] drm/amd/powerplay: delete SMUM_WAIT_INDIRECT_FIELD

[Rex Zhu]

repeated defining in hwmgr.h
use PHM_WAIT_INDIRECT_FIELD instand.

Change-Id: I4c06638c4fb2af2bae18a0c0f4f825b555f2bea3
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 11 ---
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c |  2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c |  2 +-
 3 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index ebe988b..cc67d225 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -151,17 +151,6 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
 
 #define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
 
-#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
-   port, index, value, mask)   \
-   smum_wait_on_indirect_register(hwmgr,   \
-   mm##port##_INDEX, index, value, mask)
-
-#define SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)\
-   SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, 
value, mask)
-
-#define SMUM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)
  \
-   SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) << 
SMUM_FIELD_SHIFT(reg, field), \
-   SMUM_FIELD_MASK(reg, field) )
 
 #define SMUM_GET_FIELD(value, reg, field)  \
(((value) & SMUM_FIELD_MASK(reg, field))\
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index b922de5..7709f62 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -1937,7 +1937,7 @@ static int ci_start_smc(struct pp_hwmgr *hwmgr)
 
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
-   SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
+   PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
 INTERRUPTS_ENABLED, 1);
 
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index b729a39..78aa112 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -80,7 +80,7 @@ static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
/* de-assert reset */
iceland_start_smc(hwmgr);
 
-   SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
+   PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
 INTERRUPTS_ENABLED, 1);
 
return 0;
-- 
1.9.1

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[PATCH 13/18] drm/amd/powerplay: delete SMUM_SET_FIELD

[Rex Zhu]

repeated defining in hwmgr.h

Signed-off-by: Rex Zhu 

Change-Id: I62316f35417784c4cf30a75e148bd1895a184a5b
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h   |  5 -
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 12 ++--
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 2263b13..6c78f60 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -184,11 +184,6 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
 #define SMUM_READ_FIELD(device, reg, field)   \
SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 
-#define SMUM_SET_FIELD(value, reg, field, field_val)  \
-   (((value) & ~SMUM_FIELD_MASK(reg, field)) |\
-   (SMUM_FIELD_MASK(reg, field) & ((field_val) << \
-   SMUM_FIELD_SHIFT(reg, field
-
 #define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
   reg, field)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 8aee9c8..ab8d83f 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -191,17 +191,17 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
/* Disable MEC parsing/prefetching */
tmp = cgs_read_register(hwmgr->device,
mmCP_MEC_CNTL);
-   tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
-   tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
+   tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
+   tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
 
tmp = cgs_read_register(hwmgr->device,
mmCP_CPC_IC_BASE_CNTL);
 
-   tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
-   tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
-   tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
-   tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
+   tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
+   tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
+   tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
+   tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
 
reg_data = smu_lower_32_bits(info.mc_addr) &
-- 
1.9.1

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[PATCH 11/18] drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD

[Rex Zhu]

repeated defining in hwmgr.h

Change-Id: I03b1adfb164d43e9f33e6442f666c013f2e98a05
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h |  6 --
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 14 +++---
 .../gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c| 18 +-
 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c| 14 +++---
 4 files changed, 23 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index fdffd63..56d123f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -199,10 +199,4 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field)
 
-
-#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)\
-   cgs_write_ind_register(device, port, ix##reg, \
-   SMUM_SET_FIELD(cgs_read_ind_register(device, port, 
ix##reg), \
-   reg, field, fieldval))
-
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 75ed7c3..15059078 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -66,7 +66,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr 
*hwmgr)
/* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); */
 
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
result = smu7_upload_smu_firmware_image(hwmgr);
@@ -77,11 +77,11 @@ static int fiji_start_smu_in_protection_mode(struct 
pp_hwmgr *hwmgr)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_STATUS, 0);
 
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
/* De-assert reset */
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
/* Wait for ROM firmware to initialize interrupt hendler */
@@ -89,7 +89,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr 
*hwmgr)
SMC_INTR_CNTL_MASK_0, 0x10040, 0x); */
 
/* Set SMU Auto Start */
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_INPUT_DATA, AUTO_START, 1);
 
/* Clear firmware interrupt enable flag */
@@ -134,7 +134,7 @@ static int fiji_start_smu_in_non_protection_mode(struct 
pp_hwmgr *hwmgr)
ixFIRMWARE_FLAGS, 0);
 
/* Assert reset */
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
result = smu7_upload_smu_firmware_image(hwmgr);
@@ -145,11 +145,11 @@ static int fiji_start_smu_in_non_protection_mode(struct 
pp_hwmgr *hwmgr)
smu7_program_jump_on_start(hwmgr);
 
/* Enable clock */
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
/* De-assert reset */
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
/* Wait for firmware to initialize */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index fd4ccd0..eefa13b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -223,7 +223,7 @@ static int polaris10_start_smu_in_protection_mode(struct 
pp_hwmgr *hwmgr)
/* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, 
boot_seq_done, 0) */
 
/* Assert reset */
-   SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
result = smu7_upload_smu_firmware_image(hwmgr);
@@ -233,11 +233,11 @@ 

[PATCH 09/18] drm/amd/powerplay: delete SMU_WRITE_INDIRECT_FIELD

[Rex Zhu]

the macro is as same as PHM_WRITE_INDIRECT_FIELD

Change-Id: I62389ad2d699530e3a7d6a81f7427c21fd88b7be
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 15 ---
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c |  4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c |  8 
 3 files changed, 6 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 099758d..d065aa7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -193,11 +193,6 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
   reg, field)
 
-
-
-
-
-
 /*Operations on named fields.*/
 
 #define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
@@ -213,14 +208,4 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
SMUM_SET_FIELD(cgs_read_ind_register(device, port, 
ix##reg), \
reg, field, fieldval))
 
-
-#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)  
\
-   cgs_write_ind_register(device, port, ix##reg,   
\
-   SMUM_SET_FIELD(cgs_read_ind_register(device, port, 
ix##reg),\
-  reg, field, fieldval))
-
-
-
-
-
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index b28e4e9..e867094 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -1933,9 +1933,9 @@ static int ci_start_smc(struct pp_hwmgr *hwmgr)
ci_program_jump_on_start(hwmgr);
 
/* enable smc clock */
-   SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
+   PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
-   SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
+   PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
 INTERRUPTS_ENABLED, 1);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 3a134ea..fe57335 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -41,7 +41,7 @@
 
 static int iceland_start_smc(struct pp_hwmgr *hwmgr)
 {
-   SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
  SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
return 0;
@@ -49,7 +49,7 @@ static int iceland_start_smc(struct pp_hwmgr *hwmgr)
 
 static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
 {
-   SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
  SMC_SYSCON_RESET_CNTL,
  rst_reg, 1);
 }
@@ -57,14 +57,14 @@ static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
 
 static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
 {
-   SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
  SMC_SYSCON_CLOCK_CNTL_0,
  ck_disable, 1);
 }
 
 static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
 {
-   SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+   PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
  SMC_SYSCON_CLOCK_CNTL_0,
  ck_disable, 0);
 }
-- 
1.9.1

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Re: [PATCH] drm/amd/amdgpu: Partial revert of iova debugfs

[Christian König]

Am 20.09.2017 um 13:42 schrieb Tom St Denis:

We discovered that on some devices even with iommu enabled
you can access all of system memory through the iommu translation.

Therefore, we revert the read method to the translation only service
and drop the write method completely.

Signed-off-by: Tom St Denis 


Reviewed-by: Christan König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 90 +
  1 file changed, 13 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0e5f78f3a97e..ce435dbbb398 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1784,98 +1784,34 @@ static ssize_t amdgpu_iova_to_phys_read(struct file *f, 
char __user *buf,
   size_t size, loff_t *pos)
  {
struct amdgpu_device *adev = file_inode(f)->i_private;
-   ssize_t result, n;
int r;
uint64_t phys;
-   void *ptr;
struct iommu_domain *dom;
  
-	dom = iommu_get_domain_for_dev(adev->dev);

-   if (!dom)
-   return -EFAULT;
-
-   result = 0;
-   while (size) {
-   // get physical address and map
-   phys = iommu_iova_to_phys(dom, *pos);
-
-   // copy upto one page
-   if (size > PAGE_SIZE)
-   n = PAGE_SIZE;
-   else
-   n = size;
-
-   // to end of the page
-   if (((*pos & (PAGE_SIZE - 1)) + n) >= PAGE_SIZE)
-   n = PAGE_SIZE - (*pos & (PAGE_SIZE - 1));
-
-   ptr = kmap(pfn_to_page(PFN_DOWN(phys)));
-   if (!ptr)
-   return -EFAULT;
-
-   r = copy_to_user(buf, ptr, n);
-   kunmap(pfn_to_page(PFN_DOWN(phys)));
-   if (r)
-   return -EFAULT;
-
-   *pos += n;
-   size -= n;
-   result += n;
-   }
-
-   return result;
-}
+   // always return 8 bytes
+   if (size != 8)
+   return -EINVAL;
  
-static ssize_t amdgpu_iova_to_phys_write(struct file *f, const char __user *buf,

-  size_t size, loff_t *pos)
-{
-   struct amdgpu_device *adev = file_inode(f)->i_private;
-   ssize_t result, n;
-   int r;
-   uint64_t phys;
-   void *ptr;
-   struct iommu_domain *dom;
+   // only accept page addresses
+   if (*pos & 0xFFF)
+   return -EINVAL;
  
  	dom = iommu_get_domain_for_dev(adev->dev);

-   if (!dom)
-   return -EFAULT;
-
-   result = 0;
-   while (size) {
-   // get physical address and map
+   if (dom)
phys = iommu_iova_to_phys(dom, *pos);
+   else
+   phys = *pos;
  
-		// copy upto one page

-   if (size > PAGE_SIZE)
-   n = PAGE_SIZE;
-   else
-   n = size;
-
-   // to end of the page
-   if (((*pos & (PAGE_SIZE - 1)) + n) >= PAGE_SIZE)
-   n = PAGE_SIZE - (*pos & (PAGE_SIZE - 1));
-
-   ptr = kmap(pfn_to_page(PFN_DOWN(phys)));
-   if (!ptr)
-   return -EFAULT;
-
-   r = copy_from_user(ptr, buf, n);
-   kunmap(pfn_to_page(PFN_DOWN(phys)));
-   if (r)
-   return -EFAULT;
-
-   *pos += n;
-   size -= n;
-   result += n;
-   }
+   r = copy_to_user(buf, , 8);
+   if (r)
+   return -EFAULT;
  
-	return result;

+   return 8;
  }
  
  static const struct file_operations amdgpu_ttm_iova_fops = {

.owner = THIS_MODULE,
.read = amdgpu_iova_to_phys_read,
-   .write = amdgpu_iova_to_phys_write,
.llseek = default_llseek
  };
  



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[PATCH 10/18] drm/amd/powerplay: delete SMUM_WRITE_FIELD

[Rex Zhu]

the macro is as same as PHM_WRITE_FIELD

Signed-off-by: Rex Zhu 

Change-Id: I678e6277b6d582ab6a651a5fba07989634bf1aee
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 3 ---
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c | 6 +++---
 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c| 6 +++---
 4 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index d065aa7..fdffd63 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -199,9 +199,6 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field)
 
-#define SMUM_WRITE_FIELD(device, reg, field, fieldval)\
-   cgs_write_register(device, mm##reg, \
-   SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, 
fieldval))
 
 #define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)\
cgs_write_ind_register(device, port, ix##reg, \
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index e867094..17f3432 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -104,7 +104,7 @@ static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
}
 
cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
-   SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 0);
+   PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 0);
return 0;
 }
 
@@ -2321,14 +2321,14 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
}
 
cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
-   SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 1);
+   PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 1);
 
for (; byte_count >= 4; byte_count -= 4) {
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4;
}
-   SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 0);
+   PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 0);
 
if (0 != byte_count) {
pr_err("SMC size must be dividable by 4\n");
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index fe57335..b729a39 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -97,7 +97,7 @@ static int iceland_upload_smc_firmware_data(struct pp_hwmgr 
*hwmgr,
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the 
SMC RAM area.", return -EINVAL);
 
cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
-   SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 1);
+   PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 1);
 
while (byte_count >= 4) {
data = src[0] * 0x100 + src[1] * 0x1 + src[2] * 0x100 + 
src[3];
@@ -106,7 +106,7 @@ static int iceland_upload_smc_firmware_data(struct pp_hwmgr 
*hwmgr,
byte_count -= 4;
}
 
-   SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 0);
+   PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_0, 0);
 
PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 
4.", return -EINVAL);
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index a360c3c..8e95211 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -40,7 +40,7 @@ static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, 
uint32_t smc_addr,
PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the 
SMC RAM area.", return -EINVAL);
 
cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
-   SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
+   PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
return 0;
 }
 
@@ -506,12 +506,12 @@ static int smu7_upload_smc_firmware_data(struct pp_hwmgr 
*hwmgr, uint32_t length
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the 
SMC 

[PATCH 07/18] drm/amd/powerplay: move macros to hwmgr.h

[Rex Zhu]

the SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL
is irrelated to SMU, so move to hwmgr.h
and rename to
PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL

Signed-off-by: Rex Zhu 

Change-Id: I2036309e8dd4cc3b211ae06a3d0ddfd9f16a92e7
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h   | 13 +
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h  | 13 ++---
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  |  4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c |  6 +++---
 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c |  4 ++--
 5 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 5ee7d85..1140b2a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -896,4 +896,17 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr 
*hwmgr, uint8_t voltage_t
PHM_FIELD_MASK(reg, field) )
 
 
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+   port, index, value, mask)   \
+   phm_wait_for_indirect_register_unequal(hwmgr,   \
+   mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) 
\
+   PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, 
port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, 
fieldval) \
+   PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg,   \
+   (fieldval) << PHM_FIELD_SHIFT(reg, field),  \
+   PHM_FIELD_MASK(reg, field))
+
 #endif /* _HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index c64abd5..125fa3e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -198,17 +198,13 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
smum_wait_on_indirect_register(hwmgr,   \
mm##port##_INDEX_11, index, value, mask)
 
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,\
-   port, index, value, mask)   \
-   smum_wait_for_indirect_register_unequal(hwmgr,  \
-   mm##port##_INDEX_11, index, value, mask)
+
 
 
 #define SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, 
value, mask)
 
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, 
mask) \
-   SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, 
port, ix##reg, value, mask)
+
 
 
 /*Operations on named fields.*/
@@ -238,10 +234,5 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field))
 
-#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, 
fieldval) \
-   SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg,  \
-   (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
-   SMUM_FIELD_MASK(reg, field))
-
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index d40f4a3..762fe16 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -104,7 +104,7 @@ static int fiji_start_smu_in_protection_mode(struct 
pp_hwmgr *hwmgr)
SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
 
/* Wait for done bit to be set */
-   SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
+   PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
SMU_STATUS, SMU_DONE, 0);
 
/* Check pass/failed indicator */
@@ -126,7 +126,7 @@ static int fiji_start_smu_in_non_protection_mode(struct 
pp_hwmgr *hwmgr)
int result = 0;
 
/* wait for smc boot up */
-   SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
+   PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
 
/* Clear firmware interrupt enable flag */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 884ba2c..3cc946d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -220,7 +220,7 @@ static int polaris10_start_smu_in_protection_mode(struct 
pp_hwmgr *hwmgr)
int result = 0;
 
/* Wait for smc boot up */
-   /* 

[PATCH 06/18] drm/amd/powerplay: move macros to hwmgr.h

[Rex Zhu]

the SMUM_WAIT_INDIRECT_FIELD_UNEQUAL
is irrelated to SMU, so move to hwmgr.h
and rename to PHM_WAIT_INDIRECT_FIELD_UNEQUAL

Signed-off-by: Rex Zhu 

Change-Id: Ieeb89b022edc9f3897c39641dd00e7409aa0faf9
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 13 +
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 11 +--
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c|  2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c |  2 +-
 4 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 4553149..5ee7d85 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -883,4 +883,17 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr 
*hwmgr, uint8_t voltage_t
PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, 
field))
 
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, 
value, mask)\
+   phm_wait_for_indirect_register_unequal(hwmgr,   
\
+   mm##port##_INDEX, index, value, mask)
+
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)\
+   PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, 
ix##reg, value, mask)
+
+#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) 
 \
+   PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
+   (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+   PHM_FIELD_MASK(reg, field) )
+
+
 #endif /* _HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 54b151b..c64abd5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -117,6 +117,7 @@ extern void smum_wait_for_indirect_register_unequal(
uint32_t indirect_port, uint32_t index,
uint32_t value, uint32_t mask);
 
+
 extern int smu_allocate_memory(void *device, uint32_t size,
 enum cgs_gpu_mem_type type,
 uint32_t byte_align, uint64_t *mc_addr,
@@ -242,15 +243,5 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field))
 
-#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, 
value, mask)\
-   smum_wait_for_indirect_register_unequal(hwmgr,  \
-   mm##port##_INDEX, index, value, mask)
-
-#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)\
-   SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, 
ix##reg, value, mask)
-
-#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)
  \
-   SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) << 
SMUM_FIELD_SHIFT(reg, field), \
-   SMUM_FIELD_MASK(reg, field) )
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index eafac95..d40f4a3 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -63,7 +63,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr 
*hwmgr)
int result = 0;
 
/* Wait for smc boot up */
-   /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
+   /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); */
 
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index fd63d28..3a134ea 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -137,7 +137,7 @@ static int iceland_smu_upload_firmware_image(struct 
pp_hwmgr *hwmgr)
}
 
/* wait for smc boot up */
-   SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
+   PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
 RCU_UC_EVENTS, boot_seq_done, 0);
 
/* clear firmware interrupt enable flag */
-- 
1.9.1

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[PATCH 04/18] drm/amd/powerplay: use SMU_IND_INDEX/DATA_11 pair in VFPF macros to support virtualization

[Rex Zhu]

Change-Id: I81163535116224db66b20d0afe33909aa1d4bf11
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 8bdffaa..54b151b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -195,12 +195,12 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
 #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,\
port, index, value, mask)   \
smum_wait_on_indirect_register(hwmgr,   \
-   mm##port##_INDEX_0, index, value, mask)
+   mm##port##_INDEX_11, index, value, mask)
 
 #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,\
port, index, value, mask)   \
smum_wait_for_indirect_register_unequal(hwmgr,  \
-   mm##port##_INDEX_0, index, value, mask)
+   mm##port##_INDEX_11, index, value, mask)
 
 
 #define SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index 87c8d9e..b28e4e9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -2344,7 +2344,7 @@ static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
pr_info("smc is running, no need to load smc firmware\n");
return 0;
}
-   SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
+   PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
boot_seq_done, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 
SMC_SYSCON_MISC_CNTL,
pre_fetcher_en, 1);
-- 
1.9.1

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[PATCH 05/18] drm/amd/powerpolay: add new helper functions in hwmgr.h

[Rex Zhu]

Change-Id: I37f87d31c8467b1c8b9a2bfa5e40083634f19fdb
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 42 --
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 10 --
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   |  2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c |  3 +-
 .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c   |  2 +-
 5 files changed, 50 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index fcf9ca9..6408611 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -378,7 +378,7 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t 
index,
  * reached the given value.The indirect space is described by giving
  * the memory-mapped index of the indirect index register.
  */
-void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
@@ -386,14 +386,50 @@ void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 {
if (hwmgr == NULL || hwmgr->device == NULL) {
pr_err("Invalid Hardware Manager!");
-   return;
+   return -EINVAL;
}
 
cgs_write_register(hwmgr->device, indirect_port, index);
-   phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
+   return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
 }
 
+int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+   uint32_t index,
+   uint32_t value, uint32_t mask)
+{
+   uint32_t i;
+   uint32_t cur_value;
 
+   if (hwmgr == NULL || hwmgr->device == NULL)
+   return -EINVAL;
+
+   for (i = 0; i < hwmgr->usec_timeout; i++) {
+   cur_value = cgs_read_register(hwmgr->device,
+   index);
+   if ((cur_value & mask) != (value & mask))
+   break;
+   udelay(1);
+   }
+
+   /* timeout means wrong logic */
+   if (i == hwmgr->usec_timeout)
+   return -ETIME;
+   return 0;
+}
+
+int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
+   uint32_t indirect_port,
+   uint32_t index,
+   uint32_t value,
+   uint32_t mask)
+{
+   if (hwmgr == NULL || hwmgr->device == NULL)
+   return -EINVAL;
+
+   cgs_write_register(hwmgr->device, indirect_port, index);
+   return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
+   value, mask);
+}
 
 bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index f2e01e4..4553149 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -786,12 +786,19 @@ extern int hwmgr_handle_task(struct pp_instance *handle,
 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
uint32_t value, uint32_t mask);
 
-extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
uint32_t mask);
 
+extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+   uint32_t index,
+   uint32_t value, uint32_t mask);
+extern int phm_wait_for_indirect_register_unequal(
+   struct pp_hwmgr *hwmgr,
+   uint32_t indirect_port, uint32_t index,
+   uint32_t value, uint32_t mask);
 
 
 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
@@ -876,5 +883,4 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr 
*hwmgr, uint8_t voltage_t
PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, 
field))
 
-
 #endif /* _HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index f9afe88..b98ade6 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -79,7 +79,7 @@ static uint32_t 

[PATCH 02/18] drm/amd/powerplay: delete dead code in hwmgr.h

[Rex Zhu]

Change-Id: I82f9d6e6d59609d47124e868c53e1cc7717c45d1
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index f4b6f0e..dc37dd9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -61,10 +61,6 @@ struct vi_dpm_table {
struct vi_dpm_level dpm_level[1];
 };
 
-enum PP_Result {
-   PP_Result_TableImmediateExit = 0x13,
-};
-
 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
 #define PCIE_PERF_REQ_FORCE_LOWPOWER1
 #define PCIE_PERF_REQ_GEN1 2
@@ -103,13 +99,6 @@ enum PHM_BackEnd_Magic {
PHM_Rv_Magic  = 0x20161121
 };
 
-
-#define PHM_PCIE_POWERGATING_TARGET_GFX0
-#define PHM_PCIE_POWERGATING_TARGET_DDI1
-#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
-#define PHM_PCIE_POWERGATING_TARGET_PHY3
-
-
 struct phm_set_power_state_input {
const struct pp_hw_power_state *pcurrent_state;
const struct pp_hw_power_state *pnew_state;
-- 
1.9.1

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Re: [PATCH] drm/amdgpu:fix uvd ring fini routine(v2)

[Christian König]

Am 20.09.2017 um 11:31 schrieb Monk Liu:

fix missing finish uvd enc_ring.
v2:
since the adev pointer check in already in ring_fini
so drop the check outsider

Change-Id: Ib74237ca5adcb3b128c9b751fced0b7db7b09e86
Signed-off-by: Monk Liu 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 331e34a..e8bd50c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -269,6 +269,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
  
  int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)

  {
+   int i;
kfree(adev->uvd.saved_bo);
  
  	amd_sched_entity_fini(>uvd.ring.sched, >uvd.entity);

@@ -279,6 +280,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
  
  	amdgpu_ring_fini(>uvd.ring);
  
+	for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)

+   amdgpu_ring_fini(>uvd.ring_enc[i]);
+
release_firmware(adev->uvd.fw);
  
  	return 0;



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[PATCH 00/18] refine smumgr code in powerplay

[Rex Zhu]

the smumgr layer is redundant in powerplay.
so delete struct smumgr, move smu callback functions and
backend data to hwmgr.
the macros SMUM_* in smumgr.h is functionally repeated
with macros PHM_* in hwmgr.h, and the macros is irrelated
to smu. so delete the macros in smumgr.h

Rex Zhu (18):
  drm/amd/powerplay: refine interface in struct pp_smumgr_func
  drm/amd/powerplay: delete dead code in hwmgr.h
  drm/amd/powerplay: refine powerplay code.
  drm/amd/powerplay: use SMU_IND_INDEX/DATA_11 pair in VFPF macros
to support virtualization
  drm/amd/powerpolay: add new helper functions in hwmgr.h
  drm/amd/powerplay: move macros to hwmgr.h
  drm/amd/powerplay: move macros to hwmgr.h
  drm/amd/powerplay: move macros to hwmgr.h
  drm/amd/powerplay: delete SMU_WRITE_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_WRITE_FIELD
  drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD
  drm/amd/powerplay: delete PHM_READ_VFPF_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_SET_FIELD
  drm/amd/powerplay: delete SMUM_READ_FIELD
  drm/amd/powerplay: move macros to hwmgr.h
  drm/amd/powerplay: delete SMUM_WAIT_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_FIELD_MASK
  drm/amd/powerplay: delete dead code in smumgr

 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  |  60 ++--
 .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c  |   8 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c |  90 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c|  63 -
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c |  26 +-
 .../amd/powerplay/hwmgr/smu7_clockpowergating.c|  60 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 139 +-
 .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c   |  26 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c |  12 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 148 +-
 .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c |  18 +-
 .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c   |  16 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 113 +++-
 drivers/gpu/drm/amd/powerplay/inc/pp_instance.h|   2 -
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 202 +-
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c  | 186 ++---
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h  |   4 +-
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c   |  14 +-
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 308 ++---
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c| 109 
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 130 -
 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c |  99 ---
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  76 ++---
 .../gpu/drm/amd/powerplay/smumgr/polaris10_smc.c   | 142 +-
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 126 -
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   | 130 -
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h   |   8 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 213 +++---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h |  36 +--
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c  | 256 -
 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c   | 124 -
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c|  64 ++---
 .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c   | 194 ++---
 .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h   |  16 +-
 34 files changed, 1493 insertions(+), 1725 deletions(-)

-- 
1.9.1

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[PATCH umr 1/2] Revert "switch over from ttm trace to iova debugfs entry (v3)"

[Tom St Denis]

This reverts commit 0e1c378fce66db833e08770d888dda1c5ec7936a.
---
 src/lib/CMakeLists.txt |   1 +
 src/lib/close_asic.c   |   2 +-
 src/lib/discover.c |   3 -
 src/lib/free_maps.c|  44 ++
 src/lib/read_vram.c| 218 -
 src/umr.h  |  14 +++-
 6 files changed, 254 insertions(+), 28 deletions(-)
 create mode 100644 src/lib/free_maps.c

diff --git a/src/lib/CMakeLists.txt b/src/lib/CMakeLists.txt
index a21fdf8eea2d..78d827ac1bf1 100644
--- a/src/lib/CMakeLists.txt
+++ b/src/lib/CMakeLists.txt
@@ -14,6 +14,7 @@ add_library(umrcore STATIC
   discover.c
   dump_ib.c
   find_reg.c
+  free_maps.c
   mmio.c
   query_drm.c
   read_sensor.c
diff --git a/src/lib/close_asic.c b/src/lib/close_asic.c
index a140409e617b..d532a11fa671 100644
--- a/src/lib/close_asic.c
+++ b/src/lib/close_asic.c
@@ -29,6 +29,7 @@
 void umr_free_asic(struct umr_asic *asic)
 {
int x;
+   umr_free_maps(asic);
if (asic->pci.mem != NULL) {
// free PCI mapping
pci_device_unmap_range(asic->pci.pdevice, asic->pci.mem, 
asic->pci.pdevice->regions[asic->pci.region].size);
@@ -56,7 +57,6 @@ void umr_close_asic(struct umr_asic *asic)
cond_close(asic->fd.vram);
cond_close(asic->fd.gpr);
cond_close(asic->fd.drm);
-   cond_close(asic->fd.iova);
umr_free_asic(asic);
}
 }
diff --git a/src/lib/discover.c b/src/lib/discover.c
index ff7950e4e6ba..dcc212fc39e4 100644
--- a/src/lib/discover.c
+++ b/src/lib/discover.c
@@ -222,8 +222,6 @@ struct umr_asic *umr_discover_asic(struct umr_options 
*options)
asic->fd.vram = open(fname, O_RDWR);
snprintf(fname, sizeof(fname)-1, 
"/sys/kernel/debug/dri/%d/amdgpu_gpr", asic->instance);
asic->fd.gpr = open(fname, O_RDWR);
-   snprintf(fname, sizeof(fname)-1, 
"/sys/kernel/debug/dri/%d/amdgpu_iova", asic->instance);
-   asic->fd.iova = open(fname, O_RDWR);
asic->fd.drm = -1; // default to closed
// if appending to the fd list remember to update 
close_asic() and discover_by_did()...
} else {
@@ -237,7 +235,6 @@ struct umr_asic *umr_discover_asic(struct umr_options 
*options)
asic->fd.vram = -1;
asic->fd.gpr = -1;
asic->fd.drm = -1;
-   asic->fd.iova = -1;
}
 
if (options->use_pci) {
diff --git a/src/lib/free_maps.c b/src/lib/free_maps.c
new file mode 100644
index ..e1d27cb177f7
--- /dev/null
+++ b/src/lib/free_maps.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis 
+ *
+ */
+#include "umr.h"
+
+static void recurse_free(struct umr_map *map)
+{
+   if (map->left)
+   recurse_free(map->left);
+   if (map->right)
+   recurse_free(map->right);
+   free(map);
+}
+
+void umr_free_maps(struct umr_asic *asic)
+{
+   if (!asic->maps)
+   return;
+
+   recurse_free(asic->maps->maps);
+   free(asic->maps);
+   asic->maps = NULL;
+}
diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index 3a327fb8e681..6e8f1f931895 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/read_vram.c
@@ -25,6 +25,163 @@
 #include "umrapp.h"
 #include 
 
+// find a mapping or create node for it
+static struct umr_map *find_map(struct umr_dma_maps *maps, uint64_t dma_addr, 
int create)
+{
+   struct umr_map *n = maps->maps, **nn;
+   uint64_t key;
+
+   // addresses aren't terribly random
+   // so if we use an identity function on the search
+   // key we'll end up with a really unbalanced tree
+   // so mix up 

[PATCH] drm/amd/amdgpu: Partial revert of iova debugfs

[Tom St Denis]

We discovered that on some devices even with iommu enabled
you can access all of system memory through the iommu translation.

Therefore, we revert the read method to the translation only service
and drop the write method completely.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 90 +
 1 file changed, 13 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0e5f78f3a97e..ce435dbbb398 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1784,98 +1784,34 @@ static ssize_t amdgpu_iova_to_phys_read(struct file *f, 
char __user *buf,
   size_t size, loff_t *pos)
 {
struct amdgpu_device *adev = file_inode(f)->i_private;
-   ssize_t result, n;
int r;
uint64_t phys;
-   void *ptr;
struct iommu_domain *dom;
 
-   dom = iommu_get_domain_for_dev(adev->dev);
-   if (!dom)
-   return -EFAULT;
-
-   result = 0;
-   while (size) {
-   // get physical address and map
-   phys = iommu_iova_to_phys(dom, *pos);
-
-   // copy upto one page
-   if (size > PAGE_SIZE)
-   n = PAGE_SIZE;
-   else
-   n = size;
-
-   // to end of the page
-   if (((*pos & (PAGE_SIZE - 1)) + n) >= PAGE_SIZE)
-   n = PAGE_SIZE - (*pos & (PAGE_SIZE - 1));
-
-   ptr = kmap(pfn_to_page(PFN_DOWN(phys)));
-   if (!ptr)
-   return -EFAULT;
-
-   r = copy_to_user(buf, ptr, n);
-   kunmap(pfn_to_page(PFN_DOWN(phys)));
-   if (r)
-   return -EFAULT;
-
-   *pos += n;
-   size -= n;
-   result += n;
-   }
-
-   return result;
-}
+   // always return 8 bytes
+   if (size != 8)
+   return -EINVAL;
 
-static ssize_t amdgpu_iova_to_phys_write(struct file *f, const char __user 
*buf,
-  size_t size, loff_t *pos)
-{
-   struct amdgpu_device *adev = file_inode(f)->i_private;
-   ssize_t result, n;
-   int r;
-   uint64_t phys;
-   void *ptr;
-   struct iommu_domain *dom;
+   // only accept page addresses
+   if (*pos & 0xFFF)
+   return -EINVAL;
 
dom = iommu_get_domain_for_dev(adev->dev);
-   if (!dom)
-   return -EFAULT;
-
-   result = 0;
-   while (size) {
-   // get physical address and map
+   if (dom)
phys = iommu_iova_to_phys(dom, *pos);
+   else
+   phys = *pos;
 
-   // copy upto one page
-   if (size > PAGE_SIZE)
-   n = PAGE_SIZE;
-   else
-   n = size;
-
-   // to end of the page
-   if (((*pos & (PAGE_SIZE - 1)) + n) >= PAGE_SIZE)
-   n = PAGE_SIZE - (*pos & (PAGE_SIZE - 1));
-
-   ptr = kmap(pfn_to_page(PFN_DOWN(phys)));
-   if (!ptr)
-   return -EFAULT;
-
-   r = copy_from_user(ptr, buf, n);
-   kunmap(pfn_to_page(PFN_DOWN(phys)));
-   if (r)
-   return -EFAULT;
-
-   *pos += n;
-   size -= n;
-   result += n;
-   }
+   r = copy_to_user(buf, , 8);
+   if (r)
+   return -EFAULT;
 
-   return result;
+   return 8;
 }
 
 static const struct file_operations amdgpu_ttm_iova_fops = {
.owner = THIS_MODULE,
.read = amdgpu_iova_to_phys_read,
-   .write = amdgpu_iova_to_phys_write,
.llseek = default_llseek
 };
 
-- 
2.12.0

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Re: [PATCH] drm/amd/amdgpu: Fix iova debugfs for non-iommu case

[Tom St Denis]

On 20/09/17 03:07 AM, Christian König wrote:

Am 19.09.2017 um 23:38 schrieb Tom St Denis:

On 19/09/17 02:33 PM, Christian König wrote:
[root@carrizo ~]# xxd -l 1024 -s 0xC 
/sys/kernel/debug/dri/0/amdgpu_iova


Actually 0xC is a special address, e.g. video BIOS if I'm not 
completely mistaken.


Not sure  why that would be mapped by the driver but I can also read 
the kernel's bss section with this...


$ xxd -l 1048576 -s 0x01e4c000 /sys/kernel/debug/dri/0/amdgpu_iova

..
01e6a430: 4c69 6e75 7820 7665 7273 696f 6e20 342e  Linux version 4.
01e6a440: 3133 2e30 2d72 6335 2b20 2872 6f6f 7440  13.0-rc5+ (root@
01e6a450: 6361 7272 697a 6f29 2028 6763 6320 7665  carrizo) (gcc ve
01e6a460: 7273 696f 6e20 362e 332e 3120 3230 3136  rsion 6.3.1 2016
01e6a470: 3132 3231 2028 5265 6420 4861 7420 362e  1221 (Red Hat 6.
01e6a480: 332e 312d 3129 2028 4743 4329 2920 2333  3.1-1) (GCC)) #3
01e6a490: 3120 534d 5020 5475 6520 5365 7020 3139  1 SMP Tue Sep 19
01e6a4a0: 2030 373a 3138 3a33 3120 4544 5420 3230   07:18:31 EDT 20


That's part of the dmesg buffer apparently.

I pointed it at all sorts of address (bios/system ram/etc) it pretty 
much will read anything.


Yeah, feared that this would be the case. OK in this case your original 
concern was completely correct and we can't allow this in general.



Which means we want to go to a different v2 of this patch

https://lists.freedesktop.org/archives/amd-gfx/2017-September/013329.html

Where I check if domain==NULL and return the input or use the 
iova_to_phys to translate.


Then in umr I have to revert the last commit on master and apply the 
original patch I had sent to the list:


https://lists.freedesktop.org/archives/amd-gfx/2017-September/013332.html


Tom
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[PATCH] drm/amdgpu:fix uvd ring fini routine(v2)

[Monk Liu]

fix missing finish uvd enc_ring.
v2:
since the adev pointer check in already in ring_fini
so drop the check outsider

Change-Id: Ib74237ca5adcb3b128c9b751fced0b7db7b09e86
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 331e34a..e8bd50c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -269,6 +269,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 
 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 {
+   int i;
kfree(adev->uvd.saved_bo);
 
amd_sched_entity_fini(>uvd.ring.sched, >uvd.entity);
@@ -279,6 +280,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 
amdgpu_ring_fini(>uvd.ring);
 
+   for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
+   amdgpu_ring_fini(>uvd.ring_enc[i]);
+
release_firmware(adev->uvd.fw);
 
return 0;
-- 
2.7.4

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RE: [PATCH 0/4] some changes for thermal interrupts

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Eric Huang
> Sent: Tuesday, September 19, 2017 2:07 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, JinHuiEric
> Subject: [PATCH 0/4] some changes for thermal interrupts
> 
> Eric Huang (4):
>   drm/amdgpu: add cgs query info of pci bus devfn
>   drm/amd/powerplay: add register thermal interrupt in hwmgr_hw_init
>   drm/amd/powerplay: implement register thermal interrupt for Vega10
>   drm/amd/powerplay: change alert temperature range

Series is:
Reviewed-by: Alex Deucher 

> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c|  3 +
>  drivers/gpu/drm/amd/include/cgs_common.h   |  1 +
>  .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  4 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 75
> +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 33
> ++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  6 ++
>  6 files changed, 119 insertions(+), 3 deletions(-)
> 
> --
> 2.7.4
> 
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Re: [PATCH] drm/amd/amdgpu: Fix iova debugfs for non-iommu case

[Christian König]

Am 19.09.2017 um 23:38 schrieb Tom St Denis:

On 19/09/17 02:33 PM, Christian König wrote:
[root@carrizo ~]# xxd -l 1024 -s 0xC 
/sys/kernel/debug/dri/0/amdgpu_iova


Actually 0xC is a special address, e.g. video BIOS if I'm not 
completely mistaken.


Not sure  why that would be mapped by the driver but I can also read 
the kernel's bss section with this...


$ xxd -l 1048576 -s 0x01e4c000 /sys/kernel/debug/dri/0/amdgpu_iova

..
01e6a430: 4c69 6e75 7820 7665 7273 696f 6e20 342e  Linux version 4.
01e6a440: 3133 2e30 2d72 6335 2b20 2872 6f6f 7440  13.0-rc5+ (root@
01e6a450: 6361 7272 697a 6f29 2028 6763 6320 7665  carrizo) (gcc ve
01e6a460: 7273 696f 6e20 362e 332e 3120 3230 3136  rsion 6.3.1 2016
01e6a470: 3132 3231 2028 5265 6420 4861 7420 362e  1221 (Red Hat 6.
01e6a480: 332e 312d 3129 2028 4743 4329 2920 2333  3.1-1) (GCC)) #3
01e6a490: 3120 534d 5020 5475 6520 5365 7020 3139  1 SMP Tue Sep 19
01e6a4a0: 2030 373a 3138 3a33 3120 4544 5420 3230   07:18:31 EDT 20


That's part of the dmesg buffer apparently.

I pointed it at all sorts of address (bios/system ram/etc) it pretty 
much will read anything.


Yeah, feared that this would be the case. OK in this case your original 
concern was completely correct and we can't allow this in general.


Christian.



Tom
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Re: [PATCH 1/2] drm/amd/amgpu: update raven sdma golden setting

[Zhang, Jerry (Junwei)]

On 09/20/2017 02:22 PM, Evan Quan wrote:

Change-Id: Ia41bf64501557723fa811ad98a7b5630f12d9ed8
Signed-off-by: Evan Quan 

Reviewed-by: Junwei Zhang 


---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fd7c72a..2b2316a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -89,7 +89,7 @@ static const u32 golden_settings_sdma_vg10[] = {

  static const u32 golden_settings_sdma_4_1[] =
  {
-   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 
0x02831f07,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 
0x02831d07,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0x, 0x3f000100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x0100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfff7, 
0x00403000,


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RE: [PATCH 2/3] drm/amdgpu/sriov:fix memory leak after gpu reset

[Liu, Monk]

No ,we cannot do this in SW init, because PSP need all other component finish 
their HW init and get the fw_size, before it can call ucode_init, so if we put 
this in SW init, the fw_size is still 0


BR Monk

-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] 
Sent: 2017年9月19日 19:44
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/amdgpu/sriov:fix memory leak after gpu reset

Am 19.09.2017 um 08:41 schrieb Monk Liu:
> GPU reset will require all hw doing hw_init thus ucode_init_bo will be 
> invoked again, which lead to memory leak
>
> skip the fw_buf allocation during sriov gpu reset to avoid memory 
> leak.
>
> Change-Id: I31131eda1bd45ea2f5bdc50c5da5fc5a9fe9027d
> Signed-off-by: Monk Liu 

Acked-by: Christian König  for now.

But we should really clean this up and do the allocation during SW init.

Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 64 
> +++
>   2 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 6ff2959..3d0c633 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1185,6 +1185,9 @@ struct amdgpu_firmware {
>   
>   /* gpu info firmware data pointer */
>   const struct firmware *gpu_info_fw;
> +
> + void *fw_buf_ptr;
> + uint64_t fw_buf_mc;
>   };
>   
>   /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> index f306374..6564902 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> @@ -360,8 +360,6 @@ static int amdgpu_ucode_patch_jt(struct 
> amdgpu_firmware_info *ucode,
>   int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
>   {
>   struct amdgpu_bo **bo = >firmware.fw_buf;
> - uint64_t fw_mc_addr;
> - void *fw_buf_ptr = NULL;
>   uint64_t fw_offset = 0;
>   int i, err;
>   struct amdgpu_firmware_info *ucode = NULL; @@ -372,37 +370,39 @@ 
> int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
>   return 0;
>   }
>   
> - err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
> - amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM 
> : AMDGPU_GEM_DOMAIN_GTT,
> - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
> - NULL, NULL, 0, bo);
> - if (err) {
> - dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", 
> err);
> - goto failed;
> - }
> + if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
> + err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, 
> true,
> + amdgpu_sriov_vf(adev) ? 
> AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
> + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
> + NULL, NULL, 0, bo);
> + if (err) {
> + dev_err(adev->dev, "(%d) Firmware buffer allocate 
> failed\n", err);
> + goto failed;
> + }
>   
> - err = amdgpu_bo_reserve(*bo, false);
> - if (err) {
> - dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", 
> err);
> - goto failed_reserve;
> - }
> + err = amdgpu_bo_reserve(*bo, false);
> + if (err) {
> + dev_err(adev->dev, "(%d) Firmware buffer reserve 
> failed\n", err);
> + goto failed_reserve;
> + }
>   
> - err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM 
> : AMDGPU_GEM_DOMAIN_GTT,
> - _mc_addr);
> - if (err) {
> - dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
> - goto failed_pin;
> - }
> + err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? 
> AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
> + >firmware.fw_buf_mc);
> + if (err) {
> + dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", 
> err);
> + goto failed_pin;
> + }
>   
> - err = amdgpu_bo_kmap(*bo, _buf_ptr);
> - if (err) {
> - dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
> - goto failed_kmap;
> - }
> + err = amdgpu_bo_kmap(*bo, >firmware.fw_buf_ptr);
> + if (err) {
> + dev_err(adev->dev, "(%d) Firmware buffer kmap 
> failed\n", err);
> + goto failed_kmap;
> + }
>   
> - amdgpu_bo_unreserve(*bo);
> + amdgpu_bo_unreserve(*bo);
> + }
>   
> - memset(fw_buf_ptr, 0, 

[PATCH 2/2] drm/amd/amgpu: update vega10 sdma golden setting

[Evan Quan]

Change-Id: I96cd1d463a5743f918a03cad5160ea0bbd908ad0
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 2b2316a..7d41e11 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -54,7 +54,7 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device 
*adev);
 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
 
 static const u32 golden_settings_sdma_4[] = {
-   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 
0x02831f07,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 
0x02831d07,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x0100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfff7, 
0x00403000,
-- 
2.7.4

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