date:20170929

[PATCH] drm/amdgpu: Reserve shared memory on VRAM for SR-IOV

2017-09-29 Thread Horace Chen

SR-IOV need to reserve a piece of shared VRAM at the exact place
to exchange data betweem PF and VF. The start address and size of
the shared mem are passed to guest through VBIOS structure
VRAM_UsageByFirmware.

VRAM_UsageByFirmware is a general feature in VBIOS, it indicates
that VBIOS need to reserve a piece of memory on the VRAM.

Because the mem address is specified. Reserve it early in
amdgpu_ttm_init to make sure that it can monoplize the space.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 14 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 18 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 80 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  9 
 4 files changed, 120 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a5b0b67..7bbc51f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1380,6 +1380,18 @@ struct amdgpu_atcs {
 };
 
 /*
+ * Firmware VRAM reservation
+ */
+struct amdgpu_fw_vram_usage {
+   u64 start_offset;
+   u64 size;
+   struct amdgpu_bo *reserved_bo;
+   void *va;
+};
+
+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
+
+/*
  * CGS
  */
 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
@@ -1588,6 +1600,8 @@ struct amdgpu_device {
struct delayed_work late_init_work;
 
struct amdgpu_virt  virt;
+   /* firmware VRAM reservation */
+   struct amdgpu_fw_vram_usage fw_vram_usage;
 
/* link all shadow bo */
struct list_headshadow_list;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index ce44358..f66d33e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1807,6 +1807,8 @@ int amdgpu_atombios_allocate_fb_scratch(struct 
amdgpu_device *adev)
uint16_t data_offset;
int usage_bytes = 0;
struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
+   u64 start_addr;
+   u64 size;
 
if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, 
_offset)) {
firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE 
*)(ctx->bios + data_offset);
@@ -1815,7 +1817,21 @@ int amdgpu_atombios_allocate_fb_scratch(struct 
amdgpu_device *adev)
  
le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
  
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
 
-   usage_bytes = 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 
1024;
+   start_addr = 
firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
+   size = 
firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
+
+   if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 
<<
+   ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->fw_vram_usage.start_offset = (start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->fw_vram_usage.size = size << 10;
+   /* Use the default scratch size */
+   usage_bytes = 0;
+   } else {
+   usage_bytes = 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 
1024;
+   }
}
ctx->scratch_size_bytes = 0;
if (usage_bytes == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a86d856..c7f6d2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -658,6 +658,85 @@ void amdgpu_gart_location(struct amdgpu_device *adev, 
struct amdgpu_mc *mc)
 }
 
 /*
+ * Firmware Reservation function
+ */
+/**
+ * amdgpu_fw_reserve_vram_fini - free fw reserved vram
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * free fw reserved vram if it has been reserved.
+ */
+void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
+{
+
+   if (adev->fw_vram_usage.reserved_bo == NULL)
+   return;
+
+   amdgpu_bo_free_kernel(>fw_vram_usage.reserved_bo,
+   NULL, >fw_vram_usage.va);
+}
+
+/**
+ * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * create bo vram reservation from fw.
+ */
+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
+{
+   int r = 0;
+   u64 gpu_addr;
+   u64 vram_size = adev->mc.visible_vram_size;
+
+   adev->fw_vram_usage.va =

Recall: [PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread Zhu, Rex

Zhu, Rex would like to recall the message, "[PATCH] drm/amdgpu: correct 
reference clock value on vega10".
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RE: [PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread Zhu, Rex

Reviewed-by:
Rex Zhu 

Best Regards
Rex
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
ken.w...@amd.com
Sent: Friday, September 29, 2017 4:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject: [PATCH] drm/amdgpu: correct reference clock value on vega10

From: Ken Wang 

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)  static u32 soc15_get_xclk(struct amdgpu_device *adev)  {
if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
+   return 27000;
else
return adev->clock.spll.reference_freq;  }
--
2.7.4

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RE: [amd-staging-drm-next] regression - no fan info (sensors) on RX580

2017-09-29 Thread Zhu, Rex

Yes, caused by the commit e37a7b4088da
("drm/amd/powerplay: tidy up ret checks in amd_powerplay.c")

Replace error when split patches.

Have sent the fix patch.
Please review.

Best Regards
Rex 


-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com] 
Sent: Friday, September 29, 2017 10:11 PM
To: Dieter Nützel; Zhu, Rex
Cc: amd-devel; DRI Devel; Wentland, Harry; Michel Dänzer
Subject: Re: [amd-staging-drm-next] regression - no fan info (sensors) on RX580

Rex, probably related to the recent cleanups in powerplay.

On Fri, Sep 29, 2017 at 10:09 AM, Dieter Nützel  wrote:
> Hello all,
>
> since latest update
>
> 1d7da702e70d3c27408a3bb312c71d6be9f7bebe
> drm/amd/powerplay: fix spelling mistake: "dividable" -> "divisible"
>
> I didn't get fan info with my RX580 (Polaris21) any longer.
>
> Worked with this commit:
>
> 786df0b89fe5a0b405d4de0a1ce03003c0743ec3
> drm/amd/display: fix pflip irq registor for raven
>
> Sorry, I do not have full time for bisect, because we are on way to 
> our vacation.
>
> Maybe in the evening (only a few commits).
>
> Greetings,
> Dieter
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[PATCH 2/2] drm/amd/powerplay: fix ret checks in amd_powerplay.c

2017-09-29 Thread Rex Zhu

regresstion issue caused by

commit e37a7b4088da
("drm/amd/powerplay: tidy up ret checks in amd_powerplay.c")

Change-Id: I46be14d8230ad7bc9039782a56a94bb060a21423
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 74 +--
 1 file changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 586cab7..f3f303e 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -230,7 +230,7 @@ static int pp_set_powergating_state(void *handle,
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -378,7 +378,7 @@ static int pp_dpm_force_performance_level(void *handle,
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -396,7 +396,7 @@ static int pp_dpm_force_performance_level(void *handle,
hwmgr->request_dpm_level = level;
hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, 
NULL);
ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
-   if (!ret)
+   if (ret)
hwmgr->dpm_level = hwmgr->request_dpm_level;
 
mutex_unlock(_handle->pp_lock);
@@ -413,7 +413,7 @@ static enum amd_dpm_forced_level 
pp_dpm_get_performance_level(
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -432,7 +432,7 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -456,7 +456,7 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -479,7 +479,7 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return;
 
hwmgr = pp_handle->hwmgr;
@@ -501,7 +501,7 @@ static void pp_dpm_powergate_uvd(void *handle, bool gate)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return;
 
hwmgr = pp_handle->hwmgr;
@@ -523,7 +523,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum 
amd_pp_task task_id,
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
mutex_lock(_handle->pp_lock);
@@ -543,7 +543,7 @@ static enum amd_pm_state_type 
pp_dpm_get_current_power_state(void *handle)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -585,7 +585,7 @@ static void pp_dpm_set_fan_control_mode(void *handle, 
uint32_t mode)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return;
 
hwmgr = pp_handle->hwmgr;
@@ -608,7 +608,7 @@ static uint32_t pp_dpm_get_fan_control_mode(void *handle)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -631,7 +631,7 @@ static int pp_dpm_set_fan_speed_percent(void *handle, 
uint32_t percent)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -654,7 +654,7 @@ static int pp_dpm_get_fan_speed_percent(void *handle, 
uint32_t *speed)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -678,7 +678,7 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t 
*rpm)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -700,7 +700,7 @@ static int pp_dpm_get_temperature(void *handle)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -725,7 +725,7 @@ static int pp_dpm_get_pp_num_states(void *handle,
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -770,7 +770,7 @@ static int pp_dpm_get_pp_table(void *handle, char **table)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -813,7 +813,7 @@ static int pp_dpm_set_pp_table(void *handle, const char 
*buf, size_t size)
 
ret = pp_check(pp_handle);
 
-   if (!ret)
+   if (ret)
return ret;
 
hwmgr = pp_handle->hwmgr;
@@ -855,7 +855,7 @@ static int

[PATCH 1/2] drm/amd/powerplay: fix a logic error in pp_hw_init

2017-09-29 Thread Rex Zhu

Change-Id: I8607e51a0e4153b36268e2bcf4fe594c2bfbfe23
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index df70cc7..586cab7 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -163,12 +163,11 @@ static int pp_hw_init(void *handle)
}
if (ret == PP_DPM_DISABLED)
goto exit;
+   ret = hwmgr_hw_init(pp_handle);
+   if (ret)
+   goto exit;
}
-
-   ret = hwmgr_hw_init(pp_handle);
-   if (ret)
-   goto exit;
-   return 0;
+   return ret;
 exit:
pp_handle->pm_en = 0;
cgs_notify_dpm_enabled(hwmgr->device, false);
-- 
1.9.1

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RE: [PATCH] drm/amd/powerplay: fix a warning in pp_hw_init

2017-09-29 Thread Zhu, Rex

Hi Alex,

Thanks for pointing out the logic error in pp_hw_init.
Please review the attached patch.

Best Regards
Rex



-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Alex 
Deucher
Sent: Saturday, September 30, 2017 12:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amd/powerplay: fix a warning in pp_hw_init

Make sure hwmgr is valid.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 44b0616..e96ab0b 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -146,7 +146,7 @@ static int pp_hw_init(void *handle)  {
int ret = 0;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
-   struct pp_hwmgr *hwmgr;
+   struct pp_hwmgr *hwmgr = NULL;
 
ret = pp_check(pp_handle);
 
@@ -171,7 +171,8 @@ static int pp_hw_init(void *handle)
return 0;
 exit:
pp_handle->pm_en = 0;
-   cgs_notify_dpm_enabled(hwmgr->device, false);
+   if (hwmgr)
+   cgs_notify_dpm_enabled(hwmgr->device, false);
return 0;
 
 }
--
2.5.5

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0001-drm-amd-powerplay-fix-a-logic-error-in-pp_hw_init.patch
Description: 0001-drm-amd-powerplay-fix-a-logic-error-in-pp_hw_init.patch
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Re: [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper

2017-09-29 Thread Chunming Zhou




On 2017年09月29日 20:37, Marek Olšák wrote:

On Fri, Sep 29, 2017 at 4:12 AM, Chunming Zhou  wrote:


On 2017年09月29日 06:10, Marek Olšák wrote:

From: Marek Olšák 

---
   include/drm/drm.h | 24 
   xf86drm.c | 22 ++
   xf86drm.h |  3 +++
   3 files changed, 49 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index bf3674a..4da1667 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -687,38 +687,57 @@ struct drm_prime_handle {
 /** Flags.. only applicable for handle->fd */
 __u32 flags;
 /** Returned dmabuf file descriptor */
 __s32 fd;
   };
 struct drm_syncobj_create {
 __u32 handle;
+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
 __u32 flags;
   };
 struct drm_syncobj_destroy {
 __u32 handle;
 __u32 pad;
   };
 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
   #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)

Typo for '(1 << 1)' ?

No, this was copied from kernel headers.
Yes, I double checked just now, that's two separate ioctls use them, so 
they are safe.


Sorry for noise of this.

David Zhou



With that fixes, the set is Reviewed-by: Chunming Zhou 

Thanks.

Marek


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Re: [PATCH 1/3] drm/syncobj: extract two helpers from drm_syncobj_create

2017-09-29 Thread Chunming Zhou


My mean is like the attached, I revert part of yours.

Regards,

David zhou


On 2017年09月29日 22:15, Marek Olšák wrote:

On Fri, Sep 29, 2017 at 4:13 PM, Marek Olšák  wrote:

On Fri, Sep 29, 2017 at 4:44 AM, Chunming Zhou  wrote:


On 2017年09月13日 04:42, Marek Olšák wrote:

From: Marek Olšák 

For amdgpu.

drm_syncobj_create is renamed to drm_syncobj_create_as_handle, and new
helpers drm_syncobj_create and drm_syncobj_get_handle are added.

Signed-off-by: Marek Olšák 
---
   drivers/gpu/drm/drm_syncobj.c | 49
+++
   include/drm/drm_syncobj.h |  4 
   2 files changed, 49 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 0422b8c..0bb1741 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -262,8 +262,14 @@ void drm_syncobj_free(struct kref *kref)
   }
   EXPORT_SYMBOL(drm_syncobj_free);
   -static int drm_syncobj_create(struct drm_file *file_private,
- u32 *handle, uint32_t flags)

You can add a new parameter for passing dma fence, then in patch3, you can
directly use it for AMDGPU_FENCE_TO HANDLE_GET_SYNCOBJ.

otherwise the set looks good to me.

Sorry I just pushed this.

Actually, you commented on a deleted line. The function already has
dma_fence among the parameters.

Marek


>From a34c466f4a8617c18bf191d83bff3a3382166b00 Mon Sep 17 00:00:00 2001
From: Chunming Zhou 
Date: Sat, 30 Sep 2017 09:53:53 +0800
Subject: [PATCH] drm: Don't split drm_syncobj_create

Change-Id: Icc6e4d8e94236675d6267d211e53698834d29869
Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  6 +
 drivers/gpu/drm/drm_syncobj.c  | 42 +-
 include/drm/drm_syncobj.h  |  7 +++---
 3 files changed, 10 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ab83dfc..882becc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1351,14 +1351,10 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
 
 	switch (info->in.what) {
 	case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
-		r = drm_syncobj_create(, 0, fence);
+		r = drm_syncobj_create(filp, fence, >out.handle, 0);
 		dma_fence_put(fence);
 		if (r)
 			return r;
-		r = drm_syncobj_get_handle(filp, syncobj, >out.handle);
-		drm_syncobj_put(syncobj);
-		return r;
-
 	case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
 		r = drm_syncobj_create(, 0, fence);
 		dma_fence_put(fence);
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 62adc7a..28e1463 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -268,8 +268,9 @@ EXPORT_SYMBOL(drm_syncobj_free);
  * @flags: DRM_SYNCOBJ_* flags
  * @fence: if non-NULL, the syncobj will represent this fence
  */
-int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
-		   struct dma_fence *fence)
+int drm_syncobj_create(struct drm_file *file_private,
+		   struct dma_fence *fence,
+		   u32 *handle, uint32_t flags)
 {
 	int ret;
 	struct drm_syncobj *syncobj;
@@ -293,22 +294,6 @@ int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
 	if (fence)
 		drm_syncobj_replace_fence(syncobj, fence);
 
-	*out_syncobj = syncobj;
-	return 0;
-}
-EXPORT_SYMBOL(drm_syncobj_create);
-
-/**
- * drm_syncobj_get_handle - get a handle from a syncobj
- */
-int drm_syncobj_get_handle(struct drm_file *file_private,
-			   struct drm_syncobj *syncobj, u32 *handle)
-{
-	int ret;
-
-	/* take a reference to put in the idr */
-	drm_syncobj_get(syncobj);
-
 	idr_preload(GFP_KERNEL);
 	spin_lock(_private->syncobj_table_lock);
 	ret = idr_alloc(_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT);
@@ -324,22 +309,7 @@ int drm_syncobj_get_handle(struct drm_file *file_private,
 	*handle = ret;
 	return 0;
 }
-EXPORT_SYMBOL(drm_syncobj_get_handle);
-
-static int drm_syncobj_create_as_handle(struct drm_file *file_private,
-	u32 *handle, uint32_t flags)
-{
-	int ret;
-	struct drm_syncobj *syncobj;
-
-	ret = drm_syncobj_create(, flags, NULL);
-	if (ret)
-		return ret;
-
-	ret = drm_syncobj_get_handle(file_private, syncobj, handle);
-	drm_syncobj_put(syncobj);
-	return ret;
-}
+EXPORT_SYMBOL(drm_syncobj_create);
 
 static int drm_syncobj_destroy(struct drm_file *file_private,
 			   u32 handle)
@@ -568,8 +538,8 @@ drm_syncobj_create_ioctl(struct drm_device *dev, void *data,
 	if (args->flags & ~DRM_SYNCOBJ_CREATE_SIGNALED)
 		return -EINVAL;
 
-	return drm_syncobj_create_as_handle(file_private,
-	>handle, args->flags);
+	return drm_syncobj_create(file_private, NULL,
+  >handle, args->flags);
 }
 
 int
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index

[PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels

2017-09-29 Thread Evan Quan

Change-Id: I40fa698cd9a25df43aa4bf476c4aa0a8b043edf9
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 48 +-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index a20a6fe..5135328 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -619,7 +619,53 @@ static int rv_force_clock_level(struct pp_hwmgr *hwmgr,
 static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
 {
-   return 0;
+   struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
+   struct rv_voltage_dependency_table *mclk_table =
+   data->clock_vol_info.vdd_dep_on_fclk;
+   int i, now, size = 0;
+
+   switch (type) {
+   case PP_SCLK:
+   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_GetGfxclkFrequency),
+   "Attempt to get current GFXCLK Failed!",
+   return -1);
+   PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+   ),
+   "Attempt to get current GFXCLK Failed!",
+   return -1);
+
+   size += sprintf(buf + size, "0: %uMhz %s\n",
+   data->gfx_min_freq_limit / 100,
+   ((data->gfx_min_freq_limit / 100)
+== now) ? "*" : "");
+   size += sprintf(buf + size, "1: %uMhz %s\n",
+   data->gfx_max_freq_limit / 100,
+   ((data->gfx_max_freq_limit / 100)
+== now) ? "*" : "");
+   break;
+   case PP_MCLK:
+   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_GetFclkFrequency),
+   "Attempt to get current MEMCLK Failed!",
+   return -1);
+   PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+   ),
+   "Attempt to get current MEMCLK Failed!",
+   return -1);
+
+   for (i = 0; i < mclk_table->count; i++)
+   size += sprintf(buf + size, "%d: %uMhz %s\n",
+   i,
+   mclk_table->entries[i].clk / 100,
+   ((mclk_table->entries[i].clk / 100)
+== now) ? "*" : "");
+   break;
+   default:
+   break;
+   }
+
+   return size;
 }
 
 static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct 
pp_hw_power_state *state,
-- 
2.7.4

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Re: [PATCH 1/4] drm/amd/powerplay: added new raven ppsmc messages

2017-09-29 Thread Zhang, Jerry (Junwei)


On 09/30/2017 09:10 AM, Evan Quan wrote:

Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
Signed-off-by: Evan Quan 

the series is
Reviewed-by: Junwei Zhang 


---
  drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 901c960c..2b34971 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -70,7 +70,12 @@
  #define PPSMC_MSG_SetPhyclkVoltageByFreq0x26
  #define PPSMC_MSG_SetDppclkVoltageByFreq0x27
  #define PPSMC_MSG_SetSoftMinVcn 0x28
-#define PPSMC_Message_Count 0x29
+#define PPSMC_MSG_GetGfxclkFrequency0x2A
+#define PPSMC_MSG_GetFclkFrequency  0x2B
+#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
+#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
+#define PPSMC_MSG_SoftReset 0x2E
+#define PPSMC_Message_Count 0x2F


  typedef uint16_t PPSMC_Result;


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RE: [PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: Evan Quan [mailto:evan.q...@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels
> 

Add a better patch description.  Something like:
Add query for sclk and mclk to the sysfs interface.

> Change-Id: I40fa698cd9a25df43aa4bf476c4aa0a8b043edf9
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 48
> +-
>  1 file changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index a20a6fe..5135328 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -619,7 +619,53 @@ static int rv_force_clock_level(struct pp_hwmgr
> *hwmgr,
>  static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>   enum pp_clock_type type, char *buf)
>  {
> - return 0;
> + struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
> + struct rv_voltage_dependency_table *mclk_table =
> + data->clock_vol_info.vdd_dep_on_fclk;
> + int i, now, size = 0;
> +
> + switch (type) {
> + case PP_SCLK:
> +
>   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> + PPSMC_MSG_GetGfxclkFrequency),
> + "Attempt to get current GFXCLK Failed!",
> + return -1);
> + PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr-
> >smumgr,
> + ),
> + "Attempt to get current GFXCLK Failed!",
> + return -1);
> +
> + size += sprintf(buf + size, "0: %uMhz %s\n",
> + data->gfx_min_freq_limit / 100,
> + ((data->gfx_min_freq_limit / 100)
> +  == now) ? "*" : "");
> + size += sprintf(buf + size, "1: %uMhz %s\n",
> + data->gfx_max_freq_limit / 100,
> + ((data->gfx_max_freq_limit / 100)
> +  == now) ? "*" : "");
> + break;
> + case PP_MCLK:
> +
>   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> + PPSMC_MSG_GetFclkFrequency),
> + "Attempt to get current MEMCLK Failed!",
> + return -1);
> + PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr-
> >smumgr,
> + ),
> + "Attempt to get current MEMCLK Failed!",
> + return -1);

Return proper error codes in this function.

With the above comments fixed:
Reviewed-by: Alex Deucher 

> +
> + for (i = 0; i < mclk_table->count; i++)
> + size += sprintf(buf + size, "%d: %uMhz %s\n",
> + i,
> + mclk_table->entries[i].clk / 100,
> + ((mclk_table->entries[i].clk / 100)
> +  == now) ? "*" : "");
> + break;
> + default:
> + break;
> + }
> +
> + return size;
>  }
> 
>  static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct
> pp_hw_power_state *state,
> --
> 2.7.4

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RE: [PATCH 3/4] drm/amd/powerplay: get raven current sclk and mclk

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: Evan Quan [mailto:evan.q...@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 3/4] drm/amd/powerplay: get raven current sclk and mclk
> 
> Change-Id: I17120a53bc3cebd8cc7eb9f3d83124905632a409
> Signed-off-by: Evan Quan 

Add a better patch description.  Something like:
Add sclk and mclk support to the read sensors interface

With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 28
> --
>  1 file changed, 26 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index e2ad41d..a20a6fe 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -850,13 +850,37 @@ static int rv_thermal_get_temperature(struct
> pp_hwmgr *hwmgr)
>  static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
> void *value, int *size)
>  {
> + uint32_t sclk, mclk;
> + int ret = 0;
> +
>   switch (idx) {
> + case AMDGPU_PP_SENSOR_GFX_SCLK:
> + ret = smum_send_msg_to_smc(hwmgr->smumgr,
> PPSMC_MSG_GetGfxclkFrequency);
> + if (!ret) {
> + rv_read_arg_from_smc(hwmgr->smumgr, );
> + /* in units of 10KHZ */
> + *((uint32_t *)value) = sclk * 100;
> + *size = 4;
> + }
> + break;
> + case AMDGPU_PP_SENSOR_GFX_MCLK:
> + ret = smum_send_msg_to_smc(hwmgr->smumgr,
> PPSMC_MSG_GetFclkFrequency);
> + if (!ret) {
> + rv_read_arg_from_smc(hwmgr->smumgr, );
> + /* in units of 10KHZ */
> + *((uint32_t *)value) = mclk * 100;
> + *size = 4;
> + }
> + break;
>   case AMDGPU_PP_SENSOR_GPU_TEMP:
>   *((uint32_t *)value) =
> rv_thermal_get_temperature(hwmgr);
> - return 0;
> + break;
>   default:
> - return -EINVAL;
> + ret = -EINVAL;
> + break;
>   }
> +
> + return ret;
>  }
> 
>  static const struct pp_hwmgr_func rv_hwmgr_funcs = {
> --
> 2.7.4

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RE: [PATCH 1/4] drm/amd/powerplay: added new raven ppsmc messages

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: Evan Quan [mailto:evan.q...@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 1/4] drm/amd/powerplay: added new raven ppsmc
> messages
> 
> Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
> Signed-off-by: Evan Quan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> index 901c960c..2b34971 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> @@ -70,7 +70,12 @@
>  #define PPSMC_MSG_SetPhyclkVoltageByFreq0x26
>  #define PPSMC_MSG_SetDppclkVoltageByFreq0x27
>  #define PPSMC_MSG_SetSoftMinVcn 0x28
> -#define PPSMC_Message_Count 0x29
> +#define PPSMC_MSG_GetGfxclkFrequency0x2A
> +#define PPSMC_MSG_GetFclkFrequency  0x2B
> +#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
> +#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
> +#define PPSMC_MSG_SoftReset 0x2E
> +#define PPSMC_Message_Count 0x2F
> 
> 
>  typedef uint16_t PPSMC_Result;
> --
> 2.7.4

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RE: [PATCH 2/4] drm/amd/powerplay: get raven max/min gfx clocks

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: Evan Quan [mailto:evan.q...@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 2/4] drm/amd/powerplay: get raven max/min gfx clocks
> 
> Change-Id: I56e713e16b9a794857e7ecbb7ca47e0ddd727862
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 20
> 
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h |  2 ++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index 6f0b2e5..e2ad41d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -421,6 +421,26 @@ static int rv_populate_clock_table(struct pp_hwmgr
> *hwmgr)
>   rv_get_clock_voltage_dependency_table(hwmgr, 
> >vdd_dep_on_phyclk,
>   ARRAY_SIZE(VddPhyClk),
> [0]);
> 
> + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> + PPSMC_MSG_GetMinGfxclkFrequency),
> + "Attempt to get min GFXCLK Failed!",
> + return -1);
> + PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
> + ),
> + "Attempt to get min GFXCLK Failed!",
> + return -1);
> + rv_data->gfx_min_freq_limit = result * 100;
> +
> + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> + PPSMC_MSG_GetMaxGfxclkFrequency),
> + "Attempt to get max GFXCLK Failed!",
> + return -1);
> + PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
> + ),
> + "Attempt to get max GFXCLK Failed!",
> + return -1);

Return proper error codes in this function.  Maybe -EINVAL?

With that fixed:
Reviewed-by: Alex Deucher 


> + rv_data->gfx_max_freq_limit = result * 100;
> +
>   return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> index 68d61bd..9dc5030 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> @@ -283,6 +283,8 @@ struct rv_hwmgr {
>   uint32_tvclk_soft_min;
>   uint32_tdclk_soft_min;
>   uint32_tgfx_actual_soft_min_freq;
> + uint32_tgfx_min_freq_limit;
> + uint32_tgfx_max_freq_limit;
> 
>   bool   vcn_power_gated;
>   bool   vcn_dpg_mode;
> --
> 2.7.4

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[PATCH 2/4] drm/amd/powerplay: get raven max/min gfx clocks

2017-09-29 Thread Evan Quan

Change-Id: I56e713e16b9a794857e7ecbb7ca47e0ddd727862
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 20 
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h |  2 ++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 6f0b2e5..e2ad41d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -421,6 +421,26 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
rv_get_clock_voltage_dependency_table(hwmgr, >vdd_dep_on_phyclk,
ARRAY_SIZE(VddPhyClk), [0]);
 
+   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_GetMinGfxclkFrequency),
+   "Attempt to get min GFXCLK Failed!",
+   return -1);
+   PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+   ),
+   "Attempt to get min GFXCLK Failed!",
+   return -1);
+   rv_data->gfx_min_freq_limit = result * 100;
+
+   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_GetMaxGfxclkFrequency),
+   "Attempt to get max GFXCLK Failed!",
+   return -1);
+   PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+   ),
+   "Attempt to get max GFXCLK Failed!",
+   return -1);
+   rv_data->gfx_max_freq_limit = result * 100;
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index 68d61bd..9dc5030 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -283,6 +283,8 @@ struct rv_hwmgr {
uint32_tvclk_soft_min;
uint32_tdclk_soft_min;
uint32_tgfx_actual_soft_min_freq;
+   uint32_tgfx_min_freq_limit;
+   uint32_tgfx_max_freq_limit;
 
bool   vcn_power_gated;
bool   vcn_dpg_mode;
-- 
2.7.4

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Re: [PATCH] drm/amd/powerplay: fix typo on avfs disable

2017-09-29 Thread Alex Deucher

On Fri, Sep 29, 2017 at 9:15 PM, Evan Quan  wrote:
> Change-Id: I172c1e05ce026b5d600f5b3607778ab48ee2c812
> Signed-off-by: Evan Quan 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 6a85954..48de45e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2364,7 +2364,7 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, 
> bool enable)
> } else {
> PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
> false,
> -   
> data->smu_features[GNLD_AVFS].smu_feature_id),
> +   
> data->smu_features[GNLD_AVFS].smu_feature_bitmap),
> "[avfs_control] Attempt to Disable 
> AVFS feature Failed!",
> return -1);
> data->smu_features[GNLD_AVFS].enabled = false;
> --
> 2.7.4
>
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[PATCH] drm/amd/powerplay: fix typo on avfs disable

2017-09-29 Thread Evan Quan

Change-Id: I172c1e05ce026b5d600f5b3607778ab48ee2c812
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 6a85954..48de45e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2364,7 +2364,7 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, 
bool enable)
} else {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false,
-   
data->smu_features[GNLD_AVFS].smu_feature_id),
+   
data->smu_features[GNLD_AVFS].smu_feature_bitmap),
"[avfs_control] Attempt to Disable AVFS 
feature Failed!",
return -1);
data->smu_features[GNLD_AVFS].enabled = false;
-- 
2.7.4

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[PATCH 1/4] drm/amd/powerplay: added new raven ppsmc messages

2017-09-29 Thread Evan Quan

Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 901c960c..2b34971 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -70,7 +70,12 @@
 #define PPSMC_MSG_SetPhyclkVoltageByFreq0x26
 #define PPSMC_MSG_SetDppclkVoltageByFreq0x27
 #define PPSMC_MSG_SetSoftMinVcn 0x28
-#define PPSMC_Message_Count 0x29
+#define PPSMC_MSG_GetGfxclkFrequency0x2A
+#define PPSMC_MSG_GetFclkFrequency  0x2B
+#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
+#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
+#define PPSMC_MSG_SoftReset 0x2E
+#define PPSMC_Message_Count 0x2F
 
 
 typedef uint16_t PPSMC_Result;
-- 
2.7.4

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[PATCH 3/4] drm/amd/powerplay: get raven current sclk and mclk

2017-09-29 Thread Evan Quan

Change-Id: I17120a53bc3cebd8cc7eb9f3d83124905632a409
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 28 --
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index e2ad41d..a20a6fe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -850,13 +850,37 @@ static int rv_thermal_get_temperature(struct pp_hwmgr 
*hwmgr)
 static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
  void *value, int *size)
 {
+   uint32_t sclk, mclk;
+   int ret = 0;
+
switch (idx) {
+   case AMDGPU_PP_SENSOR_GFX_SCLK:
+   ret = smum_send_msg_to_smc(hwmgr->smumgr, 
PPSMC_MSG_GetGfxclkFrequency);
+   if (!ret) {
+   rv_read_arg_from_smc(hwmgr->smumgr, );
+   /* in units of 10KHZ */
+   *((uint32_t *)value) = sclk * 100;
+   *size = 4;
+   }
+   break;
+   case AMDGPU_PP_SENSOR_GFX_MCLK:
+   ret = smum_send_msg_to_smc(hwmgr->smumgr, 
PPSMC_MSG_GetFclkFrequency);
+   if (!ret) {
+   rv_read_arg_from_smc(hwmgr->smumgr, );
+   /* in units of 10KHZ */
+   *((uint32_t *)value) = mclk * 100;
+   *size = 4;
+   }
+   break;
case AMDGPU_PP_SENSOR_GPU_TEMP:
*((uint32_t *)value) = rv_thermal_get_temperature(hwmgr);
-   return 0;
+   break;
default:
-   return -EINVAL;
+   ret = -EINVAL;
+   break;
}
+
+   return ret;
 }
 
 static const struct pp_hwmgr_func rv_hwmgr_funcs = {
-- 
2.7.4

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[PATCH] amdgpu: Add deadlock detection test suit.

2017-09-29 Thread Andrey Grodzovsky

From: Andrey Grodzovsky 

Adding initial tests for locks detection when SW
scheduler FIFO is full.

The test works by submitting a batch of identical commands which make the CP
stall waiting for condition to become true. The condition is later satisfied
form a helper thread. Other events that happen during this time
might create deadlock situations. One such example is GPU reset
triggered by this stall when  amdgpu_lockup_timeout != 0.

Change-Id: Ifc3a571481a85c947b107680cf17f59187180fe0
Signed-off-by: Andrey Grodzovsky 
---
 tests/amdgpu/Makefile.am  |   6 +-
 tests/amdgpu/amdgpu_test.c|   6 ++
 tests/amdgpu/amdgpu_test.h|  15 +++
 tests/amdgpu/deadlock_tests.c | 244 ++
 4 files changed, 269 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/deadlock_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 9c02fd6..8700c4d 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -1,7 +1,8 @@
 AM_CFLAGS = \
-I $(top_srcdir)/include/drm \
-I $(top_srcdir)/amdgpu \
-   -I $(top_srcdir)
+   -I $(top_srcdir) \
+   -pthread
 
 LDADD = $(top_builddir)/libdrm.la \
$(top_builddir)/amdgpu/libdrm_amdgpu.la \
@@ -29,4 +30,5 @@ amdgpu_test_SOURCES = \
frame.h \
uvd_enc_tests.c \
vcn_tests.c \
-   uve_ib.h
+   uve_ib.h \
+   deadlock_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index cd6b826..9925503 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -97,6 +97,12 @@ static CU_SuiteInfo suites[] = {
.pCleanupFunc = suite_uvd_enc_tests_clean,
.pTests = uvd_enc_tests,
},
+   {
+   .pName = "Deadlock Tests",
+   .pInitFunc = suite_deadlock_tests_init,
+   .pCleanupFunc = suite_deadlock_tests_clean,
+   .pTests = deadlock_tests,
+   },
CU_SUITE_INFO_NULL,
 };
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index d0b61ba..ece93f4 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -135,6 +135,21 @@ int suite_uvd_enc_tests_clean();
 extern CU_TestInfo uvd_enc_tests[];
 
 /**
+ * Initialize deadlock test suite
+ */
+int suite_deadlock_tests_init();
+
+/**
+ * Deinitialize deadlock test suite
+ */
+int suite_deadlock_tests_clean();
+
+/**
+ * Tests in uvd enc test suite
+ */
+extern CU_TestInfo deadlock_tests[];
+
+/**
  * Helper functions
  */
 static inline amdgpu_bo_handle gpu_mem_alloc(
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
new file mode 100644
index 000..992d191
--- /dev/null
+++ b/tests/amdgpu/deadlock_tests.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+#include 
+#ifdef HAVE_ALLOCA_H
+# include 
+#endif
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+
+#include 
+
+
+/*
+ * This defines the delay in MS after which memory location designated for
+ * compression against reference value is written to, unblocking command
+ * processor
+ */
+#define WRITE_MEM_ADDRESS_DELAY_MS 2
+
+#definePACKET_TYPE33
+
+#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
+(((op) & 0xFF) << 8) | \
+((n) & 0x3FFF) << 16)
+
+#definePACKET3_WAIT_REG_MEM0x3C
+#defineWAIT_REG_MEM_FUNCTION(x)((x) << 0)
+   /* 0 - always
+* 1 - <
+* 2 - <=
+* 3 - ==
+* 4 - !=
+* 5 - >=
+* 6 - >
+

Re: [PATCH][drm-next] drm/radeon: make functions alloc_pasid and free_pasid static

2017-09-29 Thread Alex Deucher

On Thu, Sep 28, 2017 at 9:46 AM, Colin King  wrote:
> From: Colin Ian King 
>
> The functions alloc_pasid  and free_pasid are local to the
> source and do not need to be in global scope, so make them static.
>
> Cleans up sparse warnings:
> warning: symbol 'alloc_pasid' was not declared. Should it be static?
> warning: symbol 'free_pasid' was not declared. Should it be static?
>
> Signed-off-by: Colin Ian King 

Applied.  thanks!

Alex


> ---
>  drivers/gpu/drm/radeon/radeon_kfd.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c 
> b/drivers/gpu/drm/radeon/radeon_kfd.c
> index a2ac8ac0930d..385b4d76956d 100644
> --- a/drivers/gpu/drm/radeon/radeon_kfd.c
> +++ b/drivers/gpu/drm/radeon/radeon_kfd.c
> @@ -352,7 +352,7 @@ static uint32_t get_max_engine_clock_in_mhz(struct 
> kgd_dev *kgd)
>   */
>  static DEFINE_IDA(pasid_ida);
>
> -int alloc_pasid(unsigned int bits)
> +static int alloc_pasid(unsigned int bits)
>  {
> int pasid = -EINVAL;
>
> @@ -367,7 +367,7 @@ int alloc_pasid(unsigned int bits)
> return pasid;
>  }
>
> -void free_pasid(unsigned int pasid)
> +static void free_pasid(unsigned int pasid)
>  {
> ida_simple_remove(_ida, pasid);
>  }
> --
> 2.14.1
>
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Re: [PATCH] drm/amdgpu: Fixed a potential circular lock

2017-09-29 Thread Felix Kuehling

Thanks Oak. The change is Reviewed-by: Felix Kuehling



On 2017-09-29 10:28 AM, ozeng wrote:
> The dead circular lock senario captured is as followed.
> The idea of the fix is moving read_user_wptr outside of
> acquire_queue...release_queue critical section
>
> [   63.477482] WARNING: possible circular locking dependency detected
> [   63.484091] 4.12.0-kfd-ozeng #3 Not tainted
> [   63.488531] --
> [   63.495146] HelloWorldLoop/2526 is trying to acquire lock:
> [   63.501011]  (>mmap_sem){++}, at: [] 
> __might_fault+0x3e/0x90
> [   63.509472]
>but task is already holding lock:
> [   63.515716]  (>srbm_mutex){+.+...}, at: [] 
> lock_srbm+0x2b/0x50 [amdgpu]
> [   63.525099]
>which lock already depends on the new lock.
>
> [   63.533841]
>the existing dependency chain (in reverse order) is:
> [   63.541839]
>-> #2 (>srbm_mutex){+.+...}:
> [   63.548178]lock_acquire+0x6d/0x90
> [   63.552461]__mutex_lock+0x70/0x8c0
> [   63.556826]mutex_lock_nested+0x16/0x20
> [   63.561603]gfx_v8_0_kiq_resume+0x1039/0x14a0 [amdgpu]
> [   63.567817]gfx_v8_0_hw_init+0x204d/0x2210 [amdgpu]
> [   63.573675]amdgpu_device_init+0xdea/0x1790 [amdgpu]
> [   63.579640]amdgpu_driver_load_kms+0x63/0x220 [amdgpu]
> [   63.585743]drm_dev_register+0x145/0x1e0
> [   63.590605]amdgpu_pci_probe+0x11e/0x160 [amdgpu]
> [   63.596266]local_pci_probe+0x40/0xa0
> [   63.600803]pci_device_probe+0x134/0x150
> [   63.605650]driver_probe_device+0x2a1/0x460
> [   63.610785]__driver_attach+0xdc/0xe0
> [   63.615321]bus_for_each_dev+0x5f/0x90
> [   63.619984]driver_attach+0x19/0x20
> [   63.624337]bus_add_driver+0x40/0x270
> [   63.628908]driver_register+0x5b/0xe0
> [   63.633446]__pci_register_driver+0x5b/0x60
> [   63.638586]rtsx_pci_switch_output_voltage+0x1d/0x20 [rtsx_pci]
> [   63.645564]do_one_initcall+0x4c/0x1b0
> [   63.650205]do_init_module+0x56/0x1ea
> [   63.654767]load_module+0x208c/0x27d0
> [   63.659335]SYSC_finit_module+0x96/0xd0
> [   63.664058]SyS_finit_module+0x9/0x10
> [   63.668629]entry_SYSCALL_64_fastpath+0x1f/0xbe
> [   63.674088]
>-> #1 (reservation_ww_class_mutex){+.+.+.}:
> [   63.681257]lock_acquire+0x6d/0x90
> [   63.685551]__ww_mutex_lock.constprop.11+0x8c/0xed0
> [   63.691426]ww_mutex_lock+0x67/0x70
> [   63.695802]amdgpu_verify_access+0x6d/0x100 [amdgpu]
> [   63.701743]ttm_bo_mmap+0x8e/0x100 [ttm]
> [   63.706615]amdgpu_bo_mmap+0xd/0x60 [amdgpu]
> [   63.711814]amdgpu_mmap+0x35/0x40 [amdgpu]
> [   63.716904]mmap_region+0x3b5/0x5a0
> [   63.721255]do_mmap+0x400/0x4d0
> [   63.725260]vm_mmap_pgoff+0xb0/0xf0
> [   63.729625]SyS_mmap_pgoff+0x19e/0x260
> [   63.734292]SyS_mmap+0x1d/0x20
> [   63.738199]entry_SYSCALL_64_fastpath+0x1f/0xbe
> [   63.743681]
>-> #0 (>mmap_sem){++}:
> [   63.749641]__lock_acquire+0x1401/0x1420
> [   63.754491]lock_acquire+0x6d/0x90
> [   63.758750]__might_fault+0x6b/0x90
> [   63.763176]kgd_hqd_load+0x24f/0x270 [amdgpu]
> [   63.768432]load_mqd+0x4b/0x50 [amdkfd]
> [   63.773192]create_queue_nocpsch+0x535/0x620 [amdkfd]
> [   63.779237]pqm_create_queue+0x34d/0x4f0 [amdkfd]
> [   63.784835]kfd_ioctl_create_queue+0x282/0x670 [amdkfd]
> [   63.790973]kfd_ioctl+0x310/0x4d0 [amdkfd]
> [   63.795944]do_vfs_ioctl+0x90/0x6e0
> [   63.800268]SyS_ioctl+0x74/0x80
> [   63.804207]entry_SYSCALL_64_fastpath+0x1f/0xbe
> [   63.809607]
>other info that might help us debug this:
>
> [   63.818026] Chain exists of:
>  >mmap_sem --> reservation_ww_class_mutex --> 
> >srbm_mutex
>
> [   63.830382]  Possible unsafe locking scenario:
>
> [   63.836605]CPU0CPU1
> [   63.841364]
> [   63.846123]   lock(>srbm_mutex);
> [   63.850061]
> lock(reservation_ww_class_mutex);
> [   63.857475]lock(>srbm_mutex);
> [   63.864084]   lock(>mmap_sem);
> [   63.867657]
> *** DEADLOCK ***
>
> [   63.873884] 3 locks held by HelloWorldLoop/2526:
> [   63.878739]  #0:  (>mutex){+.+.+.}, at: [] 
> kfd_ioctl_create_queue+0x24a/0x670 [amdkfd]
> [   63.889543]  #1:  (>lock){+.+...}, at: [] 
> create_queue_nocpsch+0x3b/0x620 [amdkfd]
> [   63.899684]  #2:  (>srbm_mutex){+.+...}, at: [] 
> lock_srbm+0x2b/0x50 [amdgpu]
> [   63.909500]
>stack backtrace:
> [   63.914187] CPU: 3 PID: 2526 Comm: HelloWorldLoop Not tainted 
> 4.12.0-kfd-ozeng #3
> [   63.922184] Hardware name: AMD

RE: Regressions in amd-staging-4.12 and amd-staging-drm-next

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Martin Babutzka
> Sent: Friday, September 29, 2017 2:00 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Regressions in amd-staging-4.12 and amd-staging-drm-next
> 
> Hello,
> 
> At first congrats for submitting the pull request. I hope the dc code
> is accepted and included in the 4.15 kernel.
> 
> Me and some other users of my kernel builds (https://github.com/M-Bab/l
> inux-kernel-amdgpu-binaries) found further regressions in builds based
> on amd-staging-4.12 and amd-staging-drm-next. I can confirm these
> regressions affecting my PC with R9 380 GPU, running on Xubuntu 17.04
> with mesa 17.2 stable:
> 
> amd-staging-4.12: When the GPU needs to wake up there is a significant
> chance that the display freezes (black screen, login screen or crazy
> pattern). Can't tell if the whole system is frozen as well. This can
> happen either after wake-up from standby or after resuming from
> lockscreen (where the GPU seams to be shut off as well).
> 
> amd-staging-drm-next: Considering it is the latest codebase the
> performance is a bit underwhelming: It starts with trace messages in
> dmesg during boot (attached). Later on running anything graphical
> results in full-screen flicker and flickering black lines.

If you can bisect the flickering, that would be helpful.

Thanks,

Alex

> 
> Are these issues known already? I can try to git bisect any of them if
> you are interested.
> How should dc-kernel users proceed? Is the amd-staging-drm-next the
> recommended branch until the dc-code is merged?
> 
> Many regards,
> Martin
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RE: Regressions in amd-staging-4.12 and amd-staging-drm-next

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Martin Babutzka
> Sent: Friday, September 29, 2017 2:00 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Regressions in amd-staging-4.12 and amd-staging-drm-next
> 
> Hello,
> 
> At first congrats for submitting the pull request. I hope the dc code
> is accepted and included in the 4.15 kernel.
> 
> Me and some other users of my kernel builds (https://github.com/M-Bab/l
> inux-kernel-amdgpu-binaries) found further regressions in builds based
> on amd-staging-4.12 and amd-staging-drm-next. I can confirm these
> regressions affecting my PC with R9 380 GPU, running on Xubuntu 17.04
> with mesa 17.2 stable:
> 
> amd-staging-4.12: When the GPU needs to wake up there is a significant
> chance that the display freezes (black screen, login screen or crazy
> pattern). Can't tell if the whole system is frozen as well. This can
> happen either after wake-up from standby or after resuming from
> lockscreen (where the GPU seams to be shut off as well).
> 
> amd-staging-drm-next: Considering it is the latest codebase the
> performance is a bit underwhelming: It starts with trace messages in
> dmesg during boot (attached). Later on running anything graphical
> results in full-screen flicker and flickering black lines.
> 
> Are these issues known already? I can try to git bisect any of them if
> you are interested.
> How should dc-kernel users proceed? Is the amd-staging-drm-next the
> recommended branch until the dc-code is merged?

drm-next-4.15-dc has the latest dc code for upstream.  It has some additional 
fixes for dc against the latest core drm changes in drm-next that are not in 
amd-staging-drm-next yet.

Alex

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Regressions in amd-staging-4.12 and amd-staging-drm-next

2017-09-29 Thread Martin Babutzka

Hello,

At first congrats for submitting the pull request. I hope the dc code
is accepted and included in the 4.15 kernel.

Me and some other users of my kernel builds (https://github.com/M-Bab/l
inux-kernel-amdgpu-binaries) found further regressions in builds based
on amd-staging-4.12 and amd-staging-drm-next. I can confirm these
regressions affecting my PC with R9 380 GPU, running on Xubuntu 17.04
with mesa 17.2 stable:

amd-staging-4.12: When the GPU needs to wake up there is a significant
chance that the display freezes (black screen, login screen or crazy
pattern). Can't tell if the whole system is frozen as well. This can
happen either after wake-up from standby or after resuming from
lockscreen (where the GPU seams to be shut off as well).

amd-staging-drm-next: Considering it is the latest codebase the
performance is a bit underwhelming: It starts with trace messages in
dmesg during boot (attached). Later on running anything graphical
results in full-screen flicker and flickering black lines.

Are these issues known already? I can try to git bisect any of them if
you are interested.
How should dc-kernel users proceed? Is the amd-staging-drm-next the
recommended branch until the dc-code is merged?

Many regards,
Martin[1.758422] [ cut here ]
[1.758427] WARNING: CPU: 5 PID: 184 at drivers/gpu/drm/drm_mode_object.c:237 drm_object_property_set_value+0x57/0x70 [drm]
[1.758427] Modules linked in: amdkfd amd_iommu_v2 amdgpu(+) chash i2c_algo_bit ttm drm_kms_helper e1000e(+) syscopyarea sysfillrect ptp sysimgblt fb_sys_fops pps_core r8169 drm mii ahci libahci wmi video pinctrl_sunrisepoint pinctrl_intel i2c_hid hid
[1.758435] CPU: 5 PID: 184 Comm: systemd-udevd Not tainted 4.13.4+ #1
[1.758435] Hardware name: Gigabyte Technology Co., Ltd. B250-HD3P/B250-HD3P-CF, BIOS F3 12/07/2016
[1.758435] task: 9157d2c85580 task.stack: af3b82058000
[1.758438] RIP: 0010:drm_object_property_set_value+0x57/0x70 [drm]
[1.758439] RSP: 0018:af3b8205b830 EFLAGS: 00010246
[1.758439] RAX: c05f96e0 RBX: 9157d3245000 RCX: 9157d32451a0
[1.758440] RDX:  RSI: 9157d325d400 RDI: 9157d3245028
[1.758440] RBP: af3b8205b830 R08: 9157d3245148 R09: 9157dc306100
[1.758440] R10: 003a R11: 9157ddc3a429 R12: 
[1.758441] R13: 9157d37b R14: 9157d3245028 R15: 9157d37b
[1.758441] FS:  7f9c6d4b38c0() GS:9157eed4() knlGS:
[1.758442] CS:  0010 DS:  ES:  CR0: 80050033
[1.758442] CR2: 7ffc8a28fc18 CR3: 000412fdb000 CR4: 003406e0
[1.758443] DR0:  DR1:  DR2: 
[1.758443] DR3:  DR6: fffe0ff0 DR7: 0400
[1.758444] Call Trace:
[1.758480]  amdgpu_dm_add_sink_to_freesync_module+0x8d/0x1b0 [amdgpu]
[1.758506]  amdgpu_dm_update_connector_after_detect+0xb9/0x210 [amdgpu]
[1.758529]  amdgpu_dm_initialize_drm_device+0x350/0x750 [amdgpu]
[1.758531]  ? printk+0x52/0x6e
[1.758555]  ? mod_freesync_create+0x13e/0x190 [amdgpu]
[1.758580]  amdgpu_dm_init+0x15f/0x270 [amdgpu]
[1.758602]  dm_hw_init+0x12/0x20 [amdgpu]
[1.758620]  amdgpu_device_init+0xf16/0x1650 [amdgpu]
[1.758621]  ? kmalloc_order+0x18/0x40
[1.758622]  ? kmalloc_order_trace+0x24/0xa0
[1.758639]  amdgpu_driver_load_kms+0x8b/0x2e0 [amdgpu]
[1.758642]  drm_dev_register+0x146/0x1d0 [drm]
[1.758660]  amdgpu_pci_probe+0x118/0x140 [amdgpu]
[1.758661]  local_pci_probe+0x45/0xa0
[1.758662]  pci_device_probe+0x151/0x1a0
[1.758664]  driver_probe_device+0x29c/0x450
[1.758665]  __driver_attach+0xdf/0xf0
[1.758666]  ? driver_probe_device+0x450/0x450
[1.758667]  bus_for_each_dev+0x6c/0xc0
[1.758668]  driver_attach+0x1e/0x20
[1.758669]  bus_add_driver+0x170/0x260
[1.758670]  driver_register+0x60/0xe0
[1.758670]  __pci_register_driver+0x4c/0x50
[1.758692]  amdgpu_init+0x91/0xa4 [amdgpu]
[1.758692]  ? 0xc06b3000
[1.758693]  do_one_initcall+0x52/0x1a0
[1.758694]  ? __vunmap+0x81/0xb0
[1.758696]  ? kfree+0x14a/0x160
[1.758697]  ? kmem_cache_alloc_trace+0x149/0x1a0
[1.758698]  do_init_module+0x5f/0x1f9
[1.758699]  load_module+0x267f/0x2c90
[1.758701]  ? ima_post_read_file+0x7e/0xa0
[1.758702]  SYSC_finit_module+0xe5/0x120
[1.758703]  ? SYSC_finit_module+0xe5/0x120
[1.758704]  SyS_finit_module+0xe/0x10
[1.758705]  entry_SYSCALL_64_fastpath+0x1e/0xa9
[1.758705] RIP: 0033:0x7f9c6c3239f9
[1.758706] RSP: 002b:7ffc8a297198 EFLAGS: 0246 ORIG_RAX: 0139
[1.758707] RAX: ffda RBX: 7f9c6d45e182 RCX: 7f9c6c3239f9
[1.758707] RDX:  RSI: 7f9c6cc46e23 RDI: 0014
[1.758707] RBP: 7ffc8a296270 R08:  R09: 
[

[PATCH] drm/amd/powerplay: fix a warning in pp_hw_init

2017-09-29 Thread Alex Deucher

Make sure hwmgr is valid.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 44b0616..e96ab0b 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -146,7 +146,7 @@ static int pp_hw_init(void *handle)
 {
int ret = 0;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
-   struct pp_hwmgr *hwmgr;
+   struct pp_hwmgr *hwmgr = NULL;
 
ret = pp_check(pp_handle);
 
@@ -171,7 +171,8 @@ static int pp_hw_init(void *handle)
return 0;
 exit:
pp_handle->pm_en = 0;
-   cgs_notify_dpm_enabled(hwmgr->device, false);
+   if (hwmgr)
+   cgs_notify_dpm_enabled(hwmgr->device, false);
return 0;
 
 }
-- 
2.5.5

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Re: [pull] radeon, amdgpu, ttm drm-next-4.15

2017-09-29 Thread Michel Dänzer

On 26/09/17 10:31 PM, Alex Deucher wrote:
> Hi Dave,
> 
> First feature pull for 4.15.  Highlights:
> - Per VM BO support
> - Lots of powerplay cleanups
> - Powerplay support for CI
> - pasid mgr for kfd
> - interrupt infrastructure for recoverable page faults
> - SR-IOV fixes
> - initial GPU reset for vega10
> - prime mmap support
> - ttm page table debugging improvements
> - lots of bug fixes
> 
> The following changes since commit 7846b12fe0b5feab5446d892f41b5140c1419109:
> 
>   Merge branch 'drm-vmwgfx-next' of 
> git://people.freedesktop.org/~syeh/repos_linux into drm-next (2017-08-29 
> 10:38:14 +1000)
> 
> are available in the git repository at:
> 
>   git://people.freedesktop.org/~agd5f/linux drm-next-4.15
> 
> for you to fetch changes up to 6f87a895709eecc1542fe947e349364ad061ac00:
> 
>   drm/amdgpu: clarify license in amdgpu_trace_points.c (2017-09-26 15:14:37 
> -0400)

[...]

> Michel Dänzer (2):
>   amdgpu: Only destroy fbdev framebuffer if it was initialized
>   radeon: Only destroy fbdev framebuffer if it was initialized

These should go to 4.14. Otherwise, at least amdgpu can't be unloaded in
4.14 as long as it hasn't initialized fbdev (e.g. when there are no
displays connected).


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[PATCH] drm/radeon/dp: make radeon_dp_get_dp_link_config static

2017-09-29 Thread Alex Deucher

It's not used outside this file any longer.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/atombios_dp.c | 8 
 drivers/gpu/drm/radeon/radeon_mode.h | 4 
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c 
b/drivers/gpu/drm/radeon/atombios_dp.c
index 432cb46..a904c80 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -304,10 +304,10 @@ static int convert_bpc_to_bpp(int bpc)
 
 /* radeon specific DP functions */
 
-int radeon_dp_get_dp_link_config(struct drm_connector *connector,
-const u8 dpcd[DP_DPCD_SIZE],
-unsigned pix_clock,
-unsigned *dp_lanes, unsigned *dp_rate)
+static int radeon_dp_get_dp_link_config(struct drm_connector *connector,
+   const u8 dpcd[DP_DPCD_SIZE],
+   unsigned pix_clock,
+   unsigned *dp_lanes, unsigned *dp_rate)
 {
int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
static const unsigned link_rates[3] = { 162000, 27, 54 };
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h 
b/drivers/gpu/drm/radeon/radeon_mode.h
index da44ac2..ca0a7ed 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -762,10 +762,6 @@ extern u8 radeon_dp_getsinktype(struct radeon_connector 
*radeon_connector);
 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
struct drm_connector *connector);
-extern int radeon_dp_get_dp_link_config(struct drm_connector *connector,
-   const u8 *dpcd,
-   unsigned pix_clock,
-   unsigned *dp_lanes, unsigned *dp_rate);
 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 u8 power_state);
 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
-- 
2.5.5

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[PATCH] drm/amdgpu: Fixed a potential circular lock

2017-09-29 Thread ozeng

The dead circular lock senario captured is as followed.
The idea of the fix is moving read_user_wptr outside of
acquire_queue...release_queue critical section

[   63.477482] WARNING: possible circular locking dependency detected
[   63.484091] 4.12.0-kfd-ozeng #3 Not tainted
[   63.488531] --
[   63.495146] HelloWorldLoop/2526 is trying to acquire lock:
[   63.501011]  (>mmap_sem){++}, at: [] 
__might_fault+0x3e/0x90
[   63.509472]
   but task is already holding lock:
[   63.515716]  (>srbm_mutex){+.+...}, at: [] 
lock_srbm+0x2b/0x50 [amdgpu]
[   63.525099]
   which lock already depends on the new lock.

[   63.533841]
   the existing dependency chain (in reverse order) is:
[   63.541839]
   -> #2 (>srbm_mutex){+.+...}:
[   63.548178]lock_acquire+0x6d/0x90
[   63.552461]__mutex_lock+0x70/0x8c0
[   63.556826]mutex_lock_nested+0x16/0x20
[   63.561603]gfx_v8_0_kiq_resume+0x1039/0x14a0 [amdgpu]
[   63.567817]gfx_v8_0_hw_init+0x204d/0x2210 [amdgpu]
[   63.573675]amdgpu_device_init+0xdea/0x1790 [amdgpu]
[   63.579640]amdgpu_driver_load_kms+0x63/0x220 [amdgpu]
[   63.585743]drm_dev_register+0x145/0x1e0
[   63.590605]amdgpu_pci_probe+0x11e/0x160 [amdgpu]
[   63.596266]local_pci_probe+0x40/0xa0
[   63.600803]pci_device_probe+0x134/0x150
[   63.605650]driver_probe_device+0x2a1/0x460
[   63.610785]__driver_attach+0xdc/0xe0
[   63.615321]bus_for_each_dev+0x5f/0x90
[   63.619984]driver_attach+0x19/0x20
[   63.624337]bus_add_driver+0x40/0x270
[   63.628908]driver_register+0x5b/0xe0
[   63.633446]__pci_register_driver+0x5b/0x60
[   63.638586]rtsx_pci_switch_output_voltage+0x1d/0x20 [rtsx_pci]
[   63.645564]do_one_initcall+0x4c/0x1b0
[   63.650205]do_init_module+0x56/0x1ea
[   63.654767]load_module+0x208c/0x27d0
[   63.659335]SYSC_finit_module+0x96/0xd0
[   63.664058]SyS_finit_module+0x9/0x10
[   63.668629]entry_SYSCALL_64_fastpath+0x1f/0xbe
[   63.674088]
   -> #1 (reservation_ww_class_mutex){+.+.+.}:
[   63.681257]lock_acquire+0x6d/0x90
[   63.685551]__ww_mutex_lock.constprop.11+0x8c/0xed0
[   63.691426]ww_mutex_lock+0x67/0x70
[   63.695802]amdgpu_verify_access+0x6d/0x100 [amdgpu]
[   63.701743]ttm_bo_mmap+0x8e/0x100 [ttm]
[   63.706615]amdgpu_bo_mmap+0xd/0x60 [amdgpu]
[   63.711814]amdgpu_mmap+0x35/0x40 [amdgpu]
[   63.716904]mmap_region+0x3b5/0x5a0
[   63.721255]do_mmap+0x400/0x4d0
[   63.725260]vm_mmap_pgoff+0xb0/0xf0
[   63.729625]SyS_mmap_pgoff+0x19e/0x260
[   63.734292]SyS_mmap+0x1d/0x20
[   63.738199]entry_SYSCALL_64_fastpath+0x1f/0xbe
[   63.743681]
   -> #0 (>mmap_sem){++}:
[   63.749641]__lock_acquire+0x1401/0x1420
[   63.754491]lock_acquire+0x6d/0x90
[   63.758750]__might_fault+0x6b/0x90
[   63.763176]kgd_hqd_load+0x24f/0x270 [amdgpu]
[   63.768432]load_mqd+0x4b/0x50 [amdkfd]
[   63.773192]create_queue_nocpsch+0x535/0x620 [amdkfd]
[   63.779237]pqm_create_queue+0x34d/0x4f0 [amdkfd]
[   63.784835]kfd_ioctl_create_queue+0x282/0x670 [amdkfd]
[   63.790973]kfd_ioctl+0x310/0x4d0 [amdkfd]
[   63.795944]do_vfs_ioctl+0x90/0x6e0
[   63.800268]SyS_ioctl+0x74/0x80
[   63.804207]entry_SYSCALL_64_fastpath+0x1f/0xbe
[   63.809607]
   other info that might help us debug this:

[   63.818026] Chain exists of:
 >mmap_sem --> reservation_ww_class_mutex --> 
>srbm_mutex

[   63.830382]  Possible unsafe locking scenario:

[   63.836605]CPU0CPU1
[   63.841364]
[   63.846123]   lock(>srbm_mutex);
[   63.850061]lock(reservation_ww_class_mutex);
[   63.857475]lock(>srbm_mutex);
[   63.864084]   lock(>mmap_sem);
[   63.867657]
*** DEADLOCK ***

[   63.873884] 3 locks held by HelloWorldLoop/2526:
[   63.878739]  #0:  (>mutex){+.+.+.}, at: [] 
kfd_ioctl_create_queue+0x24a/0x670 [amdkfd]
[   63.889543]  #1:  (>lock){+.+...}, at: [] 
create_queue_nocpsch+0x3b/0x620 [amdkfd]
[   63.899684]  #2:  (>srbm_mutex){+.+...}, at: [] 
lock_srbm+0x2b/0x50 [amdgpu]
[   63.909500]
   stack backtrace:
[   63.914187] CPU: 3 PID: 2526 Comm: HelloWorldLoop Not tainted 
4.12.0-kfd-ozeng #3
[   63.922184] Hardware name: AMD Carrizo/Gardenia, BIOS 
WGA5819N_Weekly_15_08_1 08/19/2015
[   63.930865] Call Trace:
[   63.933464]  dump_stack+0x85/0xc9
[   63.936999]  print_circular_bug+0x1f9/0x207
[   63.941442]  __lock_acquire+0x1401/0x1420
[   63.945745]  ? lock_srbm+0x2b/0x50 [amdgpu]
[   63.950185]  lock_acquire+0x6d/0x90
[   63.953885]  ?

Re: [PATCH 04/10] amdgpu/dc: allow inlining constant int to fixed a lot better.

2017-09-29 Thread Harry Wentland

On 2017-09-29 03:13 AM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This uses two things that might be Linux specific,
> __builtin_constant_p (might be gcc)
> and
> BUILD_BUG_ON. (maybe other dm's can have something similiar).
> 

We can always use ifdef in our internal tree to keep Linux specific bits
without affecting other users of our code. As long as it's not all over
the place and the payoff is worthwhile, which it is in this case.

Harry

> This saves 4k in the bw calcs code.
> 
> Signed-off-by: Dave Airlie 
> ---
>  drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c | 37 
> -
>  drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h   | 26 +++--
>  2 files changed, 35 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c 
> b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
> index 0de6fa1..6ca288f 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
> @@ -25,13 +25,6 @@
>  #include "dm_services.h"
>  #include "bw_fixed.h"
>  
> -#define BITS_PER_FRACTIONAL_PART 24
> -
> -#define MIN_I32 \
> - (int64_t)(-(1LL << (63 - BITS_PER_FRACTIONAL_PART)))
> -
> -#define MAX_I32 \
> - (int64_t)((1ULL << (63 - BITS_PER_FRACTIONAL_PART)) - 1)
>  
>  #define MIN_I64 \
>   (int64_t)(-(1LL << 63))
> @@ -40,10 +33,7 @@
>   (int64_t)((1ULL << 63) - 1)
>  
>  #define FRACTIONAL_PART_MASK \
> - ((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
> -
> -#define GET_INTEGER_PART(x) \
> - ((x) >> BITS_PER_FRACTIONAL_PART)
> + ((1ULL << BW_FIXED_BITS_PER_FRACTIONAL_PART) - 1)
>  
>  #define GET_FRACTIONAL_PART(x) \
>   (FRACTIONAL_PART_MASK & (x))
> @@ -56,19 +46,14 @@ static uint64_t abs_i64(int64_t arg)
>   return (uint64_t)(-arg);
>  }
>  
> -struct bw_fixed bw_int_to_fixed(int64_t value)
> +struct bw_fixed bw_int_to_fixed_nonconst(int64_t value)
>  {
>   struct bw_fixed res;
> - ASSERT(value < MAX_I32 && value > MIN_I32);
> - res.value = value << BITS_PER_FRACTIONAL_PART;
> + ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32);
> + res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART;
>   return res;
>  }
>  
> -int32_t bw_fixed_to_int(struct bw_fixed value)
> -{
> - return GET_INTEGER_PART(value.value);
> -}
> -
>  struct bw_fixed bw_frc_to_fixed(int64_t numerator, int64_t denominator)
>  {
>   struct bw_fixed res;
> @@ -87,11 +72,11 @@ struct bw_fixed bw_frc_to_fixed(int64_t numerator, 
> int64_t denominator)
>   arg2_value = abs_i64(denominator);
>   res_value = div64_u64_rem(arg1_value, arg2_value, );
>  
> - ASSERT(res_value <= MAX_I32);
> + ASSERT(res_value <= BW_FIXED_MAX_I32);
>  
>   /* determine fractional part */
>   {
> - uint32_t i = BITS_PER_FRACTIONAL_PART;
> + uint32_t i = BW_FIXED_BITS_PER_FRACTIONAL_PART;
>  
>   do
>   {
> @@ -164,8 +149,8 @@ struct bw_fixed bw_mul(const struct bw_fixed arg1, const 
> struct bw_fixed arg2)
>   uint64_t arg1_value = abs_i64(arg1.value);
>   uint64_t arg2_value = abs_i64(arg2.value);
>  
> - uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
> - uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
> + uint64_t arg1_int = BW_FIXED_GET_INTEGER_PART(arg1_value);
> + uint64_t arg2_int = BW_FIXED_GET_INTEGER_PART(arg2_value);
>  
>   uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
>   uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
> @@ -174,9 +159,9 @@ struct bw_fixed bw_mul(const struct bw_fixed arg1, const 
> struct bw_fixed arg2)
>  
>   res.value = arg1_int * arg2_int;
>  
> - ASSERT(res.value <= MAX_I32);
> + ASSERT(res.value <= BW_FIXED_MAX_I32);
>  
> - res.value <<= BITS_PER_FRACTIONAL_PART;
> + res.value <<= BW_FIXED_BITS_PER_FRACTIONAL_PART;
>  
>   tmp = arg1_int * arg2_fra;
>  
> @@ -192,7 +177,7 @@ struct bw_fixed bw_mul(const struct bw_fixed arg1, const 
> struct bw_fixed arg2)
>  
>   tmp = arg1_fra * arg2_fra;
>  
> - tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
> + tmp = (tmp >> BW_FIXED_BITS_PER_FRACTIONAL_PART) +
>   (tmp >= (uint64_t)(bw_frc_to_fixed(1, 2).value));
>  
>   ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h 
> b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
> index 4477e62..39ee8eba3 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
> @@ -26,10 +26,19 @@
>  #ifndef BW_FIXED_H_
>  #define BW_FIXED_H_
>  
> +#define BW_FIXED_BITS_PER_FRACTIONAL_PART 24
> +
> +#define BW_FIXED_GET_INTEGER_PART(x) ((x) >> 
> BW_FIXED_BITS_PER_FRACTIONAL_PART)
>  struct bw_fixed {
>   int64_t value;
>  };
>  
> +#define BW_FIXED_MIN_I32 \
> + (int64_t)(-(1LL << (63 - BW_FIXED_BITS_PER_FRACTIONAL_PART)))
> +
> +#define

Re: [PATCH 10/10] amdgpu/dc: inline dml_round_to_multiple

2017-09-29 Thread Harry Wentland

On 2017-09-29 03:13 AM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> turns out to be a win to inline this.
> 
> Signed-off-by: Dave Airlie 

Series is
Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c | 19 ---
>  drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h |  2 --
>  drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h | 19 +++
>  3 files changed, 19 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> index 7c0eb52..df2d509 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> @@ -39,23 +39,4 @@ double dml_round(double a)
>   return floor;
>  }
>  
> -unsigned int dml_round_to_multiple(
> - unsigned int num,
> - unsigned int multiple,
> - bool up)
> -{
> - unsigned int remainder;
> -
> - if (multiple == 0)
> - return num;
> -
> - remainder = num % multiple;
>  
> - if (remainder == 0)
> - return num;
> -
> - if (up)
> - return (num + multiple - remainder);
> - else
> - return (num - remainder);
> -}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h 
> b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> index a2da3da..81c53d8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> @@ -33,7 +33,5 @@
>  #define DTRACE(str, ...) dm_logger_write(mode_lib->logger, LOG_DML, str, 
> ##__VA_ARGS__);
>  
>  double dml_round(double a);
> -unsigned int dml_round_to_multiple(
> - unsigned int num, unsigned int multiple, bool up);
>  
>  #endif /* __DC_COMMON_DEFS_H__ */
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h 
> b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
> index 1c6c631..a91b4a6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
> @@ -58,4 +58,23 @@ static inline double dml_log(double x, double base)
>   return (double) dcn_bw_log(x, base);
>  }
>  
> +static inline unsigned int dml_round_to_multiple(unsigned int num,
> +  unsigned int multiple,
> +  bool up)
> +{
> + unsigned int remainder;
> +
> + if (multiple == 0)
> + return num;
> +
> + remainder = num % multiple;
> +
> + if (remainder == 0)
> + return num;
> +
> + if (up)
> + return (num + multiple - remainder);
> + else
> + return (num - remainder);
> +}
>  #endif
> 
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Re: [PATCH 2/2] amdgpu/dc: inline a bunch of the fixed 31_32 helpers.

2017-09-29 Thread Harry Wentland

On 2017-09-29 01:45 AM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This decreases code size by a few hundred bytes.
> 
> Signed-off-by: Dave Airlie 

Series is
Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 122 ---
>  drivers/gpu/drm/amd/display/include/fixed31_32.h   | 132 
> +++--
>  2 files changed, 93 insertions(+), 161 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c 
> b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
> index 546ed67..578691c 100644
> --- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
> +++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
> @@ -132,79 +132,6 @@ struct fixed31_32 dal_fixed31_32_from_int(
>   return res;
>  }
>  
> -struct fixed31_32 dal_fixed31_32_neg(
> - struct fixed31_32 arg)
> -{
> - struct fixed31_32 res;
> -
> - res.value = -arg.value;
> -
> - return res;
> -}
> -
> -struct fixed31_32 dal_fixed31_32_abs(
> - struct fixed31_32 arg)
> -{
> - if (arg.value < 0)
> - return dal_fixed31_32_neg(arg);
> - else
> - return arg;
> -}
> -
> -bool dal_fixed31_32_lt(
> - struct fixed31_32 arg1,
> - struct fixed31_32 arg2)
> -{
> - return arg1.value < arg2.value;
> -}
> -
> -bool dal_fixed31_32_le(
> - struct fixed31_32 arg1,
> - struct fixed31_32 arg2)
> -{
> - return arg1.value <= arg2.value;
> -}
> -
> -bool dal_fixed31_32_eq(
> - struct fixed31_32 arg1,
> - struct fixed31_32 arg2)
> -{
> - return arg1.value == arg2.value;
> -}
> -
> -struct fixed31_32 dal_fixed31_32_min(
> - struct fixed31_32 arg1,
> - struct fixed31_32 arg2)
> -{
> - if (arg1.value <= arg2.value)
> - return arg1;
> - else
> - return arg2;
> -}
> -
> -struct fixed31_32 dal_fixed31_32_max(
> - struct fixed31_32 arg1,
> - struct fixed31_32 arg2)
> -{
> - if (arg1.value <= arg2.value)
> - return arg2;
> - else
> - return arg1;
> -}
> -
> -struct fixed31_32 dal_fixed31_32_clamp(
> - struct fixed31_32 arg,
> - struct fixed31_32 min_value,
> - struct fixed31_32 max_value)
> -{
> - if (dal_fixed31_32_le(arg, min_value))
> - return min_value;
> - else if (dal_fixed31_32_le(max_value, arg))
> - return max_value;
> - else
> - return arg;
> -}
> -
>  struct fixed31_32 dal_fixed31_32_shl(
>   struct fixed31_32 arg,
>   uint8_t shift)
> @@ -219,19 +146,6 @@ struct fixed31_32 dal_fixed31_32_shl(
>   return res;
>  }
>  
> -struct fixed31_32 dal_fixed31_32_shr(
> - struct fixed31_32 arg,
> - uint8_t shift)
> -{
> - struct fixed31_32 res;
> -
> - ASSERT(shift < 64);
> -
> - res.value = arg.value >> shift;
> -
> - return res;
> -}
> -
>  struct fixed31_32 dal_fixed31_32_add(
>   struct fixed31_32 arg1,
>   struct fixed31_32 arg2)
> @@ -246,24 +160,6 @@ struct fixed31_32 dal_fixed31_32_add(
>   return res;
>  }
>  
> -struct fixed31_32 dal_fixed31_32_add_int(
> - struct fixed31_32 arg1,
> - int32_t arg2)
> -{
> - return dal_fixed31_32_add(
> - arg1,
> - dal_fixed31_32_from_int(arg2));
> -}
> -
> -struct fixed31_32 dal_fixed31_32_sub_int(
> - struct fixed31_32 arg1,
> - int32_t arg2)
> -{
> - return dal_fixed31_32_sub(
> - arg1,
> - dal_fixed31_32_from_int(arg2));
> -}
> -
>  struct fixed31_32 dal_fixed31_32_sub(
>   struct fixed31_32 arg1,
>   struct fixed31_32 arg2)
> @@ -278,15 +174,6 @@ struct fixed31_32 dal_fixed31_32_sub(
>   return res;
>  }
>  
> -struct fixed31_32 dal_fixed31_32_mul_int(
> - struct fixed31_32 arg1,
> - int32_t arg2)
> -{
> - return dal_fixed31_32_mul(
> - arg1,
> - dal_fixed31_32_from_int(arg2));
> -}
> -
>  struct fixed31_32 dal_fixed31_32_mul(
>   struct fixed31_32 arg1,
>   struct fixed31_32 arg2)
> @@ -390,15 +277,6 @@ struct fixed31_32 dal_fixed31_32_div_int(
>   dal_fixed31_32_from_int(arg2).value);
>  }
>  
> -struct fixed31_32 dal_fixed31_32_div(
> - struct fixed31_32 arg1,
> - struct fixed31_32 arg2)
> -{
> - return dal_fixed31_32_from_fraction(
> - arg1.value,
> - arg2.value);
> -}
> -
>  struct fixed31_32 dal_fixed31_32_recip(
>   struct fixed31_32 arg)
>  {
> diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
> b/drivers/gpu/drm/amd/display/include/fixed31_32.h
> index 5a4364d..f0bc3c4 100644
> --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
> +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
> @@ -90,15 +90,26 @@ struct fixed31_32 dal_fixed31_32_from_int(
>   * @brief
>   * result = -arg
>   */
> -struct fixed31_32 dal_fixed31_32_neg(
> - struct fixed31_32 arg);
> +static inline struct fixed31_32

Re: [PATCH] amdgpu/nbio: use constant nbio_hdp_flush_reg structs.

2017-09-29 Thread Alex Deucher

On Thu, Sep 28, 2017 at 8:47 PM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This removes the init path as well, since the init path
> just did some constant init of some structs.
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  2 +-
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 38 
> +++---
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 38 
> +++---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  2 +-
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 15 --
>  7 files changed, 38 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 508efc8..99a5b3b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3583,7 +3583,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct 
> amdgpu_ring *ring)
>  static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>  {
> u32 ref_and_mask, reg_mem_engine;
> -   struct nbio_hdp_flush_reg *nbio_hf_reg;
> +   const struct nbio_hdp_flush_reg *nbio_hf_reg;
>
> if (ring->adev->flags & AMD_IS_APU)
> nbio_hf_reg = _v7_0_hdp_flush_reg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 7723d7b..904a1ba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -215,32 +215,28 @@ void nbio_v6_1_get_clockgating_state(struct 
> amdgpu_device *adev, u32 *flags)
> *flags |= AMD_CG_SUPPORT_BIF_LS;
>  }
>
> -struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
> +const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
> +   .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, 
> mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ),
> +   .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, 
> mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE),
> +   .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
> +   .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
> +   .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
> +   .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
> +   .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
> +   .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
> +   .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
> +   .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
> +   .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
> +   .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
> +   .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
> +   .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
> +};
> +
>  const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
> .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
> .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
>  };
>
> -int nbio_v6_1_init(struct amdgpu_device *adev)
> -{
> -   nbio_v6_1_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 
> 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
> -   nbio_v6_1_hdp_flush_reg.hdp_flush_done_offset = 
> SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp0 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp1 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp2 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp3 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp4 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp5 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp6 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp7 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp8 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp9 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK;
> -   nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = 
> BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK;
> -
> -   return 0;
> -}
> -
>  void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
>  {
> uint32_t reg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> index c5ca1e4..14ca8d4 100644
> ---

Re: [PATCH 2/2] amdgpu/pp: constify soft_dummy_pp_table.

2017-09-29 Thread Alex Deucher

On Thu, Sep 28, 2017 at 8:39 PM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> index 485f7eb..afae32e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> @@ -790,7 +790,7 @@ static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
> return pstate;
>  }
>
> -static unsigned char soft_dummy_pp_table[] = {
> +static const unsigned char soft_dummy_pp_table[] = {
> 0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 
> 0x4a, 0x00, 0x6c, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 
> 0x00, 0x80, 0x00, 0x00, 0x00,
> 0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 
> 0x00, 0x9e, 0x00, 0x00, 0x00,
> --
> 2.9.4
>
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Re: [PATCH] amdgpu/dc: remove pointless returns in the i2caux constructor paths. (v2)

2017-09-29 Thread Harry Wentland

On 2017-09-29 01:44 AM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> There was lots of return true, and error checking that was never used
> in these paths.
> 
> Just remove it all.
> 
> v2: I missed one return true.
> 
> Signed-off-by: Dave Airlie 

Thanks for catching that return as well. So much nonsensical code here.
Nice cleanup.

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c |  6 ++--
>  drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h |  2 +-
>  .../amd/display/dc/i2caux/dce100/i2caux_dce100.c   | 21 +-
>  .../display/dc/i2caux/dce110/aux_engine_dce110.c   | 20 +++---
>  .../dc/i2caux/dce110/i2c_hw_engine_dce110.c| 24 ++--
>  .../dc/i2caux/dce110/i2c_hw_engine_dce110.h|  4 ---
>  .../dc/i2caux/dce110/i2c_sw_engine_dce110.c| 20 +++---
>  .../amd/display/dc/i2caux/dce110/i2caux_dce110.c   | 30 ++--
>  .../amd/display/dc/i2caux/dce110/i2caux_dce110.h   |  2 +-
>  .../amd/display/dc/i2caux/dce112/i2caux_dce112.c   | 30 ++--
>  .../amd/display/dc/i2caux/dce120/i2caux_dce120.c   | 21 +-
>  .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c  | 32 
> --
>  .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c  | 19 +++--
>  .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 19 +++--
>  .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 21 +-
>  .../display/dc/i2caux/diagnostics/i2caux_diag.c| 20 +++---
>  drivers/gpu/drm/amd/display/dc/i2caux/engine.h |  2 +-
>  .../gpu/drm/amd/display/dc/i2caux/engine_base.c|  3 +-
>  drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c |  7 ++---
>  drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h |  2 +-
>  .../amd/display/dc/i2caux/i2c_generic_hw_engine.c  |  6 ++--
>  .../amd/display/dc/i2caux/i2c_generic_hw_engine.h  |  2 +-
>  .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c  |  6 ++--
>  .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h  |  2 +-
>  .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c  | 17 +++-
>  .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h  |  2 +-
>  drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c |  4 +--
>  drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h |  2 +-
>  28 files changed, 100 insertions(+), 246 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c 
> b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
> index 3c9608c..fc7a7d4 100644
> --- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
> +++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
> @@ -555,15 +555,13 @@ bool dal_aux_engine_submit_request(
>   return result;
>  }
>  
> -bool dal_aux_engine_construct(
> +void dal_aux_engine_construct(
>   struct aux_engine *engine,
>   struct dc_context *ctx)
>  {
> - if (!dal_i2caux_construct_engine(>base, ctx))
> - return false;
> + dal_i2caux_construct_engine(>base, ctx);
>   engine->delay = 0;
>   engine->max_defer_write_retry = 0;
> - return true;
>  }
>  
>  void dal_aux_engine_destruct(
> diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h 
> b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
> index 40b2028..8e71324 100644
> --- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
> +++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
> @@ -100,7 +100,7 @@ struct aux_engine {
>   bool acquire_reset;
>  };
>  
> -bool dal_aux_engine_construct(
> +void dal_aux_engine_construct(
>   struct aux_engine *engine,
>   struct dc_context *ctx);
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c 
> b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
> index c45a2ee..e8d3781 100644
> --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
> +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
> @@ -95,18 +95,11 @@ struct i2caux *dal_i2caux_dce100_create(
>   return NULL;
>   }
>  
> - if (dal_i2caux_dce110_construct(
> - i2caux_dce110,
> - ctx,
> - dce100_aux_regs,
> - dce100_hw_engine_regs,
> - _shift,
> - _mask))
> - return _dce110->base;
> -
> - ASSERT_CRITICAL(false);
> -
> - kfree(i2caux_dce110);
> -
> - return NULL;
> + dal_i2caux_dce110_construct(i2caux_dce110,
> + ctx,
> + dce100_aux_regs,
> + dce100_hw_engine_regs,
> + _shift,
> + _mask);
> + return _dce110->base;
>  }
> diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c 
> b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
> index

Re: [PATCH 9/9] amdgpu/dc: fix construct return values on irq service.

2017-09-29 Thread Harry Wentland

On 2017-09-29 12:34 AM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This just removes more unused return/errors paths.
> 
> Signed-off-by: Dave Airlie 

Series is
Reviewed-by: Harry Wentland 

Harry

> ---
>  .../gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c | 14 
> --
>  .../gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c | 14 
> --
>  .../gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c   | 14 
> --
>  .../gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c   | 14 
> --
>  drivers/gpu/drm/amd/display/dc/irq/irq_service.c   |  9 +
>  drivers/gpu/drm/amd/display/dc/irq/irq_service.h   |  2 +-
>  6 files changed, 22 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> index 5c55896..f7e40b2 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> @@ -406,17 +406,14 @@ static const struct irq_service_funcs 
> irq_service_funcs_dce110 = {
>   .to_dal_irq_source = to_dal_irq_source_dce110
>  };
>  
> -static bool construct(
> +static void construct(
>   struct irq_service *irq_service,
>   struct irq_service_init_data *init_data)
>  {
> - if (!dal_irq_service_construct(irq_service, init_data))
> - return false;
> + dal_irq_service_construct(irq_service, init_data);
>  
>   irq_service->info = irq_source_info_dce110;
>   irq_service->funcs = _service_funcs_dce110;
> -
> - return true;
>  }
>  
>  struct irq_service *dal_irq_service_dce110_create(
> @@ -428,9 +425,6 @@ struct irq_service *dal_irq_service_dce110_create(
>   if (!irq_service)
>   return NULL;
>  
> - if (construct(irq_service, init_data))
> - return irq_service;
> -
> - kfree(irq_service);
> - return NULL;
> + construct(irq_service, init_data);
> + return irq_service;
>  }
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
> index 61d7c28..2ad56b1 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
> @@ -265,17 +265,14 @@ static const struct irq_service_funcs 
> irq_service_funcs_dce120 = {
>   .to_dal_irq_source = to_dal_irq_source_dce110
>  };
>  
> -static bool construct(
> +static void construct(
>   struct irq_service *irq_service,
>   struct irq_service_init_data *init_data)
>  {
> - if (!dal_irq_service_construct(irq_service, init_data))
> - return false;
> + dal_irq_service_construct(irq_service, init_data);
>  
>   irq_service->info = irq_source_info_dce120;
>   irq_service->funcs = _service_funcs_dce120;
> -
> - return true;
>  }
>  
>  struct irq_service *dal_irq_service_dce120_create(
> @@ -287,9 +284,6 @@ struct irq_service *dal_irq_service_dce120_create(
>   if (!irq_service)
>   return NULL;
>  
> - if (construct(irq_service, init_data))
> - return irq_service;
> -
> - kfree(irq_service);
> - return NULL;
> + construct(irq_service, init_data);
> + return irq_service;
>  }
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
> index d6e1fb6..8a2066c 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
> @@ -277,17 +277,14 @@ static const struct irq_service_funcs 
> irq_service_funcs_dce80 = {
>   .to_dal_irq_source = to_dal_irq_source_dce110
>  };
>  
> -static bool construct(
> +static void construct(
>   struct irq_service *irq_service,
>   struct irq_service_init_data *init_data)
>  {
> - if (!dal_irq_service_construct(irq_service, init_data))
> - return false;
> + dal_irq_service_construct(irq_service, init_data);
>  
>   irq_service->info = irq_source_info_dce80;
>   irq_service->funcs = _service_funcs_dce80;
> -
> - return true;
>  }
>  
>  struct irq_service *dal_irq_service_dce80_create(
> @@ -299,11 +296,8 @@ struct irq_service *dal_irq_service_dce80_create(
>   if (!irq_service)
>   return NULL;
>  
> - if (construct(irq_service, init_data))
> - return irq_service;
> -
> - kfree(irq_service);
> - return NULL;
> + construct(irq_service, init_data);
> + return irq_service;
>  }
>  
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
> index f6e8611..74ad247 100644
> ---

Re: [PATCH 1/3] drm/syncobj: extract two helpers from drm_syncobj_create

2017-09-29 Thread Marek Olšák

On Fri, Sep 29, 2017 at 4:13 PM, Marek Olšák  wrote:
> On Fri, Sep 29, 2017 at 4:44 AM, Chunming Zhou  wrote:
>>
>>
>> On 2017年09月13日 04:42, Marek Olšák wrote:
>>>
>>> From: Marek Olšák 
>>>
>>> For amdgpu.
>>>
>>> drm_syncobj_create is renamed to drm_syncobj_create_as_handle, and new
>>> helpers drm_syncobj_create and drm_syncobj_get_handle are added.
>>>
>>> Signed-off-by: Marek Olšák 
>>> ---
>>>   drivers/gpu/drm/drm_syncobj.c | 49
>>> +++
>>>   include/drm/drm_syncobj.h |  4 
>>>   2 files changed, 49 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
>>> index 0422b8c..0bb1741 100644
>>> --- a/drivers/gpu/drm/drm_syncobj.c
>>> +++ b/drivers/gpu/drm/drm_syncobj.c
>>> @@ -262,8 +262,14 @@ void drm_syncobj_free(struct kref *kref)
>>>   }
>>>   EXPORT_SYMBOL(drm_syncobj_free);
>>>   -static int drm_syncobj_create(struct drm_file *file_private,
>>> - u32 *handle, uint32_t flags)
>>
>> You can add a new parameter for passing dma fence, then in patch3, you can
>> directly use it for AMDGPU_FENCE_TO HANDLE_GET_SYNCOBJ.
>>
>> otherwise the set looks good to me.
>
> Sorry I just pushed this.

Actually, you commented on a deleted line. The function already has
dma_fence among the parameters.

Marek
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Re: [PATCH 1/3] drm/syncobj: extract two helpers from drm_syncobj_create

2017-09-29 Thread Marek Olšák

On Fri, Sep 29, 2017 at 4:44 AM, Chunming Zhou  wrote:
>
>
> On 2017年09月13日 04:42, Marek Olšák wrote:
>>
>> From: Marek Olšák 
>>
>> For amdgpu.
>>
>> drm_syncobj_create is renamed to drm_syncobj_create_as_handle, and new
>> helpers drm_syncobj_create and drm_syncobj_get_handle are added.
>>
>> Signed-off-by: Marek Olšák 
>> ---
>>   drivers/gpu/drm/drm_syncobj.c | 49
>> +++
>>   include/drm/drm_syncobj.h |  4 
>>   2 files changed, 49 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
>> index 0422b8c..0bb1741 100644
>> --- a/drivers/gpu/drm/drm_syncobj.c
>> +++ b/drivers/gpu/drm/drm_syncobj.c
>> @@ -262,8 +262,14 @@ void drm_syncobj_free(struct kref *kref)
>>   }
>>   EXPORT_SYMBOL(drm_syncobj_free);
>>   -static int drm_syncobj_create(struct drm_file *file_private,
>> - u32 *handle, uint32_t flags)
>
> You can add a new parameter for passing dma fence, then in patch3, you can
> directly use it for AMDGPU_FENCE_TO HANDLE_GET_SYNCOBJ.
>
> otherwise the set looks good to me.

Sorry I just pushed this.

Marek
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Re: [amd-staging-drm-next] regression - no fan info (sensors) on RX580

2017-09-29 Thread Alex Deucher

Rex, probably related to the recent cleanups in powerplay.

On Fri, Sep 29, 2017 at 10:09 AM, Dieter Nützel  wrote:
> Hello all,
>
> since latest update
>
> 1d7da702e70d3c27408a3bb312c71d6be9f7bebe
> drm/amd/powerplay: fix spelling mistake: "dividable" -> "divisible"
>
> I didn't get fan info with my RX580 (Polaris21) any longer.
>
> Worked with this commit:
>
> 786df0b89fe5a0b405d4de0a1ce03003c0743ec3
> drm/amd/display: fix pflip irq registor for raven
>
> Sorry, I do not have full time for bisect, because we are on way to our
> vacation.
>
> Maybe in the evening (only a few commits).
>
> Greetings,
> Dieter
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[amd-staging-drm-next] regression - no fan info (sensors) on RX580

2017-09-29 Thread Dieter Nützel


Hello all,

since latest update

1d7da702e70d3c27408a3bb312c71d6be9f7bebe
drm/amd/powerplay: fix spelling mistake: "dividable" -> "divisible"

I didn't get fan info with my RX580 (Polaris21) any longer.

Worked with this commit:

786df0b89fe5a0b405d4de0a1ce03003c0743ec3
drm/amd/display: fix pflip irq registor for raven

Sorry, I do not have full time for bisect, because we are on way to our 
vacation.


Maybe in the evening (only a few commits).

Greetings,
Dieter
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[PATCH] drm/radeon: move ci_send_msg_to_smc to where it's used

2017-09-29 Thread Alex Deucher

It's used in ci_dpm.c so move it there and make it static.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/ci_dpm.c | 22 ++
 drivers/gpu/drm/radeon/ci_dpm.h |  1 -
 drivers/gpu/drm/radeon/ci_smc.c | 21 -
 3 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index c97fbb2..7e1b04d 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -184,6 +184,7 @@ static int ci_set_overdrive_target_tdp(struct radeon_device 
*rdev,
   u32 target_tdp);
 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 
+static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg 
msg);
 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device 
*rdev,
  PPSMC_Msg msg, u32 
parameter);
 
@@ -1651,6 +1652,27 @@ static int ci_notify_hw_of_power_source(struct 
radeon_device *rdev,
 }
 #endif
 
+static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg 
msg)
+{
+   u32 tmp;
+   int i;
+
+   if (!ci_is_smc_running(rdev))
+   return PPSMC_Result_Failed;
+
+   WREG32(SMC_MESSAGE_0, msg);
+
+   for (i = 0; i < rdev->usec_timeout; i++) {
+   tmp = RREG32(SMC_RESP_0);
+   if (tmp != 0)
+   break;
+   udelay(1);
+   }
+   tmp = RREG32(SMC_RESP_0);
+
+   return (PPSMC_Result)tmp;
+}
+
 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device 
*rdev,
  PPSMC_Msg msg, u32 
parameter)
 {
diff --git a/drivers/gpu/drm/radeon/ci_dpm.h b/drivers/gpu/drm/radeon/ci_dpm.h
index 723220f..dff2a63 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.h
+++ b/drivers/gpu/drm/radeon/ci_dpm.h
@@ -330,7 +330,6 @@ int ci_program_jump_on_start(struct radeon_device *rdev);
 void ci_stop_smc_clock(struct radeon_device *rdev);
 void ci_start_smc_clock(struct radeon_device *rdev);
 bool ci_is_smc_running(struct radeon_device *rdev);
-PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);
 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);
 int ci_read_smc_sram_dword(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c
index 3356a21..3711219 100644
--- a/drivers/gpu/drm/radeon/ci_smc.c
+++ b/drivers/gpu/drm/radeon/ci_smc.c
@@ -163,27 +163,6 @@ bool ci_is_smc_running(struct radeon_device *rdev)
return false;
 }
 
-PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
-{
-   u32 tmp;
-   int i;
-
-   if (!ci_is_smc_running(rdev))
-   return PPSMC_Result_Failed;
-
-   WREG32(SMC_MESSAGE_0, msg);
-
-   for (i = 0; i < rdev->usec_timeout; i++) {
-   tmp = RREG32(SMC_RESP_0);
-   if (tmp != 0)
-   break;
-   udelay(1);
-   }
-   tmp = RREG32(SMC_RESP_0);
-
-   return (PPSMC_Result)tmp;
-}
-
 #if 0
 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev)
 {
-- 
2.5.5

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Re: [PATCH] drm/amdgpu: Reserve shared memory on VRAM for SR-IOV

2017-09-29 Thread Christian König


Am 29.09.2017 um 09:21 schrieb Horace Chen:

SR-IOV need to reserve a piece of shared VRAM at the exact place
to exchange data betweem PF and VF. The start address and size of
the shared mem are passed to guest through VBIOS structure
VRAM_UsageByFirmware.

VRAM_UsageByFirmware is a general feature in VBIOS, it indicates
that VBIOS need to reserve a piece of memory on the VRAM.

Because the mem address is specified. Reserve it early in
amdgpu_ttm_init to make sure that it can monoplize the space.

Signed-off-by: Horace Chen 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 14 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 18 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 88 
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  9 +++
  4 files changed, 128 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a5b0b67..b802858 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1380,6 +1380,18 @@ struct amdgpu_atcs {
  };
  
  /*

+ * Firmware VRAM reservation
+ */
+struct amdgpu_fw_vram_usage {
+   u64 start_offset;
+   u64 size;
+   struct amdgpu_bo *reserved_bo;
+   volatile uint32_t *va;


Use something like cpu_address for the variable name here instead. That 
is usually not a virtual address at all, but a direct mapping.



+};
+
+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
+
+/*
   * CGS
   */
  struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
@@ -1588,6 +1600,8 @@ struct amdgpu_device {
struct delayed_work late_init_work;
  
  	struct amdgpu_virt	virt;

+   /* firmware VRAM reservation */
+   struct amdgpu_fw_vram_usage fw_vram_usage;
  
  	/* link all shadow bo */

struct list_headshadow_list;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index ce44358..f66d33e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1807,6 +1807,8 @@ int amdgpu_atombios_allocate_fb_scratch(struct 
amdgpu_device *adev)
uint16_t data_offset;
int usage_bytes = 0;
struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
+   u64 start_addr;
+   u64 size;
  
  	if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, _offset)) {

firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE 
*)(ctx->bios + data_offset);
@@ -1815,7 +1817,21 @@ int amdgpu_atombios_allocate_fb_scratch(struct 
amdgpu_device *adev)
  
le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
  
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
  
-		usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;

+   start_addr = 
firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
+   size = 
firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
+
+   if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 
<<
+   ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->fw_vram_usage.start_offset = (start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->fw_vram_usage.size = size << 10;
+   /* Use the default scratch size */
+   usage_bytes = 0;
+   } else {
+   usage_bytes = 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 
1024;
+   }
}
ctx->scratch_size_bytes = 0;
if (usage_bytes == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a86d856..02e07a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -658,6 +658,93 @@ void amdgpu_gart_location(struct amdgpu_device *adev, 
struct amdgpu_mc *mc)
  }
  
  /*

+ * Firmware Reservation function
+ */
+/**
+ * amdgpu_fw_reserve_vram_fini - free fw reserved vram
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * free fw reserved vram if it has been reserved.
+ */
+void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
+{
+
+   if (adev->fw_vram_usage.reserved_bo == NULL)
+   return;
+
+   if (likely(amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo,
+   true) == 0)) {
+   amdgpu_bo_kunmap(adev->fw_vram_usage.reserved_bo);
+   amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
+

Re: [PATCH] [rfc] amdgfx/gfx: don't use static objects for ce/de meta. (v2)

2017-09-29 Thread Christian König


Am 29.09.2017 um 02:16 schrieb Dave Airlie:

From: Dave Airlie 

This isn't safe if we have multiple GPUs plugged in, since
there is only one copy of this struct in the bss, just allocate
on stack, it's 40/108 bytes which should be safe.

Signed-off-by: Dave Airlie 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
  2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index dfc10b1..5887f29 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7076,7 +7076,7 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring 
*ring)
  {
uint64_t ce_payload_addr;
int cnt_ce;
-   static union {
+   union {
struct vi_ce_ib_state regular;
struct vi_ce_ib_state_chained_ib chained;
} ce_payload = {};
@@ -7105,7 +7105,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring 
*ring)
  {
uint64_t de_payload_addr, gds_addr, csa_addr;
int cnt_de;
-   static union {
+   union {
struct vi_de_ib_state regular;
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index deeaee14..508efc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3806,7 +3806,7 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
  
  static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)

  {
-   static struct v9_ce_ib_state ce_payload = {0};
+   struct v9_ce_ib_state ce_payload = {0};
uint64_t csa_addr;
int cnt;
  
@@ -3825,7 +3825,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
  
  static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)

  {
-   static struct v9_de_ib_state de_payload = {0};
+   struct v9_de_ib_state de_payload = {0};
uint64_t csa_addr, gds_addr;
int cnt;
  



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Re: [pull] amdgpu dc drm-next-4.15-dc

2017-09-29 Thread Chris Wilson

Quoting Alex Deucher (2017-09-27 02:36:07)
> Hi Dave,
> 
> Initial pull request for DC support.  We've completed a substantial amount of
> the cleanup and restructuring in our TODO.  There are a few additional
> cleanups that we are continuing to work on, but I don't think there are any
> showstoppers remaining. We've tried to maintain most of the history for bisect
> purposes.  Harry made sure all the commits build.  We've enabled DC for vega10
> and Raven.  Pre-vega10 parts can be enabled via module parameter 
> (amdgpu.dc=1),
> but are not enabled by default at this point until we get further testing
> upstream.

Just a heads up, allyesconfig dies:
drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.o: In function `ci_send_msg_to_smc':
ci_smc.c:(.text+0x1620): multiple definition of `ci_send_msg_to_smc'
drivers/gpu/drm/radeon/ci_smc.o:ci_smc.c:(.text+0x500): first defined here

From commit 9f4b35411cfed96d4f9f092b2fed14905af84d89
Author: Rex Zhu 
Date:   Fri Sep 8 19:34:33 2017 +0800

drm/amd/powerplay: add CI asics support to smumgr (v3)

Probably already reported, in which case sorry for the noise.
-Chris
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RE: [PATCH 2/2] drm/amdgpu: add header kgd_pp_interface.h

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, September 29, 2017 6:02 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 2/2] drm/amdgpu: add header kgd_pp_interface.h
> 
> move powerplay and amdgpu shared structures
> and definitions to kgd_pp_interface.h
> 
> Change-Id: I4272b7974edbff3395ba8a6efebb0decd0cdfa12
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   5 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|   1 -
>  drivers/gpu/drm/amd/include/amd_shared.h  | 172 -
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h| 289
> ++
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  93 +--
>  5 files changed, 293 insertions(+), 267 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/include/kgd_pp_interface.h
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 2204ff6..1453aba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -47,6 +47,8 @@
>  #include 
> 
>  #include 
> +#include "dm_pp_interface.h"
> +#include "kgd_pp_interface.h"
> 
>  #include "amd_shared.h"
>  #include "amdgpu_mode.h"
> @@ -59,7 +61,6 @@
>  #include "amdgpu_sync.h"
>  #include "amdgpu_ring.h"
>  #include "amdgpu_vm.h"
> -#include "amd_powerplay.h"
>  #include "amdgpu_dpm.h"
>  #include "amdgpu_acp.h"
>  #include "amdgpu_uvd.h"
> @@ -67,11 +68,11 @@
>  #include "amdgpu_vcn.h"
>  #include "amdgpu_mn.h"
>  #include "amdgpu_dm.h"
> -
>  #include "gpu_scheduler.h"
>  #include "amdgpu_virt.h"
>  #include "amdgpu_gart.h"
> 
> +
>  /*
>   * Modules parameters.
>   */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index f3b23f9..f3afa66 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -30,7 +30,6 @@
>  #include 
>  #include 
> 
> -#include "amd_powerplay.h"
> 
>  static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
> 
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
> b/drivers/gpu/drm/amd/include/amd_shared.h
> index 0bcf2bc..3aecf1d 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -27,7 +27,6 @@
> 
>  #define AMD_MAX_USEC_TIMEOUT 20  /* 200 ms */
> 
> -struct seq_file;
> 
>  /*
>   * Chip flags
> @@ -61,71 +60,12 @@ enum amd_clockgating_state {
>   AMD_CG_STATE_UNGATE,
>  };
> 
> -enum amd_dpm_forced_level {
> - AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
> - AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
> - AMD_DPM_FORCED_LEVEL_LOW = 0x4,
> - AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
> - AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
> - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
> - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
> - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
> - AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
> -};
> 
>  enum amd_powergating_state {
>   AMD_PG_STATE_GATE = 0,
>   AMD_PG_STATE_UNGATE,
>  };
> 
> -struct amd_vce_state {
> - /* vce clocks */
> - u32 evclk;
> - u32 ecclk;
> - /* gpu clocks */
> - u32 sclk;
> - u32 mclk;
> - u8 clk_idx;
> - u8 pstate;
> -};
> -
> -
> -#define AMD_MAX_VCE_LEVELS 6
> -
> -enum amd_vce_level {
> - AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
> - AMD_VCE_LEVEL_DC_EE = 1,  /* DC, entropy encoding */
> - AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <=
> 720 */
> - AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080
> >= res > 720 */
> - AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue,
> res <= 720 */
> - AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue,
> 1080 >= res > 720 */
> -};
> -
> -enum amd_pp_profile_type {
> - AMD_PP_GFX_PROFILE,
> - AMD_PP_COMPUTE_PROFILE,
> -};
> -
> -struct amd_pp_profile {
> - enum amd_pp_profile_type type;
> - uint32_t min_sclk;
> - uint32_t min_mclk;
> - uint16_t activity_threshold;
> - uint8_t up_hyst;
> - uint8_t down_hyst;
> -};
> -
> -enum amd_fan_ctrl_mode {
> - AMD_FAN_CTRL_NONE = 0,
> - AMD_FAN_CTRL_MANUAL = 1,
> - AMD_FAN_CTRL_AUTO = 2,
> -};
> -
> -enum pp_clock_type {
> - PP_SCLK,
> - PP_MCLK,
> - PP_PCIE,
> -};
> 
>  /* CG flags */
>  #define AMD_CG_SUPPORT_GFX_MGCG  (1 << 0)
> @@ -169,27 +109,6 @@ enum pp_clock_type {
>  #define AMD_PG_SUPPORT_GFX_PIPELINE  (1 << 12)
>  #define AMD_PG_SUPPORT_MMHUB (1 << 13)
> 
> -enum amd_pm_state_type {
> - /* not used for dpm */
> - POWER_STATE_TYPE_DEFAULT,
> - POWER_STATE_TYPE_POWERSAVE,
> - /* user selectable states */
> - POWER_STATE_TYPE_BATTERY,
> - POWER_STATE_TYPE_BALANCED,
> - POWER_STATE_TYPE_PERFORMANCE,
> - /* internal states */
>

RE: [PATCH] drm/amdgpu: Reserve shared memory on VRAM for SR-IOV

2017-09-29 Thread Deucher, Alexander

> -Original Message-
> From: Horace Chen [mailto:horace.c...@amd.com]
> Sent: Friday, September 29, 2017 3:21 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Chen, Horace
> Subject: [PATCH] drm/amdgpu: Reserve shared memory on VRAM for SR-
> IOV
> 
> SR-IOV need to reserve a piece of shared VRAM at the exact place
> to exchange data betweem PF and VF. The start address and size of
> the shared mem are passed to guest through VBIOS structure
> VRAM_UsageByFirmware.
> 
> VRAM_UsageByFirmware is a general feature in VBIOS, it indicates
> that VBIOS need to reserve a piece of memory on the VRAM.
> 
> Because the mem address is specified. Reserve it early in
> amdgpu_ttm_init to make sure that it can monoplize the space.
> 
> Signed-off-by: Horace Chen 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 14 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 18 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 88
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  9 +++
>  4 files changed, 128 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a5b0b67..b802858 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1380,6 +1380,18 @@ struct amdgpu_atcs {
>  };
> 
>  /*
> + * Firmware VRAM reservation
> + */
> +struct amdgpu_fw_vram_usage {
> + u64 start_offset;
> + u64 size;
> + struct amdgpu_bo *reserved_bo;
> + volatile uint32_t *va;
> +};
> +
> +int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
> +
> +/*
>   * CGS
>   */
>  struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device
> *adev);
> @@ -1588,6 +1600,8 @@ struct amdgpu_device {
>   struct delayed_work late_init_work;
> 
>   struct amdgpu_virt  virt;
> + /* firmware VRAM reservation */
> + struct amdgpu_fw_vram_usage fw_vram_usage;
> 
>   /* link all shadow bo */
>   struct list_headshadow_list;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> index ce44358..f66d33e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> @@ -1807,6 +1807,8 @@ int amdgpu_atombios_allocate_fb_scratch(struct
> amdgpu_device *adev)
>   uint16_t data_offset;
>   int usage_bytes = 0;
>   struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
> + u64 start_addr;
> + u64 size;
> 
>   if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL,
> _offset)) {
>   firmware_usage = (struct
> _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
> @@ -1815,7 +1817,21 @@ int amdgpu_atombios_allocate_fb_scratch(struct
> amdgpu_device *adev)
> le32_to_cpu(firmware_usage-
> >asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
> le16_to_cpu(firmware_usage-
> >asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
> 
> - usage_bytes = le16_to_cpu(firmware_usage-
> >asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
> + start_addr = firmware_usage-
> >asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
> + size = firmware_usage-
> >asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
> +
> + if ((uint32_t)(start_addr &
> ATOM_VRAM_OPERATION_FLAGS_MASK) ==
> +
>   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATIO
> N <<
> + ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
> + /* Firmware request VRAM reservation for SR-IOV */
> + adev->fw_vram_usage.start_offset = (start_addr &
> +
>   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
> + adev->fw_vram_usage.size = size << 10;
> + /* Use the default scratch size */
> + usage_bytes = 0;
> + } else {
> + usage_bytes = le16_to_cpu(firmware_usage-
> >asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
> + }
>   }
>   ctx->scratch_size_bytes = 0;
>   if (usage_bytes == 0)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a86d856..02e07a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -658,6 +658,93 @@ void amdgpu_gart_location(struct amdgpu_device
> *adev, struct amdgpu_mc *mc)
>  }
> 
>  /*
> + * Firmware Reservation function
> + */
> +/**
> + * amdgpu_fw_reserve_vram_fini - free fw reserved vram
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * free fw reserved vram if it has been reserved.
> + */
> +void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
> +{
> +
> + if (adev->fw_vram_usage.reserved_bo == NULL)
> +

Re: [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper

2017-09-29 Thread Marek Olšák

On Fri, Sep 29, 2017 at 4:12 AM, Chunming Zhou  wrote:
>
>
> On 2017年09月29日 06:10, Marek Olšák wrote:
>>
>> From: Marek Olšák 
>>
>> ---
>>   include/drm/drm.h | 24 
>>   xf86drm.c | 22 ++
>>   xf86drm.h |  3 +++
>>   3 files changed, 49 insertions(+)
>>
>> diff --git a/include/drm/drm.h b/include/drm/drm.h
>> index bf3674a..4da1667 100644
>> --- a/include/drm/drm.h
>> +++ b/include/drm/drm.h
>> @@ -687,38 +687,57 @@ struct drm_prime_handle {
>> /** Flags.. only applicable for handle->fd */
>> __u32 flags;
>> /** Returned dmabuf file descriptor */
>> __s32 fd;
>>   };
>> struct drm_syncobj_create {
>> __u32 handle;
>> +#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
>> __u32 flags;
>>   };
>> struct drm_syncobj_destroy {
>> __u32 handle;
>> __u32 pad;
>>   };
>> #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
>>   #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
>
> Typo for '(1 << 1)' ?

No, this was copied from kernel headers.

>
> With that fixes, the set is Reviewed-by: Chunming Zhou 

Thanks.

Marek
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Re: [PATCH 3/3] drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_file

2017-09-29 Thread Marek Olšák

On Fri, Sep 29, 2017 at 1:42 AM, Dave Airlie  wrote:
> On 29 September 2017 at 06:41, Marek Olšák  wrote:
>> Can I get Rb for this series?
>>
>
> For the series,
>
> Reviewed-by: Dave Airlie 
>
> Alex, please merge the two drm core precursor with patch 3.

Alex, this is for drm-next, where I can't push.

Thanks,
Marek
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Re: [PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread Alex Deucher

On Fri, Sep 29, 2017 at 3:42 AM,   wrote:
> From: Ken Wang 
>
> Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
> Signed-off-by: Ken Wang 
> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7839677..631b1e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
> amdgpu_device *adev)
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
> if (adev->asic_type == CHIP_VEGA10)
> -   return adev->clock.spll.reference_freq/4;
> +   return 27000;

Why do we need to change this?  Is the vbios table wrong?  See
amdgpu_atomfirmware_get_clock_info().

Alex

> else
> return adev->clock.spll.reference_freq;
>  }
> --
> 2.7.4
>
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[PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread Ken.Wang

From: Ken Wang 

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
+   return 27000;
else
return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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[PATCH 2/2] drm/amdgpu: add header kgd_pp_interface.h

2017-09-29 Thread Rex Zhu

move powerplay and amdgpu shared structures
and definitions to kgd_pp_interface.h

Change-Id: I4272b7974edbff3395ba8a6efebb0decd0cdfa12
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|   1 -
 drivers/gpu/drm/amd/include/amd_shared.h  | 172 -
 drivers/gpu/drm/amd/include/kgd_pp_interface.h| 289 ++
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  93 +--
 5 files changed, 293 insertions(+), 267 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/kgd_pp_interface.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2204ff6..1453aba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -47,6 +47,8 @@
 #include 
 
 #include 
+#include "dm_pp_interface.h"
+#include "kgd_pp_interface.h"
 
 #include "amd_shared.h"
 #include "amdgpu_mode.h"
@@ -59,7 +61,6 @@
 #include "amdgpu_sync.h"
 #include "amdgpu_ring.h"
 #include "amdgpu_vm.h"
-#include "amd_powerplay.h"
 #include "amdgpu_dpm.h"
 #include "amdgpu_acp.h"
 #include "amdgpu_uvd.h"
@@ -67,11 +68,11 @@
 #include "amdgpu_vcn.h"
 #include "amdgpu_mn.h"
 #include "amdgpu_dm.h"
-
 #include "gpu_scheduler.h"
 #include "amdgpu_virt.h"
 #include "amdgpu_gart.h"
 
+
 /*
  * Modules parameters.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index f3b23f9..f3afa66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -30,7 +30,6 @@
 #include 
 #include 
 
-#include "amd_powerplay.h"
 
 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 0bcf2bc..3aecf1d 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -27,7 +27,6 @@
 
 #define AMD_MAX_USEC_TIMEOUT   20  /* 200 ms */
 
-struct seq_file;
 
 /*
  * Chip flags
@@ -61,71 +60,12 @@ enum amd_clockgating_state {
AMD_CG_STATE_UNGATE,
 };
 
-enum amd_dpm_forced_level {
-   AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
-   AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
-   AMD_DPM_FORCED_LEVEL_LOW = 0x4,
-   AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
-   AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
-   AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
-   AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
-   AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
-   AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
-};
 
 enum amd_powergating_state {
AMD_PG_STATE_GATE = 0,
AMD_PG_STATE_UNGATE,
 };
 
-struct amd_vce_state {
-   /* vce clocks */
-   u32 evclk;
-   u32 ecclk;
-   /* gpu clocks */
-   u32 sclk;
-   u32 mclk;
-   u8 clk_idx;
-   u8 pstate;
-};
-
-
-#define AMD_MAX_VCE_LEVELS 6
-
-enum amd_vce_level {
-   AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
-   AMD_VCE_LEVEL_DC_EE = 1,  /* DC, entropy encoding */
-   AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
-   AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 
720 */
-   AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 
*/
-   AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res 
> 720 */
-};
-
-enum amd_pp_profile_type {
-   AMD_PP_GFX_PROFILE,
-   AMD_PP_COMPUTE_PROFILE,
-};
-
-struct amd_pp_profile {
-   enum amd_pp_profile_type type;
-   uint32_t min_sclk;
-   uint32_t min_mclk;
-   uint16_t activity_threshold;
-   uint8_t up_hyst;
-   uint8_t down_hyst;
-};
-
-enum amd_fan_ctrl_mode {
-   AMD_FAN_CTRL_NONE = 0,
-   AMD_FAN_CTRL_MANUAL = 1,
-   AMD_FAN_CTRL_AUTO = 2,
-};
-
-enum pp_clock_type {
-   PP_SCLK,
-   PP_MCLK,
-   PP_PCIE,
-};
 
 /* CG flags */
 #define AMD_CG_SUPPORT_GFX_MGCG(1 << 0)
@@ -169,27 +109,6 @@ enum pp_clock_type {
 #define AMD_PG_SUPPORT_GFX_PIPELINE(1 << 12)
 #define AMD_PG_SUPPORT_MMHUB   (1 << 13)
 
-enum amd_pm_state_type {
-   /* not used for dpm */
-   POWER_STATE_TYPE_DEFAULT,
-   POWER_STATE_TYPE_POWERSAVE,
-   /* user selectable states */
-   POWER_STATE_TYPE_BATTERY,
-   POWER_STATE_TYPE_BALANCED,
-   POWER_STATE_TYPE_PERFORMANCE,
-   /* internal states */
-   POWER_STATE_TYPE_INTERNAL_UVD,
-   POWER_STATE_TYPE_INTERNAL_UVD_SD,
-   POWER_STATE_TYPE_INTERNAL_UVD_HD,
-   POWER_STATE_TYPE_INTERNAL_UVD_HD2,
-   POWER_STATE_TYPE_INTERNAL_UVD_MVC,
-   POWER_STATE_TYPE_INTERNAL_BOOT,
-   POWER_STATE_TYPE_INTERNAL_THERMAL,
-   POWER_STATE_TYPE_INTERNAL_ACPI,
-   POWER_STATE_TYPE_INTERNAL_ULV,
-   POWER_STATE_TYPE_INTERNAL_3DPERF,
-};
-
 struct amd_ip_funcs {
/* Name of IP block */

[PATCH 1/2] drm/amdgpu: move struct amd_powerplay to amdgpu.h

2017-09-29 Thread Rex Zhu

Change-Id: Iea3b5ab620b536d1ab084ffc0859f44ffe7a
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 7 +++
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 7 ---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9090888..2204ff6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1396,6 +1396,13 @@ struct amdgpu_atcs {
 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, 
uint32_t);
 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, 
uint32_t);
 
+struct amd_powerplay {
+   struct cgs_device *cgs_device;
+   void *pp_handle;
+   const struct amd_ip_funcs *ip_funcs;
+   const struct amd_pm_funcs *pp_funcs;
+};
+
 #define AMDGPU_RESET_MAGIC_NUM 64
 struct amdgpu_device {
struct device   *dev;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h 
b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 006954e..47478e0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -122,12 +122,5 @@ struct pp_gpu_power {
support << 
PP_STATE_SUPPORT_SHIFT |\
state << 
PP_STATE_SHIFT)
 
-struct amd_powerplay {
-   struct cgs_device *cgs_device;
-   void *pp_handle;
-   const struct amd_ip_funcs *ip_funcs;
-   const struct amd_pm_funcs *pp_funcs;
-};
-
 
 #endif /* _AMD_POWERPLAY_H_ */
-- 
1.9.1

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Re: [PATCH 2/2] drm/amdgpu: add option for force enable multipipe policy for compute

2017-09-29 Thread Michel Dänzer

On 26/09/17 06:22 PM, Andres Rodriguez wrote:
> Useful for testing the effects of multipipe compute without recompiling.
> 
> Signed-off-by: Andres Rodriguez 

I'm skeptical that it's a good idea to add a module parameter for this.
See Daniel's rationale in
https://lists.freedesktop.org/archives/dri-devel/2017-September/153690.html
. In particular, since we don't fully understand how this stuff works
yet, it's better for now to stick to changing the code for experiments.

In general, the output of

 modinfo -p amdgpu

is quite a horror show already, we should try to clean that up rather
than making it worse.

-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Fw: [PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread Wang, Ken

Hi,

   I have to forwards the review request because git send email seems not work 
correctly on my machine.



From: ken.w...@amd.com 
Sent: Friday, September 29, 2017 16:38
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject: [PATCH] drm/amdgpu: correct reference clock value on vega10

From: Ken Wang 

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
 if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
+   return 27000;
 else
 return adev->clock.spll.reference_freq;
 }
--
2.7.4

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[PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread Ken.Wang

From: Ken Wang 

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
+   return 27000;
else
return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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[PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread Ken.Wang

From: Ken Wang 

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
+   return 27000;
else
return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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[PATCH] drm/amdgpu: correct reference clock value on vega10

2017-09-29 Thread ken.wang

From: Ken Wang 

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
+   return 27000;
else
return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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[PATCH] drm/amdgpu: Reserve shared memory on VRAM for SR-IOV

2017-09-29 Thread Horace Chen

SR-IOV need to reserve a piece of shared VRAM at the exact place
to exchange data betweem PF and VF. The start address and size of
the shared mem are passed to guest through VBIOS structure
VRAM_UsageByFirmware.

VRAM_UsageByFirmware is a general feature in VBIOS, it indicates
that VBIOS need to reserve a piece of memory on the VRAM.

Because the mem address is specified. Reserve it early in
amdgpu_ttm_init to make sure that it can monoplize the space.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 14 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 18 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 88 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  9 +++
 4 files changed, 128 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a5b0b67..b802858 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1380,6 +1380,18 @@ struct amdgpu_atcs {
 };
 
 /*
+ * Firmware VRAM reservation
+ */
+struct amdgpu_fw_vram_usage {
+   u64 start_offset;
+   u64 size;
+   struct amdgpu_bo *reserved_bo;
+   volatile uint32_t *va;
+};
+
+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
+
+/*
  * CGS
  */
 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
@@ -1588,6 +1600,8 @@ struct amdgpu_device {
struct delayed_work late_init_work;
 
struct amdgpu_virt  virt;
+   /* firmware VRAM reservation */
+   struct amdgpu_fw_vram_usage fw_vram_usage;
 
/* link all shadow bo */
struct list_headshadow_list;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index ce44358..f66d33e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1807,6 +1807,8 @@ int amdgpu_atombios_allocate_fb_scratch(struct 
amdgpu_device *adev)
uint16_t data_offset;
int usage_bytes = 0;
struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
+   u64 start_addr;
+   u64 size;
 
if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, 
_offset)) {
firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE 
*)(ctx->bios + data_offset);
@@ -1815,7 +1817,21 @@ int amdgpu_atombios_allocate_fb_scratch(struct 
amdgpu_device *adev)
  
le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
  
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
 
-   usage_bytes = 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 
1024;
+   start_addr = 
firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
+   size = 
firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
+
+   if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 
<<
+   ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->fw_vram_usage.start_offset = (start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->fw_vram_usage.size = size << 10;
+   /* Use the default scratch size */
+   usage_bytes = 0;
+   } else {
+   usage_bytes = 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 
1024;
+   }
}
ctx->scratch_size_bytes = 0;
if (usage_bytes == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a86d856..02e07a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -658,6 +658,93 @@ void amdgpu_gart_location(struct amdgpu_device *adev, 
struct amdgpu_mc *mc)
 }
 
 /*
+ * Firmware Reservation function
+ */
+/**
+ * amdgpu_fw_reserve_vram_fini - free fw reserved vram
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * free fw reserved vram if it has been reserved.
+ */
+void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
+{
+
+   if (adev->fw_vram_usage.reserved_bo == NULL)
+   return;
+
+   if (likely(amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo,
+   true) == 0)) {
+   amdgpu_bo_kunmap(adev->fw_vram_usage.reserved_bo);
+   amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
+   amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+   }
+   amdgpu_bo_unref(>fw_vram_usage.reserved_bo);
+
+   adev->fw_vram_usage.va = NULL;
+   adev->fw_vram_usage.reserved_bo

RE: [PATCH 1/2] drm/amdgpu: add functions to create bo at the specified position

2017-09-29 Thread Chen, Horace

OK. I have tried, it worked without any failure.
Thanks Christian.

Regards,
Horace.
-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] 
Sent: Thursday, September 28, 2017 10:01 PM
To: Chen, Horace ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: Re: [PATCH 1/2] drm/amdgpu: add functions to create bo at the 
specified position

NAK, please use the existing functionality for that.

Using amdgpu_bo_do_create() with domain=0 will just create the amdgpu_bo 
structure without allocating any backing memory.

This BO can then pinned to the desired VRAM location using amdgpu_bo_pin().

Regards,
Christian.

Am 28.09.2017 um 10:36 schrieb Horace Chen:
> Add two function to create and free bo at the specified position
> on the VRAM.
>
> Add a new parameter to amdgpu_bo_do_create to tell the start
> address of the special bo. If the start address is located in
> the GPU MC address space, the placement will be set to the exact
> place according to the size and start address. Otherwise the start
> address will be ingored.
>
> Signed-off-by: Horace Chen 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 129 
> -
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |   6 ++
>   2 files changed, 133 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 6982bae..0695160 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -284,6 +284,7 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 
> *gpu_addr,
>   }
>   
>   static int amdgpu_bo_do_create(struct amdgpu_device *adev,
> +u64 start_addr,
>  unsigned long size, int byte_align,
>  bool kernel, u32 domain, u64 flags,
>  struct sg_table *sg,
> @@ -297,9 +298,12 @@ static int amdgpu_bo_do_create(struct amdgpu_device 
> *adev,
>   u64 initial_bytes_moved, bytes_moved;
>   size_t acc_size;
>   int r;
> + int i;
> + bool vram_restricted = false;
>   
>   page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
>   size = ALIGN(size, PAGE_SIZE);
> + start_addr = ALIGN(start_addr, PAGE_SIZE);
>   
>   if (kernel) {
>   type = ttm_bo_type_kernel;
> @@ -366,6 +370,32 @@ static int amdgpu_bo_do_create(struct amdgpu_device 
> *adev,
>   bo->tbo.bdev = >mman.bdev;
>   amdgpu_ttm_placement_from_domain(bo, domain);
>   
> + /*
> +  * if domain is VRAM && start_addr in vram address space,
> +  * set the place to the specified place
> +  */
> + if ((domain == AMDGPU_GEM_DOMAIN_VRAM) &&
> + start_addr >= adev->mc.vram_start &&
> + (start_addr + size) < adev->mc.vram_end) {
> + start_addr -= adev->mc.vram_start;
> + vram_restricted = true;
> + } else if ((domain == AMDGPU_GEM_DOMAIN_GTT) &&
> + start_addr >= adev->mc.gart_start &&
> + (start_addr + size) < adev->mc.gart_end) {
> + /* if in gart address space */
> + start_addr -= adev->mc.gart_start;
> + vram_restricted = true;
> + }
> +
> + if (vram_restricted) {
> + for (i = 0; i < bo->placement.num_placement; ++i) {
> + bo->placements[i].fpfn =
> + start_addr >> PAGE_SHIFT;
> + bo->placements[i].lpfn =
> + (start_addr + size) >> PAGE_SHIFT;
> + }
> + }
> +
>   initial_bytes_moved = atomic64_read(>num_bytes_moved);
>   /* Kernel allocation are uninterruptible */
>   r = ttm_bo_init_reserved(>mman.bdev, >tbo, size, type,
> @@ -418,6 +448,101 @@ static int amdgpu_bo_do_create(struct amdgpu_device 
> *adev,
>   return r;
>   }
>   
> +/**
> + * amdgpu_bo_create_vram_restricted_kernel -
> + *create BO at the specified place on the VRAM.
> + *
> + * @adev: amdgpu device object
> + * @offset: start offset of the new BO
> + * @size: size for the new BO
> + * @byte_align: alignment for the new BO
> + * @flags: addition flags for the BO
> + * @bo_ptr: resulting BO
> + * @gpu_addr: GPU addr of the pinned BO
> + * @cpu_addr: optional CPU address mapping
> + *
> + * Allocates and pins a BO at the specified place on the VRAM.
> + *
> + * Returns 0 on success, negative error code otherwise.
> + */
> +int amdgpu_bo_create_vram_restricted_kernel(struct amdgpu_device *adev,
> +  u64 offset, unsigned long size, int byte_align,
> +  u64 flags, struct amdgpu_bo **bo_ptr,
> +  u64 *gpu_addr, void **cpu_addr)
> +{
> + int r;
> + u64 start_addr = offset + adev->mc.vram_start;
> + /* specified memory must be in contiguous*/
> + flags |=

[PATCH 07/10] amdgpu/dc: inline all the signal_types code.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

This is worth 300 bytes, and one less source file.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/basics/Makefile |  2 +-
 .../gpu/drm/amd/display/dc/basics/signal_types.c   | 80 --
 drivers/gpu/drm/amd/display/include/signal_types.h | 59 +---
 3 files changed, 52 insertions(+), 89 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/basics/signal_types.c

diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile 
b/drivers/gpu/drm/amd/display/dc/basics/Makefile
index 0658162..43c5ccd 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile
@@ -4,7 +4,7 @@
 # subcomponents.
 
 BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o \
-   logger.o log_helpers.o signal_types.o vector.o
+   logger.o log_helpers.o vector.o
 
 AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
 
diff --git a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c 
b/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
deleted file mode 100644
index 534c803..000
--- a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/signal_types.h"
-
-bool dc_is_hdmi_signal(enum signal_type signal)
-{
-   return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
-}
-
-bool dc_is_dp_sst_signal(enum signal_type signal)
-{
-   return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-   signal == SIGNAL_TYPE_EDP);
-}
-
-bool dc_is_dp_signal(enum signal_type signal)
-{
-   return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-   signal == SIGNAL_TYPE_EDP ||
-   signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-}
-
-bool dc_is_embedded_signal(enum signal_type signal)
-{
-   return (signal == SIGNAL_TYPE_EDP || signal == SIGNAL_TYPE_LVDS);
-}
-
-bool dc_is_dvi_signal(enum signal_type signal)
-{
-   switch (signal) {
-   case SIGNAL_TYPE_DVI_SINGLE_LINK:
-   case SIGNAL_TYPE_DVI_DUAL_LINK:
-   return true;
-   break;
-   default:
-   return false;
-   }
-}
-
-bool dc_is_dvi_single_link_signal(enum signal_type signal)
-{
-   return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
-}
-
-bool dc_is_dual_link_signal(enum signal_type signal)
-{
-   return (signal == SIGNAL_TYPE_DVI_DUAL_LINK);
-}
-
-bool dc_is_audio_capable_signal(enum signal_type signal)
-{
-   return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-   signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
-   dc_is_hdmi_signal(signal));
-}
-
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h 
b/drivers/gpu/drm/amd/display/include/signal_types.h
index 1a2ca53..b5ebde6 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -40,13 +40,56 @@ enum signal_type {
 };
 
 /* help functions for signal types manipulation */
-bool dc_is_hdmi_signal(enum signal_type signal);
-bool dc_is_dp_sst_signal(enum signal_type signal);
-bool dc_is_dp_signal(enum signal_type signal);
-bool dc_is_embedded_signal(enum signal_type signal);
-bool dc_is_dvi_signal(enum signal_type signal);
-bool dc_is_dvi_single_link_signal(enum signal_type signal);
-bool dc_is_dual_link_signal(enum signal_type signal);
-bool dc_is_audio_capable_signal(enum signal_type signal);
+static inline bool dc_is_hdmi_signal(enum signal_type signal)
+{
+   return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
+}
+
+static inline bool dc_is_dp_sst_signal(enum signal_type signal)
+{
+   return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
+   signal == SIGNAL_TYPE_EDP);
+}
+
+static inline bool dc_is_dp_signal(enum signal_type signal)
+{
+

[PATCH 04/10] amdgpu/dc: allow inlining constant int to fixed a lot better.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

This uses two things that might be Linux specific,
__builtin_constant_p (might be gcc)
and
BUILD_BUG_ON. (maybe other dm's can have something similiar).

This saves 4k in the bw calcs code.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c | 37 -
 drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h   | 26 +++--
 2 files changed, 35 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c 
b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
index 0de6fa1..6ca288f 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
@@ -25,13 +25,6 @@
 #include "dm_services.h"
 #include "bw_fixed.h"
 
-#define BITS_PER_FRACTIONAL_PART 24
-
-#define MIN_I32 \
-   (int64_t)(-(1LL << (63 - BITS_PER_FRACTIONAL_PART)))
-
-#define MAX_I32 \
-   (int64_t)((1ULL << (63 - BITS_PER_FRACTIONAL_PART)) - 1)
 
 #define MIN_I64 \
(int64_t)(-(1LL << 63))
@@ -40,10 +33,7 @@
(int64_t)((1ULL << 63) - 1)
 
 #define FRACTIONAL_PART_MASK \
-   ((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
-
-#define GET_INTEGER_PART(x) \
-   ((x) >> BITS_PER_FRACTIONAL_PART)
+   ((1ULL << BW_FIXED_BITS_PER_FRACTIONAL_PART) - 1)
 
 #define GET_FRACTIONAL_PART(x) \
(FRACTIONAL_PART_MASK & (x))
@@ -56,19 +46,14 @@ static uint64_t abs_i64(int64_t arg)
return (uint64_t)(-arg);
 }
 
-struct bw_fixed bw_int_to_fixed(int64_t value)
+struct bw_fixed bw_int_to_fixed_nonconst(int64_t value)
 {
struct bw_fixed res;
-   ASSERT(value < MAX_I32 && value > MIN_I32);
-   res.value = value << BITS_PER_FRACTIONAL_PART;
+   ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32);
+   res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART;
return res;
 }
 
-int32_t bw_fixed_to_int(struct bw_fixed value)
-{
-   return GET_INTEGER_PART(value.value);
-}
-
 struct bw_fixed bw_frc_to_fixed(int64_t numerator, int64_t denominator)
 {
struct bw_fixed res;
@@ -87,11 +72,11 @@ struct bw_fixed bw_frc_to_fixed(int64_t numerator, int64_t 
denominator)
arg2_value = abs_i64(denominator);
res_value = div64_u64_rem(arg1_value, arg2_value, );
 
-   ASSERT(res_value <= MAX_I32);
+   ASSERT(res_value <= BW_FIXED_MAX_I32);
 
/* determine fractional part */
{
-   uint32_t i = BITS_PER_FRACTIONAL_PART;
+   uint32_t i = BW_FIXED_BITS_PER_FRACTIONAL_PART;
 
do
{
@@ -164,8 +149,8 @@ struct bw_fixed bw_mul(const struct bw_fixed arg1, const 
struct bw_fixed arg2)
uint64_t arg1_value = abs_i64(arg1.value);
uint64_t arg2_value = abs_i64(arg2.value);
 
-   uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
-   uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
+   uint64_t arg1_int = BW_FIXED_GET_INTEGER_PART(arg1_value);
+   uint64_t arg2_int = BW_FIXED_GET_INTEGER_PART(arg2_value);
 
uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
@@ -174,9 +159,9 @@ struct bw_fixed bw_mul(const struct bw_fixed arg1, const 
struct bw_fixed arg2)
 
res.value = arg1_int * arg2_int;
 
-   ASSERT(res.value <= MAX_I32);
+   ASSERT(res.value <= BW_FIXED_MAX_I32);
 
-   res.value <<= BITS_PER_FRACTIONAL_PART;
+   res.value <<= BW_FIXED_BITS_PER_FRACTIONAL_PART;
 
tmp = arg1_int * arg2_fra;
 
@@ -192,7 +177,7 @@ struct bw_fixed bw_mul(const struct bw_fixed arg1, const 
struct bw_fixed arg2)
 
tmp = arg1_fra * arg2_fra;
 
-   tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
+   tmp = (tmp >> BW_FIXED_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)(bw_frc_to_fixed(1, 2).value));
 
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h 
b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
index 4477e62..39ee8eba3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
@@ -26,10 +26,19 @@
 #ifndef BW_FIXED_H_
 #define BW_FIXED_H_
 
+#define BW_FIXED_BITS_PER_FRACTIONAL_PART 24
+
+#define BW_FIXED_GET_INTEGER_PART(x) ((x) >> BW_FIXED_BITS_PER_FRACTIONAL_PART)
 struct bw_fixed {
int64_t value;
 };
 
+#define BW_FIXED_MIN_I32 \
+   (int64_t)(-(1LL << (63 - BW_FIXED_BITS_PER_FRACTIONAL_PART)))
+
+#define BW_FIXED_MAX_I32 \
+   (int64_t)((1ULL << (63 - BW_FIXED_BITS_PER_FRACTIONAL_PART)) - 1)
+
 static inline struct bw_fixed bw_min2(const struct bw_fixed arg1,
  const struct bw_fixed arg2)
 {
@@ -56,9 +65,22 @@ static inline struct bw_fixed bw_max3(struct bw_fixed v1,
return bw_max2(bw_max2(v1, v2), v3);
 }
 
-struct bw_fixed bw_int_to_fixed(int64_t value);
+struct bw_fixed bw_int_to_fixed_nonconst(int64_t

[PATCH 09/10] amdgpu/dc: rename bios get_image symbol to something more searchable.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

This just makes it easier to find.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c| 6 +++---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c | 2 +-
 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index f6828f4..2e003b5 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -412,7 +412,7 @@ static enum bp_result 
bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
if (!DATA_TABLES(VoltageObjectInfo))
return result;
 
-   voltage_info_address = get_image(>base, 
DATA_TABLES(VoltageObjectInfo), sizeof(ATOM_COMMON_TABLE_HEADER));
+   voltage_info_address = bios_get_image(>base, 
DATA_TABLES(VoltageObjectInfo), sizeof(ATOM_COMMON_TABLE_HEADER));
 
header = (ATOM_COMMON_TABLE_HEADER *) voltage_info_address;
 
@@ -2328,7 +2328,7 @@ static uint32_t get_dest_obj_list(struct bios_parser *bp,
return 0;
 
offset += sizeof(uint8_t);
-   *id_list = (uint16_t *)get_image(>base, offset, *number * 
sizeof(uint16_t));
+   *id_list = (uint16_t *)bios_get_image(>base, offset, *number * 
sizeof(uint16_t));
 
if (!*id_list)
return 0;
@@ -2355,7 +2355,7 @@ static uint32_t get_src_obj_list(struct bios_parser *bp, 
ATOM_OBJECT *object,
return 0;
 
offset += sizeof(uint8_t);
-   *id_list = (uint16_t *)get_image(>base, offset, *number * 
sizeof(uint16_t));
+   *id_list = (uint16_t *)bios_get_image(>base, offset, *number * 
sizeof(uint16_t));
 
if (!*id_list)
return 0;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 852bb0d..0c623b3 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -535,7 +535,7 @@ static enum bp_result 
bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
if (!DATA_TABLES(voltageobject_info))
return result;
 
-   voltage_info_address = get_image(>base,
+   voltage_info_address = bios_get_image(>base,
DATA_TABLES(voltageobject_info),
sizeof(struct atom_common_table_header));
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index 8e56d2f..5c9e510 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -33,7 +33,7 @@
 #include "command_table.h"
 #include "bios_parser_types_internal.h"
 
-uint8_t *get_image(struct dc_bios *bp,
+uint8_t *bios_get_image(struct dc_bios *bp,
uint32_t offset,
uint32_t size)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
index a8fbb82..c0047ef 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
@@ -28,13 +28,13 @@
 
 struct bios_parser;
 
-uint8_t *get_image(struct dc_bios *bp, uint32_t offset,
+uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,
uint32_t size);
 
 bool bios_is_accelerated_mode(struct dc_bios *bios);
 void bios_set_scratch_acc_mode_change(struct dc_bios *bios);
 void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
 
-#define GET_IMAGE(type, offset) ((type *) get_image(>base, offset, 
sizeof(type)))
+#define GET_IMAGE(type, offset) ((type *) bios_get_image(>base, offset, 
sizeof(type)))
 
 #endif
-- 
2.9.4

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[PATCH 10/10] amdgpu/dc: inline dml_round_to_multiple

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

turns out to be a win to inline this.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c | 19 ---
 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h |  2 --
 drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h | 19 +++
 3 files changed, 19 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c 
b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
index 7c0eb52..df2d509 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
@@ -39,23 +39,4 @@ double dml_round(double a)
return floor;
 }
 
-unsigned int dml_round_to_multiple(
-   unsigned int num,
-   unsigned int multiple,
-   bool up)
-{
-   unsigned int remainder;
-
-   if (multiple == 0)
-   return num;
-
-   remainder = num % multiple;
 
-   if (remainder == 0)
-   return num;
-
-   if (up)
-   return (num + multiple - remainder);
-   else
-   return (num - remainder);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h 
b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
index a2da3da..81c53d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
@@ -33,7 +33,5 @@
 #define DTRACE(str, ...) dm_logger_write(mode_lib->logger, LOG_DML, str, 
##__VA_ARGS__);
 
 double dml_round(double a);
-unsigned int dml_round_to_multiple(
-   unsigned int num, unsigned int multiple, bool up);
 
 #endif /* __DC_COMMON_DEFS_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h 
b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
index 1c6c631..a91b4a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
@@ -58,4 +58,23 @@ static inline double dml_log(double x, double base)
return (double) dcn_bw_log(x, base);
 }
 
+static inline unsigned int dml_round_to_multiple(unsigned int num,
+unsigned int multiple,
+bool up)
+{
+   unsigned int remainder;
+
+   if (multiple == 0)
+   return num;
+
+   remainder = num % multiple;
+
+   if (remainder == 0)
+   return num;
+
+   if (up)
+   return (num + multiple - remainder);
+   else
+   return (num - remainder);
+}
 #endif
-- 
2.9.4

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[PATCH 03/10] amdgpu/dc: inline some of the bw_fixed code.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

This results in a ~4.5k code size reduction.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c |  93 
 drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h   | 111 
 2 files changed, 96 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c 
b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
index fbf2adc..0de6fa1 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
@@ -56,16 +56,6 @@ static uint64_t abs_i64(int64_t arg)
return (uint64_t)(-arg);
 }
 
-struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct 
bw_fixed v3)
-{
-   return bw_min2(bw_min2(v1, v2), v3);
-}
-
-struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct 
bw_fixed v3)
-{
-   return bw_max2(bw_max2(v1, v2), v3);
-}
-
 struct bw_fixed bw_int_to_fixed(int64_t value)
 {
struct bw_fixed res;
@@ -133,16 +123,6 @@ struct bw_fixed bw_frc_to_fixed(int64_t numerator, int64_t 
denominator)
return res;
 }
 
-struct bw_fixed bw_min2(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return (arg1.value <= arg2.value) ? arg1 : arg2;
-}
-
-struct bw_fixed bw_max2(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return (arg2.value <= arg1.value) ? arg1 : arg2;
-}
-
 struct bw_fixed bw_floor2(
const struct bw_fixed arg,
const struct bw_fixed significance)
@@ -174,24 +154,6 @@ struct bw_fixed bw_ceil2(
return result;
 }
 
-struct bw_fixed bw_add(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   struct bw_fixed res;
-
-   res.value = arg1.value + arg2.value;
-
-   return res;
-}
-
-struct bw_fixed bw_sub(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   struct bw_fixed res;
-
-   res.value = arg1.value - arg2.value;
-
-   return res;
-}
-
 struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
 {
struct bw_fixed res;
@@ -242,58 +204,3 @@ struct bw_fixed bw_mul(const struct bw_fixed arg1, const 
struct bw_fixed arg2)
return res;
 }
 
-struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   struct bw_fixed res = bw_frc_to_fixed(arg1.value, arg2.value);
-   return res;
-}
-
-struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   struct bw_fixed res;
-   div64_u64_rem(arg1.value, arg2.value, );
-   return res;
-}
-struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw)
-{
-   struct bw_fixed result = { 0 };
-
-   if (raw < 0) {
-   raw = -raw;
-   result.value = -(raw >> (32 - BITS_PER_FRACTIONAL_PART));
-   } else {
-   result.value = raw >> (32 - BITS_PER_FRACTIONAL_PART);
-   }
-
-   return result;
-}
-
-bool bw_equ(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return arg1.value == arg2.value;
-}
-
-bool bw_neq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return arg1.value != arg2.value;
-}
-
-bool bw_leq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return arg1.value <= arg2.value;
-}
-
-bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return arg1.value >= arg2.value;
-}
-
-bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return arg1.value < arg2.value;
-}
-
-bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-{
-   return arg1.value > arg2.value;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h 
b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
index b31d07a..4477e62 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
@@ -30,9 +30,31 @@ struct bw_fixed {
int64_t value;
 };
 
-struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct 
bw_fixed v3);
+static inline struct bw_fixed bw_min2(const struct bw_fixed arg1,
+ const struct bw_fixed arg2)
+{
+   return (arg1.value <= arg2.value) ? arg1 : arg2;
+}
 
-struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct 
bw_fixed v3);
+static inline struct bw_fixed bw_max2(const struct bw_fixed arg1,
+ const struct bw_fixed arg2)
+{
+   return (arg2.value <= arg1.value) ? arg1 : arg2;
+}
+
+static inline struct bw_fixed bw_min3(struct bw_fixed v1,
+ struct bw_fixed v2,
+ struct bw_fixed v3)
+{
+   return bw_min2(bw_min2(v1, v2), v3);
+}
+
+static inline struct bw_fixed bw_max3(struct bw_fixed v1,
+ struct bw_fixed v2,
+ struct bw_fixed v3)
+{
+   return bw_max2(bw_max2(v1,

[PATCH 06/10] amdgpu/dc: inline fixed31_32 div_int

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 9 -
 drivers/gpu/drm/amd/display/include/fixed31_32.h   | 9 ++---
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c 
b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 1764a33..2693689 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -266,15 +266,6 @@ struct fixed31_32 dal_fixed31_32_sqr(
return res;
 }
 
-struct fixed31_32 dal_fixed31_32_div_int(
-   struct fixed31_32 arg1,
-   int64_t arg2)
-{
-   return dal_fixed31_32_from_fraction(
-   arg1.value,
-   dal_fixed31_32_from_int(arg2).value);
-}
-
 struct fixed31_32 dal_fixed31_32_recip(
struct fixed31_32 arg)
 {
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 2c9e223..3248f69 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -308,9 +308,12 @@ struct fixed31_32 dal_fixed31_32_sqr(
  * @brief
  * result = arg1 / arg2
  */
-struct fixed31_32 dal_fixed31_32_div_int(
-   struct fixed31_32 arg1,
-   int64_t arg2);
+static inline struct fixed31_32 dal_fixed31_32_div_int(struct fixed31_32 arg1,
+  int64_t arg2)
+{
+   return dal_fixed31_32_from_fraction(arg1.value,
+   
dal_fixed31_32_from_int(arg2).value);
+}
 
 /*
  * @brief
-- 
2.9.4

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[PATCH 02/10] amdgpu/dc: move some one line dp functions to inlines.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 38ccc01..305ca0d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1191,12 +1191,12 @@ struct dc_link_settings 
get_common_supported_link_settings (
return link_settings;
 }
 
-bool reached_minimum_lane_count(enum dc_lane_count lane_count)
+static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
 {
return lane_count <= LANE_COUNT_ONE;
 }
 
-bool reached_minimum_link_rate(enum dc_link_rate link_rate)
+static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
 {
return link_rate <= LINK_RATE_LOW;
 }
-- 
2.9.4

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[PATCH 01/10] amdgpu/dc: hide some unused aux/i2c payload apis.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

I've no idea if these are used on other platforms, but they
aren't used outside this file here, so make them static.

Drops 300 bytes.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 16 
 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h  | 10 --
 2 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 315160d..d5294798b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -126,7 +126,7 @@ struct aux_payloads {
struct vector payloads;
 };
 
-struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, 
uint32_t count)
+static struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context 
*ctx, uint32_t count)
 {
struct i2c_payloads *payloads;
 
@@ -144,17 +144,17 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct 
dc_context *ctx, uint32_
 
 }
 
-struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
+static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
 {
return (struct i2c_payload *)p->payloads.container;
 }
 
-uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
+static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
 {
return p->payloads.count;
 }
 
-void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
+static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
 {
if (!p || !*p)
return;
@@ -164,7 +164,7 @@ void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
 
 }
 
-struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, 
uint32_t count)
+static struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context 
*ctx, uint32_t count)
 {
struct aux_payloads *payloads;
 
@@ -181,17 +181,17 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct 
dc_context *ctx, uint32_
return NULL;
 }
 
-struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
+static struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
 {
return (struct aux_payload *)p->payloads.container;
 }
 
-uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
+static uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
 {
return p->payloads.count;
 }
 
-void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
+static void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
 {
if (!p || !*p)
return;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h 
b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index af7ea5e..0bf73b7 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -57,16 +57,6 @@ struct dp_receiver_id_info;
 struct i2c_payloads;
 struct aux_payloads;
 
-struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, 
uint32_t count);
-struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p);
-uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p);
-void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p);
-
-struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, 
uint32_t count);
-struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p);
-uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p);
-void dal_ddc_aux_payloads_destroy(struct aux_payloads **p);
-
 void dal_ddc_i2c_payloads_add(
struct i2c_payloads *payloads,
uint32_t address,
-- 
2.9.4

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[PATCH 05/10] amdgpu/dc: use the builtin constant p trick on the 31/32 fixed point.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

This only gets us 100 bytes, but may as well be consistent.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 22 ++
 drivers/gpu/drm/amd/display/include/fixed31_32.h   | 15 +--
 2 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c 
b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 578691c..1764a33 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -54,14 +54,12 @@ static inline uint64_t complete_integer_division_u64(
return result;
 }
 
-#define BITS_PER_FRACTIONAL_PART \
-   32
 
 #define FRACTIONAL_PART_MASK \
-   ((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
+   ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1)
 
 #define GET_INTEGER_PART(x) \
-   ((x) >> BITS_PER_FRACTIONAL_PART)
+   ((x) >> FIXED31_32_BITS_PER_FRACTIONAL_PART)
 
 #define GET_FRACTIONAL_PART(x) \
(FRACTIONAL_PART_MASK & (x))
@@ -89,7 +87,7 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
 
/* determine fractional part */
{
-   uint32_t i = BITS_PER_FRACTIONAL_PART;
+   uint32_t i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
 
do {
remainder <<= 1;
@@ -120,14 +118,14 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
return res;
 }
 
-struct fixed31_32 dal_fixed31_32_from_int(
+struct fixed31_32 dal_fixed31_32_from_int_nonconst(
int64_t arg)
 {
struct fixed31_32 res;
 
ASSERT((LONG_MIN <= arg) && (arg <= LONG_MAX));
 
-   res.value = arg << BITS_PER_FRACTIONAL_PART;
+   res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
 
return res;
 }
@@ -198,7 +196,7 @@ struct fixed31_32 dal_fixed31_32_mul(
 
ASSERT(res.value <= LONG_MAX);
 
-   res.value <<= BITS_PER_FRACTIONAL_PART;
+   res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
 
tmp = arg1_int * arg2_fra;
 
@@ -214,7 +212,7 @@ struct fixed31_32 dal_fixed31_32_mul(
 
tmp = arg1_fra * arg2_fra;
 
-   tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
+   tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)dal_fixed31_32_half.value);
 
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
@@ -244,7 +242,7 @@ struct fixed31_32 dal_fixed31_32_sqr(
 
ASSERT(res.value <= LONG_MAX);
 
-   res.value <<= BITS_PER_FRACTIONAL_PART;
+   res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
 
tmp = arg_int * arg_fra;
 
@@ -258,7 +256,7 @@ struct fixed31_32 dal_fixed31_32_sqr(
 
tmp = arg_fra * arg_fra;
 
-   tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
+   tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)dal_fixed31_32_half.value);
 
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
@@ -560,7 +558,7 @@ static inline uint32_t ux_dy(
/* 4. make space for fractional part to be filled in after integer */
result <<= fractional_bits;
/* 5. shrink fixed point fractional part to of fractional_bits width*/
-   fractional_part >>= BITS_PER_FRACTIONAL_PART - fractional_bits;
+   fractional_part >>= FIXED31_32_BITS_PER_FRACTIONAL_PART - 
fractional_bits;
/* 6. merge the result */
return result | fractional_part;
 }
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index f0bc3c4..2c9e223 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -28,6 +28,8 @@
 
 #include "os_types.h"
 
+#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
+
 /*
  * @brief
  * Arithmetic operations on real numbers
@@ -78,8 +80,17 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
  * @brief
  * result = arg
  */
-struct fixed31_32 dal_fixed31_32_from_int(
-   int64_t arg);
+struct fixed31_32 dal_fixed31_32_from_int_nonconst(int64_t arg);
+static inline struct fixed31_32 dal_fixed31_32_from_int(int64_t arg)
+{
+   if (__builtin_constant_p(arg)) {
+   struct fixed31_32 res;
+   BUILD_BUG_ON((LONG_MIN > arg) || (arg > LONG_MAX));
+   res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
+   return res;
+   } else
+   return dal_fixed31_32_from_int_nonconst(arg);
+}
 
 /*
  * @brief
-- 
2.9.4

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[PATCH 08/10] amdgpu/dc: set some of the link dp code to static.

2017-09-29 Thread Dave Airlie

From: Dave Airlie 

These aren't currently used outside this file.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 18 +-
 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h  |  8 
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 305ca0d..888d268 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -32,6 +32,14 @@ enum {
LINK_TRAINING_MAX_CR_RETRY = 100
 };
 
+static bool decide_fallback_link_setting(
+   struct dc_link_settings initial_link_settings,
+   struct dc_link_settings *current_link_setting,
+   enum link_training_result training_result);
+static struct dc_link_settings get_common_supported_link_settings (
+   struct dc_link_settings link_setting_a,
+   struct dc_link_settings link_setting_b);
+
 static void wait_for_training_aux_rd_interval(
struct dc_link *link,
uint32_t default_wait_in_micro_secs)
@@ -1150,7 +1158,7 @@ bool dp_hbr_verify_link_cap(
return success;
 }
 
-struct dc_link_settings get_common_supported_link_settings (
+static struct dc_link_settings get_common_supported_link_settings (
struct dc_link_settings link_setting_a,
struct dc_link_settings link_setting_b)
 {
@@ -1215,7 +1223,7 @@ enum dc_lane_count reduce_lane_count(enum dc_lane_count 
lane_count)
}
 }
 
-enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
+static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
 {
switch (link_rate) {
case LINK_RATE_HIGH3:
@@ -1231,7 +1239,7 @@ enum dc_link_rate reduce_link_rate(enum dc_link_rate 
link_rate)
}
 }
 
-enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
+static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
 {
switch (lane_count) {
case LANE_COUNT_ONE:
@@ -1243,7 +1251,7 @@ enum dc_lane_count increase_lane_count(enum dc_lane_count 
lane_count)
}
 }
 
-enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
+static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
 {
switch (link_rate) {
case LINK_RATE_LOW:
@@ -1265,7 +1273,7 @@ enum dc_link_rate increase_link_rate(enum dc_link_rate 
link_rate)
  * false - has reached minimum setting
  * and no further fallback could be done
  */
-bool decide_fallback_link_setting(
+static bool decide_fallback_link_setting(
struct dc_link_settings initial_link_settings,
struct dc_link_settings *current_link_setting,
enum link_training_result training_result)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h 
b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index 7168dcc..616c73e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -37,14 +37,6 @@ bool dp_hbr_verify_link_cap(
struct dc_link *link,
struct dc_link_settings *known_limit_link_setting);
 
-bool decide_fallback_link_setting(struct dc_link_settings link_setting_init,
-   struct dc_link_settings *link_setting_current,
-   enum link_training_result training_result);
-
-struct dc_link_settings get_common_supported_link_settings (
-   struct dc_link_settings link_setting_a,
-   struct dc_link_settings link_setting_b);
-
 bool dp_validate_mode_timing(
struct dc_link *link,
const struct dc_crtc_timing *timing);
-- 
2.9.4

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