[PATCH 1/1] drm/amdgpu: only set dma_buf ops when it is valid
Change-Id: I37daecbf695da13eaeea1d362c270b92a894393a
---
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index a14234b..8afec21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -221,9 +221,10 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device
*dev,
return ERR_PTR(-EPERM);
buf = drm_gem_prime_export(dev, gobj, flags);
- if (!IS_ERR(buf))
+ if (!IS_ERR(buf)) {
buf->file->f_mapping = dev->anon_inode->i_mapping;
- buf->ops = &amdgpu_dmabuf_ops;
+ buf->ops = &amdgpu_dmabuf_ops;
+ }
return buf;
}
--
2.7.4
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[PATCH 1/2] drm/ttm: Allow page allocations w/o triggering OOM..
This to allow drivers to choose to avoid OOM invocation and handle
page allocation failures instead.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 +++
drivers/gpu/drm/ttm/ttm_page_alloc.c | 6 ++
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 3 +++
drivers/gpu/drm/ttm/ttm_tt.c | 13 +++--
include/drm/ttm/ttm_bo_api.h | 1 +
include/drm/ttm/ttm_bo_driver.h | 4
6 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2eb71ff..f32aab1 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -234,6 +234,9 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo,
bool zero_alloc)
if (bdev->need_dma32)
page_flags |= TTM_PAGE_FLAG_DMA32;
+ if (bdev->no_retry)
+ page_flags |= TTM_PAGE_FLAG_NO_RETRY;
+
switch (bo->type) {
case ttm_bo_type_device:
if (zero_alloc)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 0eab24e..f34c843 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -741,6 +741,9 @@ static int ttm_page_pool_get_pages(struct ttm_page_pool
*pool,
if (ttm_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
+ if (ttm_flags & TTM_PAGE_FLAG_NO_RETRY)
+ gfp_flags |= __GFP_RETRY_MAYFAIL;
+
/* ttm_alloc_new_pages doesn't reference pool so we can run
* multiple requests in parallel.
**/
@@ -893,6 +896,9 @@ static int ttm_get_pages(struct page **pages, unsigned
npages, int flags,
if (flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
+ if (flags & TTM_PAGE_FLAG_NO_RETRY)
+ gfp_flags |= __GFP_RETRY_MAYFAIL;
+
if (flags & TTM_PAGE_FLAG_DMA32)
gfp_flags |= GFP_DMA32;
else
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index c7f01a4..6949ef7 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -920,6 +920,9 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt
*ttm_dma, bool huge)
gfp_flags &= ~__GFP_COMP;
}
+ if (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY)
+ gfp_flags |= __GFP_RETRY_MAYFAIL;
+
return gfp_flags;
}
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 5a046a3..9e4d43d 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -301,7 +301,11 @@ int ttm_tt_swapin(struct ttm_tt *ttm)
swap_space = swap_storage->f_mapping;
for (i = 0; i < ttm->num_pages; ++i) {
- from_page = shmem_read_mapping_page(swap_space, i);
+ gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+ gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ?
__GFP_RETRY_MAYFAIL : 0);
+ from_page = shmem_read_mapping_page_gfp(swap_space, i,
gfp_mask);
+
if (IS_ERR(from_page)) {
ret = PTR_ERR(from_page);
goto out_err;
@@ -350,10 +354,15 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file
*persistent_swap_storage)
swap_space = swap_storage->f_mapping;
for (i = 0; i < ttm->num_pages; ++i) {
+ gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+ gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ?
__GFP_RETRY_MAYFAIL : 0);
+
from_page = ttm->pages[i];
if (unlikely(from_page == NULL))
continue;
- to_page = shmem_read_mapping_page(swap_space, i);
+
+ to_page = shmem_read_mapping_page_gfp(swap_space, i, gfp_mask);
if (IS_ERR(to_page)) {
ret = PTR_ERR(to_page);
goto out_err;
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 2cd025c..099f24b 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -176,6 +176,7 @@ struct ttm_buffer_object {
unsigned long num_pages;
size_t acc_size;
+
/**
* Members not needing protection.
*/
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 94064b1..9b417eb 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -86,6 +86,7 @@ struct ttm_backend_func {
#define TTM_PAGE_FLAG_ZERO_ALLOC (1 << 6)
#define TTM_PAGE_FLAG_DMA32 (1 << 7)
#define TTM_PAGE_FLAG_SG (1 << 8)
+#define TTM_PAGE_FLAG_NO_RETRY(1 << 9)
enum ttm_caching_state {
tt_uncached,
@@ -556,6 +
[PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.
This to have a load time option to avoid OOM on RAM allocations. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b7c181e..1387239 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -127,6 +127,7 @@ extern int amdgpu_job_hang_limit; extern int amdgpu_lbpw; extern int amdgpu_compute_multipipe; extern int amdgpu_gpu_recovery; +extern int amdgpu_alloc_no_oom; #ifdef CONFIG_DRM_AMDGPU_SI extern int amdgpu_si_support; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index d96f9ac..6e98189 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -130,6 +130,7 @@ int amdgpu_job_hang_limit = 0; int amdgpu_lbpw = -1; int amdgpu_compute_multipipe = -1; int amdgpu_gpu_recovery = -1; /* auto */ +int amdgpu_alloc_no_oom = -1; /* auto */ MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@ -285,6 +286,9 @@ module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto"); module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); +MODULE_PARM_DESC(alloc_no_oom, "Allocate RAM without triggering OOM killer, (1 = enable, 0 = disable, -1 = auto"); +module_param_named(alloc_no_oom, amdgpu_alloc_no_oom, int, 0444); + #ifdef CONFIG_DRM_AMDGPU_SI #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 5c4c3e0..fc27164 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, #endif bo->tbo.bdev = &adev->mman.bdev; + + if (amdgpu_alloc_no_oom == 1) + bo->tbo.bdev->no_retry = true; + amdgpu_ttm_placement_from_domain(bo, domain); r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Use seq_putc() in two functions
From: Markus Elfring
Date: Fri, 12 Jan 2018 22:08:50 +0100
A few single characters should be put into a sequence.
Thus use the corresponding function "seq_putc".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 9 +++--
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 10805edcf964..7ac233f5abe2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -806,8 +806,8 @@ static int amdgpu_debugfs_gem_bo_info(int id, void *ptr,
void *data)
pin_count = READ_ONCE(bo->pin_count);
if (pin_count)
seq_printf(m, " pin count %d", pin_count);
- seq_printf(m, "\n");
+ seq_putc(m, '\n');
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 3144400435b7..57ce42d960ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -419,11 +419,8 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager
*sa_manager,
list_for_each_entry(i, &sa_manager->olist, olist) {
uint64_t soffset = i->soffset + sa_manager->gpu_addr;
uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
- if (&i->olist == sa_manager->hole) {
- seq_printf(m, ">");
- } else {
- seq_printf(m, " ");
- }
+
+ seq_putc(m, (&i->olist == sa_manager->hole) ? '>' : ' ');
seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
soffset, eoffset, eoffset - soffset);
@@ -431,7 +428,7 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager
*sa_manager,
seq_printf(m, " protected by 0x%08x on context %llu",
i->fence->seqno, i->fence->context);
- seq_printf(m, "\n");
+ seq_putc(m, '\n');
}
spin_unlock(&sa_manager->wq.lock);
}
--
2.15.1
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Re: BUG: KASAN: use-after-free in amdgpu_job_free_cb
Yea, I know , just dumped diff of one file into it, please search in
code for
"ret = do_aquire_global_lock(dev, state);" it appears only in one place
in entire code base, and manually apply the one line change.
Thanks,
Andrey
On 01/12/2018 04:47 PM, Johannes Hirte wrote:
On 2018 Jan 12, Andrey Grodzovsky wrote:
Hi, looks to me like a different issue (not related) then the one
Johannes, reports, your issue was already reported by some one (can't
remember the thread of hand) and looks like in shader hang or GPU
scheduler synchronization issue while Johannes's use after free is pure
software logic issue in either KMS atomic framework or more probably in
AMDGPU/DC (DAL).
Johanes, I attached a debug patch which forces the cursor update to wait
for any page flip in progress, can you give it a try and see if the
issue is gone ? This is not an actual fix but just to evaluate the reason.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5a70682..323d020 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4908,7 +4908,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
* synchronization events.
*/
- if (lock_and_validation_needed) {
+ if (lock_and_validation_needed || state->legacy_cursor_update == true) {
ret = do_aquire_global_lock(dev, state);
if (ret)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index a1a751b..6d6ffdf 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
The patch seems incomplete.
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Re: BUG: KASAN: use-after-free in amdgpu_job_free_cb
On 2018 Jan 12, Andrey Grodzovsky wrote:
> Hi, looks to me like a different issue (not related) then the one
> Johannes, reports, your issue was already reported by some one (can't
> remember the thread of hand) and looks like in shader hang or GPU
> scheduler synchronization issue while Johannes's use after free is pure
> software logic issue in either KMS atomic framework or more probably in
> AMDGPU/DC (DAL).
>
>
> Johanes, I attached a debug patch which forces the cursor update to wait
> for any page flip in progress, can you give it a try and see if the
> issue is gone ? This is not an actual fix but just to evaluate the reason.
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 5a70682..323d020 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4908,7 +4908,7 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> * synchronization events.
> */
>
> - if (lock_and_validation_needed) {
> + if (lock_and_validation_needed || state->legacy_cursor_update ==
> true) {
>
> ret = do_aquire_global_lock(dev, state);
> if (ret)
> diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c
> b/drivers/gpu/drm/ttm/ttm_page_alloc.c
> index a1a751b..6d6ffdf 100644
> --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
> +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
The patch seems incomplete.
--
Regards,
Johannes
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Re: [PATCH] drm/amdgpu: only allow scatter/gather display with DC
I think you are getting lucky with the pageflip buffers always ending up in
vram. Also, the legacy dce code (e.g., dce_v11_0.c) always pins in vram for
modesets.
Alex
From: Li, Samuel
Sent: Friday, January 12, 2018 4:35 PM
To: Koenig, Christian; Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu: only allow scatter/gather display with DC
Somehow my test case seems working although DC not enabled?
Regards,
Samuel Li
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Friday, January 12, 2018 4:03 PM
> To: Alex Deucher ; amd-
> g...@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH] drm/amdgpu: only allow scatter/gather display with DC
>
> Am 12.01.2018 um 20:58 schrieb Alex Deucher:
> > Check if DC is enabled before allowing scanout buffers to be pinned in
> > system memory.
> >
> > Signed-off-by: Alex Deucher
>
> Reviewed-by: Christian König
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index 8ede2645a06c..859942552e9f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -507,9 +507,12 @@ uint32_t
> amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)
> > {
> > uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
> >
> > +#if defined(CONFIG_DRM_AMD_DC)
> > if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <
> CHIP_RAVEN &&
> > - adev->flags & AMD_IS_APU)
> > + adev->flags & AMD_IS_APU &&
> > + amdgpu_device_asic_has_dc_support(adev->asic_type))
> > domain |= AMDGPU_GEM_DOMAIN_GTT;
> > +#endif
> >
> > return domain;
> > }
>
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RE: [PATCH] drm/amdgpu: only allow scatter/gather display with DC
Somehow my test case seems working although DC not enabled?
Regards,
Samuel Li
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Friday, January 12, 2018 4:03 PM
> To: Alex Deucher ; amd-
> g...@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH] drm/amdgpu: only allow scatter/gather display with DC
>
> Am 12.01.2018 um 20:58 schrieb Alex Deucher:
> > Check if DC is enabled before allowing scanout buffers to be pinned in
> > system memory.
> >
> > Signed-off-by: Alex Deucher
>
> Reviewed-by: Christian König
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index 8ede2645a06c..859942552e9f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -507,9 +507,12 @@ uint32_t
> amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)
> > {
> > uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
> >
> > +#if defined(CONFIG_DRM_AMD_DC)
> > if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <
> CHIP_RAVEN &&
> > - adev->flags & AMD_IS_APU)
> > + adev->flags & AMD_IS_APU &&
> > + amdgpu_device_asic_has_dc_support(adev->asic_type))
> > domain |= AMDGPU_GEM_DOMAIN_GTT;
> > +#endif
> >
> > return domain;
> > }
>
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Re: [PATCH] drm/amdgpu: only allow scatter/gather display with DC
Am 12.01.2018 um 20:58 schrieb Alex Deucher:
Check if DC is enabled before allowing scanout buffers
to be pinned in system memory.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 8ede2645a06c..859942552e9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -507,9 +507,12 @@ uint32_t amdgpu_display_framebuffer_domains(struct
amdgpu_device *adev)
{
uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
+#if defined(CONFIG_DRM_AMD_DC)
if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
- adev->flags & AMD_IS_APU)
+ adev->flags & AMD_IS_APU &&
+ amdgpu_device_asic_has_dc_support(adev->asic_type))
domain |= AMDGPU_GEM_DOMAIN_GTT;
+#endif
return domain;
}
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[PATCH] drm/amdgpu: only allow scatter/gather display with DC
Check if DC is enabled before allowing scanout buffers
to be pinned in system memory.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 8ede2645a06c..859942552e9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -507,9 +507,12 @@ uint32_t amdgpu_display_framebuffer_domains(struct
amdgpu_device *adev)
{
uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
+#if defined(CONFIG_DRM_AMD_DC)
if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
- adev->flags & AMD_IS_APU)
+ adev->flags & AMD_IS_APU &&
+ amdgpu_device_asic_has_dc_support(adev->asic_type))
domain |= AMDGPU_GEM_DOMAIN_GTT;
+#endif
return domain;
}
--
2.13.6
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Re: BUG: KASAN: use-after-free in amdgpu_job_free_cb
Hi, looks to me like a different issue (not related) then the one Johannes, reports, your issue was already reported by some one (can't remember the thread of hand) and looks like in shader hang or GPU scheduler synchronization issue while Johannes's use after free is pure software logic issue in either KMS atomic framework or more probably in AMDGPU/DC (DAL). Johanes, I attached a debug patch which forces the cursor update to wait for any page flip in progress, can you give it a try and see if the issue is gone ? This is not an actual fix but just to evaluate the reason. Thanks, Andrey On 01/12/2018 06:43 AM, Luís Mendes wrote: Hi Andrey, Johannes, Sorry for getting into this conversation, but I think I might have something related to this. I am getting GPU hangs playing some videos, both on ARMv7 and on x86, although with slightly different blocking paths. On ARMv7 it always blocks with amdgpu_dm_do_flip. I suspect the GPU hang, fence timeout, might also be caused by a kernel synchronization issue. I am using a single HDMI display and testing with VP9 videos on Kodi, but can also be triggered with youtube videos on firefox. Could this not exactly be a GPU hang, but rather a software lockup, that impedes the dma fence to be properly completed on the host side (due to a synchronization issue on the host side)? It is always related to the page flip and sometimes I get kernel messages after a while after the hang stating drm_flip_done timeout or similar. Kernel stack trace is always like: [ 73.432967] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout, last signaled seq=4183, last emitted seq=4185 [ 73.443847] [drm] IP block:gmc_v8_0 is hung! [ 73.443854] [drm] IP block:gfx_v8_0 is hung! [ 73.444019] [drm] GPU recovery disabled. [ 243.672640] INFO: task kworker/u4:3:89 blocked for more than 120 seconds. [ 243.679466] Not tainted 4.15.0-rc4-drmnext2g #1 [ 243.685337] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 243.693200] kworker/u4:3D089 2 0x [ 243.693232] Workqueue: events_unbound commit_work [drm_kms_helper] [ 243.693251] [<80b8c6d4>] (__schedule) from [<80b8cdd0>] (schedule+0x4c/0xac) [ 243.693259] [<80b8cdd0>] (schedule) from [<80b91024>] (schedule_timeout+0x228/0x444) [ 243.693270] [<80b91024>] (schedule_timeout) from [<80886738>] (dma_fence_default_wait+0x2b4/0x2d8) [ 243.693276] [<80886738>] (dma_fence_default_wait) from [<80885d60>] (dma_fence_wait_timeout+0x40/0x150) [ 243.693284] [<80885d60>] (dma_fence_wait_timeout) from [<80887b1c>] (reservation_object_wait_timeout_rcu+0xfc/0x34c) [ 243.693509] [<80887b1c>] (reservation_object_wait_timeout_rcu) from [<7f331988>] (amdgpu_dm_do_flip+0xec/0x36c [amdgpu]) [ 243.693789] [<7f331988>] (amdgpu_dm_do_flip [amdgpu]) from [<7f33309c>] (amdgpu_dm_atomic_commit_tail+0xbfc/0xe58 [amdgpu]) [ 243.693941] [<7f33309c>] (amdgpu_dm_atomic_commit_tail [amdgpu]) from [<7f15758c>] (commit_tail+0x50/0x94 [drm_kms_helper]) [ 243.693964] [<7f15758c>] (commit_tail [drm_kms_helper]) from [<7f1575ec>] (commit_work+0x1c/0x20 [drm_kms_helper]) [ 243.693981] [<7f1575ec>] (commit_work [drm_kms_helper]) from [<8016f4c8>] (process_one_work+0x1a8/0x4ac) [ 243.693987] [<8016f4c8>] (process_one_work) from [<8017050c>] (worker_thread+0x68/0x598) [ 243.693994] [<8017050c>] (worker_thread) from [<80175e50>] (kthread+0x16c/0x174) [ 243.694003] [<80175e50>] (kthread) from [<80109de8>] (ret_from_fork+0x14/0x2c) Regards, Luís Thanks for the dmesg, unfortunately nothing suspicious from there. Looking again at KASAN it hints at a race between cursor update and non blocking part of flip with regard to accessing CRTC states, maybe cursor update is not properly synchronized against a flip in flight on same CRTC... P.S What is your setup ? How many displays ? Thanks, Andrey Thanks, Andrey On 01/11/2018 05:55 PM, Johannes Hirte wrote: On 2018 Jan 10, Andrey Grodzovsky wrote: Hi, is there a particular scenario when this happens , Unfortunately no, I still search for a reproducer. Sometimes it takes several days until the next use-after-free. can you add dmesg with echo 0x10 > /sys/module/drm/parameters/debug? I assume you want the debug output when a use-after-free happened. Here it is: Jan 11 23:21:33 probook kernel: [drm:drm_atomic_state_init] Allocated atomic state a67d7f62 Jan 11 23:21:33 probook kernel: [drm:drm_atomic_get_plane_state] Added [PLANE:40:plane-4] 9b693a40 state to a67d7f62 Jan 11 23:21:33 probook kernel: [drm:drm_atomic_get_crtc_state] Added [CRTC:41:crtc-0] fd68d0e6 state to a67d7f62 Jan 11 23:21:33 probook kernel: [drm:drm_atomic_set_crtc_for_plane] Link plane state 9b693a40 to [CRTC:41:crtc-0] Jan 11 23:21:33 probook kernel: [drm:drm_atomic_set_fb_for_plane] Set [FB:48] for plane state 9b693a40 Jan 11 23:21:33 probook kernel: [drm:drm_atomic_check_only] checking a67d7f6
[PATCH 11/20] drm/amdgpu: add PASID mapping for GFX v7
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index ff9111656ad7..d260549b2848 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3255,6 +3255,13 @@ static void gfx_v7_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+WRITE_DATA_DST_SEL(0)));
+ amdgpu_ring_write(ring, mmIH_VMID_0_LUT + vmid);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, pasid);
+
/* bits 0-15 are the VM contexts0-15 */
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
@@ -5117,7 +5124,7 @@ static const struct amdgpu_ring_funcs
gfx_v7_0_ring_funcs_gfx = {
5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user
fence, vm fence */
7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
- 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
+ 22 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
@@ -5147,7 +5154,7 @@ static const struct amdgpu_ring_funcs
gfx_v7_0_ring_funcs_compute = {
7 + /* gfx_v7_0_ring_emit_hdp_flush */
5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
7 + /* gfx_v7_0_ring_emit_pipeline_sync */
- 17 + /* gfx_v7_0_ring_emit_vm_flush */
+ 22 + /* gfx_v7_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user
fence, vm fence */
.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
.emit_ib = gfx_v7_0_ring_emit_ib_compute,
--
2.14.1
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[PATCH 08/20] drm/amdgpu: add PASID mapping for SDMA v2.4
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index b843f5bc52c9..824390b83c87 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -871,6 +871,11 @@ static void sdma_v2_4_ring_emit_vm_flush(struct
amdgpu_ring *ring,
}
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid));
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
@@ -1206,7 +1211,7 @@ static const struct amdgpu_ring_funcs
sdma_v2_4_ring_funcs = {
6 + /* sdma_v2_4_ring_emit_hdp_flush */
3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
6 + /* sdma_v2_4_ring_emit_pipeline_sync */
- 12 + /* sdma_v2_4_ring_emit_vm_flush */
+ 15 + /* sdma_v2_4_ring_emit_vm_flush */
10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence,
vm fence */
.emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
.emit_ib = sdma_v2_4_ring_emit_ib,
--
2.14.1
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[PATCH 09/20] drm/amdgpu: add PASID mapping for SDMA v3
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index a17db3ff7e5c..f55f8bd68f17 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1137,6 +1137,11 @@ static void sdma_v3_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
}
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid));
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
@@ -1640,7 +1645,7 @@ static const struct amdgpu_ring_funcs
sdma_v3_0_ring_funcs = {
6 + /* sdma_v3_0_ring_emit_hdp_flush */
3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
6 + /* sdma_v3_0_ring_emit_pipeline_sync */
- 12 + /* sdma_v3_0_ring_emit_vm_flush */
+ 15 + /* sdma_v3_0_ring_emit_vm_flush */
10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence,
vm fence */
.emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
.emit_ib = sdma_v3_0_ring_emit_ib,
--
2.14.1
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[PATCH 01/20] dma-buf: make returning the exclusive fence optional
Change reservation_object_get_fences_rcu to make the exclusive fence
pointer optional.
If not specified the exclusive fence is put into the fence array as
well.
This is helpful for a couple of cases where we need all fences in a
single array.
Signed-off-by: Christian König
---
drivers/dma-buf/reservation.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/dma-buf/reservation.c b/drivers/dma-buf/reservation.c
index b759a569b7b8..461afa9febd4 100644
--- a/drivers/dma-buf/reservation.c
+++ b/drivers/dma-buf/reservation.c
@@ -374,8 +374,9 @@ EXPORT_SYMBOL(reservation_object_copy_fences);
* @pshared: the array of shared fence ptrs returned (array is krealloc'd to
* the required size, and must be freed by caller)
*
- * RETURNS
- * Zero or -errno
+ * Retrieve all fences from the reservation object. If the pointer for the
+ * exclusive fence is not specified the fence is put into the array of the
+ * shared fences as well. Returns either zero or -ENOMEM.
*/
int reservation_object_get_fences_rcu(struct reservation_object *obj,
struct dma_fence **pfence_excl,
@@ -389,8 +390,8 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
do {
struct reservation_object_list *fobj;
- unsigned seq;
- unsigned int i;
+ unsigned int i, seq;
+ size_t sz = 0;
shared_count = i = 0;
@@ -402,9 +403,14 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
goto unlock;
fobj = rcu_dereference(obj->fence);
- if (fobj) {
+ if (fobj)
+ sz += sizeof(*shared) * fobj->shared_max;
+
+ if (!pfence_excl && fence_excl)
+ sz += sizeof(*shared);
+
+ if (sz) {
struct dma_fence **nshared;
- size_t sz = sizeof(*shared) * fobj->shared_max;
nshared = krealloc(shared, sz,
GFP_NOWAIT | __GFP_NOWARN);
@@ -420,13 +426,19 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
break;
}
shared = nshared;
- shared_count = fobj->shared_count;
-
+ shared_count = fobj ? fobj->shared_count : 0;
for (i = 0; i < shared_count; ++i) {
shared[i] = rcu_dereference(fobj->shared[i]);
if (!dma_fence_get_rcu(shared[i]))
break;
}
+
+ if (!pfence_excl && fence_excl) {
+ shared[i] = fence_excl;
+ fence_excl = NULL;
+ ++i;
+ ++shared_count;
+ }
}
if (i != shared_count || read_seqcount_retry(&obj->seq, seq)) {
@@ -448,7 +460,8 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
*pshared_count = shared_count;
*pshared = shared;
- *pfence_excl = fence_excl;
+ if (pfence_excl)
+ *pfence_excl = fence_excl;
return ret;
}
--
2.14.1
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[PATCH 18/20] drm/amdgpu: rename pas_id to pasid
sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.h
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 8
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cz_ih.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega10_ih.c| 2 +-
8 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 29cf10927a92..b8a7dba69595 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -109,7 +109,7 @@ struct amdgpu_iv_entry {
unsigned vmid_src;
uint64_t timestamp;
unsigned timestamp_src;
- unsigned pas_id;
+ unsigned pasid;
unsigned pasid_src;
unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
const uint32_t *iv_entry;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index fc79c19917e6..532263ab6e16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -86,7 +86,7 @@ TRACE_EVENT(amdgpu_iv,
__field(unsigned, vmid_src)
__field(uint64_t, timestamp)
__field(unsigned, timestamp_src)
-__field(unsigned, pas_id)
+__field(unsigned, pasid)
__array(unsigned, src_data, 4)
),
TP_fast_assign(
@@ -97,16 +97,16 @@ TRACE_EVENT(amdgpu_iv,
__entry->vmid_src = iv->vmid_src;
__entry->timestamp = iv->timestamp;
__entry->timestamp_src = iv->timestamp_src;
- __entry->pas_id = iv->pas_id;
+ __entry->pasid = iv->pasid;
__entry->src_data[0] = iv->src_data[0];
__entry->src_data[1] = iv->src_data[1];
__entry->src_data[2] = iv->src_data[2];
__entry->src_data[3] = iv->src_data[3];
),
- TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu
pas_id:%u src_data: %08x %08x %08x %08x\n",
+ TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu
pasid:%u src_data: %08x %08x %08x %08x\n",
__entry->client_id, __entry->src_id,
__entry->ring_id, __entry->vmid,
- __entry->timestamp, __entry->pas_id,
+ __entry->timestamp, __entry->pasid,
__entry->src_data[0], __entry->src_data[1],
__entry->src_data[2], __entry->src_data[3])
);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index d5a05c19708f..07c7852180d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -281,7 +281,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
entry->src_data[0] = dw[1] & 0xfff;
entry->ring_id = dw[2] & 0xff;
entry->vmid = (dw[2] >> 8) & 0xff;
- entry->pas_id = (dw[2] >> 16) & 0x;
+ entry->pasid = (dw[2] >> 16) & 0x;
/* wptr/rptr are in bytes! */
adev->irq.ih.rptr += 16;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index f576e9cbbc61..cfd0ad03c938 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -260,7 +260,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
entry->src_data[0] = dw[1] & 0xfff;
entry->ring_id = dw[2] & 0xff;
entry->vmid = (dw[2] >> 8) & 0xff;
- entry->pas_id = (dw[2] >> 16) & 0x;
+ entry->pasid = (dw[2] >> 16) & 0x;
/* wptr/rptr are in bytes! */
adev->irq.ih.rptr += 16;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7ec54c23c07d..aca837c004c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -262,10 +262,10 @@ static int gmc_v9_0_process_interrupt(struct
amdgpu_device *adev,
if (printk_ratelimit()) {
dev_err(adev->dev,
- "[%s] VMC page fault (src_id:%u ring:%u vmid:%u
pas_id:%u)\n",
+ "[%s] VMC page fault (src_id:%u ring:%u vmid:%u
pasid:%u)\n",
entry->vmid_src ? "mmhub" : "gfxhub",
entry->src_id, entry->ring_id, entry->vmid,
- entry->pas_id);
+ e
[PATCH 06/20] drm/amdgpu: forward pasid to backend flush implementations
rd the pasid from the VM code to the emit_vm_flush function and update
all implementations with the new parameter.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 6 --
18 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b7c181ebfe4e..e828f174bdef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1124,8 +1124,9 @@ struct amdgpu_job {
void*owner;
uint64_tfence_ctx; /* the fence_context this job uses */
boolvm_needs_flush;
- unsignedvmid;
uint64_tvm_pd_addr;
+ unsignedvmid;
+ unsignedpasid;
uint32_tgds_base, gds_size;
uint32_tgws_base, gws_size;
uint32_toa_base, oa_size;
@@ -1860,7 +1861,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib),
(vmid), (c))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
-#define amdgpu_ring_emit_vm_flush(r, vmid, addr)
(r)->funcs->emit_vm_flush((r), (vmid), (addr))
+#define amdgpu_ring_emit_vm_flush(r, vmid, pasid, addr)
(r)->funcs->emit_vm_flush((r), (vmid), (pasid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags)
(r)->funcs->emit_fence((r), (addr), (seq), (flags))
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as)
(r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 3b9d318cf166..c13cf7e79b2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -237,6 +237,7 @@ static int amdgpu_vmid_grab_reserved_locked(struct
amdgpu_vm *vm,
id->last_flush = NULL;
}
job->vmid = id - id_mgr->ids;
+ job->pasid = vm->pasid;
trace_amdgpu_vm_grab_id(vm, ring, job);
out:
return r;
@@ -388,6 +389,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
list_move_tail(&id->list, &id_mgr->ids_lru);
job->vmid = id - id_mgr->ids;
+ job->pasid = vm->pasid;
trace_amdgpu_vm_grab_id(vm, ring, job);
error:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 102dad3edf6a..12b9a06f4d21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -126,7 +126,7 @@ struct amdgpu_ring_funcs {
uint64_t seq, unsigned flags);
void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
- uint64_t pd_addr);
+ unsigned pasid, uint64_t pd_addr);
void (*emit_hdp_flush)(struct amdgpu_ring *ring);
void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ae54335ae426..69a9a1da1b25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -512,7 +512,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct
amdgpu_job *job, bool need_
struct dma_fence *fence;
trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
- amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
+ amdgpu_ring_emit_vm_flush(ring, job->vmid, job->pasid,
+ job->vm_pd_addr);
r = amdgpu_fence_emit(ring, &fence);
if (r)
diff --git a/drivers/gpu/drm/am
Re: BUG: KASAN: use-after-free in amdgpu_job_free_cb
On 2018 Jan 11, Andrey Grodzovsky wrote: > Thanks for the dmesg, unfortunately nothing suspicious from there. > > Looking again at KASAN it hints at a race between cursor update and non > blocking part of flip with regard to accessing CRTC states, maybe cursor > update is not properly synchronized against a flip in flight on same CRTC... > > P.S What is your setup ? How many displays ? > It's a Carizzo A10-8700B R6 with 16G RAM, 512M assigned to graphics card. Only the laptop display (1920x1080) is connected via eDP, so nothing special. -- Regards, Johannes ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 16/20] drm/amdgpu: add PASID mapping for VCE v4
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 4e93dfe945f8..968f14a3cc0b 100755
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -35,6 +35,7 @@
#include "vce/vce_4_0_offset.h"
#include "vce/vce_4_0_default.h"
#include "vce/vce_4_0_sh_mask.h"
+#include "oss/osssys_4_0_offset.h"
#include "mmhub/mmhub_1_0_offset.h"
#include "mmhub/mmhub_1_0_sh_mask.h"
@@ -968,10 +969,12 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring
*ring,
unsigned int vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -984,6 +987,11 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring
*ring,
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+ amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ amdgpu_ring_write(ring, reg);
+ amdgpu_ring_write(ring, pasid);
+
amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, 0x);
@@ -1070,7 +1078,7 @@ static const struct amdgpu_ring_funcs
vce_v4_0_ring_vm_funcs = {
.set_wptr = vce_v4_0_ring_set_wptr,
.parse_cs = amdgpu_vce_ring_parse_cs_vm,
.emit_frame_size =
- 17 + /* vce_v4_0_emit_vm_flush */
+ 20 + /* vce_v4_0_emit_vm_flush */
5 + 5 + /* amdgpu_vce_ring_emit_fence x2 vm fence */
1, /* vce_v4_0_ring_insert_end */
.emit_ib_size = 5, /* vce_v4_0_ring_emit_ib */
--
2.14.1
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[PATCH 15/20] drm/amdgpu: add PASID mapping for UVD v7
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 68e221ad0b15..4a1dd7b96766 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -31,6 +31,7 @@
#include "uvd/uvd_7_0_offset.h"
#include "uvd/uvd_7_0_sh_mask.h"
+#include "oss/osssys_4_0_offset.h"
#include "vce/vce_4_0_offset.h"
#include "vce/vce_4_0_default.h"
#include "vce/vce_4_0_sh_mask.h"
@@ -1294,8 +1295,9 @@ static void uvd_v7_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
uint32_t data0, data1, mask;
@@ -1311,6 +1313,10 @@ static void uvd_v7_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
data1 = lower_32_bits(pd_addr);
uvd_v7_0_vm_reg_write(ring, data0, data1);
+ data0 = (SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid) << 2;
+ data1 = pasid;
+ uvd_v7_0_vm_reg_write(ring, data0, data1);
+
data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
mask = 0x;
@@ -1347,10 +1353,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned int vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
- unsigned eng = ring->vm_inv_eng;
+ unsigned eng = ring->vm_inv_eng, reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -1363,6 +1370,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
+ reg = (SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid) << 2;
+ amdgpu_ring_write(ring, reg);
+ amdgpu_ring_write(ring, pasid);
+
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, 0x);
@@ -1716,7 +1728,7 @@ static const struct amdgpu_ring_funcs
uvd_v7_0_ring_vm_funcs = {
.emit_frame_size =
2 + /* uvd_v7_0_ring_emit_hdp_flush */
2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
- 34 + /* uvd_v7_0_ring_emit_vm_flush */
+ 40 + /* uvd_v7_0_ring_emit_vm_flush */
14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
.emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
.emit_ib = uvd_v7_0_ring_emit_ib,
@@ -1742,7 +1754,7 @@ static const struct amdgpu_ring_funcs
uvd_v7_0_enc_ring_vm_funcs = {
.get_wptr = uvd_v7_0_enc_ring_get_wptr,
.set_wptr = uvd_v7_0_enc_ring_set_wptr,
.emit_frame_size =
- 17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
+ 20 + /* uvd_v7_0_enc_ring_emit_vm_flush */
5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1, /* uvd_v7_0_enc_ring_insert_end */
.emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
--
2.14.1
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[PATCH 13/20] drm/amdgpu: add PASID mapping for GFX v9
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 367f4e724cb0..dcf3fe399f6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -32,6 +32,7 @@
#include "gc/gc_9_0_sh_mask.h"
#include "vega10_enum.h"
#include "hdp/hdp_4_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
#include "soc15_common.h"
#include "clearstate_gfx9.h"
@@ -3687,11 +3688,13 @@ static void gfx_v9_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -3704,6 +3707,9 @@ static void gfx_v9_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
hub->ctx0_ptb_addr_hi32 + (2 * vmid),
upper_32_bits(pd_addr));
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+ gfx_v9_0_write_data_to_reg(ring, usepfp, true, reg, pasid);
+
gfx_v9_0_write_data_to_reg(ring, usepfp, true,
hub->vm_inv_eng0_req + eng, req);
@@ -4299,7 +4305,7 @@ static const struct amdgpu_ring_funcs
gfx_v9_0_ring_funcs_gfx = {
.emit_frame_size = /* totally 242 maximum if 16 IBs */
5 + /* COND_EXEC */
7 + /* PIPELINE_SYNC */
- 24 + /* VM_FLUSH */
+ 29 + /* VM_FLUSH */
8 + /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
@@ -4347,7 +4353,7 @@ static const struct amdgpu_ring_funcs
gfx_v9_0_ring_funcs_compute = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
- 24 + /* gfx_v9_0_ring_emit_vm_flush */
+ 29 + /* gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm
fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
@@ -4378,7 +4384,7 @@ static const struct amdgpu_ring_funcs
gfx_v9_0_ring_funcs_kiq = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
- 24 + /* gfx_v9_0_ring_emit_vm_flush */
+ 29 + /* gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence,
vm fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
--
2.14.1
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[PATCH 20/20] drm/amdgpu: print the PASID with VM faults on GMC v8
Print that extra information on GMC v8.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 287228315b76..5b4f6c1f0993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -962,21 +962,21 @@ static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
*
* Print human readable fault information (CIK).
*/
-static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
-u32 status, u32 addr, u32 mc_client)
+static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
+u32 addr, u32 mc_client, unsigned pasid)
{
- u32 mc_id;
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
VMID);
u32 protections = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS,
PROTECTIONS);
char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
+ u32 mc_id;
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_ID);
- dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s'
(0x%08x) (%d)\n",
- protections, vmid, addr,
+ dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s
from '%s' (0x%08x) (%d)\n",
+ protections, vmid, pasid, addr,
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_RW) ?
"write" : "read", block, mc_client, mc_id);
@@ -1404,7 +1404,8 @@ static int gmc_v8_0_process_interrupt(struct
amdgpu_device *adev,
addr);
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x%08X\n",
status);
- gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
+ gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
+entry->pasid);
}
return 0;
--
2.14.1
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[PATCH 02/20] drm/amdgpu: add amdgpu_pasid_free_delayed v2
Free up a pasid after all fences signaled.
v2: also handle the case when we can't allocate a fence array.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 82 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 2 +
2 files changed, 84 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 5248a3232aff..842caa5ed73b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -40,6 +40,12 @@
*/
static DEFINE_IDA(amdgpu_pasid_ida);
+/* Helper to free pasid from a fence callback */
+struct amdgpu_pasid_cb {
+ struct dma_fence_cb cb;
+ unsigned int pasid;
+};
+
/**
* amdgpu_pasid_alloc - Allocate a PASID
* @bits: Maximum width of the PASID in bits, must be at least 1
@@ -75,6 +81,82 @@ void amdgpu_pasid_free(unsigned int pasid)
ida_simple_remove(&amdgpu_pasid_ida, pasid);
}
+static void amdgpu_pasid_free_cb(struct dma_fence *fence,
+struct dma_fence_cb *_cb)
+{
+ struct amdgpu_pasid_cb *cb =
+ container_of(_cb, struct amdgpu_pasid_cb, cb);
+
+ amdgpu_pasid_free(cb->pasid);
+ dma_fence_put(fence);
+ kfree(cb);
+}
+
+/**
+ * amdgpu_pasid_free_delayed - free pasid when fences signal
+ *
+ * @resv: reservation object with the fences to wait for
+ * @pasid: pasid to free
+ *
+ * Free the pasid only after all the fences in resv are signaled.
+ */
+void amdgpu_pasid_free_delayed(struct reservation_object *resv,
+ unsigned int pasid)
+{
+ struct dma_fence *fence, **fences;
+ struct amdgpu_pasid_cb *cb;
+ unsigned count;
+ int r;
+
+ r = reservation_object_get_fences_rcu(resv, NULL, &count, &fences);
+ if (r)
+ goto fallback;
+
+ if (count == 0) {
+ amdgpu_pasid_free(pasid);
+ return;
+ }
+
+ if (count == 1) {
+ fence = fences[0];
+ kfree(fences);
+ } else {
+ uint64_t context = dma_fence_context_alloc(1);
+ struct dma_fence_array *array;
+
+ array = dma_fence_array_create(count, fences, context,
+ 1, false);
+ if (!array) {
+ kfree(fences);
+ goto fallback;
+ }
+ fence = &array->base;
+ }
+
+ cb = kmalloc(sizeof(*cb), GFP_KERNEL);
+ if (!cb) {
+ /* Last resort when we are OOM */
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+ amdgpu_pasid_free(pasid);
+ } else {
+ cb->pasid = pasid;
+ if (dma_fence_add_callback(fence, &cb->cb,
+ amdgpu_pasid_free_cb))
+ amdgpu_pasid_free_cb(fence, &cb->cb);
+ }
+
+ return;
+
+fallback:
+ /* Not enough memory for the delayed delete, as last resort
+* block for all the fences to complete.
+*/
+ reservation_object_wait_timeout_rcu(resv, true, false,
+ MAX_SCHEDULE_TIMEOUT);
+ amdgpu_pasid_free(pasid);
+}
+
/*
* VMID manager
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index ad931fa570b3..38f37c16fc5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -69,6 +69,8 @@ struct amdgpu_vmid_mgr {
int amdgpu_pasid_alloc(unsigned int bits);
void amdgpu_pasid_free(unsigned int pasid);
+void amdgpu_pasid_free_delayed(struct reservation_object *resv,
+ unsigned int pasid);
bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
struct amdgpu_vmid *id);
--
2.14.1
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[PATCH 03/20] drm/amdgpu: always allocate a PASIDs for each VM v2
Start to always allocate a pasid for each VM.
v2: use dev_warn when we run out of PASIDs
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 43 ++---
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5773a581761b..a108b30d8186 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -805,7 +805,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
{
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv;
- int r;
+ int r, pasid;
file_priv->driver_priv = NULL;
@@ -819,28 +819,25 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto out_suspend;
}
- r = amdgpu_vm_init(adev, &fpriv->vm,
- AMDGPU_VM_CONTEXT_GFX, 0);
- if (r) {
- kfree(fpriv);
- goto out_suspend;
+ pasid = amdgpu_pasid_alloc(16);
+ if (pasid < 0) {
+ dev_warn(adev->dev, "No more PASIDs available!");
+ pasid = 0;
}
+ r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
+ if (r)
+ goto error_pasid;
fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
if (!fpriv->prt_va) {
r = -ENOMEM;
- amdgpu_vm_fini(adev, &fpriv->vm);
- kfree(fpriv);
- goto out_suspend;
+ goto error_vm;
}
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
- if (r) {
- amdgpu_vm_fini(adev, &fpriv->vm);
- kfree(fpriv);
- goto out_suspend;
- }
+ if (r)
+ goto error_vm;
}
mutex_init(&fpriv->bo_list_lock);
@@ -849,6 +846,16 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
file_priv->driver_priv = fpriv;
+ goto out_suspend;
+
+error_vm:
+ amdgpu_vm_fini(adev, &fpriv->vm);
+
+error_pasid:
+ if (pasid)
+ amdgpu_pasid_free(pasid);
+
+ kfree(fpriv);
out_suspend:
pm_runtime_mark_last_busy(dev->dev);
@@ -871,6 +878,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_bo_list *list;
+ struct amdgpu_bo *pd;
+ unsigned int pasid;
int handle;
if (!fpriv)
@@ -895,7 +904,13 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
amdgpu_bo_unreserve(adev->virt.csa_obj);
}
+ pasid = fpriv->vm.pasid;
+ pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
+
amdgpu_vm_fini(adev, &fpriv->vm);
+ if (pasid)
+ amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
+ amdgpu_bo_unref(&pd);
idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
amdgpu_bo_list_free(list);
--
2.14.1
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Re: [PATCH 21/21] drm/amdgpu: print the PASID with VM faults on GMC v8
I fixed the fence issue in patch #3. Raised the dev_info to a dev_warn
in patch #4 and moved the trace into the functions in #5.
Any objects or can I get your rb for the whole series?
Thanks,
Christian.
Am 11.01.2018 um 06:50 schrieb Chunming Zhou:
Except some small nitpicks in patch #3, #4, #5, the series looks ok to
me, Reviewed-by: Chunming Zhou
Regards,
David Zhou
On 2018年01月10日 20:54, Christian König wrote:
Print that extra information on GMC v8.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 287228315b76..5b4f6c1f0993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -962,21 +962,21 @@ static void gmc_v8_0_gart_fini(struct
amdgpu_device *adev)
*
* Print human readable fault information (CIK).
*/
-static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
- u32 status, u32 addr, u32 mc_client)
+static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32
status,
+ u32 addr, u32 mc_client, unsigned pasid)
{
- u32 mc_id;
u32 vmid = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
u32 protections = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS,
PROTECTIONS);
char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
+ u32 mc_id;
mc_id = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_ID);
- dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s
from '%s' (0x%08x) (%d)\n",
- protections, vmid, addr,
+ dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page
%u, %s from '%s' (0x%08x) (%d)\n",
+ protections, vmid, pasid, addr,
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_RW) ?
"write" : "read", block, mc_client, mc_id);
@@ -1404,7 +1404,8 @@ static int gmc_v8_0_process_interrupt(struct
amdgpu_device *adev,
addr);
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x%08X\n",
status);
- gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
+ gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
+ entry->pasid);
}
return 0;
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Re: BUG: KASAN: use-after-free in amdgpu_job_free_cb
Hi Andrey, Johannes, Sorry for getting into this conversation, but I think I might have something related to this. I am getting GPU hangs playing some videos, both on ARMv7 and on x86, although with slightly different blocking paths. On ARMv7 it always blocks with amdgpu_dm_do_flip. I suspect the GPU hang, fence timeout, might also be caused by a kernel synchronization issue. I am using a single HDMI display and testing with VP9 videos on Kodi, but can also be triggered with youtube videos on firefox. Could this not exactly be a GPU hang, but rather a software lockup, that impedes the dma fence to be properly completed on the host side (due to a synchronization issue on the host side)? It is always related to the page flip and sometimes I get kernel messages after a while after the hang stating drm_flip_done timeout or similar. Kernel stack trace is always like: [ 73.432967] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout, last signaled seq=4183, last emitted seq=4185 [ 73.443847] [drm] IP block:gmc_v8_0 is hung! [ 73.443854] [drm] IP block:gfx_v8_0 is hung! [ 73.444019] [drm] GPU recovery disabled. [ 243.672640] INFO: task kworker/u4:3:89 blocked for more than 120 seconds. [ 243.679466] Not tainted 4.15.0-rc4-drmnext2g #1 [ 243.685337] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 243.693200] kworker/u4:3D089 2 0x [ 243.693232] Workqueue: events_unbound commit_work [drm_kms_helper] [ 243.693251] [<80b8c6d4>] (__schedule) from [<80b8cdd0>] (schedule+0x4c/0xac) [ 243.693259] [<80b8cdd0>] (schedule) from [<80b91024>] (schedule_timeout+0x228/0x444) [ 243.693270] [<80b91024>] (schedule_timeout) from [<80886738>] (dma_fence_default_wait+0x2b4/0x2d8) [ 243.693276] [<80886738>] (dma_fence_default_wait) from [<80885d60>] (dma_fence_wait_timeout+0x40/0x150) [ 243.693284] [<80885d60>] (dma_fence_wait_timeout) from [<80887b1c>] (reservation_object_wait_timeout_rcu+0xfc/0x34c) [ 243.693509] [<80887b1c>] (reservation_object_wait_timeout_rcu) from [<7f331988>] (amdgpu_dm_do_flip+0xec/0x36c [amdgpu]) [ 243.693789] [<7f331988>] (amdgpu_dm_do_flip [amdgpu]) from [<7f33309c>] (amdgpu_dm_atomic_commit_tail+0xbfc/0xe58 [amdgpu]) [ 243.693941] [<7f33309c>] (amdgpu_dm_atomic_commit_tail [amdgpu]) from [<7f15758c>] (commit_tail+0x50/0x94 [drm_kms_helper]) [ 243.693964] [<7f15758c>] (commit_tail [drm_kms_helper]) from [<7f1575ec>] (commit_work+0x1c/0x20 [drm_kms_helper]) [ 243.693981] [<7f1575ec>] (commit_work [drm_kms_helper]) from [<8016f4c8>] (process_one_work+0x1a8/0x4ac) [ 243.693987] [<8016f4c8>] (process_one_work) from [<8017050c>] (worker_thread+0x68/0x598) [ 243.693994] [<8017050c>] (worker_thread) from [<80175e50>] (kthread+0x16c/0x174) [ 243.694003] [<80175e50>] (kthread) from [<80109de8>] (ret_from_fork+0x14/0x2c) Regards, Luís >Thanks for the dmesg, unfortunately nothing suspicious from there. > >Looking again at KASAN it hints at a race between cursor update and non >blocking part of flip with regard to accessing CRTC states, maybe cursor >update is not properly synchronized against a flip in flight on same CRTC... > >P.S What is your setup ? How many displays ? > > >Thanks, > >Andrey > > >Thanks, > >Andrey > >On 01/11/2018 05:55 PM, Johannes Hirte wrote: >> On 2018 Jan 10, Andrey Grodzovsky wrote: >>> Hi, is there a particular scenario when this happens , >> Unfortunately no, I still search for a reproducer. Sometimes it takes >> several days until the next use-after-free. >> >>> can you add dmesg with echo 0x10 > /sys/module/drm/parameters/debug? >> I assume you want the debug output when a use-after-free happened. Here >> it is: >> >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_state_init] Allocated atomic >> state a67d7f62 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_get_plane_state] Added >> [PLANE:40:plane-4] 9b693a40 state to a67d7f62 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_get_crtc_state] Added >> [CRTC:41:crtc-0] fd68d0e6 state to a67d7f62 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_set_crtc_for_plane] Link >> plane state 9b693a40 to [CRTC:41:crtc-0] >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_set_fb_for_plane] Set >> [FB:48] for plane state 9b693a40 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_check_only] checking >> a67d7f62 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_commit] committing >> a67d7f62 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_state_default_clear] >> Clearing atomic state a67d7f62 >> Jan 11 23:21:33 probook kernel: [drm:__drm_atomic_state_free] Freeing atomic >> state a67d7f62 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_state_init] Allocated atomic >> state aff36e64 >> Jan 11 23:21:33 probook kernel: [drm:drm_atomic_get_plane_state] Added >> [PLANE:40:plane-4] bef4ac0a state to aff36e64 >> Jan 11 23:21:33 p
[PATCH 07/20] drm/amdgpu: add PASID mapping for CIK SDMA
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 985a6868b0a8..1d4787b78779 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -894,6 +894,10 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring,
}
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid));
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
@@ -1282,7 +1286,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
6 + /* cik_sdma_ring_emit_hdp_flush */
3 + /* cik_sdma_ring_emit_hdp_invalidate */
6 + /* cik_sdma_ring_emit_pipeline_sync */
- 12 + /* cik_sdma_ring_emit_vm_flush */
+ 15 + /* cik_sdma_ring_emit_vm_flush */
9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm
fence */
.emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
.emit_ib = cik_sdma_ring_emit_ib,
--
2.14.1
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[PATCH 04/20] drm/amdgpu: trace allocated PASIDs
Trace all allocated PASIDs.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 22 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 842caa5ed73b..3b9d318cf166 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -69,6 +69,9 @@ int amdgpu_pasid_alloc(unsigned int bits)
break;
}
+ if (pasid >= 0)
+ trace_amdgpu_pasid_allocated(pasid);
+
return pasid;
}
@@ -78,6 +81,7 @@ int amdgpu_pasid_alloc(unsigned int bits)
*/
void amdgpu_pasid_free(unsigned int pasid)
{
+ trace_amdgpu_pasid_freed(pasid);
ida_simple_remove(&amdgpu_pasid_ida, pasid);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index cace7a93fc94..9890c39ee810 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -378,6 +378,28 @@ TRACE_EVENT(amdgpu_vm_flush,
__entry->vm_hub,__entry->pd_addr)
);
+DECLARE_EVENT_CLASS(amdgpu_pasid,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid),
+ TP_STRUCT__entry(
+__field(unsigned, pasid)
+),
+ TP_fast_assign(
+ __entry->pasid = pasid;
+ ),
+ TP_printk("pasid=%u", __entry->pasid)
+);
+
+DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_allocated,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid)
+);
+
+DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_freed,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid)
+);
+
TRACE_EVENT(amdgpu_bo_list_set,
TP_PROTO(struct amdgpu_bo_list *list, struct amdgpu_bo *bo),
TP_ARGS(list, bo),
--
2.14.1
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[PATCH 17/20] drm/amdgpu: add PASID mapping for VCN v1
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 171e5e406b8b..05e5bed965c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -31,6 +31,7 @@
#include "vcn/vcn_1_0_offset.h"
#include "vcn/vcn_1_0_sh_mask.h"
#include "hdp/hdp_4_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
#include "mmhub/mmhub_9_1_offset.h"
#include "mmhub/mmhub_9_1_sh_mask.h"
@@ -891,8 +892,9 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
uint32_t data0, data1, mask;
@@ -908,6 +910,10 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct
amdgpu_ring *ring,
data1 = lower_32_bits(pd_addr);
vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+ data0 = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ data1 = pasid;
+ vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+
data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
mask = 0x;
@@ -1025,10 +1031,12 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned int vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -1043,6 +1051,11 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+ amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ amdgpu_ring_write(ring, reg << 2);
+ amdgpu_ring_write(ring, pasid);
+
amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
amdgpu_ring_write(ring,
(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
@@ -1136,7 +1149,7 @@ static const struct amdgpu_ring_funcs
vcn_v1_0_dec_ring_vm_funcs = {
.set_wptr = vcn_v1_0_dec_ring_set_wptr,
.emit_frame_size =
2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
- 34 + /* vcn_v1_0_dec_ring_emit_vm_flush */
+ 40 + /* vcn_v1_0_dec_ring_emit_vm_flush */
14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
6,
.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
@@ -1164,7 +1177,7 @@ static const struct amdgpu_ring_funcs
vcn_v1_0_enc_ring_vm_funcs = {
.get_wptr = vcn_v1_0_enc_ring_get_wptr,
.set_wptr = vcn_v1_0_enc_ring_set_wptr,
.emit_frame_size =
- 17 + /* vcn_v1_0_enc_ring_emit_vm_flush */
+ 20 + /* vcn_v1_0_enc_ring_emit_vm_flush */
5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1, /* vcn_v1_0_enc_ring_insert_end */
.emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
--
2.14.1
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Re: [PATCH libdrm 2/2] libdrm: clean up non list code path for vamgr
Am 12.01.2018 um 06:45 schrieb Chunming Zhou:
Change-Id: I7ca19a1f6404356a6c69ab4af27c8e13454f0279
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu_internal.h | 2 -
amdgpu/amdgpu_vamgr.c| 152 ++-
2 files changed, 46 insertions(+), 108 deletions(-)
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index fd522f39..7484780b 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -53,8 +53,6 @@ struct amdgpu_bo_va_hole {
};
struct amdgpu_bo_va_mgr {
- /* the start virtual address */
- uint64_t va_offset;
uint64_t va_min;
uint64_t va_max;
Is va_min and va_max actually still used after that series? If not I
would remove them as well.
Apart from that I would indeed add the warning when the calloc during
free fails.
With that fixed the series is Reviewed-by: Christian König
.
Regards,
Christian.
struct list_head va_holes;
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index 66bb8ecd..b826ac81 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -61,13 +61,20 @@ int amdgpu_va_range_query(amdgpu_device_handle dev,
drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t
start,
uint64_t max, uint64_t alignment)
{
- mgr->va_offset = start;
+ struct amdgpu_bo_va_hole *n;
+
mgr->va_min = start;
mgr->va_max = max;
mgr->va_alignment = alignment;
list_inithead(&mgr->va_holes);
pthread_mutex_init(&mgr->bo_va_mutex, NULL);
+ pthread_mutex_lock(&mgr->bo_va_mutex);
+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ n->size = mgr->va_max;
+ n->offset = mgr->va_min;
+ list_add(&n->list, &mgr->va_holes);
+ pthread_mutex_unlock(&mgr->bo_va_mutex);
}
drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr)
@@ -136,35 +143,8 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr,
uint64_t size,
}
}
- if (base_required) {
- if (base_required < mgr->va_offset) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
- offset = mgr->va_offset;
- waste = base_required - mgr->va_offset;
- } else {
- offset = mgr->va_offset;
- waste = offset % alignment;
- waste = waste ? alignment - waste : 0;
- }
-
- if (offset + waste + size > mgr->va_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
-
- if (waste) {
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = waste;
- n->offset = offset;
- list_add(&n->list, &mgr->va_holes);
- }
-
- offset += waste;
- mgr->va_offset += size + waste;
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
+ return AMDGPU_INVALID_VA_ADDRESS;
}
static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
@@ -232,41 +212,14 @@ static uint64_t amdgpu_vamgr_find_va_in_range(struct
amdgpu_bo_va_mgr *mgr, uint
}
}
- if (mgr->va_offset > range_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- } else if (mgr->va_offset > range_min) {
- offset = mgr->va_offset;
- waste = offset % alignment;
- waste = waste ? alignment - waste : 0;
- if (offset + waste + size > range_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
- } else {
- offset = mgr->va_offset;
- waste = range_min % alignment;
- waste = waste ? alignment - waste : 0;
- waste += range_min - offset ;
- }
-
- if (waste) {
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = waste;
- n->offset = offset;
- list_add(&n->list, &mgr->va_holes);
- }
-
- offset += waste;
- mgr->va_offset = size + offset;
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
+ return AMDGPU_INVALID_VA_ADDRESS;
}
drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size)
{
- struct amdgpu_bo_va_hole *hole;
+ struct amdgpu_bo_va_hole *hole, *next;
if (va == AMDGPU_INVALID_VA_ADDRESS)
return;
@@ -274,61 +227,48 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr,
uint64_t va, uint64_t size)
size = ALIGN(size, mgr->va_alignment);
pthread_mutex_lock(&mgr->bo_va_mutex);
- if ((va + size) == mgr->va_offset) {
[PATCH 12/20] drm/amdgpu: add PASID mapping for GFX v8
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4d1f9404d17e..70c517b5d012 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6347,6 +6347,14 @@ static void gfx_v8_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+WRITE_DATA_DST_SEL(0)) |
+WR_CONFIRM);
+ amdgpu_ring_write(ring, mmIH_VMID_0_LUT + vmid);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, pasid);
+
/* bits 0-15 are the VM contexts0-15 */
/* invalidate the cache */
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -6872,7 +6880,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_gfx = {
.emit_frame_size = /* maximum 215dw if count 16 IBs in */
5 + /* COND_EXEC */
7 + /* PIPELINE_SYNC */
- 19 + /* VM_FLUSH */
+ 24 + /* VM_FLUSH */
8 + /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
@@ -6918,7 +6926,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_compute = {
7 + /* gfx_v8_0_ring_emit_hdp_flush */
5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
7 + /* gfx_v8_0_ring_emit_pipeline_sync */
- 17 + /* gfx_v8_0_ring_emit_vm_flush */
+ 22 + /* gfx_v8_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user
fence, vm fence */
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
.emit_ib = gfx_v8_0_ring_emit_ib_compute,
@@ -6948,7 +6956,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_kiq = {
7 + /* gfx_v8_0_ring_emit_hdp_flush */
5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
7 + /* gfx_v8_0_ring_emit_pipeline_sync */
- 17 + /* gfx_v8_0_ring_emit_vm_flush */
+ 22 + /* gfx_v8_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence,
vm fence */
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
.emit_ib = gfx_v8_0_ring_emit_ib_compute,
--
2.14.1
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[PATCH 10/20] drm/amdgpu: add PASID mapping for SDMA v4
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 64926191edd7..c3f34d1a7169 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -35,6 +35,7 @@
#include "mmhub/mmhub_1_0_sh_mask.h"
#include "hdp/hdp_4_0_offset.h"
#include "sdma0/sdma0_4_1_default.h"
+#include "oss/osssys_4_0_offset.h"
#include "soc15_common.h"
#include "soc15.h"
@@ -1136,10 +1137,12 @@ static void sdma_v4_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -1154,6 +1157,12 @@ static void sdma_v4_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2);
amdgpu_ring_write(ring, upper_32_bits(pd_addr));
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ amdgpu_ring_write(ring, reg);
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
--
2.14.1
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Re: [PATCH libdrm 2/2] libdrm: clean up non list code path for vamgr
On 2018年01月12日 16:04, Christian König wrote:
Am 12.01.2018 um 06:45 schrieb Chunming Zhou:
Change-Id: I7ca19a1f6404356a6c69ab4af27c8e13454f0279
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu_internal.h | 2 -
amdgpu/amdgpu_vamgr.c | 152
++-
2 files changed, 46 insertions(+), 108 deletions(-)
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index fd522f39..7484780b 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -53,8 +53,6 @@ struct amdgpu_bo_va_hole {
};
struct amdgpu_bo_va_mgr {
- /* the start virtual address */
- uint64_t va_offset;
uint64_t va_min;
uint64_t va_max;
Is va_min and va_max actually still used after that series?
Yes, still used for svm manager.
If not I would remove them as well.
Apart from that I would indeed add the warning when the calloc during
free fails.
With that fixed the series is Reviewed-by: Christian König
.
Thanks for review.
Regards,
David Zhou
Regards,
Christian.
struct list_head va_holes;
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index 66bb8ecd..b826ac81 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -61,13 +61,20 @@ int amdgpu_va_range_query(amdgpu_device_handle dev,
drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr,
uint64_t start,
uint64_t max, uint64_t alignment)
{
- mgr->va_offset = start;
+ struct amdgpu_bo_va_hole *n;
+
mgr->va_min = start;
mgr->va_max = max;
mgr->va_alignment = alignment;
list_inithead(&mgr->va_holes);
pthread_mutex_init(&mgr->bo_va_mutex, NULL);
+ pthread_mutex_lock(&mgr->bo_va_mutex);
+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ n->size = mgr->va_max;
+ n->offset = mgr->va_min;
+ list_add(&n->list, &mgr->va_holes);
+ pthread_mutex_unlock(&mgr->bo_va_mutex);
}
drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr)
@@ -136,35 +143,8 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr
*mgr, uint64_t size,
}
}
- if (base_required) {
- if (base_required < mgr->va_offset) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
- offset = mgr->va_offset;
- waste = base_required - mgr->va_offset;
- } else {
- offset = mgr->va_offset;
- waste = offset % alignment;
- waste = waste ? alignment - waste : 0;
- }
-
- if (offset + waste + size > mgr->va_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
-
- if (waste) {
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = waste;
- n->offset = offset;
- list_add(&n->list, &mgr->va_holes);
- }
-
- offset += waste;
- mgr->va_offset += size + waste;
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
+ return AMDGPU_INVALID_VA_ADDRESS;
}
static uint64_t amdgpu_vamgr_find_va_in_range(struct
amdgpu_bo_va_mgr *mgr, uint64_t size,
@@ -232,41 +212,14 @@ static uint64_t
amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint
}
}
- if (mgr->va_offset > range_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- } else if (mgr->va_offset > range_min) {
- offset = mgr->va_offset;
- waste = offset % alignment;
- waste = waste ? alignment - waste : 0;
- if (offset + waste + size > range_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
- } else {
- offset = mgr->va_offset;
- waste = range_min % alignment;
- waste = waste ? alignment - waste : 0;
- waste += range_min - offset ;
- }
-
- if (waste) {
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = waste;
- n->offset = offset;
- list_add(&n->list, &mgr->va_holes);
- }
-
- offset += waste;
- mgr->va_offset = size + offset;
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
+ return AMDGPU_INVALID_VA_ADDRESS;
}
drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va,
uint64_t size)
{
- struct amdgpu_bo_va_hole *hole;
+ struct amdgpu_bo_va_hole *hole, *next;
if (va == AMDGPU_INVALID_VA_ADDRESS)
return;
@@ -274,61 +227,48 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr
*mgr, uint64_t va, uint64_t size)
size = ALIGN(size, mgr->va_alignment);
pthread_mutex_lock(&mgr->bo_va_mutex);
- if ((va + size) == mgr->va_offset) {
- mgr->va_offset = va;
- /* Delete uppermost hole if it reaches the new top */
- if (!LIST_IS_EMPTY(&mgr->va_holes)) {
- hole = container_of(mgr->va_holes.next, hole, list);
- if ((hole->offset + hole->size) == va)
[PATCH 14/20] drm/amdgpu: add PASID mapping for UVD v6
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index c6e22eff89e7..4122cca65785 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1077,6 +1077,13 @@ static void uvd_v6_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
amdgpu_ring_write(ring, 0x8);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid) << 2);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+ amdgpu_ring_write(ring, pasid);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+ amdgpu_ring_write(ring, 0x8);
+
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
@@ -1135,6 +1142,8 @@ static void uvd_v6_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, pd_addr >> 12);
+ /* TODO: PASID handling. */
+
amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
amdgpu_ring_write(ring, vmid);
}
@@ -1580,7 +1589,7 @@ static const struct amdgpu_ring_funcs
uvd_v6_0_ring_vm_funcs = {
2 + /* uvd_v6_0_ring_emit_hdp_flush */
2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
10 + /* uvd_v6_0_ring_emit_pipeline_sync */
- 20 + /* uvd_v6_0_ring_emit_vm_flush */
+ 26 + /* uvd_v6_0_ring_emit_vm_flush */
14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
.emit_ib = uvd_v6_0_ring_emit_ib,
--
2.14.1
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[PATCH 05/20] drm/amdgpu: trace the PASID instead of the VM pointer
Makes more sense than tracing the kernel pointer.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 9890c39ee810..fc79c19917e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -217,7 +217,7 @@ TRACE_EVENT(amdgpu_vm_grab_id,
struct amdgpu_job *job),
TP_ARGS(vm, ring, job),
TP_STRUCT__entry(
-__field(struct amdgpu_vm *, vm)
+__field(u32, pasid)
__field(u32, ring)
__field(u32, vmid)
__field(u32, vm_hub)
@@ -226,15 +226,15 @@ TRACE_EVENT(amdgpu_vm_grab_id,
),
TP_fast_assign(
- __entry->vm = vm;
+ __entry->pasid = vm->pasid;
__entry->ring = ring->idx;
__entry->vmid = job->vmid;
__entry->vm_hub = ring->funcs->vmhub,
__entry->pd_addr = job->vm_pd_addr;
__entry->needs_flush = job->vm_needs_flush;
),
- TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx
needs_flush=%u",
- __entry->vm, __entry->ring, __entry->vmid,
+ TP_printk("pasid=%d, ring=%u, id=%u, hub=%u, pd_addr=%010Lx
needs_flush=%u",
+ __entry->pasid, __entry->ring, __entry->vmid,
__entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
);
--
2.14.1
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Re: [PATCH 21/21] drm/amdgpu: print the PASID with VM faults on GMC v8
feel free to add my rb
发自坚果 Pro
Christian K鰊ig 于 2018年1月12日 下午6:39写道：
I fixed the fence issue in patch #3. Raised the dev_info to a dev_warn
in patch #4 and moved the trace into the functions in #5.
Any objects or can I get your rb for the whole series?
Thanks,
Christian.
Am 11.01.2018 um 06:50 schrieb Chunming Zhou:
> Except some small nitpicks in patch #3, #4, #5, the series looks ok to
> me, Reviewed-by: Chunming Zhou
>
>
> Regards,
> David Zhou
> On 2018年01月10日 20:54, Christian König wrote:
>> Print that extra information on GMC v8.
>>
>> Signed-off-by: Christian König
>> ---
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 +++--
>> 1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> index 287228315b76..5b4f6c1f0993 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> @@ -962,21 +962,21 @@ static void gmc_v8_0_gart_fini(struct
>> amdgpu_device *adev)
>>*
>>* Print human readable fault information (CIK).
>>*/
>> -static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
>> - u32 status, u32 addr, u32 mc_client)
>> +static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32
>> status,
>> + u32 addr, u32 mc_client, unsigned pasid)
>> {
>> -u32 mc_id;
>> u32 vmid = REG_GET_FIELD(status,
>> VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
>> u32 protections = REG_GET_FIELD(status,
>> VM_CONTEXT1_PROTECTION_FAULT_STATUS,
>> PROTECTIONS);
>> char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
>> (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
>> +u32 mc_id;
>> mc_id = REG_GET_FIELD(status,
>> VM_CONTEXT1_PROTECTION_FAULT_STATUS,
>> MEMORY_CLIENT_ID);
>> -dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s
>> from '%s' (0x%08x) (%d)\n",
>> - protections, vmid, addr,
>> +dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page
>> %u, %s from '%s' (0x%08x) (%d)\n",
>> + protections, vmid, pasid, addr,
>> REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
>>MEMORY_CLIENT_RW) ?
>> "write" : "read", block, mc_client, mc_id);
>> @@ -1404,7 +1404,8 @@ static int gmc_v8_0_process_interrupt(struct
>> amdgpu_device *adev,
>> addr);
>> dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS
>> 0x%08X\n",
>> status);
>> -gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
>> +gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
>> + entry->pasid);
>> }
>> return 0;
>
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[PATCH 19/20] drm/amdgpu: print the PASID with VM faults on GMC v7
Print that extra information on GMC v7.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b73599912b42..6b2896d057fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -746,21 +746,21 @@ static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
*
* Print human readable fault information (CIK).
*/
-static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
-u32 status, u32 addr, u32 mc_client)
+static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
+u32 addr, u32 mc_client, unsigned pasid)
{
- u32 mc_id;
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
VMID);
u32 protections = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS,
PROTECTIONS);
char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
+ u32 mc_id;
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_ID);
- dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s'
(0x%08x) (%d)\n",
- protections, vmid, addr,
+ dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s
from '%s' (0x%08x) (%d)\n",
+ protections, vmid, pasid, addr,
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_RW) ?
"write" : "read", block, mc_client, mc_id);
@@ -1254,7 +1254,8 @@ static int gmc_v7_0_process_interrupt(struct
amdgpu_device *adev,
addr);
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x%08X\n",
status);
- gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
+ gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
+entry->pasid);
}
return 0;
--
2.14.1
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