RE: [PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs

[Zhu, Rex]

Sure.
We should add the PP_SMC_POWER_PROFILE_AUTO in PP_SMC_POWER_PROFILE.
And will be implemented as auto wattman feature.

Best Regards
Rex
-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com] 
Sent: Tuesday, January 16, 2018 11:59 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs

On Tue, Jan 16, 2018 at 6:50 AM, Rex Zhu  wrote:
> when cat pp_power_profile_mode on Vega10
> NUMMODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL
>   0 3D_FULL_SCREEN : 70  60  1  3
>   1   POWER_SAVING : 90  60  0  0
>   2  VIDEO*: 70  60  0  0
>   3 VR : 70  90  0  0
>   4   COMPUTER : 30  60  0  6
>   5 CUSTOM :  0   0  0  0
>
> the result show all the profile mode we can support and custom mode.
> user can echo the num(0-4) to pp_power_profile_mode to select the 
> profile mode or can echo "5 value value value value" to enter CUSTOM mode.
> the four parameter is set_point/FPS/USER_RLC_BUSY/MIN_ACTIVE_LEVEL.
>
> Change-Id: I72634646a9a179ccd57f175b4c0b3f45e538a03f
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  8 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 81 
> +-
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h | 11 +++-
>  3 files changed, 98 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 8a8d09dd..986f1d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -366,6 +366,14 @@ enum amdgpu_pcie_gen {
> (adev)->powerplay.pp_handle, virtual_addr_low, \
> virtual_addr_hi, mc_addr_low, mc_addr_hi, 
> size)
>
> +#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
> +   ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
> +   (adev)->powerplay.pp_handle, buf))
> +
> +#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
> +   ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
> +   (adev)->powerplay.pp_handle, parameter, size))
> +
>  struct amdgpu_dpm {
> struct amdgpu_ps*ps;
> /* number of valid power states */ diff --git 
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index e5ee7cf..662edca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -584,6 +584,73 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
> return count;
>  }
>
> +static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
> +   struct device_attribute *attr,
> +   char *buf)
> +{
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +
> +   if (adev->powerplay.pp_funcs->get_power_profile_mode)
> +   return amdgpu_dpm_get_power_profile_mode(adev, buf);
> +
> +   return snprintf(buf, PAGE_SIZE, "\n"); }
> +
> +
> +static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
> +   struct device_attribute *attr,
> +   const char *buf,
> +   size_t count)
> +{
> +   int ret = 0xff;
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +   uint32_t parameter_size = 0;
> +   long parameter[64];
> +   char *sub_str, buf_cpy[128];
> +   char *tmp_str;
> +   uint32_t i = 0;
> +   char tmp[2];
> +   long int profile_mode = 0;
> +   const char delimiter[3] = {' ', '\n', '\0'};
> +
> +   tmp[0] = *(buf);
> +   tmp[1] = '\0';
> +   ret = kstrtol(tmp, 0, &profile_mode);
> +   if (ret)
> +   goto fail;
> +
> +   if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> +   if (count < 2 || count > 127)
> +   return -EINVAL;
> +   while (isspace(*++buf))
> +   i++;
> +   memcpy(buf_cpy, buf, count-i);
> +   tmp_str = buf_cpy;
> +   while (tmp_str[0]) {
> +   sub_str = strsep(&tmp_str, delimiter);
> +   ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
> +   if (ret) {
> +   count = -EINVAL;
> +   goto fail;
> +   }
> +   pr_info("value is %ld \n", parameter[parameter_size]);
> +   parameter_size++;
> +   while (isspace(*tmp_str))
> +   tmp_str++;
> +   }
> + 

[PATCH] drm/amdgpu: disable ECC check for Raven to avoid error message annoyance

[Junwei Zhang]

It should be enabled until ECC is supported for Raven.

Change-Id: If847663d503c26d2a08274ca721b4ce1bc637111
Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c12ee75..a333442 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -533,6 +533,10 @@ static int gmc_v9_0_ecc_available(struct amdgpu_device 
*adev)
 
DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
 
+   /* Temporally skip ECC for Raven to avoid error message annoyance */
+   if (adev->asic_type == CHIP_RAVEN)
+   return 0;
+
lost_sheep = 0;
for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
reg_addr = ecc_umclocalcap_addrs[i];
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 14/21] drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback

[Chunming Zhou]

I'm not sure if this is a good ongoing, as I know, our per IP topology 
is intended for every generation asic bringup.


I think there are many similar logics which we can abstract, but we 
don't do that.


For emit_wreg above patches, they only can be used by vm flush part, but 
they are common func fallback.


Can we only make emit_wreg as static in their files, and replace every 
where they are used?


Regards,
David Zhou
On 2018年01月17日 03:40, Christian König wrote:

Add a new GMC function to unify vm flushing.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
  2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 93eae393b08d..230826718c98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1779,6 +1779,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
  #define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
  #define amdgpu_asic_invalidate_hdp(adev) 
(adev)->asic_funcs->invalidate_hdp((adev))
  #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) 
(adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
+#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) 
(r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
  #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) 
(adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
  #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) 
(adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
  #define amdgpu_gmc_get_pte_flags(adev, flags) 
(adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index a4a8374f7f3f..114350a4693f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -52,6 +52,9 @@ struct amdgpu_gmc_funcs {
/* flush the vm tlb via mmio */
void (*flush_gpu_tlb)(struct amdgpu_device *adev,
  uint32_t vmid);
+   /* flush the vm tlb via ring */
+   uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
+  unsigned pasid, uint64_t pd_addr);
/* write pte/pde updates using the cpu */
int (*set_pte_pde)(struct amdgpu_device *adev,
   void *cpu_pt_addr, /* cpu addr of page table */


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

gmc8, gmc9, not gfx...


On 2018年01月17日 14:13, Chunming Zhou wrote:

and please fix patch #21 title, which should be gfx9 not gfx8.


On 2018年01月17日 14:11, Chunming Zhou wrote:

patch #19, #20, #21 are Reviewed-by: Chunming Zhou 


On 2018年01月17日 03:40, Christian König wrote:

This way we can see the PASID in VM faults.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index f7bcfa53eff0..2efbecf486c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -33,6 +33,7 @@
  #include "vega10_enum.h"
  #include "mmhub/mmhub_1_0_offset.h"
  #include "athub/athub_1_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
    #include "soc15.h"
  #include "soc15_common.h"
@@ -369,10 +370,12 @@ static uint64_t 
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,

  unsigned vmid, unsigned pasid,
  uint64_t pd_addr)
  {
-    struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+    struct amdgpu_device *adev = ring->adev;
+    struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
  uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
  uint64_t flags = AMDGPU_PTE_VALID;
  unsigned eng = ring->vm_inv_eng;
+    uint32_t reg;
    amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
  pd_addr |= flags;
@@ -383,6 +386,13 @@ static uint64_t 
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,

  amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
    upper_32_bits(pd_addr));
  +    if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+    reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+    else
+    reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+
+    amdgpu_ring_emit_wreg(ring, reg, pasid);
+
  amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
    return pd_addr;


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v3] drm/amdgpu: reserved requested gtt buffer for smu

[Rex Zhu]

v3: - fix return value check in amdgpu_pp_alloc_mem_for_smu
- save memory size in struct powerplay
- not modify module parameter
v2: - merge tip drm-next code.
- simplify check smu_memory_size code.
- simplify allocate smu memroy code.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 43 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  6 
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 39 
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  2 +-
 8 files changed, 95 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cd3af51..ff86d6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -128,6 +128,7 @@
 extern int amdgpu_lbpw;
 extern int amdgpu_compute_multipipe;
 extern int amdgpu_gpu_recovery;
+extern uint amdgpu_smu_memory_pool_size;
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
@@ -1418,6 +1419,8 @@ enum amd_hw_ip_block_type {
 struct amd_powerplay {
struct cgs_device *cgs_device;
void *pp_handle;
+   struct amdgpu_bo *smu_prv_buffer; /* used for SMU debug */
+   u32 smu_prv_buffer_size;
const struct amd_ip_funcs *ip_funcs;
const struct amd_pm_funcs *pp_funcs;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d09c4ee..017abb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -773,6 +773,46 @@ static void amdgpu_device_check_vm_size(struct 
amdgpu_device *adev)
}
 }
 
+static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
+{
+   struct sysinfo si;
+   bool is_os_64 = (sizeof(void *) == 8) ? true : false;
+   uint64_t total_memory;
+   uint64_t dram_size_seven_GB = 0x1B800;
+   uint64_t dram_size_three_GB = 0xB800;
+
+   if (amdgpu_smu_memory_pool_size == 0)
+   return;
+
+   if (!is_os_64) {
+   DRM_WARN("Not 64-bit OS, feature not supported\n");
+   goto def_value;
+   }
+   si_meminfo(&si);
+   total_memory = (uint64_t)si.totalram * si.mem_unit;
+
+   if ((amdgpu_smu_memory_pool_size == 1) ||
+   (amdgpu_smu_memory_pool_size == 2)) {
+   if (total_memory < dram_size_three_GB)
+   goto def_value1;
+   } else if ((amdgpu_smu_memory_pool_size == 4) ||
+   (amdgpu_smu_memory_pool_size == 8)) {
+   if (total_memory < dram_size_seven_GB)
+   goto def_value1;
+   } else {
+   DRM_WARN("Smu memory pool size not supported\n");
+   goto def_value;
+   }
+   adev->powerplay.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
+
+   return;
+
+def_value1:
+   DRM_WARN("No enough system memory\n");
+def_value:
+   adev->powerplay.smu_prv_buffer_size = 0;
+}
+
 /**
  * amdgpu_device_check_arguments - validate module params
  *
@@ -814,6 +854,8 @@ static void amdgpu_device_check_arguments(struct 
amdgpu_device *adev)
amdgpu_vm_fragment_size = -1;
}
 
+   amdgpu_device_check_smu_prv_buffer_size(adev);
+
amdgpu_device_check_vm_size(adev);
 
amdgpu_device_check_block_size(adev);
@@ -2073,6 +2115,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
}
+
adev->accel_working = false;
cancel_delayed_work_sync(&adev->late_init_work);
/* free i2c buses */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0bb34db..e679bb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -130,6 +130,7 @@
 int amdgpu_lbpw = -1;
 int amdgpu_compute_multipipe = -1;
 int amdgpu_gpu_recovery = -1; /* auto */
+uint amdgpu_smu_memory_pool_size = 0;
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -311,6 +312,11 @@
 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 #endif
 
+MODULE_PARM_DESC(smu_memory_pool_size,
+   "reserve gtt for smu debug usage, 0 = disable,"
+   "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 
0444);
+
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
diff --git a/driver

Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

and please fix patch #21 tile, which should be gfx9 not gfx8.


On 2018年01月17日 14:11, Chunming Zhou wrote:

patch #19, #20, #21 are Reviewed-by: Chunming Zhou 


On 2018年01月17日 03:40, Christian König wrote:

This way we can see the PASID in VM faults.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index f7bcfa53eff0..2efbecf486c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -33,6 +33,7 @@
  #include "vega10_enum.h"
  #include "mmhub/mmhub_1_0_offset.h"
  #include "athub/athub_1_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
    #include "soc15.h"
  #include "soc15_common.h"
@@ -369,10 +370,12 @@ static uint64_t 
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,

  unsigned vmid, unsigned pasid,
  uint64_t pd_addr)
  {
-    struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+    struct amdgpu_device *adev = ring->adev;
+    struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
  uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
  uint64_t flags = AMDGPU_PTE_VALID;
  unsigned eng = ring->vm_inv_eng;
+    uint32_t reg;
    amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
  pd_addr |= flags;
@@ -383,6 +386,13 @@ static uint64_t 
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,

  amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
    upper_32_bits(pd_addr));
  +    if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+    reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+    else
+    reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+
+    amdgpu_ring_emit_wreg(ring, reg, pasid);
+
  amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
    return pd_addr;


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

and please fix patch #21 title, which should be gfx9 not gfx8.


On 2018年01月17日 14:11, Chunming Zhou wrote:

patch #19, #20, #21 are Reviewed-by: Chunming Zhou 


On 2018年01月17日 03:40, Christian König wrote:

This way we can see the PASID in VM faults.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index f7bcfa53eff0..2efbecf486c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -33,6 +33,7 @@
  #include "vega10_enum.h"
  #include "mmhub/mmhub_1_0_offset.h"
  #include "athub/athub_1_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
    #include "soc15.h"
  #include "soc15_common.h"
@@ -369,10 +370,12 @@ static uint64_t 
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,

  unsigned vmid, unsigned pasid,
  uint64_t pd_addr)
  {
-    struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+    struct amdgpu_device *adev = ring->adev;
+    struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
  uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
  uint64_t flags = AMDGPU_PTE_VALID;
  unsigned eng = ring->vm_inv_eng;
+    uint32_t reg;
    amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
  pd_addr |= flags;
@@ -383,6 +386,13 @@ static uint64_t 
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,

  amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
    upper_32_bits(pd_addr));
  +    if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+    reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+    else
+    reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+
+    amdgpu_ring_emit_wreg(ring, reg, pasid);
+
  amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
    return pd_addr;


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

patch #19, #20, #21 are Reviewed-by: Chunming Zhou 


On 2018年01月17日 03:40, Christian König wrote:

This way we can see the PASID in VM faults.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f7bcfa53eff0..2efbecf486c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -33,6 +33,7 @@
  #include "vega10_enum.h"
  #include "mmhub/mmhub_1_0_offset.h"
  #include "athub/athub_1_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
  
  #include "soc15.h"

  #include "soc15_common.h"
@@ -369,10 +370,12 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
  {
-   struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+   struct amdgpu_device *adev = ring->adev;
+   struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+   uint32_t reg;
  
  	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);

pd_addr |= flags;
@@ -383,6 +386,13 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
  upper_32_bits(pd_addr));
  
+	if (ring->funcs->vmhub == AMDGPU_GFXHUB)

+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+   else
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+
+   amdgpu_ring_emit_wreg(ring, reg, pasid);
+
amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
  
  	return pd_addr;


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 2/3] drm/amd/pp: Add stable Pstate clk display when print_clock_levels

[Zhu, Rex]

Ok, I will drop this patch. and please review the new attached patch expose 
stable pstate clock by ioctl.

Best Regards
Rex

-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com] 
Sent: Wednesday, January 17, 2018 12:03 AM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 2/3] drm/amd/pp: Add stable Pstate clk display when 
print_clock_levels

On Tue, Jan 16, 2018 at 6:59 AM, Rex Zhu  wrote:
> The additional output are at the end of sclk/mclk info as cat 
> pp_dpm_mclk
> 0: 300Mhz *
> 1: 1650Mhz
> P: 300Mhz
>
> Signed-off-by: Rex Zhu 

I'm not crazy about this patch.  I think it conflates things and breaks older 
versions of the rocm smi tool.  I'd prefer to add a new file for the pstate 
clocks or add a query to the amdgpu INFO ioctl to fetch them.

Alex


>
> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>  4 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index f68dd08..03dfba0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, sclk_table->entries[i].clk / 100,
> (i == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> + hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> now = 
> PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> CZ_NUM_NBPMEMORYCLOCK-i, 
> data->sys_info.nbp_memory_clock[i-1] / 100,
> (CZ_NUM_NBPMEMORYCLOCK-i == 
> now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> + hwmgr->pstate_mclk/100);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index 409a56b..88c6ad8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
> data->gfx_max_freq_limit / 100,
> ((data->gfx_max_freq_limit / 100)
>  == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> + hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
> mclk_table->entries[i].clk / 100,
> ((mclk_table->entries[i].clk / 100)
>  == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> + hwmgr->pstate_mclk/100);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 11a900b..6f053fa 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4301,6 +4301,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, sclk_table->dpm_levels[i].value / 
> 100,
> (i == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> + hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> smum_send_msg_to_smc(hwmgr, 
> PPSMC_MSG_API_GetMclkFrequency); @@ -4317,6 +4318,7 @@ static int 
> smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, mclk_table->dpm_levels[i].value / 
> 100,
> (i == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> + hwmgr->pstate_mclk/100);
> break;
> case PP_PCIE:
> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drive

RE: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature

[Zhu, Rex]

-Original Message-
From: Grazvydas Ignotas [mailto:nota...@gmail.com] 
Sent: Wednesday, January 17, 2018 1:53 AM
To: Zhu, Rex
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD 
feature

On Tue, Jan 16, 2018 at 2:02 PM, Rex Zhu  wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu clock and voltage through 
> sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher 
> Signed-off-by: Rex Zhu 
> +   if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)

>>PP_OVERDRIVE_MASK? I believe "overdrive" is a single word.

Yes, OverDrive as a power feature. So better change to PP_OVERDRIVE_MASK.
Thanks.


Best Regards
Rex
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature

[Zhu, Rex]

>>Setting the feature mask to 0x2fff unsets PP_SOCCLK_DPM_MASK.
>>Probably not intended.  I think you want 0x3fff.

Yes, Thanks for pointing it out.

Best Regards
Rex
-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com] 
Sent: Wednesday, January 17, 2018 1:12 AM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD 
feature

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu clock and voltage through 
> sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher 
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 3 +++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 6 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 2 ++
>  5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e679bb8..508a254 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -120,7 +120,7 @@
>  uint amdgpu_sdma_phase_quantum = 32;
>  char *amdgpu_disable_cu = NULL;
>  char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0x;
> +uint amdgpu_pp_feature_mask = 0x2fff;

Setting the feature mask to 0x2fff unsets PP_SOCCLK_DPM_MASK.
Probably not intended.  I think you want 0x3fff.

Alex

>  int amdgpu_ngg = 0;
>  int amdgpu_prim_buf_per_se = 0;
>  int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index e35bdc5..ebfbbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_CAC);
> }
>
> +   if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
> +   hwmgr->od_enabled = true;
> +
> return 0;
>  }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 6f053fa..ce74e06 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3572,8 +3572,7 @@ static int 
> smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->sclk_table.dpm_levels
> [dpm_table->sclk_table.count - 1].value = sclk;
>
> -   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinACSupport) ||
> -   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinDCSupport)) {
> +   if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
>  * as the Heatmap GPU Clock axis is also based on the default 
> values
>  */
> @@ -3618,8 +3617,7 @@ static int 
> smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->mclk_table.dpm_levels
> [dpm_table->mclk_table.count - 1].value = 
> mclk;
>
> -   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinACSupport) ||
> -   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinDCSupport)) {
> +   if (hwmgr->od_enabled) {
>
> PP_ASSERT_WITH_CODE(
> 
> (golden_dpm_table->mclk_table.dpm_levels
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index fadbc8a..12a31d1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3396,8 +3396,7 @@ static int 
> vega10_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->
> 
> gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
> value = sclk;
> -   if 
> (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> -   
> PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> +   if (hwmgr->od_enabled) {
> /* Need to do calculation based on 
> the golden DPM table
>  * as the Heatmap GPU Clock axis is 
> also based on
>  * the default values @@ 
> -3451,9 +3450,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
> mem_table.dpm_levels[dpm_table->mem_table.count - 

Re: TTM leaking swap space?

[Chunming Zhou]

Hi Felix,

Could I get your test to have a try?


Thanks,

David Zhou


On 2018年01月17日 11:21, Felix Kuehling wrote:

I'm running an eviction stress test with KFD and find that sometimes it
starts swapping. When that happens, swap usage goes up rapidly, but it
never comes down. Even after the processes terminate, and all VRAM and
GTT allocations are freed (checked in
/sys/kernel/debug/dri/0/amdgpu_{gtt|vram}_mm), swap space is still not
released.

Running the test repeatedly I was able to trigger the OOM killer quite
easily. The system died with a panic, running out of processes to kill.

The symptoms look like swap space is only allocated but never released.

A quick look at the swapping code in ttm_tt.c doesn't show any obvious
problems. I'm assuming that fput should free swap space. That should
happen when BOs are swapped back in, or destroyed. As far as I can tell,
amdgpu doesn't use persistent swap space, so I'm ignoring
TTM_PAGE_FLAG_PERSISTENT_SWAP.

Any other ideas or pointers?

Thanks,
   Felix



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

TTM leaking swap space?

[Felix Kuehling]

I'm running an eviction stress test with KFD and find that sometimes it
starts swapping. When that happens, swap usage goes up rapidly, but it
never comes down. Even after the processes terminate, and all VRAM and
GTT allocations are freed (checked in
/sys/kernel/debug/dri/0/amdgpu_{gtt|vram}_mm), swap space is still not
released.

Running the test repeatedly I was able to trigger the OOM killer quite
easily. The system died with a panic, running out of processes to kill.

The symptoms look like swap space is only allocated but never released.

A quick look at the swapping code in ttm_tt.c doesn't show any obvious
problems. I'm assuming that fput should free swap space. That should
happen when BOs are swapped back in, or destroyed. As far as I can tell,
amdgpu doesn't use persistent swap space, so I'm ignoring
TTM_PAGE_FLAG_PERSISTENT_SWAP.

Any other ideas or pointers?

Thanks,
  Felix

-- 
F e l i x   K u e h l i n g
PMTS Software Development Engineer | Vertical Workstation/Compute
1 Commerce Valley Dr. East, Markham, ON L3T 7X6 Canada
(O) +1(289)695-1597
   _ _   _   _   _
  / \   | \ / | |  _  \  \ _  |
 / A \  | \M/ | | |D) )  /|_| |
/_/ \_\ |_| |_| |_/ |__/ \|   facebook.com/AMD | amd.com

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/2] drm/amdgpu: fix CPU based VM updates

[Chunming Zhou]

The series is Ached-by: Chunming Zhou 


On 2018年01月17日 01:05, Felix Kuehling wrote:

Thanks for taking care of this. Patch 2 is a nice simplification that
should reduce the chances of breaking CPU updates in the future. The
series is Reviewed-by: Felix Kuehling 

Regards,
   Felix


On 2018-01-16 10:56 AM, Christian König wrote:

That got accidentially removed.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +-
  1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d75637f02ef4..155e6f915964 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -969,12 +969,16 @@ static void amdgpu_vm_handle_huge_pages(struct 
amdgpu_pte_update_params *p,
entry->huge = true;
amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
  
-	if (parent->base.bo->shadow) {

-   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
-   pde = pd_addr + (entry - parent->entries) * 8;
-   p->func(p, pde, dst, 1, 0, flags);
+   if (p->func == amdgpu_vm_cpu_set_ptes) {
+   pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
+   } else {
+   if (parent->base.bo->shadow) {
+   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
+   pde = pd_addr + (entry - parent->entries) * 8;
+   p->func(p, pde, dst, 1, 0, flags);
+   }
+   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
}
-   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
pde = pd_addr + (entry - parent->entries) * 8;
p->func(p, pde, dst, 1, 0, flags);
  }

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH v2 1/2] drm/ttm: Allow page allocations w/o triggering OOM..

[He, Roger]

Reviewed-by: Roger He 

Thanks
Roger(Hongbo.He)
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of 
Andrey Grodzovsky
Sent: Tuesday, January 16, 2018 11:18 PM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig, 
Christian 
Cc: He, Roger 
Subject: [PATCH v2 1/2] drm/ttm: Allow page allocations w/o triggering OOM..

This to allow drivers to choose to avoid OOM invocation and handle page 
allocation failures instead.

v2:
Remove extra new lines.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/ttm/ttm_bo.c |  3 +++
 drivers/gpu/drm/ttm/ttm_page_alloc.c |  6 ++
 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c |  3 +++
 drivers/gpu/drm/ttm/ttm_tt.c | 13 +++--
 include/drm/ttm/ttm_bo_driver.h  |  4 
 5 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 
2eb71ff..f32aab1 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -234,6 +234,9 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, 
bool zero_alloc)
if (bdev->need_dma32)
page_flags |= TTM_PAGE_FLAG_DMA32;
 
+   if (bdev->no_retry)
+   page_flags |= TTM_PAGE_FLAG_NO_RETRY;
+
switch (bo->type) {
case ttm_bo_type_device:
if (zero_alloc)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 0eab24e..f34c843 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -741,6 +741,9 @@ static int ttm_page_pool_get_pages(struct ttm_page_pool 
*pool,
if (ttm_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
 
+   if (ttm_flags & TTM_PAGE_FLAG_NO_RETRY)
+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
/* ttm_alloc_new_pages doesn't reference pool so we can run
 * multiple requests in parallel.
 **/
@@ -893,6 +896,9 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
if (flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
 
+   if (flags & TTM_PAGE_FLAG_NO_RETRY)
+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
if (flags & TTM_PAGE_FLAG_DMA32)
gfp_flags |= GFP_DMA32;
else
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index c7f01a4..6949ef7 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -920,6 +920,9 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt 
*ttm_dma, bool huge)
gfp_flags &= ~__GFP_COMP;
}
 
+   if (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY)
+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
return gfp_flags;
 }
 
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 
5a046a3..9e4d43d 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -301,7 +301,11 @@ int ttm_tt_swapin(struct ttm_tt *ttm)
swap_space = swap_storage->f_mapping;
 
for (i = 0; i < ttm->num_pages; ++i) {
-   from_page = shmem_read_mapping_page(swap_space, i);
+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ? 
__GFP_RETRY_MAYFAIL : 0);
+   from_page = shmem_read_mapping_page_gfp(swap_space, i, 
gfp_mask);
+
if (IS_ERR(from_page)) {
ret = PTR_ERR(from_page);
goto out_err;
@@ -350,10 +354,15 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file 
*persistent_swap_storage)
swap_space = swap_storage->f_mapping;
 
for (i = 0; i < ttm->num_pages; ++i) {
+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ? 
+__GFP_RETRY_MAYFAIL : 0);
+
from_page = ttm->pages[i];
if (unlikely(from_page == NULL))
continue;
-   to_page = shmem_read_mapping_page(swap_space, i);
+
+   to_page = shmem_read_mapping_page_gfp(swap_space, i, gfp_mask);
if (IS_ERR(to_page)) {
ret = PTR_ERR(to_page);
goto out_err;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h 
index 94064b1..9b417eb 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -86,6 +86,7 @@ struct ttm_backend_func {
 #define TTM_PAGE_FLAG_ZERO_ALLOC  (1 << 6)
 #define TTM_PAGE_FLAG_DMA32   (1 << 7)
 #define TTM_PAGE_FLAG_SG  (1 << 8)
+#define TTM_PAGE_FLAG_NO_RETRY(1 << 9)
 
 enum ttm_caching_state {

RE: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[He, Roger]

-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] 
Sent: Tuesday, January 16, 2018 8:46 PM
To: Grodzovsky, Andrey ; Koenig, Christian 
; He, Roger ; 
dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

Am 16.01.2018 um 13:43 schrieb Andrey Grodzovsky:
>
>
> On 01/16/2018 03:54 AM, Christian König wrote:
>> Am 16.01.2018 um 07:18 schrieb He, Roger:
>>> -Original Message-
>>> From: Andrey Grodzovsky [mailto:andrey.grodzov...@amd.com]
>>> Sent: Saturday, January 13, 2018 6:29 AM
>>> To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
>>> Cc: Koenig, Christian ; He, Roger 
>>> ; Grodzovsky, Andrey 
>>> Subject: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM 
>>> triggering.
>>>
>>> This to have a load time option to avoid OOM on RAM allocations.
>>>
>>> Signed-off-by: Andrey Grodzovsky 
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 +
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 4 
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
>>>   3 files changed, 9 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index b7c181e..1387239 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -127,6 +127,7 @@ extern int amdgpu_job_hang_limit;  extern int 
>>> amdgpu_lbpw;  extern int amdgpu_compute_multipipe;  extern int 
>>> amdgpu_gpu_recovery;
>>> +extern int amdgpu_alloc_no_oom;
>>>     #ifdef CONFIG_DRM_AMDGPU_SI
>>>   extern int amdgpu_si_support;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> index d96f9ac..6e98189 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> @@ -130,6 +130,7 @@ int amdgpu_job_hang_limit = 0;  int amdgpu_lbpw 
>>> = -1;  int amdgpu_compute_multipipe = -1;  int amdgpu_gpu_recovery = 
>>> -1; /* auto */
>>> +int amdgpu_alloc_no_oom = -1; /* auto */
>>>
>>> How about turn it on as default?
>>
>> I think we can even go a step further, drop the module parameter and 
>> just turn it always on for amdgpu.
>>
>> Christian.
>
> Will fix, just a reminder that Roger's patches - [PATCH 1/2] drm/ttm: 
> don't update global memory count for some special cases [PATCH 2/2] 
> drm/ttm: only free pages rather than update global memory count 
> together
>
> Needs to be merged before my patches since the fix a TTM bug on 
> allocation failure.

The second is merged, but I had some comments on the first and Roger 
hasn't replied yet.

Roger what's the status on that one?

Already fixed locally, but not tested yet.  Try to send out today.

Thanks
Roger(Hongbo.He)

>
> Thanks,
> Andrey
>
>>
>>>
>>> Thanks
>>> Roger(Hongbo.He)
>>>
>>> MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in 
>>> megabytes");  module_param_named(vramlimit, amdgpu_vram_limit, int, 
>>> 0600); @@ -285,6 +286,9 @@ module_param_named(compute_multipipe,
>>> amdgpu_compute_multipipe, int, 0444); MODULE_PARM_DESC(gpu_recovery, 
>>> "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = 
>>> auto"); module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 
>>> 0444);
>>>   +MODULE_PARM_DESC(alloc_no_oom, "Allocate RAM without triggering 
>>> OOM
>>> +killer, (1 = enable, 0 = disable, -1 = auto"); 
>>> +module_param_named(alloc_no_oom, amdgpu_alloc_no_oom, int, 0444);
>>> +
>>>   #ifdef CONFIG_DRM_AMDGPU_SI
>>>     #if defined(CONFIG_DRM_RADEON) ||
>>> defined(CONFIG_DRM_RADEON_MODULE) diff --git 
>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> index 5c4c3e0..fc27164 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> @@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct 
>>> amdgpu_device *adev,  #endif
>>>     bo->tbo.bdev = &adev->mman.bdev;
>>> +
>>> +    if (amdgpu_alloc_no_oom == 1)
>>> +    bo->tbo.bdev->no_retry = true;
>>> +
>>>   amdgpu_ttm_placement_from_domain(bo, domain);
>>>     r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, 
>>> type,
>>> --
>>> 2.7.4
>>>
>>> ___
>>> dri-devel mailing list
>>> dri-de...@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: fix typo in amdgpu_vce_validate_bo

[Deng, Emily]

Reviewed-by: Deng, Emily 

> -Original Message-
> From: Andy Furniss [mailto:adf.li...@gmail.com]
> Sent: Wednesday, January 17, 2018 2:06 AM
> To: Christian König ; amd-
> g...@lists.freedesktop.org; Deng, Emily 
> Subject: Re: [PATCH] drm/amdgpu: fix typo in amdgpu_vce_validate_bo
> 
> Christian König wrote:
> > Otherwise buffer placement is very restrictive and might fail.
> >
> > Fixes: "drm/amdgpu: fix VCE buffer placement restrictions v2"
> >
> > Signed-off-by: Christian König 
> > Reported-by: Deng, Emily 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > index 55a726a322e3..d274ae535530 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > @@ -585,8 +585,8 @@ static int amdgpu_vce_validate_bo(struct
> > amdgpu_cs_parser *p, uint32_t ib_idx,
> >
> > for (i = 0; i < bo->placement.num_placement; ++i) {
> > bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
> > -   bo->placements[i].lpfn = bo->placements[i].fpfn ?
> > -   min(bo->placements[i].fpfn, lpfn) : lpfn;
> > +   bo->placements[i].lpfn = bo->placements[i].lpfn ?
> > +   min(bo->placements[i].lpfn, lpfn) : lpfn;
> > }
> > return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
> >   }
> 
> This fixes VCE for me, also with this I can again test
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=102296
> 
> which also seems good now. I'll close that after I am sure I am testing
> correctly.
> 

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH v2] drm/amdgpu: reserved requested gtt buffer for smu

[Quan, Evan]

>-Original Message-
>From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Rex 
>Zhu
>Sent: Tuesday, January 16, 2018 7:47 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhu, Rex 
>Subject: [PATCH v2] drm/amdgpu: reserved requested gtt buffer for smu
>
>v2: merge tip drm-next code.
>simplify check smu_memory_size code.
>simplify allocate smu memroy code.
>
>Change-Id: Ie8e865cc7d6c9d60fe234f29ac07e9f9fae60e9f
>Signed-off-by: Rex Zhu 
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 43
>+++
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  6 
> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 39
>
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  2 +-
> 8 files changed, 94 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>index cd3af51..46cd14c 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>@@ -128,6 +128,7 @@
> extern int amdgpu_lbpw;
> extern int amdgpu_compute_multipipe;
> extern int amdgpu_gpu_recovery;
>+extern uint amdgpu_smu_memory_pool_size;
>
> #ifdef CONFIG_DRM_AMDGPU_SI
> extern int amdgpu_si_support;
>@@ -1418,6 +1419,7 @@ enum amd_hw_ip_block_type {
> struct amd_powerplay {
>   struct cgs_device *cgs_device;
>   void *pp_handle;
>+  struct amdgpu_bo *smu_prv_buffer; /* used for SMU debug */
>   const struct amd_ip_funcs *ip_funcs;
>   const struct amd_pm_funcs *pp_funcs;
> };
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index d09c4ee..f0b112c 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -773,6 +773,46 @@ static void amdgpu_device_check_vm_size(struct
>amdgpu_device *adev)
>   }
> }
>
>+static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device 
>*adev)
>+{
>+  struct sysinfo si;
>+  bool is_os_64 = (sizeof(void *) == 8) ? true : false;
>+  uint64_t total_memory;
>+  uint64_t dram_size_seven_GB = 0x1B800;
>+  uint64_t dram_size_three_GB = 0xB800;
>+
>+  if (amdgpu_smu_memory_pool_size == 0)
>+  return;
>+
>+  if (!is_os_64) {
>+  DRM_WARN("Not 64-bit OS, feature not supported\n");
>+  goto def_value;
>+  }
>+  si_meminfo(&si);
>+  total_memory = (uint64_t)si.totalram * si.mem_unit;
>+
>+  if ((amdgpu_smu_memory_pool_size == 1) ||
>+  (amdgpu_smu_memory_pool_size == 2)) {
>+  if (total_memory < dram_size_three_GB)
>+  goto def_value1;
>+  } else if ((amdgpu_smu_memory_pool_size == 4) ||
>+  (amdgpu_smu_memory_pool_size == 8)) {
>+  if (total_memory < dram_size_seven_GB)
>+  goto def_value1;
>+  } else {
>+  DRM_WARN("Smu memory pool size not supported\n");
>+  goto def_value;
>+  }
>+  amdgpu_smu_memory_pool_size = amdgpu_smu_memory_pool_size << 28;
>+
>+  return;
>+
>+def_value1:
>+  DRM_WARN("No enough system memory\n");
>+def_value:
>+  amdgpu_smu_memory_pool_size = 0;
>+}
>+
> /**
>  * amdgpu_device_check_arguments - validate module params
>  *
>@@ -814,6 +854,8 @@ static void amdgpu_device_check_arguments(struct
>amdgpu_device *adev)
>   amdgpu_vm_fragment_size = -1;
>   }
>
>+  amdgpu_device_check_smu_prv_buffer_size(adev);
>+
>   amdgpu_device_check_vm_size(adev);
>
>   amdgpu_device_check_block_size(adev);
>@@ -2073,6 +2115,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
>   release_firmware(adev->firmware.gpu_info_fw);
>   adev->firmware.gpu_info_fw = NULL;
>   }
>+
>   adev->accel_working = false;
>   cancel_delayed_work_sync(&adev->late_init_work);
>   /* free i2c buses */
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>index 0bb34db..e679bb8 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>@@ -130,6 +130,7 @@
> int amdgpu_lbpw = -1;
> int amdgpu_compute_multipipe = -1;
> int amdgpu_gpu_recovery = -1; /* auto */
>+uint amdgpu_smu_memory_pool_size = 0;
>
> MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
> module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
>@@ -311,6 +312,11 @@
> module_param_named(cik_support, amdgpu_cik_support, int, 0444);
> #endif
>
>+MODULE_PARM_DESC(smu_memory_pool_size,
>+  "reserve gtt for smu debug usage, 0 = disable,"
>+  "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
>+module_param_named(smu_memory_pool_size,

Re: [PATCH 01/21] drm/amdgpu: wire up emit_wreg for gfx v6

[Alex Deucher]

On Tue, Jan 16, 2018 at 2:39 PM, Christian König
 wrote:
> Needed for vm_flush unification.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 39acafbc84d6..e72f3e5d24b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -2402,6 +2402,18 @@ static void gfx_v6_0_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
> }
>  }
>
> +static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
> +   uint32_t reg, uint32_t val)
> +{
> +   int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> +
> +   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> +   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
> +WRITE_DATA_DST_SEL(0)));
> +   amdgpu_ring_write(ring, reg);
> +   amdgpu_ring_write(ring, 0);
> +   amdgpu_ring_write(ring, val);
> +}
>
>  static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
>  {
> @@ -3529,6 +3541,7 @@ static const struct amdgpu_ring_funcs 
> gfx_v6_0_ring_funcs_gfx = {
> .test_ib = gfx_v6_0_ring_test_ib,
> .insert_nop = amdgpu_ring_insert_nop,
> .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
> +   .emit_wreg = gfx_v6_0_ring_emit_wreg,

I think you need to update the compute ring_funcs as well for all the gfx IPs.

Alex

>  };
>
>  static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
> --
> 2.14.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 11/21] drm/amdgpu: wire up emit_wreg for UVD v7

[Alex Deucher]

On Tue, Jan 16, 2018 at 2:40 PM, Christian König
 wrote:
> Needed for vm_flush unification.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 24 +---
>  1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 44f1a3dde4d6..42c4296909e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1255,17 +1255,17 @@ static void uvd_v7_0_enc_ring_emit_ib(struct 
> amdgpu_ring *ring,
> amdgpu_ring_write(ring, ib->length_dw);
>  }
>
> -static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
> -   uint32_t data0, uint32_t data1)
> +static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
> +   uint32_t reg, uint32_t val)
>  {
> struct amdgpu_device *adev = ring->adev;
>
> amdgpu_ring_write(ring,
> PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
> -   amdgpu_ring_write(ring, data0);
> +   amdgpu_ring_write(ring, reg << 2);
> amdgpu_ring_write(ring,
> PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
> -   amdgpu_ring_write(ring, data1);
> +   amdgpu_ring_write(ring, val);
> amdgpu_ring_write(ring,
> PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
> amdgpu_ring_write(ring, 8);


I think this is a special command specifically for writing VM
registers.  I think you just want a regular PACKET0 like I suggested
for UVD 6.  If that's not the case,
uvd_v7_0_ring_emit_hdp_flush() and are
uvd_v7_0_ring_emit_hdp_invalidate() probably wrong then.  Same for UVD
6.

Independent of this patch, it would be nice two switch the magic
numbers written to VCPU_CMD with nicer defines...


Alex


> @@ -1305,11 +1305,11 @@ static void uvd_v7_0_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
>
> data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
> data1 = upper_32_bits(pd_addr);
> -   uvd_v7_0_vm_reg_write(ring, data0, data1);
> +   uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>
> data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
> data1 = lower_32_bits(pd_addr);
> -   uvd_v7_0_vm_reg_write(ring, data0, data1);
> +   uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>
> data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
> data1 = lower_32_bits(pd_addr);
> @@ -1319,7 +1319,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
> /* flush TLB */
> data0 = (hub->vm_inv_eng0_req + eng) << 2;
> data1 = req;
> -   uvd_v7_0_vm_reg_write(ring, data0, data1);
> +   uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>
> /* wait for flush */
> data0 = (hub->vm_inv_eng0_ack + eng) << 2;
> @@ -1380,6 +1380,14 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
> amdgpu_ring_write(ring, 1 << vmid);
>  }
>
> +static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
> +   uint32_t reg, uint32_t val)
> +{
> +   amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
> +   amdgpu_ring_write(ring, reg << 2);
> +   amdgpu_ring_write(ring, val);
> +}
> +
>  #if 0
>  static bool uvd_v7_0_is_idle(void *handle)
>  {
> @@ -1730,6 +1738,7 @@ static const struct amdgpu_ring_funcs 
> uvd_v7_0_ring_vm_funcs = {
> .pad_ib = amdgpu_ring_generic_pad_ib,
> .begin_use = amdgpu_uvd_ring_begin_use,
> .end_use = amdgpu_uvd_ring_end_use,
> +   .emit_wreg = uvd_v7_0_ring_emit_wreg,
>  };
>
>  static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
> @@ -1756,6 +1765,7 @@ static const struct amdgpu_ring_funcs 
> uvd_v7_0_enc_ring_vm_funcs = {
> .pad_ib = amdgpu_ring_generic_pad_ib,
> .begin_use = amdgpu_uvd_ring_begin_use,
> .end_use = amdgpu_uvd_ring_end_use,
> +   .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
>  };
>
>  static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
> --
> 2.14.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Alex Deucher]

On Tue, Jan 16, 2018 at 2:40 PM, Christian König
 wrote:
> Needed for vm_flush unification.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index c6e22eff89e7..b48b843c66ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct 
> amdgpu_ring *ring,
> amdgpu_ring_write(ring, ib->length_dw);
>  }
>
> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
> +   uint32_t reg, uint32_t val)
> +{
> +   amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
> +   amdgpu_ring_write(ring, reg << 2);
> +   amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
> +   amdgpu_ring_write(ring, val);
> +   amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
> +   amdgpu_ring_write(ring, 0x8);

Is this valid on UVD6?  I think this may be a UVD7 thing.  Looking at
the other UVD code, I think we just want:
amdgpu_ring_write(ring, PACKET0(reg, 0));
amdgpu_ring_write(ring, val);

Alex


> +}
> +
>  static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned vmid, unsigned pasid,
> uint64_t pd_addr)
> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs 
> uvd_v6_0_ring_vm_funcs = {
> .pad_ib = amdgpu_ring_generic_pad_ib,
> .begin_use = amdgpu_uvd_ring_begin_use,
> .end_use = amdgpu_uvd_ring_end_use,
> +   .emit_wreg = uvd_v6_0_ring_emit_wreg,
>  };
>
>  static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
> --
> 2.14.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v3] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Felix Kuehling]

Reviewed-by: Felix Kuehling 


On 2018-01-16 02:50 PM, Andrey Grodzovsky wrote:
> Avoid OOM on syatem pages allocations.
>
> v2:
> Remove modeprobe parameter, make this behaviour the only option.
>
> v3:
> Move setting no_retry flag into amdgpu_ttm_init.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 290cdf0..d32f482 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1387,6 +1387,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
>   return r;
>   }
>   adev->mman.initialized = true;
> +
> + /* We opt to avoid OOM on system pages allocations */
> + adev->mman.bdev.no_retry = true;
> +
>   r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
>   adev->gmc.real_vram_size >> PAGE_SHIFT);
>   if (r) {

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v3] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Andrey Grodzovsky]

Avoid OOM on syatem pages allocations.

v2:
Remove modeprobe parameter, make this behaviour the only option.

v3:
Move setting no_retry flag into amdgpu_ttm_init.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 290cdf0..d32f482 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1387,6 +1387,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
return r;
}
adev->mman.initialized = true;
+
+   /* We opt to avoid OOM on system pages allocations */
+   adev->mman.bdev.no_retry = true;
+
r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
adev->gmc.real_vram_size >> PAGE_SHIFT);
if (r) {
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 18/21] drm/amdgpu: implement gmc_v9_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v9.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 -
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 29 
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 25 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 23 ++---
 drivers/gpu/drm/amd/amdgpu/soc15.h  |  2 ++
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   | 43 ---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c   | 22 +++-
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 61 -
 8 files changed, 53 insertions(+), 153 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 114350a4693f..b3d1bd2f51cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -69,7 +69,6 @@ struct amdgpu_gmc_funcs {
/* get the pde for a given mc addr */
void (*get_vm_pde)(struct amdgpu_device *adev, int level,
   u64 *dst, u64 *flags);
-   uint32_t (*get_invalidate_req)(unsigned int vmid);
 };
 
 struct amdgpu_gmc {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b69bbd2d7df1..afdf57206efa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3688,31 +3688,16 @@ static void gfx_v9_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
uint64_t pd_addr)
 {
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-   int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
-   uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-   uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
 
-   amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-   pd_addr |= flags;
-
-   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-  hub->ctx0_ptb_addr_lo32 + (2 * vmid),
-  lower_32_bits(pd_addr));
-
-   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-  hub->ctx0_ptb_addr_hi32 + (2 * vmid),
-  upper_32_bits(pd_addr));
-
-   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-  hub->vm_inv_eng0_req + eng, req);
+   amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
/* wait for the invalidate to complete */
-   gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
- eng, 0, 1 << vmid, 1 << vmid, 0x20);
+   gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + eng,
+ 0, 1 << vmid, 1 << vmid, 0x20);
 
/* compute doesn't have PFP */
-   if (usepfp) {
+   if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
/* sync PFP to ME, otherwise we might get invalid PFP reads */
amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
amdgpu_ring_write(ring, 0x0);
@@ -4312,7 +4297,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_gfx = {
.emit_frame_size = /* totally 242 maximum if 16 IBs */
5 +  /* COND_EXEC */
7 +  /* PIPELINE_SYNC */
-   24 + /* VM_FLUSH */
+   SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
8 +  /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
@@ -4361,7 +4346,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-   24 + /* gfx_v9_0_ring_emit_vm_flush */
+   SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* 
gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm 
fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
@@ -4393,7 +4378,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_kiq = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-   24 + /* gfx_v9_0_ring_emit_vm_flush */
+   SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* 
gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, 
vm fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index b7e3a4dc952c..f7bcfa53eff0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/

[PATCH 14/21] drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback

[Christian König]

Add a new GMC function to unify vm flushing.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 93eae393b08d..230826718c98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1779,6 +1779,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
 #define amdgpu_asic_invalidate_hdp(adev) 
(adev)->asic_funcs->invalidate_hdp((adev))
 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) 
(adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
+#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) 
(r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) 
(adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) 
(adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
 #define amdgpu_gmc_get_pte_flags(adev, flags) 
(adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index a4a8374f7f3f..114350a4693f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -52,6 +52,9 @@ struct amdgpu_gmc_funcs {
/* flush the vm tlb via mmio */
void (*flush_gpu_tlb)(struct amdgpu_device *adev,
  uint32_t vmid);
+   /* flush the vm tlb via ring */
+   uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
+  unsigned pasid, uint64_t pd_addr);
/* write pte/pde updates using the cpu */
int (*set_pte_pde)(struct amdgpu_device *adev,
   void *cpu_pt_addr, /* cpu addr of page table */
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 16/21] drm/amdgpu: implement gmc_v7_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v7.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/cik.h  |  2 ++
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 15 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 +++--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 19 +++
 4 files changed, 26 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index c4989f51ecef..201d8786f9cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -24,6 +24,8 @@
 #ifndef __CIK_H__
 #define __CIK_H__
 
+#define CIK_FLUSH_GPU_TLB_NUM_WREG 2
+
 void cik_srbm_select(struct amdgpu_device *adev,
 u32 me, u32 pipe, u32 queue, u32 vmid);
 int cik_set_ip_blocks(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index fbbac8498044..1d32dedb2534 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -886,18 +886,7 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring 
*ring,
u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
  SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 
-   amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-   if (vmid < 8) {
-   amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + 
vmid));
-   } else {
-   amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + 
vmid - 8));
-   }
-   amdgpu_ring_write(ring, pd_addr >> 12);
-
-   /* flush TLB */
-   amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-   amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-   amdgpu_ring_write(ring, 1 << vmid);
+   amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, 
extra_bits));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
@@ -1290,7 +1279,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs 
= {
6 + /* cik_sdma_ring_emit_hdp_flush */
3 + /* cik_sdma_ring_emit_hdp_invalidate */
6 + /* cik_sdma_ring_emit_pipeline_sync */
-   12 + /* cik_sdma_ring_emit_vm_flush */
+   CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* 
cik_sdma_ring_emit_vm_flush */
9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm 
fence */
.emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
.emit_ib = cik_sdma_ring_emit_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index a8899ecd9387..91879ccbedd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3244,26 +3244,7 @@ static void gfx_v7_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
 {
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
-   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-WRITE_DATA_DST_SEL(0)));
-   if (vmid < 8) {
-   amdgpu_ring_write(ring,
- (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-   } else {
-   amdgpu_ring_write(ring,
- (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 
8));
-   }
-   amdgpu_ring_write(ring, 0);
-   amdgpu_ring_write(ring, pd_addr >> 12);
-
-   /* bits 0-15 are the VM contexts0-15 */
-   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-WRITE_DATA_DST_SEL(0)));
-   amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-   amdgpu_ring_write(ring, 0);
-   amdgpu_ring_write(ring, 1 << vmid);
+   amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
/* wait for the invalidate to complete */
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -5132,7 +5113,7 @@ static const struct amdgpu_ring_funcs 
gfx_v7_0_ring_funcs_gfx = {
5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user 
fence, vm fence */
7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
-   17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
+   CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* 
gfx_v7_0_ring_emit_vm_flush */
3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
@@ -5163,7 +5144,7 @@ static const struct amdgpu_ring_funcs 
gfx_v7_0_ring_funcs_compute = {
7 + /* gfx_v7_0_ring_emit_hdp_flush */
5 + /* gfx_v7_0_ring_emit_hdp_invalidate */

[PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Christian König]

This way we can see the PASID in VM faults.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f7bcfa53eff0..2efbecf486c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -33,6 +33,7 @@
 #include "vega10_enum.h"
 #include "mmhub/mmhub_1_0_offset.h"
 #include "athub/athub_1_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
 
 #include "soc15.h"
 #include "soc15_common.h"
@@ -369,10 +370,12 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
 {
-   struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+   struct amdgpu_device *adev = ring->adev;
+   struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+   uint32_t reg;
 
amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -383,6 +386,13 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
  upper_32_bits(pd_addr));
 
+   if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+   else
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+
+   amdgpu_ring_emit_wreg(ring, reg, pasid);
+
amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
 
return pd_addr;
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 20/21] drm/amdgpu: add PASID mapping for GFX v8

[Christian König]

This way we can see the PASID in VM faults.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vi.h   | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index da02c61dda38..1d0ae23d439f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -622,6 +622,8 @@ static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 
+   amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
+
/* bits 0-15 are the VM contexts0-15 */
amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 6cc2bee4abf7..0429fe332269 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -24,7 +24,7 @@
 #ifndef __VI_H__
 #define __VI_H__
 
-#define VI_FLUSH_GPU_TLB_NUM_WREG  2
+#define VI_FLUSH_GPU_TLB_NUM_WREG  3
 
 void vi_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 01/21] drm/amdgpu: wire up emit_wreg for gfx v6

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 39acafbc84d6..e72f3e5d24b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2402,6 +2402,18 @@ static void gfx_v6_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
}
 }
 
+static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
+   uint32_t reg, uint32_t val)
+{
+   int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+WRITE_DATA_DST_SEL(0)));
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, 0);
+   amdgpu_ring_write(ring, val);
+}
 
 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
 {
@@ -3529,6 +3541,7 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_gfx = {
.test_ib = gfx_v6_0_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
+   .emit_wreg = gfx_v6_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 19/21] drm/amdgpu: add PASID mapping for GMC v7

[Christian König]

This way we can see the PASID in VM faults.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/cik.h  | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index 201d8786f9cb..e49c6f15a0a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -24,7 +24,7 @@
 #ifndef __CIK_H__
 #define __CIK_H__
 
-#define CIK_FLUSH_GPU_TLB_NUM_WREG 2
+#define CIK_FLUSH_GPU_TLB_NUM_WREG 3
 
 void cik_srbm_select(struct amdgpu_device *adev,
 u32 me, u32 pipe, u32 queue, u32 vmid);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 2daf118e69ac..63fb47ae1f12 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -446,6 +446,8 @@ static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 
+   amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
+
/* bits 0-15 are the VM contexts0-15 */
amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 17/21] drm/amdgpu: implement gmc_v8_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v8.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 27 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 19 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 17 ++---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 15 +--
 drivers/gpu/drm/amd/amdgpu/vi.h|  2 ++
 5 files changed, 27 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index ebec33f87fb1..964bf715405c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6333,28 +6333,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
 {
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
-   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-WRITE_DATA_DST_SEL(0)) |
-WR_CONFIRM);
-   if (vmid < 8) {
-   amdgpu_ring_write(ring,
- (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-   } else {
-   amdgpu_ring_write(ring,
- (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 
8));
-   }
-   amdgpu_ring_write(ring, 0);
-   amdgpu_ring_write(ring, pd_addr >> 12);
-
-   /* bits 0-15 are the VM contexts0-15 */
-   /* invalidate the cache */
-   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-WRITE_DATA_DST_SEL(0)));
-   amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-   amdgpu_ring_write(ring, 0);
-   amdgpu_ring_write(ring, 1 << vmid);
+   amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
/* wait for the invalidate to complete */
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -6886,7 +6865,7 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_gfx = {
.emit_frame_size = /* maximum 215dw if count 16 IBs in */
5 +  /* COND_EXEC */
7 +  /* PIPELINE_SYNC */
-   19 + /* VM_FLUSH */
+   VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
8 +  /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
@@ -6933,7 +6912,7 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_compute = {
7 + /* gfx_v8_0_ring_emit_hdp_flush */
5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
7 + /* gfx_v8_0_ring_emit_pipeline_sync */
-   17 + /* gfx_v8_0_ring_emit_vm_flush */
+   VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* 
gfx_v8_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user 
fence, vm fence */
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
.emit_ib = gfx_v8_0_ring_emit_ib_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c6146573c843..da02c61dda38 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -610,6 +610,24 @@ static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device 
*adev,
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }
 
+static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+   unsigned vmid, unsigned pasid,
+   uint64_t pd_addr)
+{
+   uint32_t reg;
+
+   if (vmid < 8)
+   reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
+   else
+   reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
+   amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
+
+   /* bits 0-15 are the VM contexts0-15 */
+   amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
+
+   return pd_addr;
+}
+
 /**
  * gmc_v8_0_set_pte_pde - update the page tables using MMIO
  *
@@ -1637,6 +1655,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
 
 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
+   .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
.set_pte_pde = gmc_v8_0_set_pte_pde,
.set_prt = gmc_v8_0_set_prt,
.get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 0fb4b4409ef1..0aa336371816 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -862,20 +862,7 @@ static void sdma_v2_4_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
 unsigned vmid, unsigned pasid,
 uint64_t pd_addr)
 {
-   amdgpu_ring_

[PATCH 05/21] drm/amdgpu: wire up emit_wreg for SI DMA

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c 
b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 697475a25749..c70e1d35975c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -497,6 +497,14 @@ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll 
interval */
 }
 
+static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring,
+ uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
+   amdgpu_ring_write(ring, (0xf << 16) | reg);
+   amdgpu_ring_write(ring, val);
+}
+
 static int si_dma_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -789,6 +797,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
.test_ib = si_dma_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = si_dma_ring_pad_ib,
+   .emit_wreg = si_dma_ring_emit_wreg,
 };
 
 static void si_dma_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 04/21] drm/amdgpu: wire up emit_wreg for gfx v9

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1f580328f571..b69bbd2d7df1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4004,10 +4004,23 @@ static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring 
*ring, uint32_t reg)
 }
 
 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
- uint32_t val)
+   uint32_t val)
 {
+   uint32_t cmd = 0;
+
+   switch (ring->funcs->type) {
+   case AMDGPU_RING_TYPE_GFX:
+   cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
+   break;
+   case AMDGPU_RING_TYPE_KIQ:
+   cmd = (1 << 16); /* no inc addr */
+   break;
+   default:
+   cmd = WR_CONFIRM;
+   break;
+   }
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
+   amdgpu_ring_write(ring, cmd);
amdgpu_ring_write(ring, reg);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, val);
@@ -4331,6 +4344,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_gfx = {
.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
.emit_tmz = gfx_v9_0_ring_emit_tmz,
+   .emit_wreg = gfx_v9_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
@@ -4362,6 +4376,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
.set_priority = gfx_v9_0_ring_set_priority_compute,
+   .emit_wreg = gfx_v9_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 13/21] drm/amdgpu: wire up emit_wreg for VCN v1

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 85a0ecaba3e3..8efe7f3ec0a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1061,6 +1061,14 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
amdgpu_ring_write(ring, 1 << vmid);
 }
 
+static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
+   uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+   amdgpu_ring_write(ring, reg << 2);
+   amdgpu_ring_write(ring, val);
+}
+
 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -1152,6 +1160,7 @@ static const struct amdgpu_ring_funcs 
vcn_v1_0_dec_ring_vm_funcs = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_vcn_ring_begin_use,
.end_use = amdgpu_vcn_ring_end_use,
+   .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 12/21] drm/amdgpu: wire up emit_wreg for VCE v4

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index a54e88821de3..9a0d6d9824d0 100755
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -1001,6 +1001,14 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, 1 << vmid);
 }
 
+static void vce_v4_0_emit_wreg(struct amdgpu_ring *ring,
+  uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
+   amdgpu_ring_write(ring, reg << 2);
+   amdgpu_ring_write(ring, val);
+}
+
 static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -1084,6 +1092,7 @@ static const struct amdgpu_ring_funcs 
vce_v4_0_ring_vm_funcs = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_vce_ring_begin_use,
.end_use = amdgpu_vce_ring_end_use,
+   .emit_wreg = vce_v4_0_emit_wreg,
 };
 
 static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 03/21] drm/amdgpu: wire up emit_wreg for gfx v8

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3fd7eb2a9a7b..ebec33f87fb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6618,8 +6618,22 @@ static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring 
*ring, uint32_t reg)
 static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
  uint32_t val)
 {
+   uint32_t cmd;
+
+   switch (ring->funcs->type) {
+   case AMDGPU_RING_TYPE_GFX:
+   cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
+   break;
+   case AMDGPU_RING_TYPE_KIQ:
+   cmd = 1 << 16; /* no inc addr */
+   break;
+   default:
+   cmd = WR_CONFIRM;
+   break;
+   }
+
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
+   amdgpu_ring_write(ring, cmd);
amdgpu_ring_write(ring, reg);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, val);
@@ -6903,6 +6917,7 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_gfx = {
.emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
.init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
.patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
+   .emit_wreg = gfx_v8_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 15/21] drm/amdgpu: implement gmc_v6_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v6.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 25 -
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 20 
 drivers/gpu/drm/amd/amdgpu/si.h   |  2 ++
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 15 +++
 4 files changed, 29 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index e72f3e5d24b8..29ce3cc6816e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -38,6 +38,7 @@
 #include "dce/dce_6_0_sh_mask.h"
 #include "gca/gfx_7_2_enum.h"
 #include "si_enums.h"
+#include "si.h"
 
 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -2359,25 +2360,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
 {
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
-   /* write new base address */
-   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
-WRITE_DATA_DST_SEL(0)));
-   if (vmid < 8) {
-   amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + 
vmid ));
-   } else {
-   amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + 
(vmid - 8)));
-   }
-   amdgpu_ring_write(ring, 0);
-   amdgpu_ring_write(ring, pd_addr >> 12);
-
-   /* bits 0-15 are the VM contexts0-15 */
-   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
-WRITE_DATA_DST_SEL(0)));
-   amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-   amdgpu_ring_write(ring, 0);
-   amdgpu_ring_write(ring, 1 << vmid);
+   amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
/* wait for the invalidate to complete */
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -3528,7 +3511,7 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_gfx = {
5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, 
vm fence */
7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
-   17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
+   SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* 
gfx_v6_0_ring_emit_vm_flush */
3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
.emit_ib = gfx_v6_0_ring_emit_ib,
@@ -3555,7 +3538,7 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_compute = {
5 + /* gfx_v6_0_ring_emit_hdp_flush */
5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
7 + /* gfx_v6_0_ring_emit_pipeline_sync */
-   17 + /* gfx_v6_0_ring_emit_vm_flush */
+   SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* 
gfx_v6_0_ring_emit_vm_flush */
14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm 
fence */
.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
.emit_ib = gfx_v6_0_ring_emit_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 709b167f5a6a..62d05d8c18c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -361,6 +361,25 @@ static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid)
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }
 
+static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+   unsigned vmid, unsigned pasid,
+   uint64_t pd_addr)
+{
+   uint32_t reg;
+
+   /* write new base address */
+   if (vmid < 8)
+   reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
+   else
+   reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
+   amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
+
+   /* bits 0-15 are the VM contexts0-15 */
+   amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
+
+   return pd_addr;
+}
+
 static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
uint32_t gpu_page_idx, uint64_t addr,
uint64_t flags)
@@ -1124,6 +1143,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 
 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
+   .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
.set_pte_pde = gmc_v6_0_set_pte_pde,
.set_prt = gmc_v6_0_set_prt,
.get_vm_pde = gmc_v6_0_get_vm_pde,
diff --git a/drivers/gpu/drm/amd/amdgpu/si.h b/drivers/gpu/drm/amd/amdgpu/si.h
inde

[PATCH 08/21] drm/amdgpu: wire up emit_wreg for SDMA v3

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 3e22ae4c3802..935c3a8b6629 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1155,6 +1155,15 @@ static void sdma_v3_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry 
count, poll interval */
 }
 
+static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
+uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, val);
+}
+
 static int sdma_v3_0_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1653,6 +1662,7 @@ static const struct amdgpu_ring_funcs 
sdma_v3_0_ring_funcs = {
.test_ib = sdma_v3_0_ring_test_ib,
.insert_nop = sdma_v3_0_ring_insert_nop,
.pad_ib = sdma_v3_0_ring_pad_ib,
+   .emit_wreg = sdma_v3_0_ring_emit_wreg,
 };
 
 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 11/21] drm/amdgpu: wire up emit_wreg for UVD v7

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 44f1a3dde4d6..42c4296909e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1255,17 +1255,17 @@ static void uvd_v7_0_enc_ring_emit_ib(struct 
amdgpu_ring *ring,
amdgpu_ring_write(ring, ib->length_dw);
 }
 
-static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
-   uint32_t data0, uint32_t data1)
+static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
+   uint32_t reg, uint32_t val)
 {
struct amdgpu_device *adev = ring->adev;
 
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
-   amdgpu_ring_write(ring, data0);
+   amdgpu_ring_write(ring, reg << 2);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
-   amdgpu_ring_write(ring, data1);
+   amdgpu_ring_write(ring, val);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
amdgpu_ring_write(ring, 8);
@@ -1305,11 +1305,11 @@ static void uvd_v7_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
 
data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
data1 = upper_32_bits(pd_addr);
-   uvd_v7_0_vm_reg_write(ring, data0, data1);
+   uvd_v7_0_ring_emit_wreg(ring, data0, data1);
 
data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
-   uvd_v7_0_vm_reg_write(ring, data0, data1);
+   uvd_v7_0_ring_emit_wreg(ring, data0, data1);
 
data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
@@ -1319,7 +1319,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
/* flush TLB */
data0 = (hub->vm_inv_eng0_req + eng) << 2;
data1 = req;
-   uvd_v7_0_vm_reg_write(ring, data0, data1);
+   uvd_v7_0_ring_emit_wreg(ring, data0, data1);
 
/* wait for flush */
data0 = (hub->vm_inv_eng0_ack + eng) << 2;
@@ -1380,6 +1380,14 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
amdgpu_ring_write(ring, 1 << vmid);
 }
 
+static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
+   uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
+   amdgpu_ring_write(ring, reg << 2);
+   amdgpu_ring_write(ring, val);
+}
+
 #if 0
 static bool uvd_v7_0_is_idle(void *handle)
 {
@@ -1730,6 +1738,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_uvd_ring_begin_use,
.end_use = amdgpu_uvd_ring_end_use,
+   .emit_wreg = uvd_v7_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
@@ -1756,6 +1765,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_enc_ring_vm_funcs = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_uvd_ring_begin_use,
.end_use = amdgpu_uvd_ring_end_use,
+   .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
 };
 
 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index c6e22eff89e7..b48b843c66ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, ib->length_dw);
 }
 
+static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
+   uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+   amdgpu_ring_write(ring, reg << 2);
+   amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+   amdgpu_ring_write(ring, val);
+   amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+   amdgpu_ring_write(ring, 0x8);
+}
+
 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
@@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_uvd_ring_begin_use,
.end_use = amdgpu_uvd_ring_end_use,
+   .emit_wreg = uvd_v6_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 09/21] drm/amdgpu: wire up emit_wreg for SDMA v4

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f0b10cb63940..282b402d93ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1172,6 +1172,15 @@ static void sdma_v4_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
 }
 
+static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
+uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, val);
+}
+
 static int sdma_v4_0_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1608,6 +1617,7 @@ static const struct amdgpu_ring_funcs 
sdma_v4_0_ring_funcs = {
.test_ib = sdma_v4_0_ring_test_ib,
.insert_nop = sdma_v4_0_ring_insert_nop,
.pad_ib = sdma_v4_0_ring_pad_ib,
+   .emit_wreg = sdma_v4_0_ring_emit_wreg,
 };
 
 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 06/21] drm/amdgpu: wire up emit_wreg for CIK SDMA

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 66d9b5f85d6e..fbbac8498044 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -907,6 +907,14 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll 
interval */
 }
 
+static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
+   uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, val);
+}
+
 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 bool enable)
 {
@@ -1295,6 +1303,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs 
= {
.test_ib = cik_sdma_ring_test_ib,
.insert_nop = cik_sdma_ring_insert_nop,
.pad_ib = cik_sdma_ring_pad_ib,
+   .emit_wreg = cik_sdma_ring_emit_wreg,
 };
 
 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 02/21] drm/amdgpu: wire up emit_wreg for gfx v7

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e29c22a72764..a8899ecd9387 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3290,6 +3290,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
}
 }
 
+static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
+   uint32_t reg, uint32_t val)
+{
+   int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+WRITE_DATA_DST_SEL(0)));
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, 0);
+   amdgpu_ring_write(ring, val);
+}
+
 /*
  * RLC
  * The RLC is a multi-purpose microengine that handles a
@@ -5134,6 +5147,7 @@ static const struct amdgpu_ring_funcs 
gfx_v7_0_ring_funcs_gfx = {
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
.emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
+   .emit_wreg = gfx_v7_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 07/21] drm/amdgpu: wire up emit_wreg for SDMA v2.4

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index c4de1c18bf77..0fb4b4409ef1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -889,6 +889,15 @@ static void sdma_v2_4_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry 
count, poll interval */
 }
 
+static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
+uint32_t reg, uint32_t val)
+{
+   amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, val);
+}
+
 static int sdma_v2_4_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1219,6 +1228,7 @@ static const struct amdgpu_ring_funcs 
sdma_v2_4_ring_funcs = {
.test_ib = sdma_v2_4_ring_test_ib,
.insert_nop = sdma_v2_4_ring_insert_nop,
.pad_ib = sdma_v2_4_ring_pad_ib,
+   .emit_wreg = sdma_v2_4_ring_emit_wreg,
 };
 
 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH umr] Fix --force command for named and DID specified commands

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 src/app/main.c |  2 +-
 src/lib/discover.c |  2 +-
 src/lib/discover_by_did.c  | 37 -
 src/lib/discover_by_name.c |  8 
 4 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/src/app/main.c b/src/app/main.c
index 2ecd5a39c903..e5ca9acabdd6 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -169,8 +169,8 @@ int main(int argc, char **argv)
if (sscanf(argv[i+1], "0x%lx", 
&options.forcedid) == 0) {
strncpy(options.dev_name, argv[i+1], 
sizeof(options.dev_name) - 1);
options.forcedid = 0;
-   options.instance = -1;
}
+   options.instance = -1;
++i;
} else {
printf("--force requires a number/name\n");
diff --git a/src/lib/discover.c b/src/lib/discover.c
index 6613eec42d53..4af3733c8af8 100644
--- a/src/lib/discover.c
+++ b/src/lib/discover.c
@@ -138,7 +138,7 @@ struct umr_asic *umr_discover_asic(struct umr_options 
*options)
}
 
// try to scan via debugfs
-   if (!options->no_kernel) {
+   if (options->instance >= 0 && !options->no_kernel) {
asic = calloc(1, sizeof *asic);
if (asic) {
asic->instance = options->instance;
diff --git a/src/lib/discover_by_did.c b/src/lib/discover_by_did.c
index 4e7c3f43faa5..0649da90ba08 100644
--- a/src/lib/discover_by_did.c
+++ b/src/lib/discover_by_did.c
@@ -230,6 +230,41 @@ static const struct {
{ 0x687f, &umr_create_vega10 },
 };
 
+static int find_first_did(long did)
+{
+   char name[128], device[128];
+   FILE *f, *f2;
+
+   int x;
+
+   for (x = 0; x < 16; x++) {
+   snprintf(name, sizeof(name)-1, "/sys/kernel/debug/dri/%d/name", 
x);
+   f = fopen(name, "r");
+   if (f) {
+   unsigned tmp_did;
+   fscanf(f, "%*s %s", name);
+   fclose(f);
+
+   // strip off dev= for kernels > 4.7
+   if (strstr(name, "dev="))
+   memmove(name, name+4, strlen(name)-3);
+
+   snprintf(device, sizeof(device)-1, 
"/sys/bus/pci/devices/%s/device", name);
+   f2 = fopen(device, "r");
+   if (f2) {
+   fscanf(f, "0x%04x", &tmp_did);
+   if (tmp_did == did) {
+   fclose(f2);
+   return x;
+   }
+   }
+   fclose(f2);
+   }
+   }
+   return -1;
+}
+
+
 struct umr_asic *umr_discover_asic_by_did(struct umr_options *options, long 
did)
 {
unsigned x;
@@ -242,7 +277,7 @@ struct umr_asic *umr_discover_asic_by_did(struct 
umr_options *options, long did)
 
if (asic) {
asic->did = did;
-   asic->instance = options->instance;
+   asic->instance = find_first_did(did);
umr_scan_config(asic);
 
// set all file handles to -1 (so a call to close_asic won't 
close handle 0)
diff --git a/src/lib/discover_by_name.c b/src/lib/discover_by_name.c
index c0b49ad69475..f183640567b4 100644
--- a/src/lib/discover_by_name.c
+++ b/src/lib/discover_by_name.c
@@ -68,10 +68,10 @@ struct umr_asic *umr_discover_asic_by_name(struct 
umr_options *options, char *na
if (options->instance == -1) {
// try and discover an instance that works
struct umr_options tmp_opt;
-   memset(&tmp_opt, 0, sizeof(tmp_opt));
-   tmp_opt.forcedid = -1;
-   tmp_opt.quiet = 1;
-   for (x = 0; x < 10; x++) {
+   for (x = 0; x < 16; x++) {
+   memset(&tmp_opt, 0, sizeof(tmp_opt));
+   tmp_opt.quiet = 1;
+   tmp_opt.forcedid = -1;
tmp_opt.instance = x;
tmp = umr_discover_asic(&tmp_opt);
if (tmp) {
-- 
2.14.3

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: fix typo in amdgpu_vce_validate_bo

[Andy Furniss]

Christian König wrote:

Otherwise buffer placement is very restrictive and might fail.

Fixes: "drm/amdgpu: fix VCE buffer placement restrictions v2"

Signed-off-by: Christian König 
Reported-by: Deng, Emily 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 55a726a322e3..d274ae535530 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -585,8 +585,8 @@ static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser 
*p, uint32_t ib_idx,
  
  	for (i = 0; i < bo->placement.num_placement; ++i) {

bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
-   bo->placements[i].lpfn = bo->placements[i].fpfn ?
-   min(bo->placements[i].fpfn, lpfn) : lpfn;
+   bo->placements[i].lpfn = bo->placements[i].lpfn ?
+   min(bo->placements[i].lpfn, lpfn) : lpfn;
}
return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
  }


This fixes VCE for me, also with this I can again test

https://bugs.freedesktop.org/show_bug.cgi?id=102296

which also seems good now. I'll close that after I am sure I am testing 
correctly.



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature

[Grazvydas Ignotas]

On Tue, Jan 16, 2018 at 2:02 PM, Rex Zhu  wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu
> clock and voltage through sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher 
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 3 +++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 6 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 2 ++
>  5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e679bb8..508a254 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -120,7 +120,7 @@
>  uint amdgpu_sdma_phase_quantum = 32;
>  char *amdgpu_disable_cu = NULL;
>  char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0x;
> +uint amdgpu_pp_feature_mask = 0x2fff;
>  int amdgpu_ngg = 0;
>  int amdgpu_prim_buf_per_se = 0;
>  int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index e35bdc5..ebfbbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_CAC);
> }
>
> +   if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)

PP_OVERDRIVE_MASK? I believe "overdrive" is a single word.

Gražvydas
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Andrey Grodzovsky]

On 01/16/2018 11:42 AM, Felix Kuehling wrote:

On 2018-01-16 10:18 AM, Andrey Grodzovsky wrote:

Avoid OOM on syatem pages allocations.

v2:
Remove modeprobe parameter, making this behaviour the only option.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5c4c3e0..b4dc3bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
  #endif
  
  	bo->tbo.bdev = &adev->mman.bdev;

+
+   /* We opt to avoid OOM on system pages allocations */
+   bo->tbo.bdev->no_retry = true;
+

Couldn't this be done once in amdgpu_ttm_init just after calling
ttm_bo_device_init? No need to do this for every BO creation.

Regards,
   Felix


Good catch, will fix.

Thanks,
Andrey




amdgpu_ttm_placement_from_domain(bo, domain);
  
  	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 8/8] drm/amd/pp: Add edit/show OD clock/voltage support in sysfs

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> when cat pp_od_clk_voltage it show
> OD_SCLK:
> 0:300Mhz800 mV
> 1:466Mhz818 mV
> 2:751Mhz824 mV
> 3:   1019Mhz987 mV
> 4:   1074Mhz   1037 mV
> 5:   1126Mhz   1087 mV
> 6:   1169Mhz   1137 mV
> 7:   1206Mhz   1150 mV
> OD_MCLK:
> 0:300Mhz800 mV
> 1:   1650Mhz   1000 mV
>
> echo "s/m level clock voltage" to change
> sclk/mclk's  clock and voltage
>
> echo "r" to restore default value.

How do the changes actually get applied?  I don't see any calls to
power_state_set.

Alex

>
> Change-Id: I4d1e70aee31850694a0ff13db8bbfe2524a1d3ae
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  4 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 89 
> +-
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 19 ++
>  4 files changed, 112 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 986f1d5..4b5755e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
> ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
> (adev)->powerplay.pp_handle, parameter, size))
>
> +#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
> +   ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
> +   (adev)->powerplay.pp_handle, type, parameter, size))
> +
>  struct amdgpu_dpm {
> struct amdgpu_ps*ps;
> /* number of valid power states */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index ed9012a..f2d3987 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -360,6 +360,81 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
> return count;
>  }
>
> +static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
> +   struct device_attribute *attr,
> +   const char *buf,
> +   size_t count)
> +{
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +   int ret;
> +   uint32_t parameter_size = 0;
> +   long parameter[64];
> +   char buf_cpy[128];
> +   char *tmp_str;
> +   char *sub_str;
> +   const char delimiter[3] = {' ', '\n', '\0'};
> +   uint32_t type;
> +
> +   if (count > 127)
> +   return -EINVAL;
> +
> +   pr_info("%c \n", *buf);
> +   if (*buf == 's')
> +   type = 0;
> +   else if (*buf == 'm')
> +   type = 1;
> +   else if(*buf == 'r')
> +   type = 2;
> +   else {
> +   pr_info("= \n");
> +   return -EINVAL;
> +   }
> +   memcpy(buf_cpy, buf, count+1);
> +
> +   tmp_str = buf_cpy;
> +
> +   while (isspace(*++tmp_str));
> +
> +   while (tmp_str[0]) {
> +   sub_str = strsep(&tmp_str, delimiter);
> +   ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
> +   if (ret)
> +   return -EINVAL;
> +   parameter_size++;
> +
> +   while (isspace(*tmp_str))
> +   tmp_str++;
> +   }
> +
> +   if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
> +   ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
> +   parameter, parameter_size);
> +
> +   if (ret)
> +   return -EINVAL;
> +
> +   return count;
> +}
> +
> +static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
> +   struct device_attribute *attr,
> +   char *buf)
> +{
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +   uint32_t size = 0;
> +
> +   if (adev->powerplay.pp_funcs->print_clock_levels) {
> +   size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
> +   size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, 
> buf+size);
> +   return size;
> +   } else {
> +   return snprintf(buf, PAGE_SIZE, "\n");
> +   }
> +
> +}
> +
>  static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -842,6 +917,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | 
> S_IWUSR,
>  static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
> amdgpu_get_pp_power_profile_mode,
> amdgpu_set_pp_power_profile_mode);
> +static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
> +   amdgpu_get_pp_od_clk

Re: [PATCH 5/8] drm/amd/pp: Move DPMTABLE_* definitions to common header file

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> Change-Id: I46cdf4f39f4c9c448a2c76b67f1cbbfed26c7488
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h|  5 -
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h  |  6 --
>  drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 11 +++
>  3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
> index 8eec974..1ce84cc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
> @@ -34,11 +34,6 @@
>  #define SMU7_VOLTAGE_CONTROL_BY_SVID2   0x2
>  #define SMU7_VOLTAGE_CONTROL_MERGED 0x3
>
> -#define DPMTABLE_OD_UPDATE_SCLK 0x0001
> -#define DPMTABLE_OD_UPDATE_MCLK 0x0002
> -#define DPMTABLE_UPDATE_SCLK0x0004
> -#define DPMTABLE_UPDATE_MCLK0x0008
> -
>  enum gpu_pt_config_reg_type {
> GPU_CONFIGREG_MMR = 0,
> GPU_CONFIGREG_SMC_IND,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index 689fe9f..ab3e879 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -189,12 +189,6 @@ struct vega10_vbios_boot_state {
> uint32_tdcef_clock;
>  };
>
> -#define DPMTABLE_OD_UPDATE_SCLK 0x0001
> -#define DPMTABLE_OD_UPDATE_MCLK 0x0002
> -#define DPMTABLE_UPDATE_SCLK0x0004
> -#define DPMTABLE_UPDATE_MCLK0x0008
> -#define DPMTABLE_OD_UPDATE_VDDC 0x0010
> -
>  struct vega10_smc_state_table {
> uint32_tsoc_boot_level;
> uint32_tgfx_boot_level;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index 97d25cd..d846cbb 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -358,6 +358,17 @@ struct phm_clocks {
> uint32_t clock[MAX_NUM_CLOCKS];
>  };
>
> +#define DPMTABLE_OD_UPDATE_SCLK 0x0001
> +#define DPMTABLE_OD_UPDATE_MCLK 0x0002
> +#define DPMTABLE_UPDATE_SCLK0x0004
> +#define DPMTABLE_UPDATE_MCLK0x0008
> +#define DPMTABLE_OD_UPDATE_VDDC 0x0010
> +
> +/* To determine if sclk and mclk are in overdrive state */
> +#define SCLK_OVERDRIVE_ENABLED   0x0001
> +#define MCLK_OVERDRIVE_ENABLED   0x0002
> +#define VDDC_OVERDRIVE_ENABLED   0x0010
> +
>  struct phm_odn_performance_level {
> uint32_t clock;
> uint32_t vddc;
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 4/8] drm/amd/pp: Add hwmgr interface for edit dpm table

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> Add odn_edit_dpm_table function
> points for setting user assigned clock/voltage.
>
> Change-Id: I7e49ffdc30b77d07b46bf12ebb275fa0ff901588
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 6 ++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h   | 3 +++
>  2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index d6772a8..97d25cd 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -364,6 +364,12 @@ struct phm_odn_performance_level {
> bool enabled;
>  };
>
> +enum PHM_ODN_DPM_TABLE_TYPE {
> +   PHM_ODN_SCLK_VDDC_TABLE,
> +   PHM_ODN_MCLK_VDDC_TABLE,
> +   PHM_ODN_RESET_DEFAULT_TABLE
> +};
> +
>  struct phm_odn_clock_levels {
> uint32_t size;
> uint32_t options;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index c496742..36e5378 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -345,6 +345,9 @@ struct pp_hwmgr_func {
> struct PP_TemperatureRange *range);
> int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
> int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, 
> uint32_t size);
> +   int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
> +   enum PHM_ODN_DPM_TABLE_TYPE type,
> +   long *input, uint32_t size);
>  };
>
>  struct pp_table_func {
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/8] drm/amd/pp: Add OD driver clock/voltage display on smu7

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> Change-Id: I54bb964a3905f675e93411f93810cc1aa1f67d12
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h   |  2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +
>  2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 401b895..fba44a5 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -107,6 +107,8 @@ enum pp_clock_type {
> PP_SCLK,
> PP_MCLK,
> PP_PCIE,
> +   OD_SCLK,
> +   OD_MCLK,
>  };
>
>  enum amd_pp_sensors {
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index f3d9c64..a0007a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4355,6 +4355,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> struct smu7_single_dpm_table *sclk_table = 
> &(data->dpm_table.sclk_table);
> struct smu7_single_dpm_table *mclk_table = 
> &(data->dpm_table.mclk_table);
> struct smu7_single_dpm_table *pcie_table = 
> &(data->dpm_table.pcie_speed_table);
> +   struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
> +   struct phm_odn_clock_levels *odn_sclk_table = 
> &(odn_table->odn_core_clock_dpm_levels);
> +   struct phm_odn_clock_levels *odn_mclk_table = 
> &(odn_table->odn_memory_clock_dpm_levels);
> int i, now, size = 0;
> uint32_t clock, pcie_speed;
>
> @@ -4409,6 +4412,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> (pcie_table->dpm_levels[i].value == 
> 2) ? "8.0GT/s, x16" : "",
> (i == now) ? "*" : "");
> break;
> +   case OD_SCLK:
> +   if (hwmgr->od_enabled) {
> +   size = sprintf(buf, "%s: \n", "OD_SCLK");
> +   for (i = 0; i < odn_sclk_table->num_of_pl; i++)
> +   size += sprintf(buf + size, "%d: %10uMhz %10u 
> mV\n",
> +   i, odn_sclk_table->entries[i].clock / 
> 100,
> +   odn_sclk_table->entries[i].vddc);
> +   }
> +   break;
> +   case OD_MCLK:
> +   if (hwmgr->od_enabled) {
> +   size = sprintf(buf, "%s: \n", "OD_MCLK");
> +   for (i = 0; i < odn_mclk_table->num_of_pl; i++)
> +   size += sprintf(buf + size, "%d: %10uMhz %10u 
> mV\n",
> +   i, odn_mclk_table->entries[i].clock / 
> 100,
> +   odn_mclk_table->entries[i].vddc);
> +   }
> +   break;
> default:
> break;
> }
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu
> clock and voltage through sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher 
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 3 +++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 6 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 2 ++
>  5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e679bb8..508a254 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -120,7 +120,7 @@
>  uint amdgpu_sdma_phase_quantum = 32;
>  char *amdgpu_disable_cu = NULL;
>  char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0x;
> +uint amdgpu_pp_feature_mask = 0x2fff;

Setting the feature mask to 0x2fff unsets PP_SOCCLK_DPM_MASK.
Probably not intended.  I think you want 0x3fff.

Alex

>  int amdgpu_ngg = 0;
>  int amdgpu_prim_buf_per_se = 0;
>  int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index e35bdc5..ebfbbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_CAC);
> }
>
> +   if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
> +   hwmgr->od_enabled = true;
> +
> return 0;
>  }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 6f053fa..ce74e06 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3572,8 +3572,7 @@ static int 
> smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->sclk_table.dpm_levels
> [dpm_table->sclk_table.count - 1].value = sclk;
>
> -   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinACSupport) ||
> -   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinDCSupport)) {
> +   if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
>  * as the Heatmap GPU Clock axis is also based on the default 
> values
>  */
> @@ -3618,8 +3617,7 @@ static int 
> smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->mclk_table.dpm_levels
> [dpm_table->mclk_table.count - 1].value = mclk;
>
> -   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinACSupport) ||
> -   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
> PHM_PlatformCaps_OD6PlusinDCSupport)) {
> +   if (hwmgr->od_enabled) {
>
> PP_ASSERT_WITH_CODE(
> 
> (golden_dpm_table->mclk_table.dpm_levels
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index fadbc8a..12a31d1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3396,8 +3396,7 @@ static int 
> vega10_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->
> 
> gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
> value = sclk;
> -   if 
> (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> -   
> PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> +   if (hwmgr->od_enabled) {
> /* Need to do calculation based on 
> the golden DPM table
>  * as the Heatmap GPU Clock axis is 
> also based on
>  * the default values
> @@ -3451,9 +3450,7 @@ static int 
> vega10_populate_and_upload_sclk_mclk_dpm_levels(
> mem_table.dpm_levels[dpm_table->mem_table.count - 1].
> value = mclk;
>
> -   if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> -   PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> -
> +   if (hwmgr->od_enabled) {
> PP_ASSERT_WITH_CODE(
> golden_dpm_table->mem_table.dpm_levels
>   

Re: [PATCH 6/8] drm/amd/pp: Update avfs voltage when set power state

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> when Over-driver engine clock and voltage were set,
> need to recalculate AVFS voltage on VI asics.
>
> Change-Id: If2a2226d64c0c2aa37c2e84f36b0dad8b7dee25e
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 80 
> ++
>  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h |  1 +
>  2 files changed, 53 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index a0007a8..c69749d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
> DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
>  };
>
> -static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
>  static const unsigned long PhwVIslands_Magic = (unsigned 
> long)(PHM_VIslands_Magic);
>  static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
> enum pp_clock_type type, uint32_t mask);
> @@ -1351,6 +1350,53 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr 
> *hwmgr)
> return 0;
>  }
>
> +static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
> +{
> +   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
> *)(hwmgr->smu_backend);
> +
> +   if (smu_data == NULL)
> +   return -EINVAL;
> +
> +   if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> +   return 0;
> +
> +   if (enable) {
> +   if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> +   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
> +   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> +   hwmgr, PPSMC_MSG_EnableAvfs),
> +   "Failed to enable AVFS!",
> +   return -EINVAL);
> +   }
> +   } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> +   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
> +   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> +   hwmgr, PPSMC_MSG_DisableAvfs),
> +   "Failed to disable AVFS!",
> +   return -EINVAL);
> +   }
> +
> +   return 0;
> +}
> +
> +static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
> +{
> +   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
> *)(hwmgr->smu_backend);
> +
> +   if (smu_data == NULL)
> +   return -EINVAL;
> +
> +   if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> +   return 0;
> +
> +   if (smu_data->avfs.brecalculate_avfs) {
> +   smu7_avfs_control(hwmgr, false);
> +   smu7_avfs_control(hwmgr, true);
> +   smu_data->avfs.brecalculate_avfs = true;

do we need to set brecalculate_avfs here?  Won't it effectively be set
permanently at this point?  When does the driver ever set
brecalculate_avfs to false?

Alex

> +   }
> +   return 0;
> +}
> +
>  int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
>  {
> int tmp_result, result = 0;
> @@ -3923,6 +3969,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr 
> *hwmgr, const void *input)
> "Failed to populate and upload SCLK MCLK DPM levels!",
> result = tmp_result);
>
> +   tmp_result = smu7_update_avfs(hwmgr);
> +   PP_ASSERT_WITH_CODE((0 == tmp_result),
> +   "Failed to update avfs voltages!",
> +   result = tmp_result);
> +
> tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
> PP_ASSERT_WITH_CODE((0 == tmp_result),
> "Failed to generate DPM level enabled mask!",
> @@ -4704,33 +4755,6 @@ static int smu7_set_power_profile_state(struct 
> pp_hwmgr *hwmgr,
> return result;
>  }
>
> -static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
> -{
> -   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
> *)(hwmgr->smu_backend);
> -
> -   if (smu_data == NULL)
> -   return -EINVAL;
> -
> -   if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> -   return 0;
> -
> -   if (enable) {
> -   if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> -   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
> -   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> -   hwmgr, PPSMC_MSG_EnableAvfs),
> -   "Failed to enable AVFS!",
> -   return -EINVAL);
> -   } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> -   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
> -   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> -

Re: [PATCH 1/2] drm/amdgpu: fix CPU based VM updates

[Felix Kuehling]

Thanks for taking care of this. Patch 2 is a nice simplification that
should reduce the chances of breaking CPU updates in the future. The
series is Reviewed-by: Felix Kuehling 

Regards,
  Felix


On 2018-01-16 10:56 AM, Christian König wrote:
> That got accidentially removed.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +-
>  1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index d75637f02ef4..155e6f915964 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -969,12 +969,16 @@ static void amdgpu_vm_handle_huge_pages(struct 
> amdgpu_pte_update_params *p,
>   entry->huge = true;
>   amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
>  
> - if (parent->base.bo->shadow) {
> - pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
> - pde = pd_addr + (entry - parent->entries) * 8;
> - p->func(p, pde, dst, 1, 0, flags);
> + if (p->func == amdgpu_vm_cpu_set_ptes) {
> + pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
> + } else {
> + if (parent->base.bo->shadow) {
> + pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
> + pde = pd_addr + (entry - parent->entries) * 8;
> + p->func(p, pde, dst, 1, 0, flags);
> + }
> + pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
>   }
> - pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
>   pde = pd_addr + (entry - parent->entries) * 8;
>   p->func(p, pde, dst, 1, 0, flags);
>  }

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 7/8] drm/amd/pp: Implement edit_dpm_table on smu7

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu  wrote:
> Change-Id: I301be04db3c56e16e2c10091016efa5439fbc744
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 104 
> ++-
>  1 file changed, 103 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index c69749d..8dbec14 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4834,6 +4834,108 @@ static int smu7_get_thermal_temperature_range(struct 
> pp_hwmgr *hwmgr,
> return 0;
>  }
>
> +static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
> +   enum PHM_ODN_DPM_TABLE_TYPE type,
> +   uint32_t clk,
> +   uint32_t voltage)
> +{
> +   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> +   if (hwmgr->dyn_state.max_clock_voltage_on_ac.vddc * 120 / 100 < 
> voltage)
> +   return false;
> +
> +   if (type == PHM_ODN_SCLK_VDDC_TABLE) {
> +   if (data->vbios_boot_state.sclk_bootup_value > clk ||
> +   hwmgr->dyn_state.max_clock_voltage_on_ac.sclk * 120 / 
> 100 < clk)
> +   return false;
> +   } else if (type == PHM_ODN_MCLK_VDDC_TABLE) {
> +   if (data->vbios_boot_state.mclk_bootup_value > clk ||
> +   hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * 120 / 
> 100 < clk)
> +   return false;
> +   } else {
> +   return false;
> +   }
> +
> +   return true;
> +}
> +
> +static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
> +   enum PHM_ODN_DPM_TABLE_TYPE type,
> +   long *input, uint32_t size)
> +{
> +   uint32_t i;
> +   const phm_ppt_v1_clock_voltage_dependency_table 
> *pgolden_vdd_dep_table = NULL;
> +   struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
> +   struct smu7_odn_clock_voltage_dependency_table 
> *podn_vdd_dep_in_backend = NULL;
> +   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +   struct phm_ppt_v1_information *table_info =
> +   (struct phm_ppt_v1_information *)hwmgr->pptable;
> +   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
> *)(hwmgr->smu_backend);
> +   uint32_t input_clk;
> +   uint32_t input_vol;
> +   uint32_t input_level;
> +
> +   PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
> +   return -EINVAL);
> +
> +   if (PHM_ODN_SCLK_VDDC_TABLE == type) {
> +   podn_dpm_table_in_backend = 
> &data->odn_dpm_table.odn_core_clock_dpm_levels;
> +   podn_vdd_dep_in_backend = 
> &data->odn_dpm_table.vdd_dependency_on_sclk;
> +   PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && 
> podn_vdd_dep_in_backend),
> +   "Failed to get ODN SCLK and Voltage tables",
> +   return -EINVAL);
> +   data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
> +   } else if (PHM_ODN_MCLK_VDDC_TABLE == type) {
> +   podn_dpm_table_in_backend = 
> &data->odn_dpm_table.odn_memory_clock_dpm_levels;
> +   podn_vdd_dep_in_backend = 
> &data->odn_dpm_table.vdd_dependency_on_mclk;
> +
> +   PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && 
> podn_vdd_dep_in_backend),
> +   "Failed to get ODN MCLK and Voltage tables",
> +   return -EINVAL);
> +   data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
> +   } else if (PHM_ODN_RESET_DEFAULT_TABLE == type) {
> +   smu7_odn_initial_default_setting(hwmgr);
> +   data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK | 
> DPMTABLE_UPDATE_MCLK;
> +   smu_data->avfs.brecalculate_avfs = true;
> +   return 0;
> +   } else {
> +   return -EINVAL;
> +   }
> +
> +   if (hwmgr->pp_table_version == PP_TABLE_V1)
> +   pgolden_vdd_dep_table = PHM_ODN_MCLK_VDDC_TABLE == type ?
> +   table_info->vdd_dep_on_mclk:
> +   table_info->vdd_dep_on_sclk;
> +
> +   PP_ASSERT_WITH_CODE(pgolden_vdd_dep_table
> +   && pgolden_vdd_dep_table->count > 0,
> +   "Invalid golden_vdd_dep_table",
> +   return -EINVAL);
> +
> +   for (i = 0; i < size;) {
> +   if (i + 3 > size || input[i] >= 
> podn_dpm_table_in_backend->num_of_pl) {
> +   pr_info("invalid clock voltage input \n");
> +   return 0;
> +   }
> +   i

Re: [PATCH v2 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Felix Kuehling]

On 2018-01-16 10:18 AM, Andrey Grodzovsky wrote:
> Avoid OOM on syatem pages allocations.
>
> v2:
> Remove modeprobe parameter, making this behaviour the only option.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 5c4c3e0..b4dc3bd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device 
> *adev,
>  #endif
>  
>   bo->tbo.bdev = &adev->mman.bdev;
> +
> + /* We opt to avoid OOM on system pages allocations */
> + bo->tbo.bdev->no_retry = true;
> +

Couldn't this be done once in amdgpu_ttm_init just after calling
ttm_bo_device_init? No need to do this for every BO creation.

Regards,
  Felix

>   amdgpu_ttm_placement_from_domain(bo, domain);
>  
>   r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amd/pp: Add stable Pstate clk display support in debugfs

[Alex Deucher]

On Tue, Jan 16, 2018 at 6:59 AM, Rex Zhu  wrote:
> The additional output are: PSTATE_SCLK and PSTATE_MCLK value
> in MHz as:
>
> 300 MHz (PSTATE_SCLK)
> 300 MHz (PSTATE_MCLK)
>
> Change-Id: I96dac70d7e7d9702a5bfc3a40bd9bb57a21abdd7
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  4 
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h |  2 ++
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 23 ++-
>  3 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 662edca..ed9012a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1591,6 +1591,10 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file 
> *m, struct amdgpu_device *a
> seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
> if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void 
> *)&value, &size))
> seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
> +   if (!amdgpu_dpm_read_sensor(adev, 
> AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
> +   seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
> +   if (!amdgpu_dpm_read_sensor(adev, 
> AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
> +   seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
> if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void 
> *)&value, &size))
> seq_printf(m, "\t%u mV (VDDGFX)\n", value);
> if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void 
> *)&value, &size))
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index a823c03..401b895 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -122,6 +122,8 @@ enum amd_pp_sensors {
> AMDGPU_PP_SENSOR_VCE_POWER,
> AMDGPU_PP_SENSOR_UVD_POWER,
> AMDGPU_PP_SENSOR_GPU_POWER,
> +   AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
> +   AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
>  };
>
>  enum amd_pp_task {
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 5e22521..d9cb424 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -992,22 +992,27 @@ static int pp_dpm_read_sensor(void *handle, int idx,
> int ret = 0;
>
> ret = pp_check(pp_handle);
> -
> if (ret)
> return ret;
>
> +   if (value == NULL)
> +   return -EINVAL;
> +
> hwmgr = pp_handle->hwmgr;
>
> -   if (hwmgr->hwmgr_func->read_sensor == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   switch (idx) {
> +   case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
> +   *((uint32_t *)value) = hwmgr->pstate_sclk;
> return 0;
> +   case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
> +   *((uint32_t *)value) = hwmgr->pstate_mclk;
> +   return 0;
> +   default:
> +   mutex_lock(&pp_handle->pp_lock);
> +   ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
> +   mutex_unlock(&pp_handle->pp_lock);
> +   return ret;
> }
> -
> -   mutex_lock(&pp_handle->pp_lock);
> -   ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
> -   mutex_unlock(&pp_handle->pp_lock);
> -
> -   return ret;
>  }
>
>  static struct amd_vce_state*
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/3] drm/amd/pp: Store stable Pstate clocks

[Alex Deucher]

On Tue, Jan 16, 2018 at 6:59 AM, Rex Zhu  wrote:
> User can use to calculate profiling ratios when
> set UMD Pstate.
>
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

>
> Change-Id: I3c6b82ebface57eb969d474c57149e8658ab7014
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c |  2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c |  3 +++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 14 --
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  5 +
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 ++
>  5 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index e574af1..f68dd08 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1189,6 +1189,8 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr 
> *hwmgr)
>
> cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
> cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
> +   hwmgr->pstate_sclk = table->entries[0].clk;
> +   hwmgr->pstate_mclk = 0;
>
> level = cz_get_max_sclk_level(hwmgr) - 1;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index 569073e..409a56b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -451,6 +451,9 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>
> hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
>
> +   hwmgr->pstate_sclk = RAVEN_UMD_PSTATE_GFXCLK;
> +   hwmgr->pstate_mclk = RAVEN_UMD_PSTATE_FCLK;
> +
> return result;
>  }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index b60e50e..11a900b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2579,8 +2579,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr 
> *hwmgr, enum amd_dpm_forced_le
> break;
> }
> }
> -   if (count < 0 || level == 
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> +   if (count < 0 || level == 
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
> *sclk_mask = 0;
> +   tmp_sclk = 
> hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
> +   }
>
> if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> *sclk_mask = 
> hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
> @@ -2595,8 +2597,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr 
> *hwmgr, enum amd_dpm_forced_le
> break;
> }
> }
> -   if (count < 0 || level == 
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> +   if (count < 0 || level == 
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
> *sclk_mask = 0;
> +   tmp_sclk =  
> table_info->vdd_dep_on_sclk->entries[0].clk;
> +   }
>
> if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
> @@ -2608,6 +2612,9 @@ static int smu7_get_profiling_clk(struct pp_hwmgr 
> *hwmgr, enum amd_dpm_forced_le
> *mclk_mask = golden_dpm_table->mclk_table.count - 1;
>
> *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
> +   hwmgr->pstate_sclk = tmp_sclk;
> +   hwmgr->pstate_mclk = tmp_mclk;
> +
> return 0;
>  }
>
> @@ -2619,6 +2626,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
> uint32_t mclk_mask = 0;
> uint32_t pcie_mask = 0;
>
> +   if (hwmgr->pstate_sclk == 0)
> +   smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, 
> &pcie_mask);
> +
> switch (level) {
> case AMD_DPM_FORCED_LEVEL_HIGH:
> ret = smu7_force_dpm_highest(hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index d5abd46..adfbbc1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4178,6 +4178,8 @@ static int vega10_get_profiling_clk_mask(struct 
> pp_hwmgr *hwmgr, enum amd_dpm_fo
> *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
> *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
> *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
> +   hwmgr->pstate_sclk = 
> table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
> +   hwmgr->pstate_mclk = 
> table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
>  

Re: [PATCH 2/3] drm/amd/pp: Add stable Pstate clk display when print_clock_levels

[Alex Deucher]

On Tue, Jan 16, 2018 at 6:59 AM, Rex Zhu  wrote:
> The additional output are at the end of sclk/mclk info as
> cat pp_dpm_mclk
> 0: 300Mhz *
> 1: 1650Mhz
> P: 300Mhz
>
> Signed-off-by: Rex Zhu 

I'm not crazy about this patch.  I think it conflates things and
breaks older versions of the rocm smi tool.  I'd prefer to add a new
file for the pstate clocks or add a query to the amdgpu INFO ioctl to
fetch them.

Alex


>
> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>  4 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index f68dd08..03dfba0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, sclk_table->entries[i].clk / 100,
> (i == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> CZ_NUM_NBPMEMORYCLOCK-i, 
> data->sys_info.nbp_memory_clock[i-1] / 100,
> (CZ_NUM_NBPMEMORYCLOCK-i == now) ? 
> "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> hwmgr->pstate_mclk/100);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index 409a56b..88c6ad8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
> data->gfx_max_freq_limit / 100,
> ((data->gfx_max_freq_limit / 100)
>  == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
> mclk_table->entries[i].clk / 100,
> ((mclk_table->entries[i].clk / 100)
>  == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> hwmgr->pstate_mclk/100);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 11a900b..6f053fa 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4301,6 +4301,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, sclk_table->dpm_levels[i].value / 
> 100,
> (i == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
> @@ -4317,6 +4318,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, mclk_table->dpm_levels[i].value / 
> 100,
> (i == now) ? "*" : "");
> +   size += sprintf(buf + size, "P: %uMhz\n", 
> hwmgr->pstate_mclk/100);
> break;
> case PP_PCIE:
> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index adfbbc1..d646b27b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4571,6 +4571,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
>   

Re: [PATCH 2/2] drm/amd/pp: Add custom power profile mode support on Vega10

[Alex Deucher]

On Tue, Jan 16, 2018 at 6:50 AM, Rex Zhu  wrote:
> v2: delete uncessary blank line.
> Add static const modifiers to an array
>
> Signed-off-by: Rex Zhu 
>
> Change-Id: If6b81ade742ef434717010ca0783d2af9145c975

Reviewed-by: Alex Deucher 

Do you have a similar patch for smu7 yet?


> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 38 +++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 78 
> ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 +
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  3 +
>  4 files changed, 120 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 8859b67..5e22521 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1081,6 +1081,42 @@ static int pp_dpm_get_power_profile_state(void *handle,
> return 0;
>  }
>
> +static int pp_get_power_profile_mode(void *handle, char *buf)
> +{
> +   struct pp_hwmgr *hwmgr;
> +   struct pp_instance *pp_handle = (struct pp_instance *)handle;
> +
> +   if (!buf || pp_check(pp_handle))
> +   return -EINVAL;
> +
> +   hwmgr = pp_handle->hwmgr;
> +
> +   if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
> +   pr_info("%s was not implemented.\n", __func__);
> +   return snprintf(buf, PAGE_SIZE, "\n");
> +   }
> +
> +   return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
> +}
> +
> +static int pp_set_power_profile_mode(void *handle, long *input, uint32_t 
> size)
> +{
> +   struct pp_hwmgr *hwmgr;
> +   struct pp_instance *pp_handle = (struct pp_instance *)handle;
> +
> +   if (pp_check(pp_handle))
> +   return -EINVAL;
> +
> +   hwmgr = pp_handle->hwmgr;
> +
> +   if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> +   pr_info("%s was not implemented.\n", __func__);
> +   return -EINVAL;
> +   }
> +
> +   return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
> +}
> +
>  static int pp_dpm_set_power_profile_state(void *handle,
> struct amd_pp_profile *request)
>  {
> @@ -1464,6 +1500,8 @@ static int pp_get_display_mode_validation_clocks(void 
> *handle,
> .switch_power_profile = pp_dpm_switch_power_profile,
> .set_clockgating_by_smu = pp_set_clockgating_by_smu,
> .notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
> +   .get_power_profile_mode = pp_get_power_profile_mode,
> +   .set_power_profile_mode = pp_set_power_profile_mode,
>  /* export to DC */
> .get_sclk = pp_dpm_get_sclk,
> .get_mclk = pp_dpm_get_mclk,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 7e6feed..d5abd46 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -760,6 +760,8 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr 
> *hwmgr)
>
> hwmgr->backend = data;
>
> +   hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
> +
> vega10_set_default_registry_data(hwmgr);
>
> data->disable_dpm_mask = 0xff;
> @@ -3963,6 +3965,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, 
> int idx,
> ret = -EINVAL;
> break;
> }
> +
> return ret;
>  }
>
> @@ -5021,6 +5024,79 @@ static int vega10_register_thermal_interrupt(struct 
> pp_hwmgr *hwmgr,
> return 0;
>  }
>
> +static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
> +{
> +   struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
> +   uint32_t i, size = 0;
> +   static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
> +   {90, 60, 0, 0,},
> +   {70, 60, 0, 0,},
> +   {70, 90, 0, 0,},
> +   {30, 60, 0, 6,},
> +   };
> +   static const char *profile_name[6] = {"3D_FULL_SCREEN",
> +   "POWER_SAVING",
> +   "VIDEO",
> +   "VR",
> +   "COMPUTER",
> +   "CUSTOM"};
> +   static const char *title[6] = {"NUM",
> +   "MODE_NAME",
> +   "BUSY_SET_POINT",
> +   "FPS",
> +   "USE_RLC_BUSY",
> +   "MIN_ACTIVE_LEVEL"};
> +
> +   if (!buf)
> +   return -EINVAL;
> +
> +   size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
> +   title[1], title[2],

Re: [PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs

[Alex Deucher]

On Tue, Jan 16, 2018 at 6:50 AM, Rex Zhu  wrote:
> when cat pp_power_profile_mode on Vega10
> NUMMODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL
>   0 3D_FULL_SCREEN : 70  60  1  3
>   1   POWER_SAVING : 90  60  0  0
>   2  VIDEO*: 70  60  0  0
>   3 VR : 70  90  0  0
>   4   COMPUTER : 30  60  0  6
>   5 CUSTOM :  0   0  0  0
>
> the result show all the profile mode we can support and custom mode.
> user can echo the num(0-4) to pp_power_profile_mode to select the profile
> mode or can echo "5 value value value value" to enter CUSTOM mode.
> the four parameter is set_point/FPS/USER_RLC_BUSY/MIN_ACTIVE_LEVEL.
>
> Change-Id: I72634646a9a179ccd57f175b4c0b3f45e538a03f
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  8 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 81 
> +-
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h | 11 +++-
>  3 files changed, 98 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 8a8d09dd..986f1d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -366,6 +366,14 @@ enum amdgpu_pcie_gen {
> (adev)->powerplay.pp_handle, virtual_addr_low, \
> virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
>
> +#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
> +   ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
> +   (adev)->powerplay.pp_handle, buf))
> +
> +#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
> +   ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
> +   (adev)->powerplay.pp_handle, parameter, size))
> +
>  struct amdgpu_dpm {
> struct amdgpu_ps*ps;
> /* number of valid power states */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index e5ee7cf..662edca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -584,6 +584,73 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
> return count;
>  }
>
> +static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
> +   struct device_attribute *attr,
> +   char *buf)
> +{
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +
> +   if (adev->powerplay.pp_funcs->get_power_profile_mode)
> +   return amdgpu_dpm_get_power_profile_mode(adev, buf);
> +
> +   return snprintf(buf, PAGE_SIZE, "\n");
> +}
> +
> +
> +static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
> +   struct device_attribute *attr,
> +   const char *buf,
> +   size_t count)
> +{
> +   int ret = 0xff;
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +   uint32_t parameter_size = 0;
> +   long parameter[64];
> +   char *sub_str, buf_cpy[128];
> +   char *tmp_str;
> +   uint32_t i = 0;
> +   char tmp[2];
> +   long int profile_mode = 0;
> +   const char delimiter[3] = {' ', '\n', '\0'};
> +
> +   tmp[0] = *(buf);
> +   tmp[1] = '\0';
> +   ret = kstrtol(tmp, 0, &profile_mode);
> +   if (ret)
> +   goto fail;
> +
> +   if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> +   if (count < 2 || count > 127)
> +   return -EINVAL;
> +   while (isspace(*++buf))
> +   i++;
> +   memcpy(buf_cpy, buf, count-i);
> +   tmp_str = buf_cpy;
> +   while (tmp_str[0]) {
> +   sub_str = strsep(&tmp_str, delimiter);
> +   ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
> +   if (ret) {
> +   count = -EINVAL;
> +   goto fail;
> +   }
> +   pr_info("value is %ld \n", parameter[parameter_size]);
> +   parameter_size++;
> +   while (isspace(*tmp_str))
> +   tmp_str++;
> +   }
> +   }
> +   parameter[parameter_size] = profile_mode;
> +   if (adev->powerplay.pp_funcs->set_power_profile_mode)
> +   ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, 
> parameter_size);
> +
> +   if (!ret)
> +   return count;
> +fail:
> +   return -EINVAL;
> +}
> +
>  static ssize_t amdgpu_get_pp_power_profile(struct 

[PATCH 2/2] drm/amdgpu: move PD/PT address calculation into backend function

[Christian König]

This way we can better handle the differences for CPU based updates.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 79 +-
 1 file changed, 29 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 155e6f915964..c008d27c94a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -75,7 +75,8 @@ struct amdgpu_pte_update_params {
/* indirect buffer to fill with commands */
struct amdgpu_ib *ib;
/* Function which actually does the update */
-   void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
+   void (*func)(struct amdgpu_pte_update_params *params,
+struct amdgpu_bo *bo, uint64_t pe,
 uint64_t addr, unsigned count, uint32_t incr,
 uint64_t flags);
/* The next two are used during VM update by CPU
@@ -578,6 +579,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
  * amdgpu_vm_do_set_ptes - helper to call the right asic function
  *
  * @params: see amdgpu_pte_update_params definition
+ * @bo: PD/PT to update
  * @pe: addr of the page entry
  * @addr: dst addr to write into pe
  * @count: number of page entries to update
@@ -588,10 +590,12 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm 
*vm,
  * to setup the page table using the DMA.
  */
 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
+ struct amdgpu_bo *bo,
  uint64_t pe, uint64_t addr,
  unsigned count, uint32_t incr,
  uint64_t flags)
 {
+   pe += amdgpu_bo_gpu_offset(bo);
trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
 
if (count < 3) {
@@ -608,6 +612,7 @@ static void amdgpu_vm_do_set_ptes(struct 
amdgpu_pte_update_params *params,
  * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
  *
  * @params: see amdgpu_pte_update_params definition
+ * @bo: PD/PT to update
  * @pe: addr of the page entry
  * @addr: dst addr to write into pe
  * @count: number of page entries to update
@@ -617,13 +622,14 @@ static void amdgpu_vm_do_set_ptes(struct 
amdgpu_pte_update_params *params,
  * Traces the parameters and calls the DMA function to copy the PTEs.
  */
 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
+  struct amdgpu_bo *bo,
   uint64_t pe, uint64_t addr,
   unsigned count, uint32_t incr,
   uint64_t flags)
 {
uint64_t src = (params->src + (addr >> 12) * 8);
 
-
+   pe += amdgpu_bo_gpu_offset(bo);
trace_amdgpu_vm_copy_ptes(pe, src, count);
 
amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
@@ -657,6 +663,7 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t 
*pages_addr, uint64_t addr)
  * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
  *
  * @params: see amdgpu_pte_update_params definition
+ * @bo: PD/PT to update
  * @pe: kmap addr of the page entry
  * @addr: dst addr to write into pe
  * @count: number of page entries to update
@@ -666,6 +673,7 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t 
*pages_addr, uint64_t addr)
  * Write count number of PT/PD entries directly.
  */
 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
+  struct amdgpu_bo *bo,
   uint64_t pe, uint64_t addr,
   unsigned count, uint32_t incr,
   uint64_t flags)
@@ -673,6 +681,8 @@ static void amdgpu_vm_cpu_set_ptes(struct 
amdgpu_pte_update_params *params,
unsigned int i;
uint64_t value;
 
+   pe += (unsigned long)amdgpu_bo_kptr(bo);
+
trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
 
for (i = 0; i < count; i++) {
@@ -714,8 +724,7 @@ static void amdgpu_vm_update_pde(struct 
amdgpu_pte_update_params *params,
 struct amdgpu_vm_pt *parent,
 struct amdgpu_vm_pt *entry)
 {
-   struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL, *pbo;
-   uint64_t pd_addr, shadow_addr = 0;
+   struct amdgpu_bo *bo = parent->base.bo, *pbo;
uint64_t pde, pt, flags;
unsigned level;
 
@@ -723,29 +732,17 @@ static void amdgpu_vm_update_pde(struct 
amdgpu_pte_update_params *params,
if (entry->huge)
return;
 
-   if (vm->use_cpu_for_update) {
-   pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
-   } else {
-   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
-   shadow = parent->base.bo->shadow;
-   if (shadow)
-

[PATCH 1/2] drm/amdgpu: fix CPU based VM updates

[Christian König]

That got accidentially removed.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d75637f02ef4..155e6f915964 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -969,12 +969,16 @@ static void amdgpu_vm_handle_huge_pages(struct 
amdgpu_pte_update_params *p,
entry->huge = true;
amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
 
-   if (parent->base.bo->shadow) {
-   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
-   pde = pd_addr + (entry - parent->entries) * 8;
-   p->func(p, pde, dst, 1, 0, flags);
+   if (p->func == amdgpu_vm_cpu_set_ptes) {
+   pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
+   } else {
+   if (parent->base.bo->shadow) {
+   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
+   pde = pd_addr + (entry - parent->entries) * 8;
+   p->func(p, pde, dst, 1, 0, flags);
+   }
+   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
}
-   pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
pde = pd_addr + (entry - parent->entries) * 8;
p->func(p, pde, dst, 1, 0, flags);
 }
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/pp: Refine code abbreviate variable name

[Alex Deucher]

On Tue, Jan 16, 2018 at 7:00 AM, Rex Zhu  wrote:
> abbreviate variable name number_of_performance_levels
> to num_of_pl in struct phm_odn_clock_levels
>
> Change-Id: I132c59dfd28933c4f6eba74fa53ffd0d014ec354
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c  | 8 
>  drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index d646b27b..fadbc8a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -1386,8 +1386,8 @@ static int vega10_setup_default_dpm_tables(struct 
> pp_hwmgr *hwmgr)
>
> if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
> PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
> -   data->odn_dpm_table.odn_core_clock_dpm_levels.
> -   number_of_performance_levels = 
> data->dpm_table.gfx_table.count;
> +   data->odn_dpm_table.odn_core_clock_dpm_levels.num_of_pl =
> +   
> data->dpm_table.gfx_table.count;
> for (i = 0; i < data->dpm_table.gfx_table.count; i++) {
> 
> data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].clock =
> 
> data->dpm_table.gfx_table.dpm_levels[i].value;
> @@ -1407,8 +1407,8 @@ static int vega10_setup_default_dpm_tables(struct 
> pp_hwmgr *hwmgr)
> dep_gfx_table->entries[i].cks_voffset;
> }
>
> -   data->odn_dpm_table.odn_memory_clock_dpm_levels.
> -   number_of_performance_levels = 
> data->dpm_table.mem_table.count;
> +   data->odn_dpm_table.odn_memory_clock_dpm_levels.num_of_pl =
> +   
> data->dpm_table.mem_table.count;
> for (i = 0; i < data->dpm_table.mem_table.count; i++) {
> 
> data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].clock =
> 
> data->dpm_table.mem_table.dpm_levels[i].value;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index 933aa44..d6772a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -368,8 +368,8 @@ struct phm_odn_clock_levels {
> uint32_t size;
> uint32_t options;
> uint32_t flags;
> -   uint32_t number_of_performance_levels;
> -   /* variable-sized array, specify by ulNumberOfPerformanceLevels. */
> +   uint32_t num_of_pl;
> +   /* variable-sized array, specify by num_of_pl. */
> struct phm_odn_performance_level entries[8];
>  };
>
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 5/5] drm/amd/pp: Fix SMIO implementation on CI

[Alex Deucher]

On Tue, Jan 16, 2018 at 6:18 AM, Rex Zhu  wrote:
> Setup smio table(smio registers's address and voltage ID)
> for various voltage domain.
>
> Change-Id: I14be46053ffb2954c1533f4e67d3b0632107af7a
> Reviewed-by: Alex Deucher 
> Signed-off-by: Rex Zhu 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 31 
> +++-
>  1 file changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> index 03b5f10..98be127 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> @@ -860,10 +860,13 @@ static int ci_populate_smc_vddc_table(struct pp_hwmgr 
> *hwmgr,
> PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC 
> voltage table", return -EINVAL);
>
> /* GPIO voltage control */
> -   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
> -   table->VddcLevel[count].Smio |= 
> data->vddc_voltage_table.entries[count].smio_low;
> -   else
> +   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
> +   table->VddcLevel[count].Smio = (uint8_t) count;
> +   table->Smio[count] |= 
> data->vddc_voltage_table.entries[count].smio_low;
> +   table->SmioMaskVddcVid |= 
> data->vddc_voltage_table.entries[count].smio_low;
> +   } else {
> table->VddcLevel[count].Smio = 0;
> +   }
> }
>
> CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
> @@ -885,10 +888,13 @@ static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr 
> *hwmgr,
> &(data->vddci_voltage_table.entries[count]),
> &(table->VddciLevel[count]));
> PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI 
> voltage table", return -EINVAL);
> -   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
> -   table->VddciLevel[count].Smio |= 
> data->vddci_voltage_table.entries[count].smio_low;
> -   else
> -   table->VddciLevel[count].Smio |= 0;
> +   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
> +   table->VddciLevel[count].Smio = (uint8_t) count;
> +   table->Smio[count] |= 
> data->vddci_voltage_table.entries[count].smio_low;
> +   table->SmioMaskVddciVid |= 
> data->vddci_voltage_table.entries[count].smio_low;
> +   } else {
> +   table->VddciLevel[count].Smio = 0;
> +   }
> }
>
> CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
> @@ -910,10 +916,13 @@ static int ci_populate_smc_mvdd_table(struct pp_hwmgr 
> *hwmgr,
> &(data->mvdd_voltage_table.entries[count]),
> &table->MvddLevel[count]);
> PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd 
> voltage table", return -EINVAL);
> -   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
> -   table->MvddLevel[count].Smio |= 
> data->mvdd_voltage_table.entries[count].smio_low;
> -   else
> -   table->MvddLevel[count].Smio |= 0;
> +   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
> +   table->MvddLevel[count].Smio = (uint8_t) count;
> +   table->Smio[count] |= 
> data->mvdd_voltage_table.entries[count].smio_low;
> +   table->SmioMaskMvddVid |= 
> data->mvdd_voltage_table.entries[count].smio_low;
> +   } else {
> +   table->MvddLevel[count].Smio = 0;
> +   }
> }
>
> CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm: amd: dc: don't use FP math when Kcov is enabled

[Arnd Bergmann]

On Tue, Dec 5, 2017 at 6:01 PM, Harry Wentland  wrote:
>>
>
> Thanks, Arnd. This is what I was missing. I'll take another look.
>
> It would still work without KCOV, although I agree that's not ideal by any 
> means.

Any update on this? I see building DCN1.0 with KCOV using gcc-8 is still broken.

   Arnd
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 1/2] drm/ttm: Allow page allocations w/o triggering OOM..

[Christian König]

Am 16.01.2018 um 16:18 schrieb Andrey Grodzovsky:

This to allow drivers to choose to avoid OOM invocation and handle
page allocation failures instead.

v2:
Remove extra new lines.

Signed-off-by: Andrey Grodzovsky 


Reviewed-by: Christian König  for the series.


---
  drivers/gpu/drm/ttm/ttm_bo.c |  3 +++
  drivers/gpu/drm/ttm/ttm_page_alloc.c |  6 ++
  drivers/gpu/drm/ttm/ttm_page_alloc_dma.c |  3 +++
  drivers/gpu/drm/ttm/ttm_tt.c | 13 +++--
  include/drm/ttm/ttm_bo_driver.h  |  4 
  5 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2eb71ff..f32aab1 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -234,6 +234,9 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, 
bool zero_alloc)
if (bdev->need_dma32)
page_flags |= TTM_PAGE_FLAG_DMA32;
  
+	if (bdev->no_retry)

+   page_flags |= TTM_PAGE_FLAG_NO_RETRY;
+
switch (bo->type) {
case ttm_bo_type_device:
if (zero_alloc)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 0eab24e..f34c843 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -741,6 +741,9 @@ static int ttm_page_pool_get_pages(struct ttm_page_pool 
*pool,
if (ttm_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
  
+		if (ttm_flags & TTM_PAGE_FLAG_NO_RETRY)

+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
/* ttm_alloc_new_pages doesn't reference pool so we can run
 * multiple requests in parallel.
 **/
@@ -893,6 +896,9 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
if (flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
  
+		if (flags & TTM_PAGE_FLAG_NO_RETRY)

+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
if (flags & TTM_PAGE_FLAG_DMA32)
gfp_flags |= GFP_DMA32;
else
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index c7f01a4..6949ef7 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -920,6 +920,9 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt 
*ttm_dma, bool huge)
gfp_flags &= ~__GFP_COMP;
}
  
+	if (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY)

+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
return gfp_flags;
  }
  
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c

index 5a046a3..9e4d43d 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -301,7 +301,11 @@ int ttm_tt_swapin(struct ttm_tt *ttm)
swap_space = swap_storage->f_mapping;
  
  	for (i = 0; i < ttm->num_pages; ++i) {

-   from_page = shmem_read_mapping_page(swap_space, i);
+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ? 
__GFP_RETRY_MAYFAIL : 0);
+   from_page = shmem_read_mapping_page_gfp(swap_space, i, 
gfp_mask);
+
if (IS_ERR(from_page)) {
ret = PTR_ERR(from_page);
goto out_err;
@@ -350,10 +354,15 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file 
*persistent_swap_storage)
swap_space = swap_storage->f_mapping;
  
  	for (i = 0; i < ttm->num_pages; ++i) {

+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ? 
__GFP_RETRY_MAYFAIL : 0);
+
from_page = ttm->pages[i];
if (unlikely(from_page == NULL))
continue;
-   to_page = shmem_read_mapping_page(swap_space, i);
+
+   to_page = shmem_read_mapping_page_gfp(swap_space, i, gfp_mask);
if (IS_ERR(to_page)) {
ret = PTR_ERR(to_page);
goto out_err;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 94064b1..9b417eb 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -86,6 +86,7 @@ struct ttm_backend_func {
  #define TTM_PAGE_FLAG_ZERO_ALLOC  (1 << 6)
  #define TTM_PAGE_FLAG_DMA32   (1 << 7)
  #define TTM_PAGE_FLAG_SG  (1 << 8)
+#define TTM_PAGE_FLAG_NO_RETRY(1 << 9)
  
  enum ttm_caching_state {

tt_uncached,
@@ -556,6 +557,7 @@ struct ttm_bo_global {
   * @dev_mapping: A pointer to the struct address_space representing the
   * device address space.
   * @wq: Work queue structure for the delayed delete workqueue.
+ * @no_retry: Don't retry allocation if it fails
   *
   */
  
@@ -592,6 +594,8 @@ stru

[PATCH v2 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Andrey Grodzovsky]

Avoid OOM on syatem pages allocations.

v2:
Remove modeprobe parameter, making this behaviour the only option.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5c4c3e0..b4dc3bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 #endif
 
bo->tbo.bdev = &adev->mman.bdev;
+
+   /* We opt to avoid OOM on system pages allocations */
+   bo->tbo.bdev->no_retry = true;
+
amdgpu_ttm_placement_from_domain(bo, domain);
 
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 1/2] drm/ttm: Allow page allocations w/o triggering OOM..

[Andrey Grodzovsky]

This to allow drivers to choose to avoid OOM invocation and handle
page allocation failures instead.

v2:
Remove extra new lines.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/ttm/ttm_bo.c |  3 +++
 drivers/gpu/drm/ttm/ttm_page_alloc.c |  6 ++
 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c |  3 +++
 drivers/gpu/drm/ttm/ttm_tt.c | 13 +++--
 include/drm/ttm/ttm_bo_driver.h  |  4 
 5 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2eb71ff..f32aab1 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -234,6 +234,9 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, 
bool zero_alloc)
if (bdev->need_dma32)
page_flags |= TTM_PAGE_FLAG_DMA32;
 
+   if (bdev->no_retry)
+   page_flags |= TTM_PAGE_FLAG_NO_RETRY;
+
switch (bo->type) {
case ttm_bo_type_device:
if (zero_alloc)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 0eab24e..f34c843 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -741,6 +741,9 @@ static int ttm_page_pool_get_pages(struct ttm_page_pool 
*pool,
if (ttm_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
 
+   if (ttm_flags & TTM_PAGE_FLAG_NO_RETRY)
+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
/* ttm_alloc_new_pages doesn't reference pool so we can run
 * multiple requests in parallel.
 **/
@@ -893,6 +896,9 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
if (flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
 
+   if (flags & TTM_PAGE_FLAG_NO_RETRY)
+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
if (flags & TTM_PAGE_FLAG_DMA32)
gfp_flags |= GFP_DMA32;
else
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index c7f01a4..6949ef7 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -920,6 +920,9 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt 
*ttm_dma, bool huge)
gfp_flags &= ~__GFP_COMP;
}
 
+   if (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY)
+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
return gfp_flags;
 }
 
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 5a046a3..9e4d43d 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -301,7 +301,11 @@ int ttm_tt_swapin(struct ttm_tt *ttm)
swap_space = swap_storage->f_mapping;
 
for (i = 0; i < ttm->num_pages; ++i) {
-   from_page = shmem_read_mapping_page(swap_space, i);
+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ? 
__GFP_RETRY_MAYFAIL : 0);
+   from_page = shmem_read_mapping_page_gfp(swap_space, i, 
gfp_mask);
+
if (IS_ERR(from_page)) {
ret = PTR_ERR(from_page);
goto out_err;
@@ -350,10 +354,15 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file 
*persistent_swap_storage)
swap_space = swap_storage->f_mapping;
 
for (i = 0; i < ttm->num_pages; ++i) {
+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ? 
__GFP_RETRY_MAYFAIL : 0);
+
from_page = ttm->pages[i];
if (unlikely(from_page == NULL))
continue;
-   to_page = shmem_read_mapping_page(swap_space, i);
+
+   to_page = shmem_read_mapping_page_gfp(swap_space, i, gfp_mask);
if (IS_ERR(to_page)) {
ret = PTR_ERR(to_page);
goto out_err;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 94064b1..9b417eb 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -86,6 +86,7 @@ struct ttm_backend_func {
 #define TTM_PAGE_FLAG_ZERO_ALLOC  (1 << 6)
 #define TTM_PAGE_FLAG_DMA32   (1 << 7)
 #define TTM_PAGE_FLAG_SG  (1 << 8)
+#define TTM_PAGE_FLAG_NO_RETRY(1 << 9)
 
 enum ttm_caching_state {
tt_uncached,
@@ -556,6 +557,7 @@ struct ttm_bo_global {
  * @dev_mapping: A pointer to the struct address_space representing the
  * device address space.
  * @wq: Work queue structure for the delayed delete workqueue.
+ * @no_retry: Don't retry allocation if it fails
  *
  */
 
@@ -592,6 +594,8 @@ struct ttm_bo_device {
struct delayed_work wq;
 
bool need_dma32;
+
+  

[bug report] drm/amdgpu: rework IP block registration (v2)

[Dan Carpenter]

Hello Alex Deucher,

The patch a12551072126: "drm/amdgpu: rework IP block registration
(v2)" from Oct 13, 2016, leads to the following static checker
warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1504 amdgpu_device_ip_fini()
error: dereferencing freed memory 'adev'

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
  1495  adev->ip_blocks[i].status.sw = false;
  1496  adev->ip_blocks[i].status.valid = false;
  1497  }
  1498  
  1499  for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1500  if (!adev->ip_blocks[i].status.late_initialized)
  1501  continue;
  1502  if (adev->ip_blocks[i].version->funcs->late_fini)
  1503  
adev->ip_blocks[i].version->funcs->late_fini((void *)adev);

The warning is because pp_late_fini() frees the parameter.  The
amdgpu_pp_late_fini() function doesn't so that's a bit weird.

  1504  adev->ip_blocks[i].status.late_initialized = false;
^^^
Dereference.

  1505  }
  1506  

regards,
dan carpenter
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Christian König]

Am 16.01.2018 um 13:43 schrieb Andrey Grodzovsky:



On 01/16/2018 03:54 AM, Christian König wrote:

Am 16.01.2018 um 07:18 schrieb He, Roger:

-Original Message-
From: Andrey Grodzovsky [mailto:andrey.grodzov...@amd.com]
Sent: Saturday, January 13, 2018 6:29 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; He, Roger 
; Grodzovsky, Andrey 
Subject: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM 
triggering.


This to have a load time option to avoid OOM on RAM allocations.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 4 
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
  3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index b7c181e..1387239 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -127,6 +127,7 @@ extern int amdgpu_job_hang_limit;  extern int 
amdgpu_lbpw;  extern int amdgpu_compute_multipipe;  extern int 
amdgpu_gpu_recovery;

+extern int amdgpu_alloc_no_oom;
    #ifdef CONFIG_DRM_AMDGPU_SI
  extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index d96f9ac..6e98189 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -130,6 +130,7 @@ int amdgpu_job_hang_limit = 0;  int amdgpu_lbpw 
= -1;  int amdgpu_compute_multipipe = -1;  int amdgpu_gpu_recovery = 
-1; /* auto */

+int amdgpu_alloc_no_oom = -1; /* auto */

How about turn it on as default?


I think we can even go a step further, drop the module parameter and 
just turn it always on for amdgpu.


Christian.


Will fix, just a reminder that Roger's patches -
[PATCH 1/2] drm/ttm: don't update global memory count for some special 
cases
[PATCH 2/2] drm/ttm: only free pages rather than update global memory 
count together


Needs to be merged before my patches since the fix a TTM bug on 
allocation failure.


The second is merged, but I had some comments on the first and Roger 
hasn't replied yet.


Roger what's the status on that one?

Regards,
Christian.



Thanks,
Andrey





Thanks
Roger(Hongbo.He)

MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in 
megabytes");  module_param_named(vramlimit, amdgpu_vram_limit, int, 
0600); @@ -285,6 +286,9 @@ module_param_named(compute_multipipe, 
amdgpu_compute_multipipe, int, 0444); MODULE_PARM_DESC(gpu_recovery, 
"Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = 
auto"); module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 
0444);

  +MODULE_PARM_DESC(alloc_no_oom, "Allocate RAM without triggering OOM
+killer, (1 = enable, 0 = disable, -1 = auto");
+module_param_named(alloc_no_oom, amdgpu_alloc_no_oom, int, 0444);
+
  #ifdef CONFIG_DRM_AMDGPU_SI
    #if defined(CONFIG_DRM_RADEON) || 
defined(CONFIG_DRM_RADEON_MODULE) diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 5c4c3e0..fc27164 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct 
amdgpu_device *adev,  #endif

    bo->tbo.bdev = &adev->mman.bdev;
+
+    if (amdgpu_alloc_no_oom == 1)
+    bo->tbo.bdev->no_retry = true;
+
  amdgpu_ttm_placement_from_domain(bo, domain);
    r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, 
type,

--
2.7.4

___
dri-devel mailing list
dri-de...@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel




___
dri-devel mailing list
dri-de...@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Andrey Grodzovsky]

On 01/16/2018 03:54 AM, Christian König wrote:

Am 16.01.2018 um 07:18 schrieb He, Roger:

-Original Message-
From: Andrey Grodzovsky [mailto:andrey.grodzov...@amd.com]
Sent: Saturday, January 13, 2018 6:29 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; He, Roger 
; Grodzovsky, Andrey 
Subject: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM 
triggering.


This to have a load time option to avoid OOM on RAM allocations.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 4 
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
  3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index b7c181e..1387239 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -127,6 +127,7 @@ extern int amdgpu_job_hang_limit;  extern int 
amdgpu_lbpw;  extern int amdgpu_compute_multipipe;  extern int 
amdgpu_gpu_recovery;

+extern int amdgpu_alloc_no_oom;
    #ifdef CONFIG_DRM_AMDGPU_SI
  extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index d96f9ac..6e98189 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -130,6 +130,7 @@ int amdgpu_job_hang_limit = 0;  int amdgpu_lbpw = 
-1;  int amdgpu_compute_multipipe = -1;  int amdgpu_gpu_recovery = 
-1; /* auto */

+int amdgpu_alloc_no_oom = -1; /* auto */

How about turn it on as default?


I think we can even go a step further, drop the module parameter and 
just turn it always on for amdgpu.


Christian.


Will fix, just a reminder that Roger's patches -
[PATCH 1/2] drm/ttm: don't update global memory count for some special cases
[PATCH 2/2] drm/ttm: only free pages rather than update global memory 
count together


Needs to be merged before my patches since the fix a TTM bug on 
allocation failure.


Thanks,
Andrey





Thanks
Roger(Hongbo.He)

MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in 
megabytes");  module_param_named(vramlimit, amdgpu_vram_limit, int, 
0600); @@ -285,6 +286,9 @@ module_param_named(compute_multipipe, 
amdgpu_compute_multipipe, int, 0444);  MODULE_PARM_DESC(gpu_recovery, 
"Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = 
auto"); module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 
0444);

  +MODULE_PARM_DESC(alloc_no_oom, "Allocate RAM without triggering OOM
+killer, (1 = enable, 0 = disable, -1 = auto");
+module_param_named(alloc_no_oom, amdgpu_alloc_no_oom, int, 0444);
+
  #ifdef CONFIG_DRM_AMDGPU_SI
    #if defined(CONFIG_DRM_RADEON) || 
defined(CONFIG_DRM_RADEON_MODULE) diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 5c4c3e0..fc27164 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct 
amdgpu_device *adev,  #endif

    bo->tbo.bdev = &adev->mman.bdev;
+
+    if (amdgpu_alloc_no_oom == 1)
+    bo->tbo.bdev->no_retry = true;
+
  amdgpu_ttm_placement_from_domain(bo, domain);
    r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
--
2.7.4

___
dri-devel mailing list
dri-de...@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 8/8] drm/amd/pp: Add edit/show OD clock/voltage support in sysfs

[Rex Zhu]

when cat pp_od_clk_voltage it show
OD_SCLK:
0:300Mhz800 mV
1:466Mhz818 mV
2:751Mhz824 mV
3:   1019Mhz987 mV
4:   1074Mhz   1037 mV
5:   1126Mhz   1087 mV
6:   1169Mhz   1137 mV
7:   1206Mhz   1150 mV
OD_MCLK:
0:300Mhz800 mV
1:   1650Mhz   1000 mV

echo "s/m level clock voltage" to change
sclk/mclk's  clock and voltage

echo "r" to restore default value.

Change-Id: I4d1e70aee31850694a0ff13db8bbfe2524a1d3ae
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  4 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 89 +-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 19 ++
 4 files changed, 112 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 986f1d5..4b5755e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->set_power_profile_mode(\
(adev)->powerplay.pp_handle, parameter, size))
 
+#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
+   ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
+   (adev)->powerplay.pp_handle, type, parameter, size))
+
 struct amdgpu_dpm {
struct amdgpu_ps*ps;
/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ed9012a..f2d3987 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -360,6 +360,81 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
return count;
 }
 
+static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf,
+   size_t count)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   int ret;
+   uint32_t parameter_size = 0;
+   long parameter[64];
+   char buf_cpy[128];
+   char *tmp_str;
+   char *sub_str;
+   const char delimiter[3] = {' ', '\n', '\0'};
+   uint32_t type;
+
+   if (count > 127)
+   return -EINVAL;
+
+   pr_info("%c \n", *buf);
+   if (*buf == 's')
+   type = 0;
+   else if (*buf == 'm')
+   type = 1;
+   else if(*buf == 'r')
+   type = 2;
+   else {
+   pr_info("= \n");
+   return -EINVAL;
+   }
+   memcpy(buf_cpy, buf, count+1);
+
+   tmp_str = buf_cpy;
+
+   while (isspace(*++tmp_str));
+
+   while (tmp_str[0]) {
+   sub_str = strsep(&tmp_str, delimiter);
+   ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
+   if (ret)
+   return -EINVAL;
+   parameter_size++;
+
+   while (isspace(*tmp_str))
+   tmp_str++;
+   }
+
+   if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
+   ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
+   parameter, parameter_size);
+
+   if (ret)
+   return -EINVAL;
+
+   return count;
+}
+
+static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   uint32_t size = 0;
+
+   if (adev->powerplay.pp_funcs->print_clock_levels) {
+   size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
+   size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
+   return size;
+   } else {
+   return snprintf(buf, PAGE_SIZE, "\n");
+   }
+
+}
+
 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -842,6 +917,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | 
S_IWUSR,
 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
amdgpu_get_pp_power_profile_mode,
amdgpu_set_pp_power_profile_mode);
+static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
+   amdgpu_get_pp_od_clk_voltage,
+   amdgpu_set_pp_od_clk_voltage);
+
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
  struct device_attribute *attr,
  char *buf)
@@ -1481,7 +1560,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_power_profile_mode\n");
return ret;
}
-
+  

[PATCH 6/8] drm/amd/pp: Update avfs voltage when set power state

[Rex Zhu]

when Over-driver engine clock and voltage were set,
need to recalculate AVFS voltage on VI asics.

Change-Id: If2a2226d64c0c2aa37c2e84f36b0dad8b7dee25e
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 80 ++
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h |  1 +
 2 files changed, 53 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a0007a8..c69749d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 };
 
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
 static const unsigned long PhwVIslands_Magic = (unsigned 
long)(PHM_VIslands_Magic);
 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -1351,6 +1350,53 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
return 0;
 }
 
+static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
*)(hwmgr->smu_backend);
+
+   if (smu_data == NULL)
+   return -EINVAL;
+
+   if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+   return 0;
+
+   if (enable) {
+   if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+   hwmgr, PPSMC_MSG_EnableAvfs),
+   "Failed to enable AVFS!",
+   return -EINVAL);
+   }
+   } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+   hwmgr, PPSMC_MSG_DisableAvfs),
+   "Failed to disable AVFS!",
+   return -EINVAL);
+   }
+
+   return 0;
+}
+
+static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
+{
+   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
*)(hwmgr->smu_backend);
+
+   if (smu_data == NULL)
+   return -EINVAL;
+
+   if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+   return 0;
+
+   if (smu_data->avfs.brecalculate_avfs) {
+   smu7_avfs_control(hwmgr, false);
+   smu7_avfs_control(hwmgr, true);
+   smu_data->avfs.brecalculate_avfs = true;
+   }
+   return 0;
+}
+
 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
int tmp_result, result = 0;
@@ -3923,6 +3969,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr 
*hwmgr, const void *input)
"Failed to populate and upload SCLK MCLK DPM levels!",
result = tmp_result);
 
+   tmp_result = smu7_update_avfs(hwmgr);
+   PP_ASSERT_WITH_CODE((0 == tmp_result),
+   "Failed to update avfs voltages!",
+   result = tmp_result);
+
tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to generate DPM level enabled mask!",
@@ -4704,33 +4755,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr 
*hwmgr,
return result;
 }
 
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
-{
-   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
*)(hwmgr->smu_backend);
-
-   if (smu_data == NULL)
-   return -EINVAL;
-
-   if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
-   return 0;
-
-   if (enable) {
-   if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
-   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
-   hwmgr, PPSMC_MSG_EnableAvfs),
-   "Failed to enable AVFS!",
-   return -EINVAL);
-   } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-   CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
-   PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
-   hwmgr, PPSMC_MSG_DisableAvfs),
-   "Failed to disable AVFS!",
-   return -EINVAL);
-
-   return 0;
-}
-
 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
uint32_t virtual_addr_low,
uint32_t virtual_addr_hi,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h 
b

[PATCH 7/8] drm/amd/pp: Implement edit_dpm_table on smu7

[Rex Zhu]

Change-Id: I301be04db3c56e16e2c10091016efa5439fbc744
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 104 ++-
 1 file changed, 103 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index c69749d..8dbec14 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4834,6 +4834,108 @@ static int smu7_get_thermal_temperature_range(struct 
pp_hwmgr *hwmgr,
return 0;
 }
 
+static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
+   enum PHM_ODN_DPM_TABLE_TYPE type,
+   uint32_t clk,
+   uint32_t voltage)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+   if (hwmgr->dyn_state.max_clock_voltage_on_ac.vddc * 120 / 100 < voltage)
+   return false;
+
+   if (type == PHM_ODN_SCLK_VDDC_TABLE) {
+   if (data->vbios_boot_state.sclk_bootup_value > clk ||
+   hwmgr->dyn_state.max_clock_voltage_on_ac.sclk * 120 / 
100 < clk)
+   return false;
+   } else if (type == PHM_ODN_MCLK_VDDC_TABLE) {
+   if (data->vbios_boot_state.mclk_bootup_value > clk ||
+   hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * 120 / 
100 < clk)
+   return false;
+   } else {
+   return false;
+   }
+
+   return true;
+}
+
+static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+   enum PHM_ODN_DPM_TABLE_TYPE type,
+   long *input, uint32_t size)
+{
+   uint32_t i;
+   const phm_ppt_v1_clock_voltage_dependency_table *pgolden_vdd_dep_table 
= NULL;
+   struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
+   struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend 
= NULL;
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   struct phm_ppt_v1_information *table_info =
+   (struct phm_ppt_v1_information *)hwmgr->pptable;
+   struct smu7_smumgr *smu_data = (struct smu7_smumgr 
*)(hwmgr->smu_backend);
+   uint32_t input_clk;
+   uint32_t input_vol;
+   uint32_t input_level;
+
+   PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
+   return -EINVAL);
+
+   if (PHM_ODN_SCLK_VDDC_TABLE == type) {
+   podn_dpm_table_in_backend = 
&data->odn_dpm_table.odn_core_clock_dpm_levels;
+   podn_vdd_dep_in_backend = 
&data->odn_dpm_table.vdd_dependency_on_sclk;
+   PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && 
podn_vdd_dep_in_backend),
+   "Failed to get ODN SCLK and Voltage tables",
+   return -EINVAL);
+   data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+   } else if (PHM_ODN_MCLK_VDDC_TABLE == type) {
+   podn_dpm_table_in_backend = 
&data->odn_dpm_table.odn_memory_clock_dpm_levels;
+   podn_vdd_dep_in_backend = 
&data->odn_dpm_table.vdd_dependency_on_mclk;
+
+   PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && 
podn_vdd_dep_in_backend),
+   "Failed to get ODN MCLK and Voltage tables",
+   return -EINVAL);
+   data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+   } else if (PHM_ODN_RESET_DEFAULT_TABLE == type) {
+   smu7_odn_initial_default_setting(hwmgr);
+   data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK | 
DPMTABLE_UPDATE_MCLK;
+   smu_data->avfs.brecalculate_avfs = true;
+   return 0;
+   } else {
+   return -EINVAL;
+   }
+
+   if (hwmgr->pp_table_version == PP_TABLE_V1)
+   pgolden_vdd_dep_table = PHM_ODN_MCLK_VDDC_TABLE == type ?
+   table_info->vdd_dep_on_mclk:
+   table_info->vdd_dep_on_sclk;
+
+   PP_ASSERT_WITH_CODE(pgolden_vdd_dep_table
+   && pgolden_vdd_dep_table->count > 0,
+   "Invalid golden_vdd_dep_table",
+   return -EINVAL);
+
+   for (i = 0; i < size;) {
+   if (i + 3 > size || input[i] >= 
podn_dpm_table_in_backend->num_of_pl) {
+   pr_info("invalid clock voltage input \n");
+   return 0;
+   }
+   input_level = input[i];
+   input_clk = input[i+1] * 100;
+   input_vol = input[i+2];
+
+   if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, 
input_vol)) {
+   podn_dpm_table_in_backend->entries[input_level].clock =

[PATCH 5/8] drm/amd/pp: Move DPMTABLE_* definitions to common header file

[Rex Zhu]

Change-Id: I46cdf4f39f4c9c448a2c76b67f1cbbfed26c7488
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h|  5 -
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h  |  6 --
 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 11 +++
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index 8eec974..1ce84cc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -34,11 +34,6 @@
 #define SMU7_VOLTAGE_CONTROL_BY_SVID2   0x2
 #define SMU7_VOLTAGE_CONTROL_MERGED 0x3
 
-#define DPMTABLE_OD_UPDATE_SCLK 0x0001
-#define DPMTABLE_OD_UPDATE_MCLK 0x0002
-#define DPMTABLE_UPDATE_SCLK0x0004
-#define DPMTABLE_UPDATE_MCLK0x0008
-
 enum gpu_pt_config_reg_type {
GPU_CONFIGREG_MMR = 0,
GPU_CONFIGREG_SMC_IND,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 689fe9f..ab3e879 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -189,12 +189,6 @@ struct vega10_vbios_boot_state {
uint32_tdcef_clock;
 };
 
-#define DPMTABLE_OD_UPDATE_SCLK 0x0001
-#define DPMTABLE_OD_UPDATE_MCLK 0x0002
-#define DPMTABLE_UPDATE_SCLK0x0004
-#define DPMTABLE_UPDATE_MCLK0x0008
-#define DPMTABLE_OD_UPDATE_VDDC 0x0010
-
 struct vega10_smc_state_table {
uint32_tsoc_boot_level;
uint32_tgfx_boot_level;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 97d25cd..d846cbb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -358,6 +358,17 @@ struct phm_clocks {
uint32_t clock[MAX_NUM_CLOCKS];
 };
 
+#define DPMTABLE_OD_UPDATE_SCLK 0x0001
+#define DPMTABLE_OD_UPDATE_MCLK 0x0002
+#define DPMTABLE_UPDATE_SCLK0x0004
+#define DPMTABLE_UPDATE_MCLK0x0008
+#define DPMTABLE_OD_UPDATE_VDDC 0x0010
+
+/* To determine if sclk and mclk are in overdrive state */
+#define SCLK_OVERDRIVE_ENABLED   0x0001
+#define MCLK_OVERDRIVE_ENABLED   0x0002
+#define VDDC_OVERDRIVE_ENABLED   0x0010
+
 struct phm_odn_performance_level {
uint32_t clock;
uint32_t vddc;
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/8] drm/amd/pp: Add OD driver clock/voltage display on smu7

[Rex Zhu]

Change-Id: I54bb964a3905f675e93411f93810cc1aa1f67d12
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h   |  2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 401b895..fba44a5 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -107,6 +107,8 @@ enum pp_clock_type {
PP_SCLK,
PP_MCLK,
PP_PCIE,
+   OD_SCLK,
+   OD_MCLK,
 };
 
 enum amd_pp_sensors {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f3d9c64..a0007a8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4355,6 +4355,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
struct smu7_single_dpm_table *sclk_table = 
&(data->dpm_table.sclk_table);
struct smu7_single_dpm_table *mclk_table = 
&(data->dpm_table.mclk_table);
struct smu7_single_dpm_table *pcie_table = 
&(data->dpm_table.pcie_speed_table);
+   struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+   struct phm_odn_clock_levels *odn_sclk_table = 
&(odn_table->odn_core_clock_dpm_levels);
+   struct phm_odn_clock_levels *odn_mclk_table = 
&(odn_table->odn_memory_clock_dpm_levels);
int i, now, size = 0;
uint32_t clock, pcie_speed;
 
@@ -4409,6 +4412,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
*hwmgr,
(pcie_table->dpm_levels[i].value == 2) 
? "8.0GT/s, x16" : "",
(i == now) ? "*" : "");
break;
+   case OD_SCLK:
+   if (hwmgr->od_enabled) {
+   size = sprintf(buf, "%s: \n", "OD_SCLK");
+   for (i = 0; i < odn_sclk_table->num_of_pl; i++)
+   size += sprintf(buf + size, "%d: %10uMhz %10u 
mV\n",
+   i, odn_sclk_table->entries[i].clock / 
100,
+   odn_sclk_table->entries[i].vddc);
+   }
+   break;
+   case OD_MCLK:
+   if (hwmgr->od_enabled) {
+   size = sprintf(buf, "%s: \n", "OD_MCLK");
+   for (i = 0; i < odn_mclk_table->num_of_pl; i++)
+   size += sprintf(buf + size, "%d: %10uMhz %10u 
mV\n",
+   i, odn_mclk_table->entries[i].clock / 
100,
+   odn_mclk_table->entries[i].vddc);
+   }
+   break;
default:
break;
}
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/8] drm/amd/pp: Add hwmgr interface for edit dpm table

[Rex Zhu]

Add odn_edit_dpm_table function
points for setting user assigned clock/voltage.

Change-Id: I7e49ffdc30b77d07b46bf12ebb275fa0ff901588
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 6 ++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h   | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index d6772a8..97d25cd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -364,6 +364,12 @@ struct phm_odn_performance_level {
bool enabled;
 };
 
+enum PHM_ODN_DPM_TABLE_TYPE {
+   PHM_ODN_SCLK_VDDC_TABLE,
+   PHM_ODN_MCLK_VDDC_TABLE,
+   PHM_ODN_RESET_DEFAULT_TABLE
+};
+
 struct phm_odn_clock_levels {
uint32_t size;
uint32_t options;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index c496742..36e5378 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -345,6 +345,9 @@ struct pp_hwmgr_func {
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, 
uint32_t size);
+   int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
+   enum PHM_ODN_DPM_TABLE_TYPE type,
+   long *input, uint32_t size);
 };
 
 struct pp_table_func {
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/8] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.

[Rex Zhu]

Add initial infrastructure for manual dpm control.

Change-Id: Id9d8dd3043d4c9b90854a94f9749bc70eaf9162e
Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 75 
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 14 +
 2 files changed, 89 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index ce74e06..f3d9c64 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -793,6 +793,76 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
return 0;
 }
 
+static int smu7_get_voltage_dependency_table(
+   const struct phm_ppt_v1_clock_voltage_dependency_table 
*allowed_dep_table,
+   struct phm_ppt_v1_clock_voltage_dependency_table 
*dep_table)
+{
+   uint8_t i = 0;
+   PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
+   "Voltage Lookup Table empty",
+   return -EINVAL);
+
+   dep_table->count = allowed_dep_table->count;
+   for (i=0; icount; i++) {
+   dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
+   dep_table->entries[i].vddInd = 
allowed_dep_table->entries[i].vddInd;
+   dep_table->entries[i].vdd_offset = 
allowed_dep_table->entries[i].vdd_offset;
+   dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
+   dep_table->entries[i].vddgfx = 
allowed_dep_table->entries[i].vddgfx;
+   dep_table->entries[i].vddci = 
allowed_dep_table->entries[i].vddci;
+   dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
+   dep_table->entries[i].phases = 
allowed_dep_table->entries[i].phases;
+   dep_table->entries[i].cks_enable = 
allowed_dep_table->entries[i].cks_enable;
+   dep_table->entries[i].cks_voffset = 
allowed_dep_table->entries[i].cks_voffset;
+   }
+
+   return 0;
+}
+
+static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+   struct phm_ppt_v1_information *table_info =
+   (struct phm_ppt_v1_information *)(hwmgr->pptable);
+   uint32_t i;
+
+   struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+   struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
+
+   if (table_info == NULL)
+   return -EINVAL;
+
+   dep_sclk_table = table_info->vdd_dep_on_sclk;
+   dep_mclk_table = table_info->vdd_dep_on_mclk;
+
+   odn_table->odn_core_clock_dpm_levels.num_of_pl =
+   
data->golden_dpm_table.sclk_table.count;
+   for (i=0; igolden_dpm_table.sclk_table.count; i++) {
+   odn_table->odn_core_clock_dpm_levels.entries[i].clock =
+   
data->golden_dpm_table.sclk_table.dpm_levels[i].value;
+   odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
+   odn_table->odn_core_clock_dpm_levels.entries[i].vddc = 
dep_sclk_table->entries[i].vddc;
+   }
+
+   smu7_get_voltage_dependency_table(dep_sclk_table,
+   (struct phm_ppt_v1_clock_voltage_dependency_table 
*)&(odn_table->vdd_dependency_on_sclk));
+
+   odn_table->odn_memory_clock_dpm_levels.num_of_pl =
+   
data->golden_dpm_table.mclk_table.count;
+   for (i=0; igolden_dpm_table.sclk_table.count; i++) {
+   odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
+   
data->golden_dpm_table.mclk_table.dpm_levels[i].value;
+   odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = 
true;
+   odn_table->odn_memory_clock_dpm_levels.entries[i].vddc = 
dep_mclk_table->entries[i].vddc;
+   }
+
+   smu7_get_voltage_dependency_table(dep_mclk_table,
+   (struct phm_ppt_v1_clock_voltage_dependency_table 
*)&(odn_table->vdd_dependency_on_mclk));
+
+   return 0;
+}
+
 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -809,6 +879,11 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr 
*hwmgr)
/* save a copy of the default DPM table */
memcpy(&(data->golden_dpm_table), &(data->dpm_table),
sizeof(struct smu7_dpm_table));
+
+   /* initialize ODN table */
+   if (hwmgr->od_enabled)
+   smu7_odn_initial_default_setting(hwmgr);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index beba25c..8

[PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature

[Rex Zhu]

when this bit was set on module load,
driver will allow the user over/under gpu
clock and voltage through sysfs.

by default, this bit was not set.

Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 3 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 6 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 2 ++
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e679bb8..508a254 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -120,7 +120,7 @@
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0x;
+uint amdgpu_pp_feature_mask = 0x2fff;
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index e35bdc5..ebfbbcf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_CAC);
}
 
+   if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
+   hwmgr->od_enabled = true;
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6f053fa..ce74e06 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3572,8 +3572,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->sclk_table.dpm_levels
[dpm_table->sclk_table.count - 1].value = sclk;
 
-   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_OD6PlusinACSupport) ||
-   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_OD6PlusinDCSupport)) {
+   if (hwmgr->od_enabled) {
/* Need to do calculation based on the golden DPM table
 * as the Heatmap GPU Clock axis is also based on the default 
values
 */
@@ -3618,8 +3617,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->mclk_table.dpm_levels
[dpm_table->mclk_table.count - 1].value = mclk;
 
-   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_OD6PlusinACSupport) ||
-   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_OD6PlusinDCSupport)) {
+   if (hwmgr->od_enabled) {
 
PP_ASSERT_WITH_CODE(
(golden_dpm_table->mclk_table.dpm_levels
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index fadbc8a..12a31d1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3396,8 +3396,7 @@ static int 
vega10_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->
gfx_table.dpm_levels[dpm_table->gfx_table.count 
- 1].
value = sclk;
-   if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) 
||
-   
PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
+   if (hwmgr->od_enabled) {
/* Need to do calculation based on the 
golden DPM table
 * as the Heatmap GPU Clock axis is 
also based on
 * the default values
@@ -3451,9 +3450,7 @@ static int 
vega10_populate_and_upload_sclk_mclk_dpm_levels(
mem_table.dpm_levels[dpm_table->mem_table.count - 1].
value = mclk;
 
-   if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-   PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
-
+   if (hwmgr->od_enabled) {
PP_ASSERT_WITH_CODE(
golden_dpm_table->mem_table.dpm_levels
[golden_dpm_table->mem_table.count - 
1].value,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 6d8183d..c496742 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
PP_OD_FUZZY_FAN_CONTROL_M

[PATCH] drm/amd/pp: Refine code abbreviate variable name

[Rex Zhu]

abbreviate variable name number_of_performance_levels
to num_of_pl in struct phm_odn_clock_levels

Change-Id: I132c59dfd28933c4f6eba74fa53ffd0d014ec354
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c  | 8 
 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index d646b27b..fadbc8a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -1386,8 +1386,8 @@ static int vega10_setup_default_dpm_tables(struct 
pp_hwmgr *hwmgr)
 
if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
-   data->odn_dpm_table.odn_core_clock_dpm_levels.
-   number_of_performance_levels = data->dpm_table.gfx_table.count;
+   data->odn_dpm_table.odn_core_clock_dpm_levels.num_of_pl =
+   data->dpm_table.gfx_table.count;
for (i = 0; i < data->dpm_table.gfx_table.count; i++) {

data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].clock =

data->dpm_table.gfx_table.dpm_levels[i].value;
@@ -1407,8 +1407,8 @@ static int vega10_setup_default_dpm_tables(struct 
pp_hwmgr *hwmgr)
dep_gfx_table->entries[i].cks_voffset;
}
 
-   data->odn_dpm_table.odn_memory_clock_dpm_levels.
-   number_of_performance_levels = data->dpm_table.mem_table.count;
+   data->odn_dpm_table.odn_memory_clock_dpm_levels.num_of_pl =
+   data->dpm_table.mem_table.count;
for (i = 0; i < data->dpm_table.mem_table.count; i++) {

data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].clock =

data->dpm_table.mem_table.dpm_levels[i].value;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 933aa44..d6772a8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -368,8 +368,8 @@ struct phm_odn_clock_levels {
uint32_t size;
uint32_t options;
uint32_t flags;
-   uint32_t number_of_performance_levels;
-   /* variable-sized array, specify by ulNumberOfPerformanceLevels. */
+   uint32_t num_of_pl;
+   /* variable-sized array, specify by num_of_pl. */
struct phm_odn_performance_level entries[8];
 };
 
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/3] drm/amd/pp: Add stable Pstate clk display support in debugfs

[Rex Zhu]

The additional output are: PSTATE_SCLK and PSTATE_MCLK value
in MHz as:

300 MHz (PSTATE_SCLK)
300 MHz (PSTATE_MCLK)

Change-Id: I96dac70d7e7d9702a5bfc3a40bd9bb57a21abdd7
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  4 
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  2 ++
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 23 ++-
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 662edca..ed9012a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1591,6 +1591,10 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, 
struct amdgpu_device *a
seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void 
*)&value, &size))
seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
+   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 
(void *)&value, &size))
+   seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
+   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 
(void *)&value, &size))
+   seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void 
*)&value, &size))
seq_printf(m, "\t%u mV (VDDGFX)\n", value);
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void 
*)&value, &size))
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index a823c03..401b895 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -122,6 +122,8 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_VCE_POWER,
AMDGPU_PP_SENSOR_UVD_POWER,
AMDGPU_PP_SENSOR_GPU_POWER,
+   AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
+   AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 };
 
 enum amd_pp_task {
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 5e22521..d9cb424 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -992,22 +992,27 @@ static int pp_dpm_read_sensor(void *handle, int idx,
int ret = 0;
 
ret = pp_check(pp_handle);
-
if (ret)
return ret;
 
+   if (value == NULL)
+   return -EINVAL;
+
hwmgr = pp_handle->hwmgr;
 
-   if (hwmgr->hwmgr_func->read_sensor == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   switch (idx) {
+   case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
+   *((uint32_t *)value) = hwmgr->pstate_sclk;
return 0;
+   case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
+   *((uint32_t *)value) = hwmgr->pstate_mclk;
+   return 0;
+   default:
+   mutex_lock(&pp_handle->pp_lock);
+   ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
+   mutex_unlock(&pp_handle->pp_lock);
+   return ret;
}
-
-   mutex_lock(&pp_handle->pp_lock);
-   ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
-   mutex_unlock(&pp_handle->pp_lock);
-
-   return ret;
 }
 
 static struct amd_vce_state*
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/3] drm/amd/pp: Add stable Pstate clk display when print_clock_levels

[Rex Zhu]

The additional output are at the end of sclk/mclk info as
cat pp_dpm_mclk
0: 300Mhz *
1: 1650Mhz
P: 300Mhz

Signed-off-by: Rex Zhu 

Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index f68dd08..03dfba0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, sclk_table->entries[i].clk / 100,
(i == now) ? "*" : "");
+   size += sprintf(buf + size, "P: %uMhz\n", 
hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
@@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
CZ_NUM_NBPMEMORYCLOCK-i, 
data->sys_info.nbp_memory_clock[i-1] / 100,
(CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" 
: "");
+   size += sprintf(buf + size, "P: %uMhz\n", 
hwmgr->pstate_mclk/100);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 409a56b..88c6ad8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
data->gfx_max_freq_limit / 100,
((data->gfx_max_freq_limit / 100)
 == now) ? "*" : "");
+   size += sprintf(buf + size, "P: %uMhz\n", 
hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
@@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
mclk_table->entries[i].clk / 100,
((mclk_table->entries[i].clk / 100)
 == now) ? "*" : "");
+   size += sprintf(buf + size, "P: %uMhz\n", 
hwmgr->pstate_mclk/100);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 11a900b..6f053fa 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4301,6 +4301,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, sclk_table->dpm_levels[i].value / 
100,
(i == now) ? "*" : "");
+   size += sprintf(buf + size, "P: %uMhz\n", 
hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
@@ -4317,6 +4318,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, mclk_table->dpm_levels[i].value / 
100,
(i == now) ? "*" : "");
+   size += sprintf(buf + size, "P: %uMhz\n", 
hwmgr->pstate_mclk/100);
break;
case PP_PCIE:
pcie_speed = smu7_get_current_pcie_speed(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index adfbbc1..d646b27b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4571,6 +4571,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr 
*hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, sclk_table->dpm_levels[i].value / 
100,
(i == now) ? "*" : "");
+   size += sprintf(buf + size, "P: %uMhz\n", 
hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
if (data->registry_data.mclk_dpm_key_disabled)
@@ -4589,6 +4590,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr 
*hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
  

[PATCH 1/3] drm/amd/pp: Store stable Pstate clocks

[Rex Zhu]

User can use to calculate profiling ratios when
set UMD Pstate.

Signed-off-by: Rex Zhu 

Change-Id: I3c6b82ebface57eb969d474c57149e8658ab7014
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c |  2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c |  3 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 14 --
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  5 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 ++
 5 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index e574af1..f68dd08 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1189,6 +1189,8 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr 
*hwmgr)
 
cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
+   hwmgr->pstate_sclk = table->entries[0].clk;
+   hwmgr->pstate_mclk = 0;
 
level = cz_get_max_sclk_level(hwmgr) - 1;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 569073e..409a56b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -451,6 +451,9 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 
+   hwmgr->pstate_sclk = RAVEN_UMD_PSTATE_GFXCLK;
+   hwmgr->pstate_mclk = RAVEN_UMD_PSTATE_FCLK;
+
return result;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b60e50e..11a900b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2579,8 +2579,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr 
*hwmgr, enum amd_dpm_forced_le
break;
}
}
-   if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+   if (count < 0 || level == 
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
*sclk_mask = 0;
+   tmp_sclk = 
hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
+   }
 
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
*sclk_mask = 
hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
@@ -2595,8 +2597,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr 
*hwmgr, enum amd_dpm_forced_le
break;
}
}
-   if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+   if (count < 0 || level == 
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
*sclk_mask = 0;
+   tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;
+   }
 
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
@@ -2608,6 +2612,9 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, 
enum amd_dpm_forced_le
*mclk_mask = golden_dpm_table->mclk_table.count - 1;
 
*pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
+   hwmgr->pstate_sclk = tmp_sclk;
+   hwmgr->pstate_mclk = tmp_mclk;
+
return 0;
 }
 
@@ -2619,6 +2626,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
uint32_t mclk_mask = 0;
uint32_t pcie_mask = 0;
 
+   if (hwmgr->pstate_sclk == 0)
+   smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, 
&pcie_mask);
+
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
ret = smu7_force_dpm_highest(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index d5abd46..adfbbc1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4178,6 +4178,8 @@ static int vega10_get_profiling_clk_mask(struct pp_hwmgr 
*hwmgr, enum amd_dpm_fo
*sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
*soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
*mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
+   hwmgr->pstate_sclk = 
table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
+   hwmgr->pstate_mclk = 
table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
}
 
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
@@ -4219,6 +4221,9 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr 
*hwmgr,
uint32_t mclk_mask = 0;
uint32_t soc_mask = 0;
 
+   if (hwmgr->pstate_sclk == 0)
+   vega10_get_profili

Re: [PATCH v2] drm/amdgpu: reserved requested gtt buffer for smu

[Christian König]

Am 16.01.2018 um 12:46 schrieb Rex Zhu:

v2: merge tip drm-next code.
 simplify check smu_memory_size code.
 simplify allocate smu memroy code.

Change-Id: Ie8e865cc7d6c9d60fe234f29ac07e9f9fae60e9f
Signed-off-by: Rex Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 43 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  6 
  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 39 
  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  2 +-
  8 files changed, 94 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cd3af51..46cd14c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -128,6 +128,7 @@
  extern int amdgpu_lbpw;
  extern int amdgpu_compute_multipipe;
  extern int amdgpu_gpu_recovery;
+extern uint amdgpu_smu_memory_pool_size;
  
  #ifdef CONFIG_DRM_AMDGPU_SI

  extern int amdgpu_si_support;
@@ -1418,6 +1419,7 @@ enum amd_hw_ip_block_type {
  struct amd_powerplay {
struct cgs_device *cgs_device;
void *pp_handle;
+   struct amdgpu_bo *smu_prv_buffer; /* used for SMU debug */
const struct amd_ip_funcs *ip_funcs;
const struct amd_pm_funcs *pp_funcs;
  };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d09c4ee..f0b112c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -773,6 +773,46 @@ static void amdgpu_device_check_vm_size(struct 
amdgpu_device *adev)
}
  }
  
+static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)

+{
+   struct sysinfo si;
+   bool is_os_64 = (sizeof(void *) == 8) ? true : false;
+   uint64_t total_memory;
+   uint64_t dram_size_seven_GB = 0x1B800;
+   uint64_t dram_size_three_GB = 0xB800;
+
+   if (amdgpu_smu_memory_pool_size == 0)
+   return;
+
+   if (!is_os_64) {
+   DRM_WARN("Not 64-bit OS, feature not supported\n");
+   goto def_value;
+   }
+   si_meminfo(&si);
+   total_memory = (uint64_t)si.totalram * si.mem_unit;
+
+   if ((amdgpu_smu_memory_pool_size == 1) ||
+   (amdgpu_smu_memory_pool_size == 2)) {
+   if (total_memory < dram_size_three_GB)
+   goto def_value1;
+   } else if ((amdgpu_smu_memory_pool_size == 4) ||
+   (amdgpu_smu_memory_pool_size == 8)) {
+   if (total_memory < dram_size_seven_GB)
+   goto def_value1;
+   } else {
+   DRM_WARN("Smu memory pool size not supported\n");
+   goto def_value;
+   }
+   amdgpu_smu_memory_pool_size = amdgpu_smu_memory_pool_size << 28;


Don't modify module parameters like this.

When the function is executed multiple times you end up with nonsense 
values.


Additional to that It's possible that they are read by userspace to 
print the current options.


Regards,
Christian.


+
+   return;
+
+def_value1:
+   DRM_WARN("No enough system memory\n");
+def_value:
+   amdgpu_smu_memory_pool_size = 0;
+}
+
  /**
   * amdgpu_device_check_arguments - validate module params
   *
@@ -814,6 +854,8 @@ static void amdgpu_device_check_arguments(struct 
amdgpu_device *adev)
amdgpu_vm_fragment_size = -1;
}
  
+	amdgpu_device_check_smu_prv_buffer_size(adev);

+
amdgpu_device_check_vm_size(adev);
  
  	amdgpu_device_check_block_size(adev);

@@ -2073,6 +2115,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
}
+
adev->accel_working = false;
cancel_delayed_work_sync(&adev->late_init_work);
/* free i2c buses */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0bb34db..e679bb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -130,6 +130,7 @@
  int amdgpu_lbpw = -1;
  int amdgpu_compute_multipipe = -1;
  int amdgpu_gpu_recovery = -1; /* auto */
+uint amdgpu_smu_memory_pool_size = 0;
  
  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");

  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -311,6 +312,11 @@
  module_param_named(cik_support, amdgpu_cik_support, int, 0444);
  #endif
  
+MODULE_PARM_DESC(smu_memory_pool_size,

+   "reserve gtt for smu debug usage, 0 = disable,"
+   "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 

[PATCH 2/2] drm/amd/pp: Add custom power profile mode support on Vega10

[Rex Zhu]

v2: delete uncessary blank line.
Add static const modifiers to an array

Signed-off-by: Rex Zhu 

Change-Id: If6b81ade742ef434717010ca0783d2af9145c975
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 38 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 78 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  3 +
 4 files changed, 120 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 8859b67..5e22521 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1081,6 +1081,42 @@ static int pp_dpm_get_power_profile_state(void *handle,
return 0;
 }
 
+static int pp_get_power_profile_mode(void *handle, char *buf)
+{
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle = (struct pp_instance *)handle;
+
+   if (!buf || pp_check(pp_handle))
+   return -EINVAL;
+
+   hwmgr = pp_handle->hwmgr;
+
+   if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
+   return snprintf(buf, PAGE_SIZE, "\n");
+   }
+
+   return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
+}
+
+static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
+{
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle = (struct pp_instance *)handle;
+
+   if (pp_check(pp_handle))
+   return -EINVAL;
+
+   hwmgr = pp_handle->hwmgr;
+
+   if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
+   return -EINVAL;
+   }
+
+   return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
+}
+
 static int pp_dpm_set_power_profile_state(void *handle,
struct amd_pp_profile *request)
 {
@@ -1464,6 +1500,8 @@ static int pp_get_display_mode_validation_clocks(void 
*handle,
.switch_power_profile = pp_dpm_switch_power_profile,
.set_clockgating_by_smu = pp_set_clockgating_by_smu,
.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
+   .get_power_profile_mode = pp_get_power_profile_mode,
+   .set_power_profile_mode = pp_set_power_profile_mode,
 /* export to DC */
.get_sclk = pp_dpm_get_sclk,
.get_mclk = pp_dpm_get_mclk,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 7e6feed..d5abd46 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -760,6 +760,8 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
hwmgr->backend = data;
 
+   hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+
vega10_set_default_registry_data(hwmgr);
 
data->disable_dpm_mask = 0xff;
@@ -3963,6 +3965,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int 
idx,
ret = -EINVAL;
break;
}
+
return ret;
 }
 
@@ -5021,6 +5024,79 @@ static int vega10_register_thermal_interrupt(struct 
pp_hwmgr *hwmgr,
return 0;
 }
 
+static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+{
+   struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+   uint32_t i, size = 0;
+   static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
+   {90, 60, 0, 0,},
+   {70, 60, 0, 0,},
+   {70, 90, 0, 0,},
+   {30, 60, 0, 6,},
+   };
+   static const char *profile_name[6] = {"3D_FULL_SCREEN",
+   "POWER_SAVING",
+   "VIDEO",
+   "VR",
+   "COMPUTER",
+   "CUSTOM"};
+   static const char *title[6] = {"NUM",
+   "MODE_NAME",
+   "BUSY_SET_POINT",
+   "FPS",
+   "USE_RLC_BUSY",
+   "MIN_ACTIVE_LEVEL"};
+
+   if (!buf)
+   return -EINVAL;
+
+   size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
+   title[1], title[2], title[3], title[4], title[5]);
+
+   for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
+   size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
+   i, profile_name[i], (i == hwmgr->power_profile_mode) ? 
"*" : " ",
+   profile_mode_setting[i][0], profile_mode_setting[i][1],
+   pro

[PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs

[Rex Zhu]

when cat pp_power_profile_mode on Vega10
NUMMODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL
  0 3D_FULL_SCREEN : 70  60  1  3
  1   POWER_SAVING : 90  60  0  0
  2  VIDEO*: 70  60  0  0
  3 VR : 70  90  0  0
  4   COMPUTER : 30  60  0  6
  5 CUSTOM :  0   0  0  0

the result show all the profile mode we can support and custom mode.
user can echo the num(0-4) to pp_power_profile_mode to select the profile
mode or can echo "5 value value value value" to enter CUSTOM mode.
the four parameter is set_point/FPS/USER_RLC_BUSY/MIN_ACTIVE_LEVEL.

Change-Id: I72634646a9a179ccd57f175b4c0b3f45e538a03f
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  8 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 81 +-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h | 11 +++-
 3 files changed, 98 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 8a8d09dd..986f1d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -366,6 +366,14 @@ enum amdgpu_pcie_gen {
(adev)->powerplay.pp_handle, virtual_addr_low, \
virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
 
+#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
+   ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
+   (adev)->powerplay.pp_handle, buf))
+
+#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
+   ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
+   (adev)->powerplay.pp_handle, parameter, size))
+
 struct amdgpu_dpm {
struct amdgpu_ps*ps;
/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index e5ee7cf..662edca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -584,6 +584,73 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
return count;
 }
 
+static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   if (adev->powerplay.pp_funcs->get_power_profile_mode)
+   return amdgpu_dpm_get_power_profile_mode(adev, buf);
+
+   return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+
+static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf,
+   size_t count)
+{
+   int ret = 0xff;
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   uint32_t parameter_size = 0;
+   long parameter[64];
+   char *sub_str, buf_cpy[128];
+   char *tmp_str;
+   uint32_t i = 0;
+   char tmp[2];
+   long int profile_mode = 0;
+   const char delimiter[3] = {' ', '\n', '\0'};
+
+   tmp[0] = *(buf);
+   tmp[1] = '\0';
+   ret = kstrtol(tmp, 0, &profile_mode);
+   if (ret)
+   goto fail;
+
+   if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
+   if (count < 2 || count > 127)
+   return -EINVAL;
+   while (isspace(*++buf))
+   i++;
+   memcpy(buf_cpy, buf, count-i);
+   tmp_str = buf_cpy;
+   while (tmp_str[0]) {
+   sub_str = strsep(&tmp_str, delimiter);
+   ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
+   if (ret) {
+   count = -EINVAL;
+   goto fail;
+   }
+   pr_info("value is %ld \n", parameter[parameter_size]);
+   parameter_size++;
+   while (isspace(*tmp_str))
+   tmp_str++;
+   }
+   }
+   parameter[parameter_size] = profile_mode;
+   if (adev->powerplay.pp_funcs->set_power_profile_mode)
+   ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, 
parameter_size);
+
+   if (!ret)
+   return count;
+fail:
+   return -EINVAL;
+}
+
 static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
char *buf, struct amd_pp_profile *query)
 {
@@ -772,7 +839,9 @@ static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
amdgpu_get_pp_compute_power_profile,
  

[PATCH v2] drm/amdgpu: reserved requested gtt buffer for smu

[Rex Zhu]

v2: merge tip drm-next code.
simplify check smu_memory_size code.
simplify allocate smu memroy code.

Change-Id: Ie8e865cc7d6c9d60fe234f29ac07e9f9fae60e9f
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 43 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  6 
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 39 
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  2 +-
 8 files changed, 94 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cd3af51..46cd14c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -128,6 +128,7 @@
 extern int amdgpu_lbpw;
 extern int amdgpu_compute_multipipe;
 extern int amdgpu_gpu_recovery;
+extern uint amdgpu_smu_memory_pool_size;
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
@@ -1418,6 +1419,7 @@ enum amd_hw_ip_block_type {
 struct amd_powerplay {
struct cgs_device *cgs_device;
void *pp_handle;
+   struct amdgpu_bo *smu_prv_buffer; /* used for SMU debug */
const struct amd_ip_funcs *ip_funcs;
const struct amd_pm_funcs *pp_funcs;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d09c4ee..f0b112c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -773,6 +773,46 @@ static void amdgpu_device_check_vm_size(struct 
amdgpu_device *adev)
}
 }
 
+static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
+{
+   struct sysinfo si;
+   bool is_os_64 = (sizeof(void *) == 8) ? true : false;
+   uint64_t total_memory;
+   uint64_t dram_size_seven_GB = 0x1B800;
+   uint64_t dram_size_three_GB = 0xB800;
+
+   if (amdgpu_smu_memory_pool_size == 0)
+   return;
+
+   if (!is_os_64) {
+   DRM_WARN("Not 64-bit OS, feature not supported\n");
+   goto def_value;
+   }
+   si_meminfo(&si);
+   total_memory = (uint64_t)si.totalram * si.mem_unit;
+
+   if ((amdgpu_smu_memory_pool_size == 1) ||
+   (amdgpu_smu_memory_pool_size == 2)) {
+   if (total_memory < dram_size_three_GB)
+   goto def_value1;
+   } else if ((amdgpu_smu_memory_pool_size == 4) ||
+   (amdgpu_smu_memory_pool_size == 8)) {
+   if (total_memory < dram_size_seven_GB)
+   goto def_value1;
+   } else {
+   DRM_WARN("Smu memory pool size not supported\n");
+   goto def_value;
+   }
+   amdgpu_smu_memory_pool_size = amdgpu_smu_memory_pool_size << 28;
+
+   return;
+
+def_value1:
+   DRM_WARN("No enough system memory\n");
+def_value:
+   amdgpu_smu_memory_pool_size = 0;
+}
+
 /**
  * amdgpu_device_check_arguments - validate module params
  *
@@ -814,6 +854,8 @@ static void amdgpu_device_check_arguments(struct 
amdgpu_device *adev)
amdgpu_vm_fragment_size = -1;
}
 
+   amdgpu_device_check_smu_prv_buffer_size(adev);
+
amdgpu_device_check_vm_size(adev);
 
amdgpu_device_check_block_size(adev);
@@ -2073,6 +2115,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
}
+
adev->accel_working = false;
cancel_delayed_work_sync(&adev->late_init_work);
/* free i2c buses */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0bb34db..e679bb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -130,6 +130,7 @@
 int amdgpu_lbpw = -1;
 int amdgpu_compute_multipipe = -1;
 int amdgpu_gpu_recovery = -1; /* auto */
+uint amdgpu_smu_memory_pool_size = 0;
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -311,6 +312,11 @@
 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 #endif
 
+MODULE_PARM_DESC(smu_memory_pool_size,
+   "reserve gtt for smu debug usage, 0 = disable,"
+   "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 
0444);
+
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 5f5aa5f..7d9c330 100644
--- a/drivers/gpu/dr

Re: [PATCH] drm/amdgpu: fix typo in amdgpu_vce_validate_bo

[Michel Dänzer]

On 2018-01-16 11:03 AM, Christian König wrote:
> Otherwise buffer placement is very restrictive and might fail.
> 
> Fixes: "drm/amdgpu: fix VCE buffer placement restrictions v2"
> 
> Signed-off-by: Christian König 
> Reported-by: Deng, Emily 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> index 55a726a322e3..d274ae535530 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> @@ -585,8 +585,8 @@ static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser 
> *p, uint32_t ib_idx,
>  
>   for (i = 0; i < bo->placement.num_placement; ++i) {
>   bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
> - bo->placements[i].lpfn = bo->placements[i].fpfn ?
> - min(bo->placements[i].fpfn, lpfn) : lpfn;
> + bo->placements[i].lpfn = bo->placements[i].lpfn ?
> + min(bo->placements[i].lpfn, lpfn) : lpfn;
>   }
>   return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
>  }
> 

Good catch.

Reviewed-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/5] drm/amd/pp: Fix SMIO implementation on CI

[Rex Zhu]

Setup smio table(smio registers's address and voltage ID)
for various voltage domain.

Change-Id: I14be46053ffb2954c1533f4e67d3b0632107af7a
Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 31 +++-
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 03b5f10..98be127 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -860,10 +860,13 @@ static int ci_populate_smc_vddc_table(struct pp_hwmgr 
*hwmgr,
PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC 
voltage table", return -EINVAL);
 
/* GPIO voltage control */
-   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
-   table->VddcLevel[count].Smio |= 
data->vddc_voltage_table.entries[count].smio_low;
-   else
+   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
+   table->VddcLevel[count].Smio = (uint8_t) count;
+   table->Smio[count] |= 
data->vddc_voltage_table.entries[count].smio_low;
+   table->SmioMaskVddcVid |= 
data->vddc_voltage_table.entries[count].smio_low;
+   } else {
table->VddcLevel[count].Smio = 0;
+   }
}
 
CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
@@ -885,10 +888,13 @@ static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr 
*hwmgr,
&(data->vddci_voltage_table.entries[count]),
&(table->VddciLevel[count]));
PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI 
voltage table", return -EINVAL);
-   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-   table->VddciLevel[count].Smio |= 
data->vddci_voltage_table.entries[count].smio_low;
-   else
-   table->VddciLevel[count].Smio |= 0;
+   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+   table->VddciLevel[count].Smio = (uint8_t) count;
+   table->Smio[count] |= 
data->vddci_voltage_table.entries[count].smio_low;
+   table->SmioMaskVddciVid |= 
data->vddci_voltage_table.entries[count].smio_low;
+   } else {
+   table->VddciLevel[count].Smio = 0;
+   }
}
 
CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
@@ -910,10 +916,13 @@ static int ci_populate_smc_mvdd_table(struct pp_hwmgr 
*hwmgr,
&(data->mvdd_voltage_table.entries[count]),
&table->MvddLevel[count]);
PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd 
voltage table", return -EINVAL);
-   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
-   table->MvddLevel[count].Smio |= 
data->mvdd_voltage_table.entries[count].smio_low;
-   else
-   table->MvddLevel[count].Smio |= 0;
+   if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+   table->MvddLevel[count].Smio = (uint8_t) count;
+   table->Smio[count] |= 
data->mvdd_voltage_table.entries[count].smio_low;
+   table->SmioMaskMvddVid |= 
data->mvdd_voltage_table.entries[count].smio_low;
+   } else {
+   table->MvddLevel[count].Smio = 0;
+   }
}
 
CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] drm/amd/pp: Implement voltage regulator config on CI

[Rex Zhu]

Store the voltage regulator configuration
so we can properly query the voltage

Change-Id: Icf916cfedbc2e5ac3037ef6f4f19b9a76ee36fff
Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/smu7.h  | 19 
 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h |  3 +-
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c  | 37 +++
 3 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu7.h
index 75a380a..e14072d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu7.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7.h
@@ -82,6 +82,25 @@
 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7VRConfig |= (configVRConfig |= config;
+   } else {
+   pr_info("VDDCshould be on SVI2 controller!");
+   }
+
+   if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
+   config = VR_SVI2_PLANE_2;
+   table->VRConfig |= (configVRConfig |= (configVRConfig |= (configdpm_table.pcie_speed_table.count;
table->PCIeGenInterval = 1;
 
+   result = ci_populate_vr_config(hwmgr, table);
+   PP_ASSERT_WITH_CODE(0 == result,
+   "Failed to populate VRConfig setting!", return result);
+   data->vr_config = table->VRConfig;
+
ci_populate_smc_svi2_config(hwmgr, table);
 
for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++)
@@ -2084,6 +2120,7 @@ static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
 
CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
+   CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/5] drm/amd/pp: Add querying current gfx voltage for Vega10

[Rex Zhu]

Change-Id: I7be7cb442c620f850044d58bd8097735e3398b07
Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 13 +
 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h   |  3 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 23b7239..7e6feed 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -51,6 +51,9 @@
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
 
+#include "smuio/smuio_9_0_offset.h"
+#include "smuio/smuio_9_0_sh_mask.h"
+
 #define VOLTAGE_SCALE  4
 #define VOLTAGE_VID_OFFSET_SCALE1   625
 #define VOLTAGE_VID_OFFSET_SCALE2   100
@@ -3900,6 +3903,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int 
idx,
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
struct vega10_dpm_table *dpm_table = &data->dpm_table;
int ret = 0;
+   uint32_t reg, val_vid;
 
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
@@ -3946,6 +3950,15 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, 
int idx,
ret = vega10_get_gpu_power(hwmgr, (struct pp_gpu_power 
*)value);
}
break;
+   case AMDGPU_PP_SENSOR_VDDGFX:
+   reg = soc15_get_register_offset(SMUIO_HWID, 0,
+   mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX,
+   mmSMUSVI0_PLANE0_CURRENTVID);
+   val_vid = (cgs_read_register(hwmgr->device, reg) &
+   
SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
+   
SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
+   *((uint32_t *)value) = 
(uint32_t)convert_to_vddc((uint8_t)val_vid);
+   return 0;
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h 
b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
index b7ab69e..414e684 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
@@ -43,7 +43,8 @@ inline static uint32_t soc15_get_register_offset(
reg = DF_BASE.instance[inst].segment[segment] + offset;
else if (hw_id == GC_HWID)
reg = GC_BASE.instance[inst].segment[segment] + offset;
-
+   else if (hw_id == SMUIO_HWID)
+   reg = SMUIO_BASE.instance[inst].segment[segment] + offset;
return reg;
 }
 
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/5] drm/amd/pp: Add querying current gfx voltage for CI/VI

[Rex Zhu]

Store the voltage regulator configuration,
so we can properly query the voltage.

Change-Id: Icec3a93f26b532e466a36d0ebac5886d43df8e6d
Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c| 12 +++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h|  1 +
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  |  2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c |  2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c |  3 +--
 5 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f9f6b4d..b60e50e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3317,7 +3317,7 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int 
idx,
void *value, int *size)
 {
uint32_t sclk, mclk, activity_percent;
-   uint32_t offset;
+   uint32_t offset, val_vid;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
/* size must be at least 4 bytes for all sensors */
@@ -3365,6 +3365,16 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int 
idx,
return -EINVAL;
*size = sizeof(struct pp_gpu_power);
return smu7_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
+   case AMDGPU_PP_SENSOR_VDDGFX:
+   if ((data->vr_config & 0xff) == 0x2)
+   val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
+   CGS_IND_REG__SMC, PWR_SVI2_STATUS, 
PLANE2_VID);
+   else
+   val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
+   CGS_IND_REG__SMC, PWR_SVI2_STATUS, 
PLANE1_VID);
+
+   *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
+   return 0;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index e021154..beba25c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -305,6 +305,7 @@ struct smu7_hwmgr {
uint32_t  frame_time_x2;
uint16_t  mem_latency_high;
uint16_t  mem_latency_low;
+   uint32_t  vr_config;
 };
 
 /* To convert to Q8.8 format for firmware */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 427daa6..7d9e2cb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -2141,7 +2141,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
result = fiji_populate_vr_config(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to populate VRConfig setting!", return result);
-
+   data->vr_config = table->VRConfig;
table->ThermGpio = 17;
table->SclkStepSize = 0x4000;
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index fd874f7..f1a3bc8 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -1991,7 +1991,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr 
*hwmgr)
result = polaris10_populate_vr_config(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to populate VRConfig setting!", return result);
-
+   hw_data->vr_config = table->VRConfig;
table->ThermGpio = 17;
table->SclkStepSize = 0x4000;
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 5eb719e..a03a345 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -2434,7 +2434,7 @@ static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
result = tonga_populate_vr_config(hwmgr, table);
PP_ASSERT_WITH_CODE(!result,
"Failed to populate VRConfig setting !", return result);
-
+   data->vr_config = table->VRConfig;
table->ThermGpio  = 17;
table->SclkStepSize = 0x4000;
 
@@ -2501,7 +2501,6 @@ static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
 
for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++)
table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-
CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-- 
1.9.1

___

[PATCH 1/5] drm/amd/pp: Export registers for read vddc on VI/Vega10

[Rex Zhu]

Change-Id: I34d323c240e65b47c3558eb7042255b61078e2bb
Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h | 1 +
 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h   | 6 --
 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h  | 3 +++
 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h | 3 +++
 4 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h 
b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
index b89347e..f35aba7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
@@ -1246,5 +1246,6 @@
 #define ixGC_CAC_OVRD_CU   
 0xe7
 #define ixCURRENT_PG_STATUS
 0xc020029c
 #define ixCURRENT_PG_STATUS_APU
 0xd020029c
+#define ixPWR_SVI2_STATUS  
 0xC0200294
 
 #endif /* SMU_7_1_3_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
index 654c109..481ee65 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
@@ -6078,6 +6078,8 @@
 #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
 #define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x0002
 #define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x0004
-
-
+#define PWR_SVI2_STATUS__PLANE1_VID_MASK 0x00ff
+#define PWR_SVI2_STATUS__PLANE1_VID__SHIFT 0x
+#define PWR_SVI2_STATUS__PLANE2_VID_MASK 0xff00
+#define PWR_SVI2_STATUS__PLANE2_VID__SHIFT 0x0008
 #endif /* SMU_7_1_3_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
index c1006fe..efd2704 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
@@ -172,4 +172,7 @@
 #define mmROM_SW_DATA_64   
0x006d
 #define mmROM_SW_DATA_64_BASE_IDX  
0
 
+#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX   
0
+#define mmSMUSVI0_PLANE0_CURRENTVID
0x0013
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
index a0be5c9..2487ab9 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
@@ -254,5 +254,8 @@
 //ROM_SW_DATA_64
 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 
   0x0
 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK   
   0xL
+/* SMUSVI0_PLANE0_CURRENTVID */
+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT  
   0x18
+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK
   0xFF00L
 
 #endif
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: reserved requested gtt buffer for smu

[Rex Zhu]

v2: simplify check smu_memory_size code.
simplify allocate smu memroy code.

Signed-off-by: Rex Zhu 

Change-Id: I6d5f4212adc3621d2bf71ca9d2a4d952867d0a01
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 43 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  6 
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 39 
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  2 +-
 8 files changed, 94 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b7c181e..d858f88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -127,6 +127,7 @@
 extern int amdgpu_lbpw;
 extern int amdgpu_compute_multipipe;
 extern int amdgpu_gpu_recovery;
+extern uint amdgpu_smu_memory_pool_size;
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
@@ -1486,6 +1487,7 @@ enum amd_hw_ip_block_type {
 struct amd_powerplay {
struct cgs_device *cgs_device;
void *pp_handle;
+   struct amdgpu_bo *smu_prv_buffer; /* used for SMU debug */
const struct amd_ip_funcs *ip_funcs;
const struct amd_pm_funcs *pp_funcs;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7114f25..04d3002 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -773,6 +773,46 @@ static void amdgpu_device_check_vm_size(struct 
amdgpu_device *adev)
}
 }
 
+static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
+{
+   struct sysinfo si;
+   bool is_os_64 = (sizeof(void *) == 8) ? true : false;
+   uint64_t total_memory;
+   uint64_t dram_size_seven_GB = 0x1B800;
+   uint64_t dram_size_three_GB = 0xB800;
+
+   if (amdgpu_smu_memory_pool_size == 0)
+   return;
+
+   if (!is_os_64) {
+   DRM_WARN("Not 64-bit OS, feature not supported\n");
+   goto def_value;
+   }
+   si_meminfo(&si);
+   total_memory = (uint64_t)si.totalram * si.mem_unit;
+
+   if ((amdgpu_smu_memory_pool_size == 1) ||
+   (amdgpu_smu_memory_pool_size == 2)) {
+   if (total_memory < dram_size_three_GB)
+   goto def_value1;
+   } else if ((amdgpu_smu_memory_pool_size == 4) ||
+   (amdgpu_smu_memory_pool_size == 8)) {
+   if (total_memory < dram_size_seven_GB)
+   goto def_value1;
+   } else {
+   DRM_WARN("Smu memory pool size not supported\n");
+   goto def_value;
+   }
+   amdgpu_smu_memory_pool_size = amdgpu_smu_memory_pool_size << 28;
+
+   return;
+
+def_value1:
+   DRM_WARN("No enough system memory\n");
+def_value:
+   amdgpu_smu_memory_pool_size = 0;
+}
+
 /**
  * amdgpu_device_check_arguments - validate module params
  *
@@ -814,6 +854,8 @@ static void amdgpu_device_check_arguments(struct 
amdgpu_device *adev)
amdgpu_vm_fragment_size = -1;
}
 
+   amdgpu_device_check_smu_prv_buffer_size(adev);
+
amdgpu_device_check_vm_size(adev);
 
amdgpu_device_check_block_size(adev);
@@ -2073,6 +2115,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
}
+
adev->accel_working = false;
cancel_delayed_work_sync(&adev->late_init_work);
/* free i2c buses */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d96f9ac..a8a51df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -130,6 +130,7 @@
 int amdgpu_lbpw = -1;
 int amdgpu_compute_multipipe = -1;
 int amdgpu_gpu_recovery = -1; /* auto */
+uint amdgpu_smu_memory_pool_size = 0;
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -311,6 +312,11 @@
 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 #endif
 
+MODULE_PARM_DESC(smu_memory_pool_size,
+   "reserve gtt for smu debug usage, 0 = disable,"
+   "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 
0444);
+
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 5f5aa5f..7d9c330 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerpl

[PATCH] drm/amdgpu: fix typo in amdgpu_vce_validate_bo

[Christian König]

Otherwise buffer placement is very restrictive and might fail.

Fixes: "drm/amdgpu: fix VCE buffer placement restrictions v2"

Signed-off-by: Christian König 
Reported-by: Deng, Emily 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 55a726a322e3..d274ae535530 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -585,8 +585,8 @@ static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser 
*p, uint32_t ib_idx,
 
for (i = 0; i < bo->placement.num_placement; ++i) {
bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
-   bo->placements[i].lpfn = bo->placements[i].fpfn ?
-   min(bo->placements[i].fpfn, lpfn) : lpfn;
+   bo->placements[i].lpfn = bo->placements[i].lpfn ?
+   min(bo->placements[i].lpfn, lpfn) : lpfn;
}
return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 }
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH libdrm] drm: fix return value

[Michel Dänzer]

Moving from the amd-gfx list to dri-devel, since this isn't amdgpu specific.


On 2018-01-16 03:54 AM, Chunming Zhou wrote:
> otherwise -ETIME is missed.
> 
> Change-Id: Ic5580a74d8027cc468c6135f8cf2f81817993423
> Signed-off-by: Chunming Zhou 
> ---
>  xf86drm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xf86drm.c b/xf86drm.c
> index 8a327170..3881bd9f 100644
> --- a/xf86drm.c
> +++ b/xf86drm.c
> @@ -4241,7 +4241,7 @@ int drmSyncobjWait(int fd, uint32_t *handles, unsigned 
> num_handles,
>  
>   ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args);
>   if (ret < 0)
> - return ret;
> + return -errno;
>  
>   if (first_signaled)
>   *first_signaled = args.first_signaled;
> 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

[Christian König]

Am 16.01.2018 um 07:18 schrieb He, Roger:

-Original Message-
From: Andrey Grodzovsky [mailto:andrey.grodzov...@amd.com]
Sent: Saturday, January 13, 2018 6:29 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; He, Roger ; 
Grodzovsky, Andrey 
Subject: [PATCH 2/2] drm/amdgpu: Use new TTM flag to avoid OOM triggering.

This to have a load time option to avoid OOM on RAM allocations.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
  3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b7c181e..1387239 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -127,6 +127,7 @@ extern int amdgpu_job_hang_limit;  extern int amdgpu_lbpw;  
extern int amdgpu_compute_multipipe;  extern int amdgpu_gpu_recovery;
+extern int amdgpu_alloc_no_oom;
  
  #ifdef CONFIG_DRM_AMDGPU_SI

  extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d96f9ac..6e98189 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -130,6 +130,7 @@ int amdgpu_job_hang_limit = 0;  int amdgpu_lbpw = -1;  int 
amdgpu_compute_multipipe = -1;  int amdgpu_gpu_recovery = -1; /* auto */
+int amdgpu_alloc_no_oom = -1; /* auto */

How about turn it on as default?


I think we can even go a step further, drop the module parameter and 
just turn it always on for amdgpu.


Christian.



Thanks
Roger(Hongbo.He)

MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");  
module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@ -285,6 +286,9 @@ 
module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);  
MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = 
auto");  module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
  
+MODULE_PARM_DESC(alloc_no_oom, "Allocate RAM without triggering OOM

+killer, (1 = enable, 0 = disable, -1 = auto");
+module_param_named(alloc_no_oom, amdgpu_alloc_no_oom, int, 0444);
+
  #ifdef CONFIG_DRM_AMDGPU_SI
  
  #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 5c4c3e0..fc27164 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -420,6 +420,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, 
 #endif
  
  	bo->tbo.bdev = &adev->mman.bdev;

+
+   if (amdgpu_alloc_no_oom == 1)
+   bo->tbo.bdev->no_retry = true;
+
amdgpu_ttm_placement_from_domain(bo, domain);
  
  	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,

--
2.7.4

___
dri-devel mailing list
dri-de...@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/2] drm/ttm: Allow page allocations w/o triggering OOM..

[Christian König]

Am 16.01.2018 um 07:02 schrieb He, Roger:


-Original Message-
From: Andrey Grodzovsky [mailto:andrey.grodzov...@amd.com]
Sent: Saturday, January 13, 2018 6:29 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; He, Roger ; 
Grodzovsky, Andrey 
Subject: [PATCH 1/2] drm/ttm: Allow page allocations w/o triggering OOM..

This to allow drivers to choose to avoid OOM invocation and handle page 
allocation failures instead.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/ttm/ttm_bo.c |  3 +++
  drivers/gpu/drm/ttm/ttm_page_alloc.c |  6 ++
  drivers/gpu/drm/ttm/ttm_page_alloc_dma.c |  3 +++
  drivers/gpu/drm/ttm/ttm_tt.c | 13 +++--
  include/drm/ttm/ttm_bo_api.h |  1 +
  include/drm/ttm/ttm_bo_driver.h  |  4 
  6 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 
2eb71ff..f32aab1 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -234,6 +234,9 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, 
bool zero_alloc)
if (bdev->need_dma32)
page_flags |= TTM_PAGE_FLAG_DMA32;
  
+	if (bdev->no_retry)

+   page_flags |= TTM_PAGE_FLAG_NO_RETRY;
+
switch (bo->type) {
case ttm_bo_type_device:
if (zero_alloc)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 0eab24e..f34c843 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -741,6 +741,9 @@ static int ttm_page_pool_get_pages(struct ttm_page_pool 
*pool,
if (ttm_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
  
+		if (ttm_flags & TTM_PAGE_FLAG_NO_RETRY)

+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
/* ttm_alloc_new_pages doesn't reference pool so we can run
 * multiple requests in parallel.
 **/
@@ -893,6 +896,9 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
if (flags & TTM_PAGE_FLAG_ZERO_ALLOC)
gfp_flags |= __GFP_ZERO;
  
+		if (flags & TTM_PAGE_FLAG_NO_RETRY)

+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
if (flags & TTM_PAGE_FLAG_DMA32)
gfp_flags |= GFP_DMA32;
else
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index c7f01a4..6949ef7 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -920,6 +920,9 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt 
*ttm_dma, bool huge)
gfp_flags &= ~__GFP_COMP;
}
  
+	if (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY)

+   gfp_flags |= __GFP_RETRY_MAYFAIL;
+
return gfp_flags;
  }
  
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 5a046a3..9e4d43d 100644

--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -301,7 +301,11 @@ int ttm_tt_swapin(struct ttm_tt *ttm)
swap_space = swap_storage->f_mapping;
  
  	for (i = 0; i < ttm->num_pages; ++i) {

-   from_page = shmem_read_mapping_page(swap_space, i);
+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ? 
__GFP_RETRY_MAYFAIL : 0);
+   from_page = shmem_read_mapping_page_gfp(swap_space, i, 
gfp_mask);
+
if (IS_ERR(from_page)) {
ret = PTR_ERR(from_page);
goto out_err;
@@ -350,10 +354,15 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file 
*persistent_swap_storage)
swap_space = swap_storage->f_mapping;
  
  	for (i = 0; i < ttm->num_pages; ++i) {

+   gfp_t gfp_mask = mapping_gfp_mask(swap_space);
+
+   gfp_mask |= (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY ?
+__GFP_RETRY_MAYFAIL : 0);
+
from_page = ttm->pages[i];
if (unlikely(from_page == NULL))
continue;
-   to_page = shmem_read_mapping_page(swap_space, i);
+
+   to_page = shmem_read_mapping_page_gfp(swap_space, i, gfp_mask);
if (IS_ERR(to_page)) {
ret = PTR_ERR(to_page);
goto out_err;
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index 
2cd025c..099f24b 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -176,6 +176,7 @@ struct ttm_buffer_object {
unsigned long num_pages;
size_t acc_size;
  
+

Please remove this newline here.
Apart from that,   this patch is Reviewed-by: Roger He 


Jup agree, apart from the nit pick the patch is Reviewed-by: Christian 
König  as well.


Christian.



T