RE: [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel

[Zhu, Rex]

Hi Andrey,

Sorry for the confusion.
I just need to push a bunch of patches that conflict with  your patch.
So apply your patch first.


Best Regards
Rex

From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
Andrey Grodzovsky
Sent: Friday, March 16, 2018 12:20 AM
To: Deucher, Alexander; amd-gfx@lists.freedesktop.org; 
ckoenig.leichtzumer...@gmail.com; Zhu, Rex
Subject: Re: [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in 
amdgpu_bo_create_kernel


That explains the merge conflict that surprised me :)



Thanks,

Andrey

On 03/15/2018 12:18 PM, Deucher, Alexander wrote:

For the series:

Reviewed-by: Alex Deucher 

I think Rex already applied the second one.


From: amd-gfx 

 on behalf of Andrey Grodzovsky 

Sent: Thursday, March 15, 2018 12:15 PM
To: amd-gfx@lists.freedesktop.org; 
ckoenig.leichtzumer...@gmail.com; Zhu, 
Rex
Cc: Grodzovsky, Andrey
Subject: [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in 
amdgpu_bo_create_kernel

and amdgpu_bo_create_reserved.

Signed-off-by: Andrey Grodzovsky 

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 48e0115..ac1fa33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -171,13 +171,15 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo 
*abo, u32 domain)
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use, and returns it still
  * reserved.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
@@ -240,12 +242,14 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr:  used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
--
2.7.4

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[PATCH] drm/amdgpu: Delete dead code when early init

[Rex Zhu]

Change-Id: I4648ad6885f3884688d8bb90ea33be7f6ad69810
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 5 -
 drivers/gpu/drm/amd/amdgpu/vi.c| 5 -
 2 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c6e8573..242c30b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -608,7 +608,6 @@ static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 
 static int soc15_common_early_init(void *handle)
 {
-   bool psp_enabled = false;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
adev->smc_rreg = NULL;
@@ -626,10 +625,6 @@ static int soc15_common_early_init(void *handle)
 
adev->asic_funcs = &soc15_asic_funcs;
 
-   if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
-   (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
-   psp_enabled = true;
-
adev->rev_id = soc15_get_rev_id(adev);
adev->external_rev_id = 0xFF;
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index e7fb165..126f127 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -896,7 +896,6 @@ static void vi_invalidate_hdp(struct amdgpu_device *adev,
 
 static int vi_common_early_init(void *handle)
 {
-   bool smc_enabled = false;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
if (adev->flags & AMD_IS_APU) {
@@ -917,10 +916,6 @@ static int vi_common_early_init(void *handle)
 
adev->asic_funcs = &vi_asic_funcs;
 
-   if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
-   (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
-   smc_enabled = true;
-
adev->rev_id = vi_get_rev_id(adev);
adev->external_rev_id = 0xFF;
switch (adev->asic_type) {
-- 
1.9.1

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[PATCH] drm/amdgpu: no job timeout setting on compute queues

[Evan Quan]

Under some heavy computing test(dgemm) environment, it may takes
the asic over 50+ seconds to finish the dispatched single job
which will trigger the timeout. It's quite annoying although it
does not seem to bring any real problems.
As a quick workround, we choose to not enfoce the timeout
setting on compute queues.

Change-Id: I210011a90898617367e897a90e9f8fb2639281a3
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 008e198..455a81e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -435,7 +435,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
   num_hw_submission, amdgpu_job_hang_limit,
-  msecs_to_jiffies(amdgpu_lockup_timeout), 
ring->name);
+  (ring->funcs->type == 
AMDGPU_RING_TYPE_COMPUTE) ?
+  MAX_SCHEDULE_TIMEOUT : 
msecs_to_jiffies(amdgpu_lockup_timeout),
+  ring->name);
if (r) {
DRM_ERROR("Failed to create scheduler on ring %s.\n",
  ring->name);
-- 
2.7.4

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Re: [PATCH] drm/amdgpu - Disable all irqs before disabling all CRTCs

[Andrey Grodzovsky]

Sorry for jumping in late,  but did you verify MST with this change ?

Just a guess but MST relies on hpd_rx interrupt for messages and 
disabling to early might have impact. Maybe trying unload/reload with 
MST display to be sure ?


Andrey


On 03/15/2018 06:23 PM, Alex Deucher wrote:

On Thu, Mar 15, 2018 at 5:11 PM,   wrote:

From: Mikita Lipski 

By moving amdgpu_irq_disable_all earlier in the sequence
fixes an issue with disabling pflip interrupts:

*ERROR* dal_irq_service_dummy_ack: called for non-implemented irq source

Earlier patch fixed a memory corruption and revealed irq
warnings.This way it seems to be there no obvious issues
with unloading the module.

Signed-off-by: Mikita Lipski 

Reviewed-by: Alex Deucher 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0b798cb..0d01735 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1432,9 +1432,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
 int i, r;

 amdgpu_amdkfd_device_fini(adev);
-   /* disable all interrupts */
-   amdgpu_irq_disable_all(adev);
-
 /* need to disable SMC first */
 for (i = 0; i < adev->num_ip_blocks; i++) {
 if (!adev->ip_blocks[i].status.hw)
@@ -2082,6 +2079,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)

 DRM_INFO("amdgpu: finishing device.\n");
 adev->shutdown = true;
+   /* disable all interrupts */
+   amdgpu_irq_disable_all(adev);
 if (adev->mode_info.mode_config_initialized){
 if (!amdgpu_device_has_dc_support(adev))
 drm_crtc_force_disable_all(adev->ddev);
--
2.7.4

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Re: [PATCH] drm/amdgpu - Disable all irqs before disabling all CRTCs

[Alex Deucher]

On Thu, Mar 15, 2018 at 5:11 PM,   wrote:
> From: Mikita Lipski 
>
> By moving amdgpu_irq_disable_all earlier in the sequence
> fixes an issue with disabling pflip interrupts:
>
> *ERROR* dal_irq_service_dummy_ack: called for non-implemented irq source
>
> Earlier patch fixed a memory corruption and revealed irq
> warnings.This way it seems to be there no obvious issues
> with unloading the module.
>
> Signed-off-by: Mikita Lipski 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 0b798cb..0d01735 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1432,9 +1432,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
> *adev)
> int i, r;
>
> amdgpu_amdkfd_device_fini(adev);
> -   /* disable all interrupts */
> -   amdgpu_irq_disable_all(adev);
> -
> /* need to disable SMC first */
> for (i = 0; i < adev->num_ip_blocks; i++) {
> if (!adev->ip_blocks[i].status.hw)
> @@ -2082,6 +2079,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
>
> DRM_INFO("amdgpu: finishing device.\n");
> adev->shutdown = true;
> +   /* disable all interrupts */
> +   amdgpu_irq_disable_all(adev);
> if (adev->mode_info.mode_config_initialized){
> if (!amdgpu_device_has_dc_support(adev))
> drm_crtc_force_disable_all(adev->ddev);
> --
> 2.7.4
>
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[PATCH 20/20] drm/amdgpu: Add userptr support for KFD

[Felix Kuehling]

This adds support for allocating, mapping, unmapping and freeing
userptr BOs, and for handling MMU notifiers.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   |  11 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 566 ++-
 2 files changed, 553 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 83e0c5c..c3024b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "amdgpu_sync.h"
@@ -59,7 +60,9 @@ struct kgd_mem {
 
uint32_t mapping_flags;
 
+   atomic_t invalid;
struct amdkfd_process_info *process_info;
+   struct page **user_pages;
 
struct amdgpu_sync sync;
 
@@ -84,6 +87,9 @@ struct amdkfd_process_info {
struct list_head vm_list_head;
/* List head for all KFD BOs that belong to a KFD process. */
struct list_head kfd_bo_list;
+   /* List of userptr BOs that are valid or invalid */
+   struct list_head userptr_valid_list;
+   struct list_head userptr_inval_list;
/* Lock to protect kfd_bo_list */
struct mutex lock;
 
@@ -91,6 +97,11 @@ struct amdkfd_process_info {
unsigned int n_vms;
/* Eviction Fence */
struct amdgpu_amdkfd_fence *eviction_fence;
+
+   /* MMU-notifier related fields */
+   atomic_t evicted_bos;
+   struct delayed_work restore_userptr_work;
+   struct pid *pid;
 };
 
 int amdgpu_amdkfd_init(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 2d6f13a..5057e64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -23,6 +23,7 @@
 #define pr_fmt(fmt) "kfd2kgd: " fmt
 
 #include 
+#include 
 #include 
 #include "amdgpu_object.h"
 #include "amdgpu_vm.h"
@@ -33,10 +34,20 @@
  */
 #define VI_BO_SIZE_ALIGN (0x8000)
 
+/* BO flag to indicate a KFD userptr BO */
+#define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
+
+/* Userptr restore delay, just long enough to allow consecutive VM
+ * changes to accumulate
+ */
+#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
+
 /* Impose limit on how much memory KFD can use */
 static struct {
uint64_t max_system_mem_limit;
+   uint64_t max_userptr_mem_limit;
int64_t system_mem_used;
+   int64_t userptr_mem_used;
spinlock_t mem_limit_lock;
 } kfd_mem_limit;
 
@@ -57,6 +68,7 @@ static const char * const domain_bit_to_string[] = {
 
 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
 
+static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
 
 
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
@@ -90,8 +102,10 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
 
spin_lock_init(&kfd_mem_limit.mem_limit_lock);
kfd_mem_limit.max_system_mem_limit = (mem >> 1) - (mem >> 3);
-   pr_debug("Kernel memory limit %lluM\n",
-   (kfd_mem_limit.max_system_mem_limit >> 20));
+   kfd_mem_limit.max_userptr_mem_limit = mem - (mem >> 2);
+   pr_debug("Kernel memory limit %lluM, userptr limit %lluM\n",
+   (kfd_mem_limit.max_system_mem_limit >> 20),
+   (kfd_mem_limit.max_userptr_mem_limit >> 20));
 }
 
 static int amdgpu_amdkfd_reserve_system_mem_limit(struct amdgpu_device *adev,
@@ -111,6 +125,16 @@ static int amdgpu_amdkfd_reserve_system_mem_limit(struct 
amdgpu_device *adev,
goto err_no_mem;
}
kfd_mem_limit.system_mem_used += (acc_size + size);
+   } else if (domain == AMDGPU_GEM_DOMAIN_CPU) {
+   if ((kfd_mem_limit.system_mem_used + acc_size >
+   kfd_mem_limit.max_system_mem_limit) ||
+   (kfd_mem_limit.userptr_mem_used + (size + acc_size) >
+   kfd_mem_limit.max_userptr_mem_limit)) {
+   ret = -ENOMEM;
+   goto err_no_mem;
+   }
+   kfd_mem_limit.system_mem_used += acc_size;
+   kfd_mem_limit.userptr_mem_used += size;
}
 err_no_mem:
spin_unlock(&kfd_mem_limit.mem_limit_lock);
@@ -126,10 +150,16 @@ static void unreserve_system_mem_limit(struct 
amdgpu_device *adev,
   sizeof(struct amdgpu_bo));
 
spin_lock(&kfd_mem_limit.mem_limit_lock);
-   if (domain == AMDGPU_GEM_DOMAIN_GTT)
+   if (domain == AMDGPU_GEM_DOMAIN_GTT) {
kfd_mem_limit.system_mem_used -= (acc_size + size);
+   } else if (domain == AMDGPU_GEM_DOMAIN_CPU) {
+   kfd_mem_limit.system_mem_used -= acc_size;
+   kfd_mem_limit.userptr_mem_used -= size;
+   }
WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
  

[PATCH 16/20] drm/amdgpu: Enable amdgpu_ttm_tt_get_user_pages in worker threads

[Felix Kuehling]

This commit allows amdgpu_ttm_tt_get_user_pages to work in a worker
thread rather than regular process context. This will be used when
KFD userptr BOs are restored after an MMU-notifier eviction.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 30 +-
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c2fae04..f1b893c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -689,7 +689,7 @@ struct amdgpu_ttm_tt {
struct ttm_dma_tt   ttm;
u64 offset;
uint64_tuserptr;
-   struct mm_struct*usermm;
+   struct task_struct  *usertask;
uint32_tuserflags;
spinlock_t  guptasklock;
struct list_headguptasks;
@@ -700,14 +700,18 @@ struct amdgpu_ttm_tt {
 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 {
struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct mm_struct *mm = gtt->usertask->mm;
unsigned int flags = 0;
unsigned pinned = 0;
int r;
 
+   if (!mm) /* Happens during process shutdown */
+   return -ESRCH;
+
if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
flags |= FOLL_WRITE;
 
-   down_read(¤t->mm->mmap_sem);
+   down_read(&mm->mmap_sem);
 
if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
/* check that we only use anonymous memory
@@ -715,9 +719,9 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct 
page **pages)
unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
struct vm_area_struct *vma;
 
-   vma = find_vma(gtt->usermm, gtt->userptr);
+   vma = find_vma(mm, gtt->userptr);
if (!vma || vma->vm_file || vma->vm_end < end) {
-   up_read(¤t->mm->mmap_sem);
+   up_read(&mm->mmap_sem);
return -EPERM;
}
}
@@ -733,7 +737,12 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, 
struct page **pages)
list_add(&guptask.list, >t->guptasks);
spin_unlock(>t->guptasklock);
 
-   r = get_user_pages(userptr, num_pages, flags, p, NULL);
+   if (mm == current->mm)
+   r = get_user_pages(userptr, num_pages, flags, p, NULL);
+   else
+   r = get_user_pages_remote(gtt->usertask,
+   mm, userptr, num_pages,
+   flags, p, NULL, NULL);
 
spin_lock(>t->guptasklock);
list_del(&guptask.list);
@@ -746,12 +755,12 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, 
struct page **pages)
 
} while (pinned < ttm->num_pages);
 
-   up_read(¤t->mm->mmap_sem);
+   up_read(&mm->mmap_sem);
return 0;
 
 release_pages:
release_pages(pages, pinned);
-   up_read(¤t->mm->mmap_sem);
+   up_read(&mm->mmap_sem);
return r;
 }
 
@@ -1072,7 +1081,7 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, 
uint64_t addr,
return -EINVAL;
 
gtt->userptr = addr;
-   gtt->usermm = current->mm;
+   gtt->usertask = current->group_leader;
gtt->userflags = flags;
spin_lock_init(>t->guptasklock);
INIT_LIST_HEAD(>t->guptasks);
@@ -1089,7 +1098,10 @@ struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt 
*ttm)
if (gtt == NULL)
return NULL;
 
-   return gtt->usermm;
+   if (gtt->usertask == NULL)
+   return NULL;
+
+   return gtt->usertask->mm;
 }
 
 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
-- 
2.7.4

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[PATCH 09/20] drm/amdkfd: Add per-process IDR for buffer handles

[Felix Kuehling]

Also used for cleaning up on process termination.

v2: Refactored cleanup on process termination

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 11 +
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 73 
 2 files changed, 84 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 0d5d924..b2b5ef8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -543,6 +543,9 @@ struct kfd_process_device {
struct file *drm_file;
void *vm;
 
+   /* GPUVM allocations storage */
+   struct idr alloc_idr;
+
/* Flag used to tell the pdd has dequeued from the dqm.
 * This is used to prevent dev->dqm->ops.process_termination() from
 * being called twice when it is already called in IOMMU callback
@@ -678,6 +681,14 @@ struct kfd_process_device 
*kfd_create_process_device_data(struct kfd_dev *dev,
 int kfd_reserved_mem_mmap(struct kfd_process *process,
  struct vm_area_struct *vma);
 
+/* KFD process API for creating and translating handles */
+int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd,
+   void *mem);
+void *kfd_process_device_translate_handle(struct kfd_process_device *p,
+   int handle);
+void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd,
+   int handle);
+
 /* Process device data iterator */
 struct kfd_process_device *kfd_get_first_process_device_data(
struct kfd_process *p);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 6618aaa..a2ae023 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -150,6 +150,40 @@ void kfd_unref_process(struct kfd_process *p)
kref_put(&p->ref, kfd_process_ref_release);
 }
 
+static void kfd_process_device_free_bos(struct kfd_process_device *pdd)
+{
+   struct kfd_process *p = pdd->process;
+   void *mem;
+   int id;
+
+   /*
+* Remove all handles from idr and release appropriate
+* local memory object
+*/
+   idr_for_each_entry(&pdd->alloc_idr, mem, id) {
+   struct kfd_process_device *peer_pdd;
+
+   list_for_each_entry(peer_pdd, &p->per_device_data,
+   per_device_list) {
+   if (!peer_pdd->vm)
+   continue;
+   peer_pdd->dev->kfd2kgd->unmap_memory_to_gpu(
+   peer_pdd->dev->kgd, mem, peer_pdd->vm);
+   }
+
+   pdd->dev->kfd2kgd->free_memory_of_gpu(pdd->dev->kgd, mem);
+   kfd_process_device_remove_obj_handle(pdd, id);
+   }
+}
+
+static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p)
+{
+   struct kfd_process_device *pdd;
+
+   list_for_each_entry(pdd, &p->per_device_data, per_device_list)
+   kfd_process_device_free_bos(pdd);
+}
+
 static void kfd_process_destroy_pdds(struct kfd_process *p)
 {
struct kfd_process_device *pdd, *temp;
@@ -171,6 +205,8 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
free_pages((unsigned long)pdd->qpd.cwsr_kaddr,
get_order(KFD_CWSR_TBA_TMA_SIZE));
 
+   idr_destroy(&pdd->alloc_idr);
+
kfree(pdd);
}
 }
@@ -187,6 +223,8 @@ static void kfd_process_wq_release(struct work_struct *work)
 
kfd_iommu_unbind_process(p);
 
+   kfd_process_free_outstanding_kfd_bos(p);
+
kfd_process_destroy_pdds(p);
dma_fence_put(p->ef);
 
@@ -371,6 +409,7 @@ static struct kfd_process *create_process(const struct 
task_struct *thread,
return process;
 
 err_init_cwsr:
+   kfd_process_free_outstanding_kfd_bos(process);
kfd_process_destroy_pdds(process);
 err_init_apertures:
pqm_uninit(&process->pqm);
@@ -421,6 +460,9 @@ struct kfd_process_device 
*kfd_create_process_device_data(struct kfd_dev *dev,
pdd->already_dequeued = false;
list_add(&pdd->per_device_list, &p->per_device_data);
 
+   /* Init idr used for memory handle translation */
+   idr_init(&pdd->alloc_idr);
+
return pdd;
 }
 
@@ -520,6 +562,37 @@ bool kfd_has_process_device_data(struct kfd_process *p)
return !(list_empty(&p->per_device_data));
 }
 
+/* Create specific handle mapped to mem from process local memory idr
+ * Assumes that the process lock is held.
+ */
+int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd,
+   void *mem)
+{
+   return idr_alloc(&pdd->alloc_idr, mem, 0, 0, GFP_KERNEL);
+}
+
+/* Translate specific handle from proces

[PATCH 13/20] drm/amdkfd: Kmap event page for dGPUs

[Felix Kuehling]

The events page must be accessible in user mode by the GPU and CPU
as well as in kernel mode by the CPU. On dGPUs user mode virtual
addresses are managed by the Thunk's GPU memory allocation code.
Therefore we can't allocate the memory in kernel mode like we do
on APUs. But KFD still needs to map the memory for kernel access.
To facilitate this, the Thunk provides the buffer handle of the
events page to KFD when creating the first event.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 56 
 drivers/gpu/drm/amd/amdkfd/kfd_events.c  | 31 --
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h|  2 ++
 3 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index a563ff2..ec0b2c0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -923,6 +923,58 @@ static int kfd_ioctl_create_event(struct file *filp, 
struct kfd_process *p,
struct kfd_ioctl_create_event_args *args = data;
int err;
 
+   /* For dGPUs the event page is allocated in user mode. The
+* handle is passed to KFD with the first call to this IOCTL
+* through the event_page_offset field.
+*/
+   if (args->event_page_offset) {
+   struct kfd_dev *kfd;
+   struct kfd_process_device *pdd;
+   void *mem, *kern_addr;
+   uint64_t size;
+
+   if (p->signal_page) {
+   pr_err("Event page is already set\n");
+   return -EINVAL;
+   }
+
+   kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset));
+   if (!kfd) {
+   pr_err("Getting device by id failed in %s\n", __func__);
+   return -EINVAL;
+   }
+
+   mutex_lock(&p->mutex);
+   pdd = kfd_bind_process_to_device(kfd, p);
+   if (IS_ERR(pdd)) {
+   err = PTR_ERR(pdd);
+   goto out_unlock;
+   }
+
+   mem = kfd_process_device_translate_handle(pdd,
+   GET_IDR_HANDLE(args->event_page_offset));
+   if (!mem) {
+   pr_err("Can't find BO, offset is 0x%llx\n",
+  args->event_page_offset);
+   err = -EINVAL;
+   goto out_unlock;
+   }
+   mutex_unlock(&p->mutex);
+
+   err = kfd->kfd2kgd->map_gtt_bo_to_kernel(kfd->kgd,
+   mem, &kern_addr, &size);
+   if (err) {
+   pr_err("Failed to map event page to kernel\n");
+   return err;
+   }
+
+   err = kfd_event_page_set(p, kern_addr, size);
+   if (err) {
+   pr_err("Failed to set event page\n");
+   return err;
+   }
+   }
+
err = kfd_event_create(filp, p, args->event_type,
args->auto_reset != 0, args->node_id,
&args->event_id, &args->event_trigger_data,
@@ -930,6 +982,10 @@ static int kfd_ioctl_create_event(struct file *filp, 
struct kfd_process *p,
&args->event_slot_index);
 
return err;
+
+out_unlock:
+   mutex_unlock(&p->mutex);
+   return err;
 }
 
 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 6fb9c0d..4890a90 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -52,6 +52,7 @@ struct kfd_event_waiter {
 struct kfd_signal_page {
uint64_t *kernel_address;
uint64_t __user *user_address;
+   bool need_to_free_pages;
 };
 
 
@@ -79,6 +80,7 @@ static struct kfd_signal_page *allocate_signal_page(struct 
kfd_process *p)
   KFD_SIGNAL_EVENT_LIMIT * 8);
 
page->kernel_address = backing_store;
+   page->need_to_free_pages = true;
pr_debug("Allocated new event signal page at %p, for process %p\n",
page, p);
 
@@ -269,8 +271,9 @@ static void shutdown_signal_page(struct kfd_process *p)
struct kfd_signal_page *page = p->signal_page;
 
if (page) {
-   free_pages((unsigned long)page->kernel_address,
-   get_order(KFD_SIGNAL_EVENT_LIMIT * 8));
+   if (page->need_to_free_pages)
+   free_pages((unsigned long)page->kernel_address,
+  get_order(KFD_SIGNAL_EVENT_LIMIT * 8));
kfree(page);
}
 }
@@ -292,6 +295,30 @@ static bool event_can_be_cpu_signaled(const struct 
kfd_event *ev)
retu

[PATCH 15/20] drm/amdgpu: Add MMU notifier type for KFD userptr

[Felix Kuehling]

This commit adds the notion of MMU notifier types GFX and HSA. GFX
continues to work like MMU notifiers did before. HSA adds support for
KFD userptr BOs. The implementation of KFD userptr eviction is a stub
for now.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c |  7 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c   | 94 
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h   | 11 ++-
 5 files changed, 97 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index c2c2bea..83e0c5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -104,6 +104,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
 
+int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
uint32_t vmid, uint64_t gpu_addr,
uint32_t *ib_cmd, uint32_t ib_len);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 2f42c60..2d6f13a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1418,6 +1418,13 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct 
kgd_dev *kgd,
return ret;
 }
 
+int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
+   struct mm_struct *mm)
+{
+   /* TODO */
+   return 0;
+}
+
 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
  *   KFD process identified by process_info
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index dc34b50..8e66f37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -536,7 +536,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
if (p->bo_list) {
amdgpu_bo_list_get_list(p->bo_list, &p->validated);
if (p->bo_list->first_userptr != p->bo_list->num_entries)
-   p->mn = amdgpu_mn_get(p->adev);
+   p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
}
 
INIT_LIST_HEAD(&duplicates);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index bd67f4c..f2ed18e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -36,12 +36,14 @@
 #include 
 
 #include "amdgpu.h"
+#include "amdgpu_amdkfd.h"
 
 struct amdgpu_mn {
/* constant after initialisation */
struct amdgpu_device*adev;
struct mm_struct*mm;
struct mmu_notifier mn;
+   enum amdgpu_mn_type type;
 
/* only used on destruction */
struct work_struct  work;
@@ -185,7 +187,7 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node 
*node,
 }
 
 /**
- * amdgpu_mn_invalidate_range_start - callback to notify about mm change
+ * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change
  *
  * @mn: our notifier
  * @mn: the mm this callback is about
@@ -195,10 +197,10 @@ static void amdgpu_mn_invalidate_node(struct 
amdgpu_mn_node *node,
  * We block for all BOs between start and end to be idle and
  * unmap them by move them into system domain again.
  */
-static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
-struct mm_struct *mm,
-unsigned long start,
-unsigned long end)
+static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn,
+struct mm_struct *mm,
+unsigned long start,
+unsigned long end)
 {
struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
struct interval_tree_node *it;
@@ -220,6 +222,49 @@ static void amdgpu_mn_invalidate_range_start(struct 
mmu_notifier *mn,
 }
 
 /**
+ * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change
+ *
+ * @mn: our notifier
+ * @mn: the mm this callback is about
+ * @start: start of updated range
+ * @end: end of updated range
+ *
+ * We temporarily evict all BOs between start and end. This
+ * necessitates evicting all user-mode queues of the process. The BOs
+ * are restorted in amdgpu_mn_invalidate_range_end_hsa.
+ */
+static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn,

[PATCH 14/20] drm/amdkfd: Add module option for testing large-BAR functionality

[Felix Kuehling]

Simulate large-BAR system by exporting only visible memory. This
limits the amount of available VRAM to the size of the BAR, but
enables CPU access to VRAM.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c| 3 +++
 drivers/gpu/drm/amd/amdkfd/kfd_module.c  | 5 +
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 6 ++
 4 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index ec0b2c0..cd679cf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1151,6 +1151,11 @@ bool kfd_dev_is_large_bar(struct kfd_dev *dev)
 {
struct kfd_local_mem_info mem_info;
 
+   if (debug_largebar) {
+   pr_debug("Simulate large-bar allocation on non large-bar 
machine\n");
+   return true;
+   }
+
if (dev->device_info->needs_iommu_device)
return false;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 7493f47..3c6c4cdd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1117,6 +1117,9 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image,
sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
sub_type_hdr->length);
 
+   if (debug_largebar)
+   local_mem_info.local_mem_size_private = 0;
+
if (local_mem_info.local_mem_size_private == 0)
ret = kfd_fill_gpu_memory_affinity(&avail_size,
kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 65574c6..b0acb06 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -71,6 +71,11 @@ module_param(send_sigterm, int, 0444);
 MODULE_PARM_DESC(send_sigterm,
"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = 
enable)");
 
+int debug_largebar;
+module_param(debug_largebar, int, 0444);
+MODULE_PARM_DESC(debug_largebar,
+   "Debug large-bar flag used to simulate large-bar capability on 
non-large bar machine (0 = disable, 1 = enable)");
+
 int ignore_crat;
 module_param(ignore_crat, int, 0444);
 MODULE_PARM_DESC(ignore_crat,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index aa93863..db27f9f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -105,6 +105,12 @@ extern int cwsr_enable;
 extern int send_sigterm;
 
 /*
+ * This kernel module is used to simulate large bar machine on non-large bar
+ * enabled machines.
+ */
+extern int debug_largebar;
+
+/*
  * Ignore CRAT table during KFD initialization, can be used to work around
  * broken CRAT tables on some AMD systems
  */
-- 
2.7.4

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[PATCH 18/20] drm/amdkfd: GFP_NOIO while holding locks taken in MMU notifier

[Felix Kuehling]

When an MMU notifier runs in memory reclaim context, it can deadlock
trying to take locks that are already held in the thread causing the
memory reclaim. The solution is to avoid memory reclaim while holding
locks that are taken in MMU notifiers by using GFP_NOIO.

This commit fixes memory allocations done while holding the dqm->lock
which is needed in the MMU notifier (dqm->ops.evict_process_queues).

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c  | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 334669996..0434f65 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -652,7 +652,7 @@ int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int 
size,
if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
return -ENOMEM;
 
-   *mem_obj = kmalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
+   *mem_obj = kmalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
if ((*mem_obj) == NULL)
return -ENOMEM;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index c00c325..2bc49c6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -412,7 +412,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE 
type,
if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
return NULL;
 
-   mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
+   mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
if (!mqd)
return NULL;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index 89e4242..481307b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -394,7 +394,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE 
type,
if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
return NULL;
 
-   mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
+   mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
if (!mqd)
return NULL;
 
-- 
2.7.4

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[PATCH 19/20] drm/amdkfd: Add quiesce_mm and resume_mm to kgd2kfd_calls

[Felix Kuehling]

These interfaces allow KGD to stop and resume all GPU user mode queue
access to a process address space. This is needed for handling MMU
notifiers of userptrs mapped for GPU access in KFD VMs.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 38 +
 drivers/gpu/drm/amd/amdkfd/kfd_module.c |  2 ++
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h   |  4 +++
 drivers/gpu/drm/amd/amdkfd/kfd_process.c| 10 +++
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h |  6 
 5 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 0434f65..7b57995 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -541,6 +541,44 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void 
*ih_ring_entry)
spin_unlock(&kfd->interrupt_lock);
 }
 
+int kgd2kfd_quiesce_mm(struct mm_struct *mm)
+{
+   struct kfd_process *p;
+   int r;
+
+   /* Because we are called from arbitrary context (workqueue) as opposed
+* to process context, kfd_process could attempt to exit while we are
+* running so the lookup function increments the process ref count.
+*/
+   p = kfd_lookup_process_by_mm(mm);
+   if (!p)
+   return -ESRCH;
+
+   r = kfd_process_evict_queues(p);
+
+   kfd_unref_process(p);
+   return r;
+}
+
+int kgd2kfd_resume_mm(struct mm_struct *mm)
+{
+   struct kfd_process *p;
+   int r;
+
+   /* Because we are called from arbitrary context (workqueue) as opposed
+* to process context, kfd_process could attempt to exit while we are
+* running so the lookup function increments the process ref count.
+*/
+   p = kfd_lookup_process_by_mm(mm);
+   if (!p)
+   return -ESRCH;
+
+   r = kfd_process_restore_queues(p);
+
+   kfd_unref_process(p);
+   return r;
+}
+
 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
  *   prepare for safe eviction of KFD BOs that belong to the specified
  *   process.
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index b0acb06..d5caa4a5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -43,6 +43,8 @@ static const struct kgd2kfd_calls kgd2kfd = {
.interrupt  = kgd2kfd_interrupt,
.suspend= kgd2kfd_suspend,
.resume = kgd2kfd_resume,
+   .quiesce_mm = kgd2kfd_quiesce_mm,
+   .resume_mm  = kgd2kfd_resume_mm,
.schedule_evict_and_restore_process =
  kgd2kfd_schedule_evict_and_restore_process,
 };
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index db27f9f..33c188c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -512,6 +512,8 @@ struct qcm_process_device {
 /* Approx. time before evicting the process again */
 #define PROCESS_ACTIVE_TIME_MS 10
 
+int kgd2kfd_quiesce_mm(struct mm_struct *mm);
+int kgd2kfd_resume_mm(struct mm_struct *mm);
 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
   struct dma_fence *fence);
 
@@ -681,6 +683,8 @@ struct kfd_process *kfd_get_process(const struct 
task_struct *);
 struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid);
 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);
 void kfd_unref_process(struct kfd_process *p);
+int kfd_process_evict_queues(struct kfd_process *p);
+int kfd_process_restore_queues(struct kfd_process *p);
 void kfd_suspend_all_processes(void);
 int kfd_resume_all_processes(void);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index fbf58e9..42e5b41 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -786,7 +786,7 @@ struct kfd_process *kfd_lookup_process_by_mm(const struct 
mm_struct *mm)
  * Eviction is reference-counted per process-device. This means multiple
  * evictions from different sources can be nested safely.
  */
-static int process_evict_queues(struct kfd_process *p)
+int kfd_process_evict_queues(struct kfd_process *p)
 {
struct kfd_process_device *pdd;
int r = 0;
@@ -822,7 +822,7 @@ static int process_evict_queues(struct kfd_process *p)
 }
 
 /* process_restore_queues - Restore all user queues of a process */
-static  int process_restore_queues(struct kfd_process *p)
+int kfd_process_restore_queues(struct kfd_process *p)
 {
struct kfd_process_device *pdd;
int r, ret = 0;
@@ -864,7 +864,7 @@ static void evict_process_worker(struct work_struct *work)
flush_delayed_work(&p->restore_work);
 
pr_debug("Started evicting pasid %d\n", p->pasid

[PATCH 03/20] drm/amdgpu: Add helper to turn an existing VM into a compute VM

[Felix Kuehling]

v2: Removed updating and checking of vm->vm_context
v3: Enable amdgpu_vm_clear_bo in amdgpu_vm_make_compute

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 67 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  1 +
 2 files changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0b237e0..bdf961a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2462,6 +2462,73 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 }
 
 /**
+ * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
+ *
+ * This only works on GFX VMs that don't have any BOs added and no
+ * page tables allocated yet.
+ *
+ * Changes the following VM parameters:
+ * - use_cpu_for_update
+ * - pte_supports_ats
+ * - pasid (old PASID is released, because compute manages its own PASIDs)
+ *
+ * Reinitializes the page directory to reflect the changed ATS
+ * setting. May leave behind an unused shadow BO for the page
+ * directory when switching from SDMA updates to CPU updates.
+ *
+ * Returns 0 for success, -errno for errors.
+ */
+int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+{
+   bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
+   int r;
+
+   r = amdgpu_bo_reserve(vm->root.base.bo, true);
+   if (r)
+   return r;
+
+   /* Sanity checks */
+   if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
+   r = -EINVAL;
+   goto error;
+   }
+
+   /* Check if PD needs to be reinitialized and do it before
+* changing any other state, in case it fails.
+*/
+   if (pte_support_ats != vm->pte_support_ats) {
+   r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
+  adev->vm_manager.root_level,
+  pte_support_ats);
+   if (r)
+   goto error;
+   }
+
+   /* Update VM state */
+   vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
+   AMDGPU_VM_USE_CPU_FOR_COMPUTE);
+   vm->pte_support_ats = pte_support_ats;
+   DRM_DEBUG_DRIVER("VM update mode is %s\n",
+vm->use_cpu_for_update ? "CPU" : "SDMA");
+   WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
+ "CPU update of VM recommended only for large BAR system\n");
+
+   if (vm->pasid) {
+   unsigned long flags;
+
+   spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
+   idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
+   spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
+
+   vm->pasid = 0;
+   }
+
+error:
+   amdgpu_bo_unreserve(vm->root.base.bo);
+   return r;
+}
+
+/**
  * amdgpu_vm_free_levels - free PD/PT levels
  *
  * @adev: amdgpu device structure
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 4dfdefb..30f0803 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -260,6 +260,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev);
 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
   int vm_context, unsigned int pasid);
+int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
  unsigned int pasid);
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 12/20] drm/amdkfd: Add ioctls for GPUVM memory management

[Felix Kuehling]

v2:
* Fix error handling after kfd_bind_process_to_device in
  kfd_ioctl_map_memory_to_gpu
v3:
* Add ioctl to acquire VM from a DRM FD
v4:
* Return number of successful map/unmap operations in failure cases
* Facilitate partial retry after failed map/unmap
* Added comments with parameter descriptions to new APIs
* Defined AMDKFD_IOC_FREE_MEMORY_OF_GPU write-only

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c| 377 
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h   |   8 +
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h |   2 +
 include/uapi/linux/kfd_ioctl.h  |  97 +-
 4 files changed, 483 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 7d40094..a563ff2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1046,6 +1047,366 @@ static int kfd_ioctl_get_tile_config(struct file *filep,
return 0;
 }
 
+static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
+   void *data)
+{
+   struct kfd_ioctl_acquire_vm_args *args = data;
+   struct kfd_process_device *pdd;
+   struct kfd_dev *dev;
+   struct file *drm_file;
+   int ret;
+
+   dev = kfd_device_by_id(args->gpu_id);
+   if (!dev)
+   return -EINVAL;
+
+   drm_file = fget(args->drm_fd);
+   if (!drm_file)
+   return -EINVAL;
+
+   mutex_lock(&p->mutex);
+
+   pdd = kfd_get_process_device_data(dev, p);
+   if (!pdd) {
+   ret = -EINVAL;
+   goto err_unlock;
+   }
+
+   if (pdd->drm_file) {
+   ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
+   goto err_unlock;
+   }
+
+   ret = kfd_process_device_init_vm(pdd, drm_file);
+   if (ret)
+   goto err_unlock;
+   /* On success, the PDD keeps the drm_file reference */
+   mutex_unlock(&p->mutex);
+
+   return 0;
+
+err_unlock:
+   mutex_unlock(&p->mutex);
+   fput(drm_file);
+   return ret;
+}
+
+bool kfd_dev_is_large_bar(struct kfd_dev *dev)
+{
+   struct kfd_local_mem_info mem_info;
+
+   if (dev->device_info->needs_iommu_device)
+   return false;
+
+   dev->kfd2kgd->get_local_mem_info(dev->kgd, &mem_info);
+   if (mem_info.local_mem_size_private == 0 &&
+   mem_info.local_mem_size_public > 0)
+   return true;
+   return false;
+}
+
+static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
+   struct kfd_process *p, void *data)
+{
+   struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
+   struct kfd_process_device *pdd;
+   void *mem;
+   struct kfd_dev *dev;
+   int idr_handle;
+   long err;
+   uint64_t offset = args->mmap_offset;
+   uint32_t flags = args->flags;
+
+   if (args->size == 0)
+   return -EINVAL;
+
+   dev = kfd_device_by_id(args->gpu_id);
+   if (!dev)
+   return -EINVAL;
+
+   if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
+   (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
+   !kfd_dev_is_large_bar(dev)) {
+   pr_err("Alloc host visible vram on small bar is not allowed\n");
+   return -EINVAL;
+   }
+
+   mutex_lock(&p->mutex);
+
+   pdd = kfd_bind_process_to_device(dev, p);
+   if (IS_ERR(pdd)) {
+   err = PTR_ERR(pdd);
+   goto err_unlock;
+   }
+
+   err = dev->kfd2kgd->alloc_memory_of_gpu(
+   dev->kgd, args->va_addr, args->size,
+   pdd->vm, (struct kgd_mem **) &mem, &offset,
+   flags);
+
+   if (err)
+   goto err_unlock;
+
+   idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
+   if (idr_handle < 0) {
+   err = -EFAULT;
+   goto err_free;
+   }
+
+   mutex_unlock(&p->mutex);
+
+   args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
+   args->mmap_offset = offset;
+
+   return 0;
+
+err_free:
+   dev->kfd2kgd->free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem);
+err_unlock:
+   mutex_unlock(&p->mutex);
+   return err;
+}
+
+static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
+   struct kfd_process *p, void *data)
+{
+   struct kfd_ioctl_free_memory_of_gpu_args *args = data;
+   struct kfd_process_device *pdd;
+   void *mem;
+   struct kfd_dev *dev;
+   int ret;
+
+   dev = kfd_device_by_id(GET_GPU_ID(args->handle));
+   if (!dev)
+   return -EINVAL;
+
+   mutex_lock(&p->mutex);
+
+   pdd = kfd_get_process_device_data(dev, p);
+   if (!pdd) {
+   pr_err("Proc

[PATCH 07/20] drm/amdkfd: Remove limit on number of GPUs

[Felix Kuehling]

Currently the number of GPUs is limited by aperture placement options
available on GFX7 and GFX8 hardware. This limitation is not necessary.
Scratch and LDS represent per-work-item and per-work-group storage
respectively. Different work-items and work-groups use the same virtual
address to access their own data. Work running on different GPUs is by
definition in different work-groups (different dispatches, in fact).
That means the same virtual addresses can be used for these apertures
on different GPUs.

Add a new AMDKFD_IOC_GET_PROCESS_APERTURES_NEW ioctl that removes the
artificial limitation on the number of GPUs that can be supported. The
new ioctl allows user mode to query the number of GPUs to allocate
enough memory for all GPUs to be reported.

This deprecates AMDKFD_IOC_GET_PROCESS_APERTURES.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 94 
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 22 +++
 include/uapi/linux/kfd_ioctl.h   | 27 +++-
 3 files changed, 128 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 6fe2496..7d40094 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -825,6 +825,97 @@ static int kfd_ioctl_get_process_apertures(struct file 
*filp,
return 0;
 }
 
+static int kfd_ioctl_get_process_apertures_new(struct file *filp,
+   struct kfd_process *p, void *data)
+{
+   struct kfd_ioctl_get_process_apertures_new_args *args = data;
+   struct kfd_process_device_apertures *pa;
+   struct kfd_process_device *pdd;
+   uint32_t nodes = 0;
+   int ret;
+
+   dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
+
+   if (args->num_of_nodes == 0) {
+   /* Return number of nodes, so that user space can alloacate
+* sufficient memory
+*/
+   mutex_lock(&p->mutex);
+
+   if (!kfd_has_process_device_data(p))
+   goto out_unlock;
+
+   /* Run over all pdd of the process */
+   pdd = kfd_get_first_process_device_data(p);
+   do {
+   args->num_of_nodes++;
+   pdd = kfd_get_next_process_device_data(p, pdd);
+   } while (pdd);
+
+   goto out_unlock;
+   }
+
+   /* Fill in process-aperture information for all available
+* nodes, but not more than args->num_of_nodes as that is
+* the amount of memory allocated by user
+*/
+   pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
+   args->num_of_nodes), GFP_KERNEL);
+   if (!pa)
+   return -ENOMEM;
+
+   mutex_lock(&p->mutex);
+
+   if (!kfd_has_process_device_data(p)) {
+   args->num_of_nodes = 0;
+   kfree(pa);
+   goto out_unlock;
+   }
+
+   /* Run over all pdd of the process */
+   pdd = kfd_get_first_process_device_data(p);
+   do {
+   pa[nodes].gpu_id = pdd->dev->id;
+   pa[nodes].lds_base = pdd->lds_base;
+   pa[nodes].lds_limit = pdd->lds_limit;
+   pa[nodes].gpuvm_base = pdd->gpuvm_base;
+   pa[nodes].gpuvm_limit = pdd->gpuvm_limit;
+   pa[nodes].scratch_base = pdd->scratch_base;
+   pa[nodes].scratch_limit = pdd->scratch_limit;
+
+   dev_dbg(kfd_device,
+   "gpu id %u\n", pdd->dev->id);
+   dev_dbg(kfd_device,
+   "lds_base %llX\n", pdd->lds_base);
+   dev_dbg(kfd_device,
+   "lds_limit %llX\n", pdd->lds_limit);
+   dev_dbg(kfd_device,
+   "gpuvm_base %llX\n", pdd->gpuvm_base);
+   dev_dbg(kfd_device,
+   "gpuvm_limit %llX\n", pdd->gpuvm_limit);
+   dev_dbg(kfd_device,
+   "scratch_base %llX\n", pdd->scratch_base);
+   dev_dbg(kfd_device,
+   "scratch_limit %llX\n", pdd->scratch_limit);
+   nodes++;
+
+   pdd = kfd_get_next_process_device_data(p, pdd);
+   } while (pdd && (nodes < args->num_of_nodes));
+   mutex_unlock(&p->mutex);
+
+   args->num_of_nodes = nodes;
+   ret = copy_to_user(
+   (void __user *)args->kfd_process_device_apertures_ptr,
+   pa,
+   (nodes * sizeof(struct kfd_process_device_apertures)));
+   kfree(pa);
+   return ret ? -EFAULT : 0;
+
+out_unlock:
+   mutex_unlock(&p->mutex);
+   return 0;
+}
+
 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
void *data)
 {
@@ -1017,6 +1108,9 @@ static const struct amdkfd_ioctl_desc am

[PATCH 10/20] drm/amdkfd: Allocate CWSR trap handler memory for dGPUs

[Felix Kuehling]

Add helpers for allocating GPUVM memory in kernel mode and use them
to allocate memory for the CWSR trap handler.

v2: Use dev instead of pdd->dev in kfd_process_free_gpuvm
v3:
* Cleaned up and simplified kfd_process_alloc_gpuvm
* Moved allocation for dGPU to kfd_process_device_init_vm

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 137 ---
 1 file changed, 127 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index a2ae023..aeb339d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -54,7 +54,6 @@ static struct kfd_process *find_process(const struct 
task_struct *thread);
 static void kfd_process_ref_release(struct kref *ref);
 static struct kfd_process *create_process(const struct task_struct *thread,
struct file *filep);
-static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep);
 
 static void evict_process_worker(struct work_struct *work);
 static void restore_process_worker(struct work_struct *work);
@@ -74,6 +73,82 @@ void kfd_process_destroy_wq(void)
}
 }
 
+static void kfd_process_free_gpuvm(struct kgd_mem *mem,
+   struct kfd_process_device *pdd)
+{
+   struct kfd_dev *dev = pdd->dev;
+
+   dev->kfd2kgd->unmap_memory_to_gpu(dev->kgd, mem, pdd->vm);
+   dev->kfd2kgd->free_memory_of_gpu(dev->kgd, mem);
+}
+
+/* kfd_process_alloc_gpuvm - Allocate GPU VM for the KFD process
+ * This function should be only called right after the process
+ * is created and when kfd_processes_mutex is still being held
+ * to avoid concurrency. Because of that exclusiveness, we do
+ * not need to take p->mutex.
+ */
+static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd,
+  uint64_t gpu_va, uint32_t size,
+  uint32_t flags, void **kptr)
+{
+   struct kfd_dev *kdev = pdd->dev;
+   struct kgd_mem *mem = NULL;
+   int handle;
+   int err;
+
+   err = kdev->kfd2kgd->alloc_memory_of_gpu(kdev->kgd, gpu_va, size,
+pdd->vm, &mem, NULL, flags);
+   if (err)
+   goto err_alloc_mem;
+
+   err = kdev->kfd2kgd->map_memory_to_gpu(kdev->kgd, mem, pdd->vm);
+   if (err)
+   goto err_map_mem;
+
+   err = kdev->kfd2kgd->sync_memory(kdev->kgd, mem, true);
+   if (err) {
+   pr_debug("Sync memory failed, wait interrupted by user 
signal\n");
+   goto sync_memory_failed;
+   }
+
+   /* Create an obj handle so kfd_process_device_remove_obj_handle
+* will take care of the bo removal when the process finishes.
+* We do not need to take p->mutex, because the process is just
+* created and the ioctls have not had the chance to run.
+*/
+   handle = kfd_process_device_create_obj_handle(pdd, mem);
+
+   if (handle < 0) {
+   err = handle;
+   goto free_gpuvm;
+   }
+
+   if (kptr) {
+   err = kdev->kfd2kgd->map_gtt_bo_to_kernel(kdev->kgd,
+   (struct kgd_mem *)mem, kptr, NULL);
+   if (err) {
+   pr_debug("Map GTT BO to kernel failed\n");
+   goto free_obj_handle;
+   }
+   }
+
+   return err;
+
+free_obj_handle:
+   kfd_process_device_remove_obj_handle(pdd, handle);
+free_gpuvm:
+sync_memory_failed:
+   kfd_process_free_gpuvm(mem, pdd);
+   return err;
+
+err_map_mem:
+   kdev->kfd2kgd->free_memory_of_gpu(kdev->kgd, mem);
+err_alloc_mem:
+   *kptr = NULL;
+   return err;
+}
+
 struct kfd_process *kfd_create_process(struct file *filep)
 {
struct kfd_process *process;
@@ -201,7 +276,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
 
list_del(&pdd->per_device_list);
 
-   if (pdd->qpd.cwsr_kaddr)
+   if (pdd->qpd.cwsr_kaddr && !pdd->qpd.cwsr_base)
free_pages((unsigned long)pdd->qpd.cwsr_kaddr,
get_order(KFD_CWSR_TBA_TMA_SIZE));
 
@@ -312,18 +387,18 @@ static const struct mmu_notifier_ops 
kfd_process_mmu_notifier_ops = {
.release = kfd_process_notifier_release,
 };
 
-static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep)
+static int kfd_process_init_cwsr_apu(struct kfd_process *p, struct file *filep)
 {
unsigned long  offset;
-   struct kfd_process_device *pdd = NULL;
-   struct kfd_dev *dev = NULL;
-   struct qcm_process_device *qpd = NULL;
+   struct kfd_process_device *pdd;
 
list_for_each_entry(pdd, &p->per_device_data, per_device_list) {
-   dev = pdd->dev;
-   qpd = &pdd->qpd;
-   if (!dev->cwsr_enabled || qpd

[PATCH 08/20] drm/amdkfd: Aperture setup for dGPUs

[Felix Kuehling]

Set up the GPUVM aperture for SVM (shared virtual memory) that allows
sharing a part of virtual address space between GPUs and CPUs.

Report the size of the the GPUVM size supported by KGD accurately.

The low part of the GPUVM aperture is reserved for kernel use. This is
for kernel-allocated buffers that are only accessed on the GPU:
- CWSR trap handler
- IB for submitting commands in user-mode context from kernel mode

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 37 ++--
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h|  4 +++
 2 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index a06b010..66852de 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -278,9 +278,8 @@
 #define MAKE_GPUVM_APP_BASE(gpu_num) \
(((uint64_t)(gpu_num) << 61) + 0x1L)
 
-#define MAKE_GPUVM_APP_LIMIT(base) \
-   (((uint64_t)(base) & \
-   0xFF00UL) | 0xFFL)
+#define MAKE_GPUVM_APP_LIMIT(base, size) \
+   (((uint64_t)(base) & 0xFF00UL) + (size) - 1)
 
 #define MAKE_SCRATCH_APP_BASE() \
(((uint64_t)(0x1UL) << 61) + 0x1L)
@@ -293,6 +292,14 @@
 #define MAKE_LDS_APP_LIMIT(base) \
(((uint64_t)(base) & 0xUL) | 0x)
 
+/* User mode manages most of the SVM aperture address space. The low
+ * 16MB are reserved for kernel use (CWSR trap handler and kernel IB
+ * for now).
+ */
+#define SVM_USER_BASE 0x100ull
+#define SVM_CWSR_BASE (SVM_USER_BASE - KFD_CWSR_TBA_TMA_SIZE)
+#define SVM_IB_BASE   (SVM_CWSR_BASE - PAGE_SIZE)
+
 int kfd_init_apertures(struct kfd_process *process)
 {
uint8_t id  = 0;
@@ -330,14 +337,28 @@ int kfd_init_apertures(struct kfd_process *process)
pdd->lds_base = MAKE_LDS_APP_BASE();
pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
 
-   pdd->gpuvm_base = MAKE_GPUVM_APP_BASE(id + 1);
-
-   pdd->gpuvm_limit =
-   MAKE_GPUVM_APP_LIMIT(pdd->gpuvm_base);
-
pdd->scratch_base = MAKE_SCRATCH_APP_BASE();
pdd->scratch_limit =
MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
+
+   if (dev->device_info->needs_iommu_device) {
+   /* APUs: GPUVM aperture in
+* non-canonical address space
+*/
+   pdd->gpuvm_base = MAKE_GPUVM_APP_BASE(id + 1);
+   pdd->gpuvm_limit = MAKE_GPUVM_APP_LIMIT(
+   pdd->gpuvm_base,
+   dev->shared_resources.gpuvm_size);
+   } else {
+   /* dGPUs: SVM aperture starting at 0
+* with small reserved space for kernel
+*/
+   pdd->gpuvm_base = SVM_USER_BASE;
+   pdd->gpuvm_limit =
+   dev->shared_resources.gpuvm_size - 1;
+   pdd->qpd.cwsr_base = SVM_CWSR_BASE;
+   pdd->qpd.ib_base = SVM_IB_BASE;
+   }
}
 
dev_dbg(kfd_device, "node id %u\n", id);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 014d608..0d5d924 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -488,8 +488,12 @@ struct qcm_process_device {
 
/* CWSR memory */
void *cwsr_kaddr;
+   uint64_t cwsr_base;
uint64_t tba_addr;
uint64_t tma_addr;
+
+   /* IB memory */
+   uint64_t ib_base;
 };
 
 /* KFD Memory Eviction */
-- 
2.7.4

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[PATCH 05/20] drm/amdkfd: Create KFD VMs on demand

[Felix Kuehling]

Instead of creating all VMs on process creation, create them when
a process is bound to a device. This will later allow registering
an existing VM from a DRM render node FD at runtime, before the
process is bound to the device. This way the render node VM can be
used for KFD instead of creating our own redundant VM.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h|  3 ++
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 60 ++--
 2 files changed, 53 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index cac7aa2..014d608 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -536,6 +536,7 @@ struct kfd_process_device {
uint64_t scratch_limit;
 
/* VM context for GPUVM allocations */
+   struct file *drm_file;
void *vm;
 
/* Flag used to tell the pdd has dequeued from the dqm.
@@ -661,6 +662,8 @@ void kfd_unref_process(struct kfd_process *p);
 void kfd_suspend_all_processes(void);
 int kfd_resume_all_processes(void);
 
+int kfd_process_device_init_vm(struct kfd_process_device *pdd,
+  struct file *drm_file);
 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev,
struct kfd_process *p);
 struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 18b2b86..6618aaa 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct mm_struct;
 
@@ -158,7 +159,9 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
pr_debug("Releasing pdd (topology id %d) for process (pasid 
%d)\n",
pdd->dev->id, p->pasid);
 
-   if (pdd->vm)
+   if (pdd->drm_file)
+   fput(pdd->drm_file);
+   else if (pdd->vm)
pdd->dev->kfd2kgd->destroy_process_vm(
pdd->dev->kgd, pdd->vm);
 
@@ -418,18 +421,51 @@ struct kfd_process_device 
*kfd_create_process_device_data(struct kfd_dev *dev,
pdd->already_dequeued = false;
list_add(&pdd->per_device_list, &p->per_device_data);
 
-   /* Create the GPUVM context for this specific device */
-   if (dev->kfd2kgd->create_process_vm(dev->kgd, &pdd->vm,
-   &p->kgd_process_info, &p->ef)) {
+   return pdd;
+}
+
+/**
+ * kfd_process_device_init_vm - Initialize a VM for a process-device
+ *
+ * @pdd: The process-device
+ * @drm_file: Optional pointer to a DRM file descriptor
+ *
+ * If @drm_file is specified, it will be used to acquire the VM from
+ * that file descriptor. If successful, the @pdd takes ownership of
+ * the file descriptor.
+ *
+ * If @drm_file is NULL, a new VM is created.
+ *
+ * Returns 0 on success, -errno on failure.
+ */
+int kfd_process_device_init_vm(struct kfd_process_device *pdd,
+  struct file *drm_file)
+{
+   struct kfd_process *p;
+   struct kfd_dev *dev;
+   int ret;
+
+   if (pdd->vm)
+   return drm_file ? -EBUSY : 0;
+
+   p = pdd->process;
+   dev = pdd->dev;
+
+   if (drm_file)
+   ret = dev->kfd2kgd->acquire_process_vm(
+   dev->kgd, drm_file,
+   &pdd->vm, &p->kgd_process_info, &p->ef);
+   else
+   ret = dev->kfd2kgd->create_process_vm(
+   dev->kgd, &pdd->vm, &p->kgd_process_info, &p->ef);
+   if (ret) {
pr_err("Failed to create process VM object\n");
-   goto err_create_pdd;
+   return ret;
}
-   return pdd;
 
-err_create_pdd:
-   list_del(&pdd->per_device_list);
-   kfree(pdd);
-   return NULL;
+   pdd->drm_file = drm_file;
+
+   return 0;
 }
 
 /*
@@ -455,6 +491,10 @@ struct kfd_process_device 
*kfd_bind_process_to_device(struct kfd_dev *dev,
if (err)
return ERR_PTR(err);
 
+   err = kfd_process_device_init_vm(pdd, NULL);
+   if (err)
+   return ERR_PTR(err);
+
return pdd;
 }
 
-- 
2.7.4

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[PATCH 17/20] drm/amdgpu: GFP_NOIO while holding locks taken in MMU notifier

[Felix Kuehling]

When an MMU notifier runs in memory reclaim context, it can deadlock
trying to take locks that are already held in the thread causing the
memory reclaim. The solution is to avoid memory reclaim while holding
locks that are taken in MMU notifiers by using GFP_NOIO.

This commit fixes kmalloc while holding rmn->lock. The GFX MMU
notifier also locks reservation objects. I have no good solution for
avoiding reclaim while holding reservation objects. The HSA MMU
notifier will not lock any reservation objects.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index f2ed18e..b4a5c03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -402,7 +402,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long 
addr)
}
 
if (!node) {
-   node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
+   node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_NOIO);
if (!node) {
up_write(&rmn->lock);
return -ENOMEM;
-- 
2.7.4

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[PATCH 11/20] drm/amdkfd: Add TC flush on VMID deallocation for Hawaii

[Felix Kuehling]

On GFX7 the CP does not perform a TC flush when queues are unmapped.
To avoid TC eviction from accessing an invalid VMID, flush it
explicitly before releasing a VMID.

v2: Fix unnecessary list_for_each_entry_safe
v3: Moved allocation to kfd_process_device_init_vm

Signed-off-by: Amber Lin 
Signed-off-by: Felix Kuehling 
---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 22 -
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c| 37 ++
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  3 ++
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 34 
 4 files changed, 95 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index b3b6dab..c18e048 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -142,12 +142,31 @@ static int allocate_vmid(struct device_queue_manager *dqm,
return 0;
 }
 
+static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
+   struct qcm_process_device *qpd)
+{
+   uint32_t len;
+
+   if (!qpd->ib_kaddr)
+   return -ENOMEM;
+
+   len = pm_create_release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
+
+   return kdev->kfd2kgd->submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
+   qpd->ib_base, (uint32_t *)qpd->ib_kaddr, len);
+}
+
 static void deallocate_vmid(struct device_queue_manager *dqm,
struct qcm_process_device *qpd,
struct queue *q)
 {
int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
 
+   /* On GFX v7, CP doesn't flush TC at dequeue */
+   if (q->device->device_info->asic_family == CHIP_HAWAII)
+   if (flush_texture_cache_nocpsch(q->device, qpd))
+   pr_err("Failed to flush TC\n");
+
kfd_flush_tlb(qpd_to_pdd(qpd));
 
/* Release the vmid mapping */
@@ -792,11 +811,12 @@ static void uninitialize(struct device_queue_manager *dqm)
 static int start_nocpsch(struct device_queue_manager *dqm)
 {
init_interrupts(dqm);
-   return 0;
+   return pm_init(&dqm->packets, dqm);
 }
 
 static int stop_nocpsch(struct device_queue_manager *dqm)
 {
+   pm_uninit(&dqm->packets);
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 0ecbd1f..7614375 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -356,6 +356,43 @@ static int pm_create_runlist_ib(struct packet_manager *pm,
return retval;
 }
 
+/* pm_create_release_mem - Create a RELEASE_MEM packet and return the size
+ * of this packet
+ * @gpu_addr - GPU address of the packet. It's a virtual address.
+ * @buffer - buffer to fill up with the packet. It's a CPU kernel pointer
+ * Return - length of the packet
+ */
+uint32_t pm_create_release_mem(uint64_t gpu_addr, uint32_t *buffer)
+{
+   struct pm4_mec_release_mem *packet;
+
+   WARN_ON(!buffer);
+
+   packet = (struct pm4_mec_release_mem *)buffer;
+   memset(buffer, 0, sizeof(*packet));
+
+   packet->header.u32All = build_pm4_header(IT_RELEASE_MEM,
+sizeof(*packet));
+
+   packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
+   packet->bitfields2.event_index = event_index___release_mem__end_of_pipe;
+   packet->bitfields2.tcl1_action_ena = 1;
+   packet->bitfields2.tc_action_ena = 1;
+   packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
+   packet->bitfields2.atc = 0;
+
+   packet->bitfields3.data_sel = data_sel___release_mem__send_32_bit_low;
+   packet->bitfields3.int_sel =
+   int_sel___release_mem__send_interrupt_after_write_confirm;
+
+   packet->bitfields4.address_lo_32b = (gpu_addr & 0x) >> 2;
+   packet->address_hi = upper_32_bits(gpu_addr);
+
+   packet->data_lo = 0;
+
+   return sizeof(*packet) / sizeof(unsigned int);
+}
+
 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
 {
pm->dqm = dqm;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index b2b5ef8..aaed005 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -494,6 +494,7 @@ struct qcm_process_device {
 
/* IB memory */
uint64_t ib_base;
+   void *ib_kaddr;
 };
 
 /* KFD Memory Eviction */
@@ -834,6 +835,8 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum 
kfd_queue_type type,
 
 void pm_release_ib(struct packet_manager *pm);
 
+uint32_t pm_create_release_mem(uint64_t gpu_addr, uint32_t *buffer);
+
 uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
 
 /* Events */
diff --

[PATCH 06/20] drm/amdkfd: Populate DRM render device minor

[Felix Kuehling]

From: Oak Zeng 

Populate DRM render device minor in kfd topology

Signed-off-by: Oak Zeng 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 
 drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 2506155..ac28abc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -441,6 +441,8 @@ static ssize_t node_show(struct kobject *kobj, struct 
attribute *attr,
dev->node_props.device_id);
sysfs_show_32bit_prop(buffer, "location_id",
dev->node_props.location_id);
+   sysfs_show_32bit_prop(buffer, "drm_render_minor",
+   dev->node_props.drm_render_minor);
 
if (dev->gpu) {
log_max_watch_addr =
@@ -1214,6 +1216,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
dev->gpu->kfd2kgd->get_max_engine_clock_in_mhz(dev->gpu->kgd);
dev->node_props.max_engine_clk_ccompute =
cpufreq_quick_get_max(0) / 1000;
+   dev->node_props.drm_render_minor =
+   gpu->shared_resources.drm_render_minor;
 
kfd_fill_mem_clk_max_info(dev);
kfd_fill_iolink_non_crat_info(dev);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
index c0be2be..eb54cfc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
@@ -71,6 +71,7 @@ struct kfd_node_properties {
uint32_t location_id;
uint32_t max_engine_clk_fcompute;
uint32_t max_engine_clk_ccompute;
+   int32_t  drm_render_minor;
uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
 };
 
-- 
2.7.4

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[PATCH 00/20] Add KFD GPUVM support for dGPUs v4

[Felix Kuehling]

Rebased and integrated review feedback from v3:
* Removed vm->vm_context field
* Use uninterruptible waiting in initial PD validation to avoid ERESTARTSYS
* Return number of successful map/unmap operations in failure cases
* Facilitate partial retry after failed map/unmap
* Added comments with parameter descriptions to new APIs
* Defined AMDKFD_IOC_FREE_MEMORY_OF_GPU write-only

This patch series also adds Userptr support in patches 15-20.

Felix Kuehling (19):
  drm/amdgpu: Move KFD-specific fields into struct amdgpu_vm
  drm/amdgpu: Fix initial validation of PD BO for KFD VMs
  drm/amdgpu: Add helper to turn an existing VM into a compute VM
  drm/amdgpu: Add kfd2kgd interface to acquire an existing VM
  drm/amdkfd: Create KFD VMs on demand
  drm/amdkfd: Remove limit on number of GPUs
  drm/amdkfd: Aperture setup for dGPUs
  drm/amdkfd: Add per-process IDR for buffer handles
  drm/amdkfd: Allocate CWSR trap handler memory for dGPUs
  drm/amdkfd: Add TC flush on VMID deallocation for Hawaii
  drm/amdkfd: Add ioctls for GPUVM memory management
  drm/amdkfd: Kmap event page for dGPUs
  drm/amdkfd: Add module option for testing large-BAR functionality
  drm/amdgpu: Add MMU notifier type for KFD userptr
  drm/amdgpu: Enable amdgpu_ttm_tt_get_user_pages in worker threads
  drm/amdgpu: GFP_NOIO while holding locks taken in MMU notifier
  drm/amdkfd: GFP_NOIO while holding locks taken in MMU notifier
  drm/amdkfd: Add quiesce_mm and resume_mm to kgd2kfd_calls
  drm/amdgpu: Add userptr support for KFD

Oak Zeng (1):
  drm/amdkfd: Populate DRM render device minor

 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |  37 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c   | 818 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c |  96 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h |  11 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  30 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  70 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  10 +
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c   | 532 ++
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c  |   3 +
 drivers/gpu/drm/amd/amdkfd/kfd_device.c|  40 +-
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |  22 +-
 drivers/gpu/drm/amd/amdkfd/kfd_events.c|  31 +-
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c   |  59 +-
 drivers/gpu/drm/amd/amdkfd/kfd_module.c|   7 +
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c   |   2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c|   2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c|  37 +
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  41 ++
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 314 +++-
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c  |   4 +
 drivers/gpu/drm/amd/amdkfd/kfd_topology.h  |   1 +
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h|  10 +
 include/uapi/linux/kfd_ioctl.h | 122 ++-
 26 files changed, 2090 insertions(+), 213 deletions(-)

-- 
2.7.4

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[PATCH 04/20] drm/amdgpu: Add kfd2kgd interface to acquire an existing VM

[Felix Kuehling]

This allows acquiring an existing VM from a render node FD to use it
for a compute process.

Such VMs get destroyed when the original file descriptor is released.
Added a callback from amdgpu_vm_fini to handle KFD VM destruction
correctly in this case.

v2:
* Removed vm->vm_context check in amdgpu_amdkfd_gpuvm_destroy_cb,
  check vm->process_info earlier instead

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|   6 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 166 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|   3 +
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h   |   2 +
 6 files changed, 124 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 6ba3dd6..c2c2bea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -145,6 +145,12 @@ uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
 int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
  void **process_info,
  struct dma_fence **ef);
+int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
+  struct file *filp,
+  void **vm, void **process_info,
+  struct dma_fence **ef);
+void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
+   struct amdgpu_vm *vm);
 void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
 uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 7485c37..ea54e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -205,6 +205,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
.get_cu_info = get_cu_info,
.get_vram_usage = amdgpu_amdkfd_get_vram_usage,
.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
+   .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
.set_vm_context_page_table_base = set_vm_context_page_table_base,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 7be4534..89264c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -165,6 +165,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
.get_cu_info = get_cu_info,
.get_vram_usage = amdgpu_amdkfd_get_vram_usage,
.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
+   .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
.set_vm_context_page_table_base = set_vm_context_page_table_base,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index c578107..2f42c60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -806,32 +806,16 @@ static int process_update_pds(struct amdkfd_process_info 
*process_info,
return 0;
 }
 
-int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
- void **process_info,
- struct dma_fence **ef)
+static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
+  struct dma_fence **ef)
 {
-   int ret;
-   struct amdgpu_vm *new_vm;
struct amdkfd_process_info *info = NULL;
-   struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
-   new_vm = kzalloc(sizeof(*new_vm), GFP_KERNEL);
-   if (!new_vm)
-   return -ENOMEM;
-
-   /* Initialize the VM context, allocate the page directory and zero it */
-   ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, 0);
-   if (ret) {
-   pr_err("Failed init vm ret %d\n", ret);
-   goto vm_init_fail;
-   }
+   int ret;
 
if (!*process_info) {
info = kzalloc(sizeof(*info), GFP_KERNEL);
-   if (!info) {
-   ret = -ENOMEM;
-   goto alloc_process_info_fail;
-   }
+   if (!info)
+ 

[PATCH 01/20] drm/amdgpu: Move KFD-specific fields into struct amdgpu_vm

[Felix Kuehling]

Remove struct amdkfd_vm and move the fields into struct amdgpu_vm.
This will allow turning a VM created by a DRM render node into a
KFD VM.

v2: Removed vm_context field

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   | 21 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 88 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h   |  9 +++
 3 files changed, 50 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index ad7292f..6ba3dd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -93,27 +93,6 @@ struct amdkfd_process_info {
struct amdgpu_amdkfd_fence *eviction_fence;
 };
 
-/* struct amdkfd_vm -
- * For Memory Eviction KGD requires a mechanism to keep track of all KFD BOs
- * belonging to a KFD process. All the VMs belonging to the same process point
- * to the same amdkfd_process_info.
- */
-struct amdkfd_vm {
-   /* Keep base as the first parameter for pointer compatibility between
-* amdkfd_vm and amdgpu_vm.
-*/
-   struct amdgpu_vm base;
-
-   /* List node in amdkfd_process_info.vm_list_head*/
-   struct list_head vm_list_node;
-
-   struct amdgpu_device *adev;
-   /* Points to the KFD process VM info*/
-   struct amdkfd_process_info *process_info;
-
-   uint64_t pd_phys_addr;
-};
-
 int amdgpu_amdkfd_init(void);
 void amdgpu_amdkfd_fini(void);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index e0371a9..d712809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -333,9 +333,9 @@ static int amdgpu_amdkfd_validate(void *param, struct 
amdgpu_bo *bo)
  * again. Page directories are only updated after updating page
  * tables.
  */
-static int vm_validate_pt_pd_bos(struct amdkfd_vm *vm)
+static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 {
-   struct amdgpu_bo *pd = vm->base.root.base.bo;
+   struct amdgpu_bo *pd = vm->root.base.bo;
struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
struct amdgpu_vm_parser param;
uint64_t addr, flags = AMDGPU_PTE_VALID;
@@ -344,7 +344,7 @@ static int vm_validate_pt_pd_bos(struct amdkfd_vm *vm)
param.domain = AMDGPU_GEM_DOMAIN_VRAM;
param.wait = false;
 
-   ret = amdgpu_vm_validate_pt_bos(adev, &vm->base, amdgpu_amdkfd_validate,
+   ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,
¶m);
if (ret) {
pr_err("amdgpu: failed to validate PT BOs\n");
@@ -357,11 +357,11 @@ static int vm_validate_pt_pd_bos(struct amdkfd_vm *vm)
return ret;
}
 
-   addr = amdgpu_bo_gpu_offset(vm->base.root.base.bo);
+   addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
amdgpu_gmc_get_vm_pde(adev, -1, &addr, &flags);
vm->pd_phys_addr = addr;
 
-   if (vm->base.use_cpu_for_update) {
+   if (vm->use_cpu_for_update) {
ret = amdgpu_bo_kmap(pd, NULL);
if (ret) {
pr_err("amdgpu: failed to kmap PD, ret=%d\n", ret);
@@ -415,14 +415,12 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct 
amdgpu_sync *sync)
  * 4a.  Validate new page tables and directories
  */
 static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem,
-   struct amdgpu_vm *avm, bool is_aql,
+   struct amdgpu_vm *vm, bool is_aql,
struct kfd_bo_va_list **p_bo_va_entry)
 {
int ret;
struct kfd_bo_va_list *bo_va_entry;
-   struct amdkfd_vm *kvm = container_of(avm,
-struct amdkfd_vm, base);
-   struct amdgpu_bo *pd = avm->root.base.bo;
+   struct amdgpu_bo *pd = vm->root.base.bo;
struct amdgpu_bo *bo = mem->bo;
uint64_t va = mem->va;
struct list_head *list_bo_va = &mem->bo_va_list;
@@ -441,10 +439,10 @@ static int add_bo_to_vm(struct amdgpu_device *adev, 
struct kgd_mem *mem,
return -ENOMEM;
 
pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
-   va + bo_size, avm);
+   va + bo_size, vm);
 
/* Add BO to VM internal data structures*/
-   bo_va_entry->bo_va = amdgpu_vm_bo_add(adev, avm, bo);
+   bo_va_entry->bo_va = amdgpu_vm_bo_add(adev, vm, bo);
if (!bo_va_entry->bo_va) {
ret = -EINVAL;
pr_err("Failed to add BO object to VM. ret == %d\n",
@@ -467,28 +465,28 @@ static int add_bo_to_vm(struct amdgpu_device *adev, 
struct kgd_mem *mem,
 * fence, so remove it temporarily.
 */
amdgpu_amdkfd_remove_eviction_fence(pd,
-   kvm->process_info->eviction_fence,
+

[PATCH 02/20] drm/amdgpu: Fix initial validation of PD BO for KFD VMs

[Felix Kuehling]

Make sure the PD BO is valid and attach the eviction fence during VM
creation. This ensures that the pd_phys_address is actually valid
and an eviction that would invalidate it triggers a KFD process
eviction like it should.

v2: Use uninterruptible waiting in initial PD validation

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index d712809..c578107 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -812,7 +812,7 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev 
*kgd, void **vm,
 {
int ret;
struct amdgpu_vm *new_vm;
-   struct amdkfd_process_info *info;
+   struct amdkfd_process_info *info = NULL;
struct amdgpu_device *adev = get_amdgpu_device(kgd);
 
new_vm = kzalloc(sizeof(*new_vm), GFP_KERNEL);
@@ -851,6 +851,23 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev 
*kgd, void **vm,
 
new_vm->process_info = *process_info;
 
+   /* Validate page directory and attach eviction fence */
+   ret = amdgpu_bo_reserve(new_vm->root.base.bo, true);
+   if (ret)
+   goto reserve_pd_fail;
+   ret = vm_validate_pt_pd_bos(new_vm);
+   if (ret) {
+   pr_err("validate_pt_pd_bos() failed\n");
+   goto validate_pd_fail;
+   }
+   ret = ttm_bo_wait(&new_vm->root.base.bo->tbo, false, false);
+   if (ret)
+   goto wait_pd_fail;
+   amdgpu_bo_fence(new_vm->root.base.bo,
+   &new_vm->process_info->eviction_fence->base, true);
+   amdgpu_bo_unreserve(new_vm->root.base.bo);
+
+   /* Update process info */
mutex_lock(&new_vm->process_info->lock);
list_add_tail(&new_vm->vm_list_node,
&(new_vm->process_info->vm_list_head));
@@ -863,6 +880,10 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev 
*kgd, void **vm,
 
return ret;
 
+wait_pd_fail:
+validate_pd_fail:
+   amdgpu_bo_unreserve(new_vm->root.base.bo);
+reserve_pd_fail:
 create_evict_fence_fail:
mutex_destroy(&info->lock);
kfree(info);
-- 
2.7.4

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[PATCH] drm/amdgpu - Disable all irqs before disabling all CRTCs

[mikita.lipski]

From: Mikita Lipski 

By moving amdgpu_irq_disable_all earlier in the sequence
fixes an issue with disabling pflip interrupts:

*ERROR* dal_irq_service_dummy_ack: called for non-implemented irq source

Earlier patch fixed a memory corruption and revealed irq
warnings.This way it seems to be there no obvious issues
with unloading the module.

Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0b798cb..0d01735 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1432,9 +1432,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
int i, r;
 
amdgpu_amdkfd_device_fini(adev);
-   /* disable all interrupts */
-   amdgpu_irq_disable_all(adev);
-
/* need to disable SMC first */
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.hw)
@@ -2082,6 +2079,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 
DRM_INFO("amdgpu: finishing device.\n");
adev->shutdown = true;
+   /* disable all interrupts */
+   amdgpu_irq_disable_all(adev);
if (adev->mode_info.mode_config_initialized){
if (!amdgpu_device_has_dc_support(adev))
drm_crtc_force_disable_all(adev->ddev);
-- 
2.7.4

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Re: [PATCH] drm/amd/display: fix dereferencing possible ERR_PTR()

[Harry Wentland]

On 2018-03-15 06:33 AM, Shirish S wrote:
> This patch fixes static checker warning caused by
> "36cc549d5986: "drm/amd/display: disable CRTCs with
> NULL FB on their primary plane (V2)"
> 
> Reported-by: Dan Carpenter 
> Signed-off-by: Shirish S 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 0564676..9e2cdc9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4893,6 +4893,9 @@ static int dm_atomic_check_plane_state_fb(struct 
> drm_atomic_state *state,
>   return -EDEADLK;
>  
>   crtc_state = drm_atomic_get_crtc_state(plane_state->state, 
> crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> +
>   if (crtc->primary == plane && crtc_state->active) {
>   if (!plane_state->fb)
>   return -EINVAL;
> 
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Re: Ryzen 5 2400G Stuttering since 2018-03-07

[Harry Wentland]

On 2018-03-15 02:47 PM, Dawson Dias wrote:
> I created a ticket: https://bugs.freedesktop.org/show_bug.cgi?id=105530
> Let me know if there is any additional information I need to add.
> 

Thanks, Dawson.

Harry

> Thanks!
> 
> -Dawson Dias
> 
> On Thu, Mar 15, 2018 at 8:44 PM, Harry Wentland  > wrote:
> 
> On 2018-03-15 11:01 AM, Michel Dänzer wrote:
> > On 2018-03-15 03:47 PM, Dawson Dias wrote:
> >> Here we go! The logs are attached. I turned TearFree to `on` from
> >> `auto`, dragged some windows around, and captured them.
> >> AFAIK, I haven't made any changes via xrandr, except for toggling the
> >> TearFree property.
> >
> > Thanks. I don't see any obvious issue in your attachments. I think it's
> > most likely a kernel DC issue. I saw Harry just filed an internal bug
> > report that might be related.
> >
> 
> I'm not sure the internal bug is related here, but it could be. I noticed 
> problems when Freesync testing but I assume it was a much older regression. I 
> haven't seen flickering on normal desktop but I haven't played with Raven 
> recently or tried TearFree recently.
> 
> Dawson, mind opening a ticket on https://bugs.freedesktop.org/ to track 
> this?
> 
> Harry
> 
> >
> 
> 
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Re: Ryzen 5 2400G Stuttering since 2018-03-07

[Dawson Dias]

I created a ticket: https://bugs.freedesktop.org/show_bug.cgi?id=105530
Let me know if there is any additional information I need to add.

Thanks!

-Dawson Dias

On Thu, Mar 15, 2018 at 8:44 PM, Harry Wentland 
wrote:

> On 2018-03-15 11:01 AM, Michel Dänzer wrote:
> > On 2018-03-15 03:47 PM, Dawson Dias wrote:
> >> Here we go! The logs are attached. I turned TearFree to `on` from
> >> `auto`, dragged some windows around, and captured them.
> >> AFAIK, I haven't made any changes via xrandr, except for toggling the
> >> TearFree property.
> >
> > Thanks. I don't see any obvious issue in your attachments. I think it's
> > most likely a kernel DC issue. I saw Harry just filed an internal bug
> > report that might be related.
> >
>
> I'm not sure the internal bug is related here, but it could be. I noticed
> problems when Freesync testing but I assume it was a much older regression.
> I haven't seen flickering on normal desktop but I haven't played with Raven
> recently or tried TearFree recently.
>
> Dawson, mind opening a ticket on https://bugs.freedesktop.org/ to track
> this?
>
> Harry
>
> >
>
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Re: Ryzen 5 2400g - colors/contrast messed up on amd-staging-drm-next and drm-next-4.17-wip

[Hubert Łępicki]

Hey,

so there appears to be some progress as of today's build of
amd-staging-drm-next branch. The system I use has 2 external displays,
identical, one connected over HDMI another over DVI.

Currently:

1. Just after the boot, gamma settings on DVI-connected one are messed
up (is this HDR mode?). The settings on the other display, connected
over HDMI seem fine.

2. I use Gnome/Ubuntu 18.04, when I enable "Night mode" (i.e. f-lux
for Linux thing), it fixes the issue for DVI-connected display. The
fix also works after I disable "Night mode".

Hope that helps :)

Hubert Łępicki

2018-03-08 15:28 GMT+01:00 Deucher, Alexander :
> + Harry, Leo
>
>
> I saw this as well with tonga.  It seems to be related to the CTM/regamma
> changes.
>
>
> Alex
>
> 
> From: amd-gfx  on behalf of Hubert
> Łępicki 
> Sent: Thursday, March 8, 2018 7:03:06 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: Ryzen 5 2400g - colors/contrast messed up on amd-staging-drm-next
> and drm-next-4.17-wip
>
> Hey,
>
> I was giving a shot your work in progress branch for the AMDGPU
> driver, hoping maybe it brings some fixes to Ryzen 5 2400g. It does
> not look like it, but I might have discovered a bug (or you may be
> well aware of it since it's work in progress...). Either way, just to
> let you know:
>
> Graphics is sort of messed up on drm-next-4.17-wip and
> amd-staging-drm-next branches on my Ryzen 5 2400g. I am attaching
> screenshots.
>
> Correct colors/contrast on Ubuntu 18.04 / stock 4.15 kernel:
> https://photos.app.goo.gl/3IXkgOXh955vygff2
> https://photos.app.goo.gl/rD2aw7jvO6cbbTLh2
> https://photos.app.goo.gl/3IXkgOXh955vygff2
> https://photos.app.goo.gl/xLYC9N7drU687L8o2
>
> Incorrect colors/contrast on Ubuntu 18.04 / amd-staging-drm-next branch:
> https://photos.app.goo.gl/nDXM7LFgnkRDMtoh1
> https://photos.app.goo.gl/aG94pY4o4L1zaLAj2
> https://photos.app.goo.gl/FogNie21obF9w0ek2
> https://photos.app.goo.gl/PHiQ9Npgo24DnoDD2
>
>
> These are photos taken with a phone camera, as on any captured
> screenshots everything is fine.
>
> I can provide better / detailed photos if you need me to.
>
> This has been observed on Ubuntu 18.04, and Arch Linux, Gigabyte
> AB350m-gaming3, Ryzen 5 2400g, on both Wayland and Xorg.
>
> Hope that helps,
> All the best,
> Hubert Łepicki
>
> --
> Pozdrawiam,
> Hubert Łępicki
>  ---
> [ http://hubertlepicki.com ]
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx



-- 
Pozdrawiam,
Hubert Łępicki
 ---
[ http://hubertlepicki.com ]
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[PATCH] drm/amdkfd: fix uninitialized variable use

[Arnd Bergmann]

When CONFIG_ACPI is disabled, we never initialize the acpi_table
structure in kfd_create_crat_image_virtual:

drivers/gpu/drm/amd/amdkfd/kfd_crat.c: In function 
'kfd_create_crat_image_virtual':
drivers/gpu/drm/amd/amdkfd/kfd_crat.c:888:40: error: 'acpi_table' may be used 
uninitialized in this function [-Werror=maybe-uninitialized]

The undefined behavior also happens for any other acpi_get_table()
failure, but then the compiler can't warn about it.

This adds an error check that prevents the structure from
being used in error, avoiding both the undefined behavior and
the warning about it.

Fixes: 520b8fb755cc ("drm/amdkfd: Add topology support for CPUs")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 7493f47e7fe1..d85112224f1d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -882,7 +882,7 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, 
size_t *size)
crat_table->length = sizeof(struct crat_header);
 
status = acpi_get_table("DSDT", 0, &acpi_table);
-   if (status == AE_NOT_FOUND)
+   if (status != AE_OK)
pr_warn("DSDT table not found for OEM information\n");
else {
crat_table->oem_revision = acpi_table->revision;
-- 
2.9.0

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Re: [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel

[Christian König]

Yeah, not really the usually flow.

Either way Reviewed-by: Christian König  for both.

Christian.

Am 15.03.2018 um 17:19 schrieb Andrey Grodzovsky:


That explains the merge conflict that surprised me :)


Thanks,

Andrey


On 03/15/2018 12:18 PM, Deucher, Alexander wrote:


For the series:

Reviewed-by: Alex Deucher 

I think Rex already applied the second one.



*From:* amd-gfx  on behalf of 
Andrey Grodzovsky 

*Sent:* Thursday, March 15, 2018 12:15 PM
*To:* amd-gfx@lists.freedesktop.org; 
ckoenig.leichtzumer...@gmail.com; Zhu, Rex

*Cc:* Grodzovsky, Andrey
*Subject:* [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr 
in amdgpu_bo_create_kernel

and amdgpu_bo_create_reserved.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 48e0115..ac1fa33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -171,13 +171,15 @@ void amdgpu_ttm_placement_from_domain(struct 
amdgpu_bo *abo, u32 domain)

  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use, and returns it still
  * reserved.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
@@ -240,12 +242,14 @@ int amdgpu_bo_create_reserved(struct 
amdgpu_device *adev,

  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr:  used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
--
2.7.4

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[ANNOUNCE] xf86-video-ati 18.0.1

[Michel Dänzer]

I'm pleased to announce the 18.0.1 release of xf86-video-ati, the Xorg
driver for ATI/AMD Radeon GPUs supported by the radeon kernel driver.
This release supports xserver versions 1.13-1.19. It also works with
xserver 1.20 RC1, so unless something unexpected happens, it should work
with xserver 1.20 as well.

This is a bug-fix release addressing issues in 18.0.0. While those
issues shouldn't affect most users, I recommend that all users of 18.0.0
update to 18.0.1.

* The Xorg process could crash when multiple primary screens are
  configured in xorg.conf.
* TearFree could trigger debugging messages in the pixman library


Michel Dänzer (3):
  Wrap the whole miPointerScreenFuncRec, instead of only Set/MoveCursor
  Pass extents to radeon_scanout_do_update by value
  Bump version for 18.0.1 release

git tag: xf86-video-ati-18.0.1

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.1.tar.bz2
MD5:  40e7c0a5a69aba3d84e0958f58705ea7  xf86-video-ati-18.0.1.tar.bz2
SHA1: b5a0b6a2fa839d668a3fb90280fede95f0bc130d  xf86-video-ati-18.0.1.tar.bz2
SHA256: 72ea3b8127d4550b64f797457f5a7851a541fa4ee2cc3f345b6c1886b81714a0  
xf86-video-ati-18.0.1.tar.bz2
SHA512: 
b468a78503a596bbf71a1b91b231ce1fa32908f619ff2dfe249352d046696a3641f2a9ff065e32545fff77100134b4b237591215e78ef885b6509d6b16112d14
  xf86-video-ati-18.0.1.tar.bz2
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.1.tar.bz2.sig

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.1.tar.gz
MD5:  c31422ce05a21aedf7db9d53b80b3589  xf86-video-ati-18.0.1.tar.gz
SHA1: a810079f3c6e37b298661af5936d8d8f6886d03c  xf86-video-ati-18.0.1.tar.gz
SHA256: 41fc2ed7a36f02e89dd6765afd92700021f8126e77afe936317d47456c21d506  
xf86-video-ati-18.0.1.tar.gz
SHA512: 
2532f4be9dc62eab4bf2f55f64fffbf587ea96902ffda6f7ee54707a91986759fc385aef04991c5f6a857a611dc2686ff5e0a66f050dada68447f2657b5d28aa
  xf86-video-ati-18.0.1.tar.gz
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.1.tar.gz.sig


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer



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Re: [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel

[Andrey Grodzovsky]

That explains the merge conflict that surprised me :)


Thanks,

Andrey


On 03/15/2018 12:18 PM, Deucher, Alexander wrote:


For the series:

Reviewed-by: Alex Deucher 

I think Rex already applied the second one.



*From:* amd-gfx  on behalf of 
Andrey Grodzovsky 

*Sent:* Thursday, March 15, 2018 12:15 PM
*To:* amd-gfx@lists.freedesktop.org; ckoenig.leichtzumer...@gmail.com; 
Zhu, Rex

*Cc:* Grodzovsky, Andrey
*Subject:* [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr 
in amdgpu_bo_create_kernel

and amdgpu_bo_create_reserved.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 48e0115..ac1fa33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -171,13 +171,15 @@ void amdgpu_ttm_placement_from_domain(struct 
amdgpu_bo *abo, u32 domain)

  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use, and returns it still
  * reserved.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
@@ -240,12 +242,14 @@ int amdgpu_bo_create_reserved(struct 
amdgpu_device *adev,

  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr:  used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
--
2.7.4

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Re: [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel

[Deucher, Alexander]

For the series:

Reviewed-by: Alex Deucher 

I think Rex already applied the second one.



From: amd-gfx  on behalf of Andrey 
Grodzovsky 
Sent: Thursday, March 15, 2018 12:15 PM
To: amd-gfx@lists.freedesktop.org; ckoenig.leichtzumer...@gmail.com; Zhu, Rex
Cc: Grodzovsky, Andrey
Subject: [PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in 
amdgpu_bo_create_kernel

and amdgpu_bo_create_reserved.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 48e0115..ac1fa33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -171,13 +171,15 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo 
*abo, u32 domain)
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use, and returns it still
  * reserved.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
@@ -240,12 +242,14 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr:  used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
--
2.7.4

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[PATCH v2 2/2] drm/amd/powerplay: Fix KASAN user after after free on driver unload.

[Andrey Grodzovsky]

Reusing local handle to initialize BO without resetting it to
NULL is wrong since it causes amdgpu_bo_create_reserved to skip
new BO creation and just reuse the given pointer for pinning.

v2:
Get rid of mc_addr and kaddr.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   | 21 +++---
 .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c   | 48 +++---
 2 files changed, 21 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index e2ee23a..01fcfb9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -327,10 +327,7 @@ static int rv_start_smu(struct pp_hwmgr *hwmgr)
 
 static int rv_smu_init(struct pp_hwmgr *hwmgr)
 {
-   struct amdgpu_bo *handle = NULL;
struct rv_smumgr *priv;
-   uint64_t mc_addr;
-   void *kaddr = NULL;
int r;
 
priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL);
@@ -345,9 +342,9 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
sizeof(Watermarks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
-   &mc_addr,
-   &kaddr);
+   &priv->smu_tables.entry[WMTABLE].handle,
+   &priv->smu_tables.entry[WMTABLE].mc_addr,
+   &priv->smu_tables.entry[WMTABLE].table);
 
if (r)
return -EINVAL;
@@ -355,18 +352,15 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[WMTABLE].version = 0x01;
priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
-   priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
-   priv->smu_tables.entry[WMTABLE].table = kaddr;
-   priv->smu_tables.entry[WMTABLE].handle = handle;
 
/* allocate space for watermarks table */
r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(DpmClocks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
-   &mc_addr,
-   &kaddr);
+   &priv->smu_tables.entry[CLOCKTABLE].handle,
+   &priv->smu_tables.entry[CLOCKTABLE].mc_addr,
+   &priv->smu_tables.entry[CLOCKTABLE].table);
 
if (r) {
amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
@@ -378,9 +372,6 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t);
priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
-   priv->smu_tables.entry[CLOCKTABLE].mc_addr = mc_addr;
-   priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
-   priv->smu_tables.entry[CLOCKTABLE].handle = handle;
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 15e1afa..c13cf4e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -377,10 +377,7 @@ static int vega10_verify_smc_interface(struct pp_hwmgr 
*hwmgr)
 
 static int vega10_smu_init(struct pp_hwmgr *hwmgr)
 {
-   struct amdgpu_bo *handle = NULL;
struct vega10_smumgr *priv;
-   uint64_t mc_addr;
-   void *kaddr = NULL;
unsigned long tools_size;
int ret;
struct cgs_firmware_info info = {0};
@@ -403,9 +400,9 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
sizeof(PPTable_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
-   &mc_addr,
-   &kaddr);
+   &priv->smu_tables.entry[PPTABLE].handle,
+   &priv->smu_tables.entry[PPTABLE].mc_addr,
+   &priv->smu_tables.entry[PPTABLE].table);
 
if (ret)
return -EINVAL;
@@ -413,18 +410,15 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[PPTABLE].version = 0x01;
priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t);
priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
-   priv->smu_tables.entry[PPTABLE].mc_addr = mc_addr;
-   priv->smu_tables.entry[PPTABLE].table = kaddr;
-   priv->smu_tables.entry[PPTABLE].handle = handle;
 
/* allocate space for watermarks table */
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(Watermarks_t),
PAGE_SIZE,
AMDGP

[PATCH v2 1/2] drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel

[Andrey Grodzovsky]

and amdgpu_bo_create_reserved.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 48e0115..ac1fa33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -171,13 +171,15 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo 
*abo, u32 domain)
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use, and returns it still
  * reserved.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
@@ -240,12 +242,14 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr:  used to initialize BOs in structures
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
  * Allocates and pins a BO for kernel internal use.
  *
+ * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
+ *
  * Returns 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
-- 
2.7.4

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Re: [PATCH] drm/amd/display: Refine disable VGA

[Alex Deucher]

On Thu, Mar 15, 2018 at 11:07 AM, Harry Wentland  wrote:
> From: Clark Zheng 
>
> bad case won't follow normal sense, it will not enable vga1 as usual, but 
> vga2,3,4 is on.
>
> Signed-off-by: Clark Zheng 
> Reviewed-by: Tony Cheng 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h   |  8 +++-
>  .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 20 
> +++-
>  2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
> b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
> index 18dbd0bd7874..057b8afd74bc 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
> @@ -408,6 +408,9 @@ struct dce_hwseq_registers {
> HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
> HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
> HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
> +   HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
> +   HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
> +   HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
> HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
> HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
> HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
> @@ -497,7 +500,10 @@ struct dce_hwseq_registers {
> type DENTIST_DISPCLK_WDIVIDER; \
> type VGA_TEST_ENABLE; \
> type VGA_TEST_RENDER_START; \
> -   type D1VGA_MODE_ENABLE;
> +   type D1VGA_MODE_ENABLE; \
> +   type D2VGA_MODE_ENABLE; \
> +   type D3VGA_MODE_ENABLE; \
> +   type D4VGA_MODE_ENABLE;
>
>  struct dce_hwseq_shift {
> HWSEQ_REG_FIELD_LIST(uint8_t)
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 4365906b14ee..8b0f6b8a5627 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -220,14 +220,24 @@ static void enable_power_gating_plane(
>  static void disable_vga(
> struct dce_hwseq *hws)
>  {
> -   unsigned int in_vga_mode = 0;
> -
> -   REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
> -
> -   if (in_vga_mode == 0)
> +   unsigned int in_vga1_mode = 0;
> +   unsigned int in_vga2_mode = 0;
> +   unsigned int in_vga3_mode = 0;
> +   unsigned int in_vga4_mode = 0;
> +
> +   REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
> +   REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
> +   REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
> +   REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
> +
> +   if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
> +   in_vga3_mode == 0 && in_vga4_mode == 0)
> return;
>
> REG_WRITE(D1VGA_CONTROL, 0);
> +   REG_WRITE(D2VGA_CONTROL, 0);
> +   REG_WRITE(D3VGA_CONTROL, 0);
> +   REG_WRITE(D4VGA_CONTROL, 0);
>
> /* HW Engineer's Notes:
>  *  During switch from vga->extended, if we set the VGA_TEST_ENABLE 
> and
> --
> 2.14.1
>
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[ANNOUNCE] xf86-video-amdgpu 18.0.1

[Michel Dänzer]

I'm pleased to announce the 18.0.1 release of xf86-video-amdgpu, the
Xorg driver for AMD Radeon GPUs supported by the amdgpu kernel driver.
This release supports xserver versions 1.13-1.19. It also works with
xserver 1.20 RC1, so unless something unexpected happens, it should work
with xserver 1.20 as well.

This is a bug-fix release addressing issues in 18.0.0. While those
issues shouldn't affect most users, I recommend that all users of 18.0.0
update to 18.0.1.

* The Xorg process could enter an infinite loop after a server reset (in
  configurations where Xorg doesn't terminate when the last client
  disconnects)
* The Xorg process could crash when multiple primary screens are
  configured in xorg.conf.
* TearFree could trigger debugging messages in the pixman library


Michel Dänzer (4):
  Only change Set/MoveCursor hooks from what we expect
  Wrap the whole miPointerScreenFuncRec, instead of only Set/MoveCursor
  Pass extents to amdgpu_scanout_do_update by value
  Bump version for 18.0.1 release

git tag: xf86-video-amdgpu-18.0.1

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-18.0.1.tar.bz2
MD5:  d8368d204cb98d4387c8890562db1143  xf86-video-amdgpu-18.0.1.tar.bz2
SHA1: a9c7125eae9870f26afa5167d5683f8d5e1b43c0  xf86-video-amdgpu-18.0.1.tar.bz2
SHA256: 7484682ccb403b3ca9e26d1c980572f08cdfa3469e2b2c9a9affc3d51b52691b  
xf86-video-amdgpu-18.0.1.tar.bz2
SHA512: 
eb3b76240d4e5084d68b5063b5b19ad5f5bb1f93ea9929301d9e17a48ddc1cb713b76529cb93d133b3547fe78ae8a4455f6b15f6ddf88c29349f82bb1a0db1c4
  xf86-video-amdgpu-18.0.1.tar.bz2
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-18.0.1.tar.bz2.sig

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-18.0.1.tar.gz
MD5:  b47ac1d853a5c9327c526b6ad858dfd0  xf86-video-amdgpu-18.0.1.tar.gz
SHA1: 6de47bf590bb3c931da323341c326ab19e159f27  xf86-video-amdgpu-18.0.1.tar.gz
SHA256: 5cbbc37aeb6c451e0d446e6e653ae2bf9269727c6394f0751507bb23ad6c16b2  
xf86-video-amdgpu-18.0.1.tar.gz
SHA512: 
857b9cf817f3cb676abd850b05286037f6c236fbdf7012af5f25424cd2436bc852cd08e3bfdd8f401e827824158344f1243f6f79aed07e28c5ca6769f806
  xf86-video-amdgpu-18.0.1.tar.gz
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-18.0.1.tar.gz.sig


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Libre software enthusiast | Mesa and X developer



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Re: Ryzen 5 2400G Stuttering since 2018-03-07

[Harry Wentland]

On 2018-03-15 11:01 AM, Michel Dänzer wrote:
> On 2018-03-15 03:47 PM, Dawson Dias wrote:
>> Here we go! The logs are attached. I turned TearFree to `on` from
>> `auto`, dragged some windows around, and captured them.
>> AFAIK, I haven't made any changes via xrandr, except for toggling the
>> TearFree property.
> 
> Thanks. I don't see any obvious issue in your attachments. I think it's
> most likely a kernel DC issue. I saw Harry just filed an internal bug
> report that might be related.
> 

I'm not sure the internal bug is related here, but it could be. I noticed 
problems when Freesync testing but I assume it was a much older regression. I 
haven't seen flickering on normal desktop but I haven't played with Raven 
recently or tried TearFree recently.

Dawson, mind opening a ticket on https://bugs.freedesktop.org/ to track this?

Harry

> 
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Re: [PATCH] drm/amd/display: Correct VGA handoff for DCN1 devices

[Harry Wentland]

On 2018-03-15 09:47 AM, Tom St Denis wrote:
> Partial revert of 1b0ff66bc0bf1a0559255cb7b066a65d55491974
> 
> Signed-off-by: Tom St Denis 

Thanks for your patch.

It seems like on some systems this is not enough as D1 is off and D2-4 are on, 
which would still early return from this function. I sent a patch that should 
resolve this in all cases.

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 4365906b14ee..7688ed5724b9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -228,6 +228,9 @@ static void disable_vga(
>   return;
>  
>   REG_WRITE(D1VGA_CONTROL, 0);
> + REG_WRITE(D2VGA_CONTROL, 0);
> + REG_WRITE(D3VGA_CONTROL, 0);
> + REG_WRITE(D4VGA_CONTROL, 0);
>  
>   /* HW Engineer's Notes:
>*  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
> 
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[PATCH] drm/amd/display: Refine disable VGA

[Harry Wentland]

From: Clark Zheng 

bad case won't follow normal sense, it will not enable vga1 as usual, but 
vga2,3,4 is on.

Signed-off-by: Clark Zheng 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h   |  8 +++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 20 +++-
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 18dbd0bd7874..057b8afd74bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -408,6 +408,9 @@ struct dce_hwseq_registers {
HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
+   HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
+   HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
+   HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
@@ -497,7 +500,10 @@ struct dce_hwseq_registers {
type DENTIST_DISPCLK_WDIVIDER; \
type VGA_TEST_ENABLE; \
type VGA_TEST_RENDER_START; \
-   type D1VGA_MODE_ENABLE;
+   type D1VGA_MODE_ENABLE; \
+   type D2VGA_MODE_ENABLE; \
+   type D3VGA_MODE_ENABLE; \
+   type D4VGA_MODE_ENABLE;
 
 struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 4365906b14ee..8b0f6b8a5627 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -220,14 +220,24 @@ static void enable_power_gating_plane(
 static void disable_vga(
struct dce_hwseq *hws)
 {
-   unsigned int in_vga_mode = 0;
-
-   REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
-
-   if (in_vga_mode == 0)
+   unsigned int in_vga1_mode = 0;
+   unsigned int in_vga2_mode = 0;
+   unsigned int in_vga3_mode = 0;
+   unsigned int in_vga4_mode = 0;
+
+   REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
+   REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
+   REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
+   REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
+
+   if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
+   in_vga3_mode == 0 && in_vga4_mode == 0)
return;
 
REG_WRITE(D1VGA_CONTROL, 0);
+   REG_WRITE(D2VGA_CONTROL, 0);
+   REG_WRITE(D3VGA_CONTROL, 0);
+   REG_WRITE(D4VGA_CONTROL, 0);
 
/* HW Engineer's Notes:
 *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
-- 
2.14.1

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Re: [PATCH V2] drm/amdgpu: Disable irq on device before destroying it

[Harry Wentland]

On 2018-03-15 10:50 AM, mikita.lip...@amd.com wrote:
> From: Mikita Lipski 
> 
> Disable irq on devices before destroying them. That prevents
> use-after-free memory access when unloading the driver.
> 
> Signed-off-by: Mikita Lipski 
> Reviewed-by: Alex Deucher 

Acked-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index b4911911..0b798cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1432,6 +1432,9 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
> *adev)
>   int i, r;
>  
>   amdgpu_amdkfd_device_fini(adev);
> + /* disable all interrupts */
> + amdgpu_irq_disable_all(adev);
> +
>   /* need to disable SMC first */
>   for (i = 0; i < adev->num_ip_blocks; i++) {
>   if (!adev->ip_blocks[i].status.hw)
> @@ -1482,8 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
> *adev)
>   adev->ip_blocks[i].status.hw = false;
>   }
>  
> - /* disable all interrupts */
> - amdgpu_irq_disable_all(adev);
>  
>   for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
>   if (!adev->ip_blocks[i].status.sw)
> 
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Re: Ryzen 5 2400G Stuttering since 2018-03-07

[Michel Dänzer]

On 2018-03-15 03:47 PM, Dawson Dias wrote:
> Here we go! The logs are attached. I turned TearFree to `on` from
> `auto`, dragged some windows around, and captured them.
> AFAIK, I haven't made any changes via xrandr, except for toggling the
> TearFree property.

Thanks. I don't see any obvious issue in your attachments. I think it's
most likely a kernel DC issue. I saw Harry just filed an internal bug
report that might be related.


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Libre software enthusiast | Mesa and X developer
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Re: [PATCH V2] drm/amdgpu: Disable irq on device before destroying it

[Christian König]

Am 15.03.2018 um 15:50 schrieb mikita.lip...@amd.com:

From: Mikita Lipski 

Disable irq on devices before destroying them. That prevents
use-after-free memory access when unloading the driver.

Signed-off-by: Mikita Lipski 
Reviewed-by: Alex Deucher 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b4911911..0b798cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1432,6 +1432,9 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
int i, r;
  
  	amdgpu_amdkfd_device_fini(adev);

+   /* disable all interrupts */
+   amdgpu_irq_disable_all(adev);
+
/* need to disable SMC first */
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.hw)
@@ -1482,8 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
adev->ip_blocks[i].status.hw = false;
}
  
-	/* disable all interrupts */

-   amdgpu_irq_disable_all(adev);
  
  	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

if (!adev->ip_blocks[i].status.sw)


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[PATCH V2] drm/amdgpu: Disable irq on device before destroying it

[mikita.lipski]

From: Mikita Lipski 

Disable irq on devices before destroying them. That prevents
use-after-free memory access when unloading the driver.

Signed-off-by: Mikita Lipski 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b4911911..0b798cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1432,6 +1432,9 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
int i, r;
 
amdgpu_amdkfd_device_fini(adev);
+   /* disable all interrupts */
+   amdgpu_irq_disable_all(adev);
+
/* need to disable SMC first */
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.hw)
@@ -1482,8 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
adev->ip_blocks[i].status.hw = false;
}
 
-   /* disable all interrupts */
-   amdgpu_irq_disable_all(adev);
 
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.sw)
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: Disable irq on device before destroying it

[Alex Deucher]

On Thu, Mar 15, 2018 at 10:23 AM, Mikita Lipski  wrote:
>
>
> On 2018-03-15 10:15 AM, Alex Deucher wrote:
>>
>> On Thu, Mar 15, 2018 at 10:10 AM,   wrote:
>>>
>>> From: Mikita Lipski 
>>>
>>> Disable irq on devices before destroying them. That prevents
>>> use-after-free memory access when unloading the driver.
>>>
>>> Signed-off-by: Mikita Lipski 
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
>>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index b4911911..593396f 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -1456,6 +1456,9 @@ static int amdgpu_device_ip_fini(struct
>>> amdgpu_device *adev)
>>>  }
>>>  }
>>>
>>> +   /* disable all interrupts */
>>> +   amdgpu_irq_disable_all(adev);
>>> +
>>
>>
>> Any reason not to move this to the top of this function before the SMC
>> loop?
>>
>> Alex
>
>
> It can be done, but it does not seem to have any functional effect.
> The use-after-free corruption is caused by disabling DCE's irq after
> destroying it.

It would just avoid the same potential issue in the SMC module in the
future.  Either way:
Reviewed-by: Alex Deucher 

>
> Nik
>
>
>>
>>>  for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
>>>  if (!adev->ip_blocks[i].status.hw)
>>>  continue;
>>> @@ -1482,8 +1485,6 @@ static int amdgpu_device_ip_fini(struct
>>> amdgpu_device *adev)
>>>  adev->ip_blocks[i].status.hw = false;
>>>  }
>>>
>>> -   /* disable all interrupts */
>>> -   amdgpu_irq_disable_all(adev);
>>>
>>>  for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
>>>  if (!adev->ip_blocks[i].status.sw)
>>> --
>>> 2.7.4
>>>
>>> ___
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Re: [PATCH] drm/amdgpu: Disable irq on device before destroying it

[Mikita Lipski]

On 2018-03-15 10:15 AM, Alex Deucher wrote:

On Thu, Mar 15, 2018 at 10:10 AM,   wrote:

From: Mikita Lipski 

Disable irq on devices before destroying them. That prevents
use-after-free memory access when unloading the driver.

Signed-off-by: Mikita Lipski 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b4911911..593396f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1456,6 +1456,9 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
 }
 }

+   /* disable all interrupts */
+   amdgpu_irq_disable_all(adev);
+


Any reason not to move this to the top of this function before the SMC loop?

Alex


It can be done, but it does not seem to have any functional effect.
The use-after-free corruption is caused by disabling DCE's irq after 
destroying it.


Nik




 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
 if (!adev->ip_blocks[i].status.hw)
 continue;
@@ -1482,8 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
 adev->ip_blocks[i].status.hw = false;
 }

-   /* disable all interrupts */
-   amdgpu_irq_disable_all(adev);

 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
 if (!adev->ip_blocks[i].status.sw)
--
2.7.4

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Re: [PATCH] drm/amdgpu: Disable irq on device before destroying it

[Alex Deucher]

On Thu, Mar 15, 2018 at 10:10 AM,   wrote:
> From: Mikita Lipski 
>
> Disable irq on devices before destroying them. That prevents
> use-after-free memory access when unloading the driver.
>
> Signed-off-by: Mikita Lipski 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index b4911911..593396f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1456,6 +1456,9 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
> *adev)
> }
> }
>
> +   /* disable all interrupts */
> +   amdgpu_irq_disable_all(adev);
> +

Any reason not to move this to the top of this function before the SMC loop?

Alex

> for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> if (!adev->ip_blocks[i].status.hw)
> continue;
> @@ -1482,8 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
> *adev)
> adev->ip_blocks[i].status.hw = false;
> }
>
> -   /* disable all interrupts */
> -   amdgpu_irq_disable_all(adev);
>
> for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> if (!adev->ip_blocks[i].status.sw)
> --
> 2.7.4
>
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[PATCH] drm/amdgpu: Disable irq on device before destroying it

[mikita.lipski]

From: Mikita Lipski 

Disable irq on devices before destroying them. That prevents
use-after-free memory access when unloading the driver.

Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b4911911..593396f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1456,6 +1456,9 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
}
}
 
+   /* disable all interrupts */
+   amdgpu_irq_disable_all(adev);
+
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.hw)
continue;
@@ -1482,8 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
adev->ip_blocks[i].status.hw = false;
}
 
-   /* disable all interrupts */
-   amdgpu_irq_disable_all(adev);
 
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.sw)
-- 
2.7.4

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[PATCH] drm/amd/display: Correct VGA handoff for DCN1 devices

[Tom St Denis]

Partial revert of 1b0ff66bc0bf1a0559255cb7b066a65d55491974

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 4365906b14ee..7688ed5724b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -228,6 +228,9 @@ static void disable_vga(
return;
 
REG_WRITE(D1VGA_CONTROL, 0);
+   REG_WRITE(D2VGA_CONTROL, 0);
+   REG_WRITE(D3VGA_CONTROL, 0);
+   REG_WRITE(D4VGA_CONTROL, 0);
 
/* HW Engineer's Notes:
 *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
-- 
2.14.3

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Re: [PATCH] drm/amd/display: fix dereferencing possible ERR_PTR()

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: S, Shirish
Sent: Thursday, March 15, 2018 6:33:51 AM
To: Deucher, Alexander; Wentland, Harry; amd-gfx@lists.freedesktop.org
Cc: S, Shirish
Subject: [PATCH] drm/amd/display: fix dereferencing possible ERR_PTR()

This patch fixes static checker warning caused by
"36cc549d5986: "drm/amd/display: disable CRTCs with
NULL FB on their primary plane (V2)"

Reported-by: Dan Carpenter 
Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0564676..9e2cdc9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4893,6 +4893,9 @@ static int dm_atomic_check_plane_state_fb(struct 
drm_atomic_state *state,
 return -EDEADLK;

 crtc_state = drm_atomic_get_crtc_state(plane_state->state, 
crtc);
+   if (IS_ERR(crtc_state))
+   return PTR_ERR(crtc_state);
+
 if (crtc->primary == plane && crtc_state->active) {
 if (!plane_state->fb)
 return -EINVAL;
--
2.7.4

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Re: [PATCH] drm/amd/pp: Remove the cgs wrapper for notify smu version on APU

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Thursday, March 15, 2018 2:47:21 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Remove the cgs wrapper for notify smu version on 
APU

Refine the commit f49e9bac191b066060a53d994f9c964fb71454f2
drm/amd/pp: Get and save Rv smu version

Change-Id: Iea668cc2161e5fcf339b408eb7eca1b028e26df2
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 -
 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 6 ++
 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c  | 6 +++---
 3 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index f2dd98d..37098c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -654,11 +654,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device 
*cgs_device,
 else
 strcpy(fw_name, 
"amdgpu/vega10_smc.bin");
 break;
-   case CHIP_CARRIZO:
-   case CHIP_STONEY:
-   case CHIP_RAVEN:
-   adev->pm.fw_version = info->version;
-   return 0;
 default:
 DRM_ERROR("SMC firmware not supported\n");
 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index 6ee9822..bed229e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -247,13 +247,11 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr)

 static int smu10_start_smu(struct pp_hwmgr *hwmgr)
 {
-   struct cgs_firmware_info info = {0};
+   struct amdgpu_device *adev = hwmgr->adev;

 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
 hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
-   info.version = hwmgr->smu_version >> 8;
-
-   cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+   adev->pm.fw_version = hwmgr->smu_version >> 8;

 if (smu10_verify_smc_interface(hwmgr))
 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
index 480deb2..8c49704 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
@@ -698,7 +698,8 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
 {
 int ret = 0;
 uint32_t fw_to_check = 0;
-   struct cgs_firmware_info info = {0};
+   struct amdgpu_device *adev = hwmgr->adev;
+
 uint32_t index = SMN_MP1_SRAM_START_ADDR +
  SMU8_FIRMWARE_HEADER_LOCATION +
  offsetof(struct SMU8_Firmware_Header, Version);
@@ -709,8 +710,7 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)

 cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
 hwmgr->smu_version = cgs_read_register(hwmgr->device, 
mmMP0PUB_IND_DATA);
-   info.version = hwmgr->smu_version >> 8;
-   cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+   adev->pm.fw_version = hwmgr->smu_version >> 8;

 fw_to_check = UCODE_ID_RLC_G_MASK |
 UCODE_ID_SDMA0_MASK |
--
1.9.1

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Re: [PATCH 1/4] dma-buf: add optional invalidate_mappings callback

[Daniel Vetter]

On Thu, Mar 15, 2018 at 10:56 AM, Christian König
 wrote:
> Am 15.03.2018 um 10:20 schrieb Daniel Vetter:
>>
>> On Tue, Mar 13, 2018 at 06:20:07PM +0100, Christian König wrote:
>> [SNIP]
>> Take a look at the DOT graphs for atomic I've done a while ago. I think we
>> could make a formidable competition for who's doing the worst diagrams :-)
>
>
> Thanks, going to give that a try.
>
>> [SNIP]
>> amdgpu: Expects that you never hold any of the heavywheight locks while
>> waiting for a fence (since gpu resets will need them).
>>
>> i915: Happily blocks on fences while holding all kinds of locks, expects
>> gpu reset to be able to recover even in this case.
>
>
> In this case I can comfort you, the looks amdgpu needs to grab during GPU
> reset are the reservation lock of the VM page tables. I have strong doubt
> that i915 will ever hold those.

Ah good, means that very likely there's at least no huge fundamental
design issue that we run into.

> Could be that we run into problems because Thread A hold lock 1 tries to
> take lock 2, then i915 holds 2 and our reset path needs 1.

Yeah that might happen, but lockdep will catch those, and generally
those cases can be fixed with slight reordering or re-annotating of
the code to avoid upsetting lockdep. As long as we don't have a
full-on functional dependency (which is what I've feared).

>> [SNIP]
>>>
>>> Yes, except for fallback paths and bootup self tests we simply never wait
>>> for fences while holding locks.
>>
>> That's not what I meant with "are you sure". Did you enable the
>> cross-release stuff (after patching the bunch of leftover core kernel
>> issues still present), annotate dma_fence with the cross-release stuff,
>> run a bunch of multi-driver (amdgpu vs i915) dma-buf sharing tests and
>> weep?
>
>
> Ok, what exactly do you mean with cross-release checking?

Current lockdep doesn't spot deadlocks like the below:

thread A: holds mutex, waiting for completion.

thread B: acquires mutex before it will ever signal the completion A
is waiting for

->deadlock

cross-release lockdep support can catch these through new fancy
annotations. Similar waiter/signaller annotations exists for waiting
on workers and anything else, and it would be a perfect fit for
waiter/signaller code around dma_fence.

lwn has you covered a usual: https://lwn.net/Articles/709849/

Cheers, Daniel

>> I didn't do the full thing yet, but just within i915 we've found tons of
>> small little deadlocks we never really considered thanks to cross release,
>> and that wasn't even including the dma_fence annotation. Luckily nothing
>> that needed a full-on driver redesign.
>>
>> I guess I need to ping core kernel maintainers about cross-release again.
>> I'd much prefer if we could validate ->invalidate_mapping and the
>> locking/fence dependency issues using that, instead of me having to read
>> and understand all the drivers.
>
> [SNIP]
>>
>> I fear that with the ->invalidate_mapping callback (which inverts the
>> control flow between importer and exporter) and tying dma_fences into all
>> this it will be a _lot_ worse. And I'm definitely too stupid to understand
>> all the dependency chains without the aid of lockdep and a full test suite
>> (we have a bunch of amdgpu/i915 dma-buf tests in igt btw).
>
>
> Yes, that is also something I worry about.
>
> Regards,
> Christian.



-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH] drm/amd/display: fix dereferencing possible ERR_PTR()

[Shirish S]

This patch fixes static checker warning caused by
"36cc549d5986: "drm/amd/display: disable CRTCs with
NULL FB on their primary plane (V2)"

Reported-by: Dan Carpenter 
Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0564676..9e2cdc9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4893,6 +4893,9 @@ static int dm_atomic_check_plane_state_fb(struct 
drm_atomic_state *state,
return -EDEADLK;
 
crtc_state = drm_atomic_get_crtc_state(plane_state->state, 
crtc);
+   if (IS_ERR(crtc_state))
+   return PTR_ERR(crtc_state);
+
if (crtc->primary == plane && crtc_state->active) {
if (!plane_state->fb)
return -EINVAL;
-- 
2.7.4

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Re: [PATCH 1/4] dma-buf: add optional invalidate_mappings callback

[Christian König]

Am 15.03.2018 um 10:20 schrieb Daniel Vetter:

On Tue, Mar 13, 2018 at 06:20:07PM +0100, Christian König wrote:
[SNIP]
Take a look at the DOT graphs for atomic I've done a while ago. I think we
could make a formidable competition for who's doing the worst diagrams :-)


Thanks, going to give that a try.


[SNIP]
amdgpu: Expects that you never hold any of the heavywheight locks while
waiting for a fence (since gpu resets will need them).

i915: Happily blocks on fences while holding all kinds of locks, expects
gpu reset to be able to recover even in this case.


In this case I can comfort you, the looks amdgpu needs to grab during 
GPU reset are the reservation lock of the VM page tables. I have strong 
doubt that i915 will ever hold those.


Could be that we run into problems because Thread A hold lock 1 tries to 
take lock 2, then i915 holds 2 and our reset path needs 1.



[SNIP]

Yes, except for fallback paths and bootup self tests we simply never wait
for fences while holding locks.

That's not what I meant with "are you sure". Did you enable the
cross-release stuff (after patching the bunch of leftover core kernel
issues still present), annotate dma_fence with the cross-release stuff,
run a bunch of multi-driver (amdgpu vs i915) dma-buf sharing tests and
weep?


Ok, what exactly do you mean with cross-release checking?


I didn't do the full thing yet, but just within i915 we've found tons of
small little deadlocks we never really considered thanks to cross release,
and that wasn't even including the dma_fence annotation. Luckily nothing
that needed a full-on driver redesign.

I guess I need to ping core kernel maintainers about cross-release again.
I'd much prefer if we could validate ->invalidate_mapping and the
locking/fence dependency issues using that, instead of me having to read
and understand all the drivers.

[SNIP]

I fear that with the ->invalidate_mapping callback (which inverts the
control flow between importer and exporter) and tying dma_fences into all
this it will be a _lot_ worse. And I'm definitely too stupid to understand
all the dependency chains without the aid of lockdep and a full test suite
(we have a bunch of amdgpu/i915 dma-buf tests in igt btw).


Yes, that is also something I worry about.

Regards,
Christian.
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Re: [PATCH 2/2] drm/amd/powerplay: Fix KASAN user after free on driver unload.

[Zhu, Rex]

Apply this patch with Christian's suggestions.


Thanks.


Best Regards

Rex



From: Christian König 
Sent: Thursday, March 15, 2018 2:21 AM
To: Grodzovsky, Andrey; amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex; Koenig, Christian
Subject: Re: [PATCH 2/2] drm/amd/powerplay: Fix KASAN user after free on driver 
unload.

Am 14.03.2018 um 19:07 schrieb Andrey Grodzovsky:
> Reusing local handle to initialize BO without resetting it to
> NULL is wrong since it causes amdgpu_bo_create_reserved to skip
> new BO creation and just reuse the given pointer for pinning.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>   drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c |  7 ++-
>   drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 16 +---
>   2 files changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> index e2ee23a..65c6ca7 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> @@ -327,7 +327,6 @@ static int rv_start_smu(struct pp_hwmgr *hwmgr)
>
>   static int rv_smu_init(struct pp_hwmgr *hwmgr)
>   {
> - struct amdgpu_bo *handle = NULL;
>struct rv_smumgr *priv;
>uint64_t mc_addr;
>void *kaddr = NULL;
> @@ -345,7 +344,7 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
>sizeof(Watermarks_t),
>PAGE_SIZE,
>AMDGPU_GEM_DOMAIN_VRAM,
> - &handle,
> + &priv->smu_tables.entry[WMTABLE].handle,
>&mc_addr,
>&kaddr);
>
> @@ -357,14 +356,13 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
>priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
>priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
>priv->smu_tables.entry[WMTABLE].table = kaddr;
> - priv->smu_tables.entry[WMTABLE].handle = handle;
>
>/* allocate space for watermarks table */
>r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
>sizeof(DpmClocks_t),
>PAGE_SIZE,
>AMDGPU_GEM_DOMAIN_VRAM,
> - &handle,
> + &priv->smu_tables.entry[CLOCKTABLE].handle,
>&mc_addr,
>&kaddr);
>
> @@ -380,7 +378,6 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
>priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
>priv->smu_tables.entry[CLOCKTABLE].mc_addr = mc_addr;
>priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
> - priv->smu_tables.entry[CLOCKTABLE].handle = handle;
>
>return 0;
>   }
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> index 15e1afa..c8b326e 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> @@ -377,7 +377,6 @@ static int vega10_verify_smc_interface(struct pp_hwmgr 
> *hwmgr)
>
>   static int vega10_smu_init(struct pp_hwmgr *hwmgr)
>   {
> - struct amdgpu_bo *handle = NULL;
>struct vega10_smumgr *priv;
>uint64_t mc_addr;
>void *kaddr = NULL;
> @@ -403,7 +402,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
>sizeof(PPTable_t),
>PAGE_SIZE,
>AMDGPU_GEM_DOMAIN_VRAM,
> - &handle,
> + &priv->smu_tables.entry[PPTABLE].handle,
>&mc_addr,
>&kaddr);
>
> @@ -415,14 +414,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
>priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
>priv->smu_tables.entry[PPTABLE].mc_addr = mc_addr;
>priv->smu_tables.entry[PPTABLE].table = kaddr;
> - priv->smu_tables.entry[PPTABLE].handle = handle;
>
>/* allocate space for watermarks table */
>ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
>sizeof(Watermarks_t),
>PAGE_SIZE,
>AMDGPU_GEM_DOMAIN_VRAM,
> - &handle,
> + &priv->smu_tables.entry[WMTABLE].handle,
>&mc_addr,
>&kaddr);
>
> @@ -434,14 +432,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
>priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
>priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
>priv->smu_tables.entry[WMTABLE].table = kaddr;
> - priv->smu_tables.entry[WMTABLE].handle = handle;
>
>/* allocate space for AVFS table */
>ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
>sizeof(AvfsTable_t),
>

Re: [PATCH 1/4] dma-buf: add optional invalidate_mappings callback

[Daniel Vetter]

On Tue, Mar 13, 2018 at 06:20:07PM +0100, Christian König wrote:
> Am 13.03.2018 um 17:00 schrieb Daniel Vetter:
> > On Tue, Mar 13, 2018 at 04:52:02PM +0100, Christian König wrote:
> > > Am 13.03.2018 um 16:17 schrieb Daniel Vetter:
> > > [SNIP]
> > Ok, so plan is to support fully pipeline moves and everything, with the
> > old sg tables lazily cleaned up. I was thinking more about evicting stuff
> > and throwing it out, where there's not going to be any new sg list but the
> > object is going to be swapped out.
> 
> Yes, exactly. Well my example was the unlikely case when the object is
> swapped out and immediately swapped in again because somebody needs it.
> 
> > 
> > I think some state flow charts (we can do SVG or DOT) in the kerneldoc
> > would be sweet.Yeah, probably a good idea.
> 
> Sounds good and I find it great that you're volunteering for that :D
> 
> Ok seriously, my drawing capabilities are a bit underdeveloped. So I would
> prefer if somebody could at least help with that.

Take a look at the DOT graphs for atomic I've done a while ago. I think we
could make a formidable competition for who's doing the worst diagrams :-)

> > > > Re GPU might cause a deadlock: Isn't that already a problem if you hold
> > > > reservations of buffers used on other gpus, which want those 
> > > > reservations
> > > > to complete the gpu reset, but that gpu reset blocks some fence that the
> > > > reservation holder is waiting for?
> > > Correct, that's why amdgpu and TTM tries quite hard to never wait for a
> > > fence while a reservation object is locked.
> > We might have a fairly huge mismatch of expectations here :-/
> 
> What do you mean with that?

i915 expects that other drivers don't have this requirement. Our gpu reset
can proceed even if it's all locked down.

> > > The only use case I haven't fixed so far is reaping deleted object during
> > > eviction, but that is only a matter of my free time to fix it.
> > Yeah, this is the hard one.
> 
> Actually it isn't so hard, it's just that I didn't had time so far to clean
> it up and we never hit that issue so far during our reset testing.
> 
> The main point missing just a bit of functionality in the reservation object
> and Chris and I already had a good idea how to implement that.
> 
> > In general the assumption is that dma_fence will get signalled no matter
> > what you're doing, assuming the only thing you need is to not block
> > interrupts. The i915 gpu reset logic to make that work is a bit a work of
> > art ...
> 
> Correct, but I don't understand why that is so hard on i915? Our GPU
> scheduler makes all of that rather trivial, e.g. fences either signal
> correctly or are aborted and set as erroneous after a timeout.

Yes, i915 does the same. It's the locking requirement we disagree on, i915
can reset while holding locks. I think right now we don't reset while
holding reservation locks, but only while holding our own locks. I think
cross-release would help model us this and uncover all the funny
dependency loops we have.

The issue I'm seeing:

amdgpu: Expects that you never hold any of the heavywheight locks while
waiting for a fence (since gpu resets will need them).

i915: Happily blocks on fences while holding all kinds of locks, expects
gpu reset to be able to recover even in this case.

Both drivers either complete the fence (with or without setting the error
status to EIO or something like that), that's not the difference. The work
of art I referenced is how we managed to complete gpu reset (including
resubmitting) while holding plenty of locks.

> > If we expect amdgpu and i915 to cooperate with shared buffers I guess one
> > has to give in. No idea how to do that best.
> 
> Again at least from amdgpu side I don't see much of an issue with that. So
> what exactly do you have in mind here?
> 
> > > > We have tons of fun with deadlocks against GPU resets, and loots of
> > > > testcases, and I kinda get the impression amdgpu is throwing a lot of
> > > > issues under the rug through trylock tricks that shut up lockdep, but
> > > > don't fix much really.
> > > Hui? Why do you think that? The only trylock I'm aware of is during 
> > > eviction
> > > and there it isn't a problem.
> > mmap fault handler had one too last time I looked, and it smelled fishy.
> 
> Good point, never wrapped my head fully around that one either.
> 
> > > > btw adding cross-release lockdep annotations for fences will probably 
> > > > turn
> > > > up _lots_ more bugs in this area.
> > > At least for amdgpu that should be handled by now.
> > You're sure? :-)
> 
> Yes, except for fallback paths and bootup self tests we simply never wait
> for fences while holding locks.

That's not what I meant with "are you sure". Did you enable the
cross-release stuff (after patching the bunch of leftover core kernel
issues still present), annotate dma_fence with the cross-release stuff,
run a bunch of multi-driver (amdgpu vs i915) dma-buf sharing tests and
weep?

I didn't do th

Re: Debugging modesetting problem

[Michel Dänzer]

On 2018-03-15 12:52 AM, Jona Stubbe wrote:
> Hi AMD graphics developers,
> 
> I've recently hit a modesetting problem: when I used the DisplayPort KVM 
> switch that I got yesterday to connect my PC (running Arch Linux) to my 4K 
> monitor, it only worked in 3 out of about 60 times of switching/replugging 
> the 
> cable (the BIOS always manages to put something onscreen, though).
> I've tried both graphics cards available to me right now: a Polaris (RX 480) 
> and a Cayman (HD 6950/6970) and neither of them modesets properly and 
> reliably.

With the Polaris card, does enabling DC help? (kernel >= 4.15,
CONFIG_DRM_AMD_DC=y, amdgpu.dc=1 on the kernel command line)


> PS: if there is a shorter-latency way of asking this kind of question (like 
> an 
> IRC channel), I'd be interested too :)

There is #radeon on FreeNode.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer



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Re: Ryzen 5 2400G Stuttering since 2018-03-07

[Michel Dänzer]

On 2018-03-15 08:51 AM, Dawson Dias wrote:
> I managed to pinpoint the issue. The stuttering is caused by enabling
> TearFree via xrandr. When on `auto`, there is no stuttering, but when
> enabled by setting it to `on`, there is intense stuttering noticeable
> when dragging windows around, but it's also very noticeable when just
> moving the mouse around on the desktop with no windows open.

Please share the Xorg log and output of dmesg and

 xrandr --verbose

captured while the stuttering is occurring.


> I use Openbox with Compton for compositing.

FWIW, with compton you shouldn't need TearFree (unless you use rotation
or other RandR transformations, but in that case it's active with auto
as well). But it's supposed to work without stuttering anyway, obviously.


-- 
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Libre software enthusiast | Mesa and X developer
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[bug report] drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)

[Dan Carpenter]

Hello Shirish S,

The patch 36cc549d5986: "drm/amd/display: disable CRTCs with NULL FB
on their primary plane (V2)" from Feb 28, 2018, leads to the
following static checker warning:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4827 
dm_atomic_check_plane_state_fb()
error: 'crtc_state' dereferencing possible ERR_PTR()

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
  4811  static int dm_atomic_check_plane_state_fb(struct drm_atomic_state 
*state,
  4812struct drm_crtc *crtc)
  4813  {
  4814  struct drm_plane *plane;
  4815  struct drm_crtc_state *crtc_state;
  4816  
  4817  WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));
  4818  
  4819  drm_for_each_plane_mask(plane, state->dev, 
crtc->state->plane_mask) {
  4820  struct drm_plane_state *plane_state =
  4821  drm_atomic_get_plane_state(state, plane);
  4822  
  4823  if (IS_ERR(plane_state))
  4824  return -EDEADLK;
  4825  
  4826  crtc_state = 
drm_atomic_get_crtc_state(plane_state->state, crtc);
^^
  4827  if (crtc->primary == plane && crtc_state->active) {
  ^^
  4828  if (!plane_state->fb)
  4829  return -EINVAL;
  4830  }
  4831  }
  4832  return 0;
  4833  }


regards,
dan carpenter
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Re: How to enable Radeon Pro Duo with mesa

[Christian König]

Am 15.03.2018 um 08:09 schrieb Lvzhihong (ReJohn):

What are you trying to do?  A large desktop spread across both chips?
Use the chips independently?  There is no support for crossfire on Linux.  If 
you want to use a desktop across multiple chips or select which chip is used 
for rendering, you can use xrandr and the prime support in X:
https://wiki.archlinux.org/index.php/PRIME

I want to select one chip to render for my application. And now I know how to 
select which chip: after set env DRI_PRIME=1 , the second chip will be used. 
But there is another problem: the second chip's performance is very bad , only 
1/4 of the first chip.

xrandr --listproviders:
Providers: number : 2
Provider 0: id: 0x7f cap: 0x9, Source Output, Sink Offload crtcs: 6 outputs: 4 
associated providers: 1 name:AMD Radeon (TM) Pro WX 7100 Graphics @ 
pci:000d:33:00.0 Provider 1: id: 0x45 cap: 0x6, Sink Output, Source Offload 
crtcs: 6 outputs: 0 associated providers: 1 name:AMD Radeon (TM) Pro WX 7100 
Graphics @ pci:000d:34:00.0

Here is the results of running glxgears:
DRI_PRIME=1 vblank_mode=0  glxgears
ATTENTION: default value of option vblank_mode overridden by environment.
5486 frames in 5.0 seconds = 1097.200 FPS

DRI_PRIME=0 vblank_mode=0  glxgears
ATTENTION: default value of option vblank_mode overridden by environment.
19846 frames in 5.0 seconds = 3969.058 FPS

How to resolve this?


This is expected. glxgears is not a real GPU benchmark, but rather a CPU 
benchmark of how fast we can page flip when vblank is disabled.


Since doing the rendering on one GPU and presenting it on another GPU is 
more work this will result in much lower fps.


Try something real and compare the numbers.

Regards,
Christian.





On Wed, Mar 14, 2018 at 5:41 AM, Lvzhihong (ReJohn)  
wrote:
Hi All ,

Does mesa support Radeon Pro Duo? I don’t know how to configure
xorg.conf to use two WX7100 card of DUO , and now I can only use the first card 
of DUO.

What are you trying to do?  A large desktop spread across both chips?
Use the chips independently?  There is no support for crossfire on Linux.  If 
you want to use a desktop across multiple chips or select which chip is used 
for rendering, you can use xrandr and the prime support in X:
https://wiki.archlinux.org/index.php/PRIME

Alex



Installed software packages: xserver-xorg  xfce4  xinit

Mesa version: 17.2.8  kernel version: 4.15



Pci information:

000d:31:00.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port
PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)

000d:32:08.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port
PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)

000d:32:10.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port
PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)

000d:33:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Ellesmere [Radeon Pro WX 7100]

000d:33:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI]
Device
aaf0

000d:34:00.0 Display controller: Advanced Micro Devices, Inc.
[AMD/ATI] Ellesmere [Radeon Pro WX 7100]



My xorg.conf:

Section "Device"

Identifier "AMD"

Driver "amdgpu"

BusID "pci:51@13:00:00"

EndSection

Section "Monitor"

 Identifier "monitor0"

 Option "enable" "true"

EndSection

Section "Screen"

 Identifier "screen0"

 Device "AMD"

 Monitor "monitor0"

 DefaultDepth 24

 SubSection "Display"

 Depth 24

 EndSubSection

EndSection



I use “startx” to start desktop , and only the first WX7100(PCI Bus ID:
000d:33:00.0) being used , the second WX7100(PCI Bus ID: 000d:34:00.0)
has no load .

  Even if I set BusID as "pci:52@13:00:00" (the second WX7100),
it still only the first WX7100 being used.



   So , How to enable Radeon Pro Duo with opensource driver , does
my xorg.conf is wrong or mesa doesn’t support Radeon Pro Duo?






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Re: [PATCH 8/8] drm/amdgpu: program system bit for pte/pde when ZFB is enabled

[Christian König]

Am 15.03.2018 um 07:12 schrieb Feifei Xu:

Change-Id: I9e4babf1e91855fb66e65cf2f82db64a1cd6fc97
Signed-off-by: Hawking Zhang 
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 6 ++
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 2 ++
  3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 3689f1d..6b172ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -44,6 +44,8 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct 
amdgpu_device *adev)
+ adev->vm_manager.vram_base_offset;
value &= 0xF000ULL;
value |= 0x1; /*valid bit*/
+   if (adev->gmc.zfb_size > 0)
+   value |= 0x2; /*system bit*/


Please use the AMDGPU_PTE_SYSTEM constant here. Would be nice to have 
that for the valid bit as well.


Christian.

  
  	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

 lower_32_bits(value));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 94e13c8..f3b6a5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -480,6 +480,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct 
amdgpu_device *adev,
if (flags & AMDGPU_VM_PAGE_WRITEABLE)
pte_flag |= AMDGPU_PTE_WRITEABLE;
  
+	if (adev->gmc.zfb_size > 0)

+   pte_flag |= AMDGPU_PTE_SYSTEM;
+
switch (flags & AMDGPU_VM_MTYPE_MASK) {
case AMDGPU_VM_MTYPE_DEFAULT:
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
@@ -515,6 +518,9 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, 
int level,
adev->gmc.vram_start;
BUG_ON(*addr & 0x003FULL);
  
+	if (adev->gmc.zfb_size > 0)

+   *flags |= AMDGPU_PTE_SYSTEM;
+
if (!adev->gmc.translate_further)
return;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

index ef79d49..471a59b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -54,6 +54,8 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device 
*adev)
adev->vm_manager.vram_base_offset;
value &= 0xF000ULL;
value |= 0x1; /* valid bit */
+   if (adev->gmc.zfb_size > 0)
+   value |= 0x2; /* system bit*/
  
  	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

 lower_32_bits(value));


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Re: [PATCH 7/8] drm/amdgpu: program AGP aperture as frame buffer when ZFB is enabled

[Christian König]

Am 15.03.2018 um 07:12 schrieb Feifei Xu:

From: Hawking Zhang 

Change-Id: I09f9ddea0ad23af00fadd9af7aaccf7160e4e569
Signed-off-by: Hawking Zhang 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
Signed-off-by: Feifei Xu 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 19 +++
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 19 +++
  2 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 0d72f52..3689f1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -71,10 +71,21 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
  {
uint64_t value;
  
-	/* Disable AGP. */

-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0x);
+   if (adev->gmc.zfb_size > 0) {
+   /* Disable LFB */
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FF);
+
+   /* Enable AGP */
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr 
>> 24);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 
24);
+   } else {
+   /* Disable AGP. */
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0x);
+   }
  
  	/* Program the system aperture low logical page number. */

WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index bd3777a..ef79d49 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -82,10 +82,21 @@ static void mmhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
uint64_t value;
uint32_t tmp;
  
-	/* Disable AGP. */

-   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FF);
+   if (adev->gmc.zfb_size > 0) {
+   /* Disable LFB */
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 0);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FF);
+
+   /* Enable AGP */
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr 
>> 24);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 
24);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 
24);
+   } else {
+   /* Disable AGP. */
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FF);
+   }
  
  	/* Program the system aperture low logical page number. */

WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,


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Re: [PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled

[Christian König]

Am 15.03.2018 um 07:12 schrieb Feifei Xu:

Change-Id: I2b45d765f1f60252fa1c02aced94f8100d575ddc
Signed-off-by: Hawking Zhang 
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 


There is a typo in the subject, apart from that the patch is 
Reviewed-by: Christian König .


Christian.


---
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++--
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 9 +++--
  2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index acfbd2d..0d72f52 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -155,8 +155,13 @@ static void gfxhub_v1_0_init_cache_regs(struct 
amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
  
  	tmp = mmVM_L2_CNTL4_DEFAULT;

-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   if (adev->gmc.zfb_size > 0) {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+   } else {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   }
WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
  }
  
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

index 3dd5816..bd3777a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -166,8 +166,13 @@ static void mmhub_v1_0_init_cache_regs(struct 
amdgpu_device *adev)
}
  
  	tmp = mmVM_L2_CNTL4_DEFAULT;

-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   if (adev->gmc.zfb_size > 0) {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+   } else {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   }
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
  }
  


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Re: [PATCH 5/8] drm/amdgpu: user reserved zfb to init vram base offset and size

[Christian König]

Am 15.03.2018 um 07:12 schrieb Feifei Xu:

Change-Id: I866dd16548304a42298b0cb28741f27cba3a76ca
Signed-off-by: Feifei Xu 
Signed-off-by: Hawking Zhang 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 --
  1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 0f61e05..94e13c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -697,7 +697,10 @@ static void gmc_v9_0_vram_gtt_location(struct 
amdgpu_device *adev,
amdgpu_device_vram_location(adev, &adev->gmc, base);
amdgpu_device_gart_location(adev, mc);
/* base offset of vram pages */
-   adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
+   if (adev->gmc.zfb_size > 0)
+   adev->vm_manager.vram_base_offset = adev->gmc.zfb_phys_addr;
+   else
+   adev->vm_manager.vram_base_offset = 
gfxhub_v1_0_get_mc_fb_offset(adev);
  }
  
  /**

@@ -761,8 +764,11 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
}
  
  	/* size in MB on si */

-   adev->gmc.mc_vram_size =
-   adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+   if (adev->gmc.zfb_size > 0)
+   adev->gmc.mc_vram_size = adev->gmc.zfb_size;
+   else
+   adev->gmc.mc_vram_size =
+   adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
  
  	if (!(adev->flags & AMD_IS_APU)) {

@@ -770,12 +776,20 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
-   adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
-   adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+   if (adev->gmc.zfb_size > 0) {
+   adev->gmc.aper_base = adev->gmc.zfb_phys_addr;
+   adev->gmc.aper_size = adev->gmc.zfb_size;
+   } else {
+   adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
+   adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+   }
  
  #ifdef CONFIG_X86_64

if (adev->flags & AMD_IS_APU) {
-   adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
+   if (adev->gmc.zfb_size > 0)
+   adev->gmc.aper_base = adev->gmc.zfb_phys_addr;
+   else
+   adev->gmc.aper_base = 
gfxhub_v1_0_get_mc_fb_offset(adev);
adev->gmc.aper_size = adev->gmc.real_vram_size;
}
  #endif


Completely drop those changes and instead override adev->gmc.aper_base 
and adev->gmc.aper_size after determining them when ZFB is active.


Christian.


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Re: [PATCH 4/8] drm/amdgpu: init zfb start address and size

[Christian König]

Am 15.03.2018 um 07:12 schrieb Feifei Xu:

Use module parameter passed from user to initialize zfb start address
and size.

Change-Id: I3d786e863114a217f89ff7c3d4ffdabf000f31a4
Signed-off-by: Feifei Xu 
Signed-off-by: Hawking Zhang 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
  1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2188763..b88cb4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -859,6 +859,16 @@ static void amdgpu_device_check_arguments(struct 
amdgpu_device *adev)
amdgpu_lockup_timeout = 1;
}
  
+	if (amdgpu_zfb[0] > 0) {

+   dev_warn(adev->dev,
+"Zero Frame Buffer is enabled.\n");
+   adev->gmc.zfb_phys_addr = amdgpu_zfb[1] << 20;
+   adev->gmc.zfb_size = amdgpu_zfb[0] << 20;


As discussed please use dma_alloc_coherent() to allocate from CMA here 
instead of specifying the DMA address manually.


Christian.


+   } else {
+   adev->gmc.zfb_phys_addr = 0;
+   adev->gmc.zfb_size = 0;
+   }
+
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, 
amdgpu_fw_load_type);
  }
  


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Re: [PATCH 3/8] drm/amdgpu: add amdgpu module parameter for zfb

[Christian König]

Am 15.03.2018 um 07:11 schrieb Feifei Xu:

Users can pass in an array to decide enable/disable Zero Frame Buffer.
zfb[0] = zfb_size(MB), zfb[1] = zfb_phys_addr(MB).
If zbf_size > 0, zfb is enabled. Otherwise disabled.
Usage for example:
 modprobe amdgpu zfb=256,8192

Change-Id: I711062eb86b6cdff74572cabb3df250c6708e473
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
  2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2e6d986..949b451 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
  extern int amdgpu_compute_multipipe;
  extern int amdgpu_gpu_recovery;
  extern int amdgpu_emu_mode;
+extern ulong amdgpu_zfb[];
  
  #ifdef CONFIG_DRM_AMDGPU_SI

  extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e670936..53ba4ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
  int amdgpu_compute_multipipe = -1;
  int amdgpu_gpu_recovery = -1; /* auto */
  int amdgpu_emu_mode = 0;
+ulong amdgpu_zfb[2] = {0,4096UL}; /* {0,0x1} */
  
  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");

  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -290,6 +291,10 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 
0444);
  MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
  module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
  
+MODULE_PARM_DESC(zfb,

+"Enable Zero Frame Buffer feature (zfb will be set like 
,(zfb_size MB,zfb_phys_addr MB),default disabled)");
+module_param_array_named(zfb, amdgpu_zfb, ulong, NULL, 0444);
+


As discussed please drop the array and just specify the size.

Christian.


  #ifdef CONFIG_DRM_AMDGPU_SI
  
  #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)


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Re: [PATCH 2/8] drm/amdgpu: add new member in amdgpu_mc for zfb support

[Christian König]

Am 15.03.2018 um 07:11 schrieb Feifei Xu:

Change-Id: I8253c8ff80e0cbd1f12e5ee801600e7619e6718f
Signed-off-by: Hawking Zhang 
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 893c249..8f35f7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -107,6 +107,9 @@ struct amdgpu_gmc {
booltranslate_further;
  
  	const struct amdgpu_gmc_funcs	*gmc_funcs;

+/* zero frame buffer */
+u64 zfb_phys_addr;
+u64 zfb_size;


Please use tabs instead of spaces for indentation.

Christian.


  };
  
  #endif


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Re: [PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages

[Christian König]

Am 15.03.2018 um 07:11 schrieb Feifei Xu:

In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded
to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return
zfb_phys_addr if ZFB is enabled.

Change-Id: I585b7d4d96ebab2a5d7178fe8d1d6a746ef0c72a
Signed-off-by: Feifei Xu 
Signed-off-by: Hawking Zhang 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +
  1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a70cbc4..0f61e05 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -697,10 +697,7 @@ static void gmc_v9_0_vram_gtt_location(struct 
amdgpu_device *adev,
amdgpu_device_vram_location(adev, &adev->gmc, base);
amdgpu_device_gart_location(adev, mc);
/* base offset of vram pages */
-   if (adev->flags & AMD_IS_APU)
-   adev->vm_manager.vram_base_offset = 
gfxhub_v1_0_get_mc_fb_offset(adev);
-   else
-   adev->vm_manager.vram_base_offset = 0;
+   adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
  }
  
  /**


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Re: Ryzen 5 2400G Stuttering since 2018-03-07

[Dawson Dias]

I managed to pinpoint the issue. The stuttering is caused by enabling
TearFree via xrandr. When on `auto`, there is no stuttering, but when
enabled by setting it to `on`, there is intense stuttering noticeable when
dragging windows around, but it's also very noticeable when just moving the
mouse around on the desktop with no windows open.
I use Openbox with Compton for compositing.

-Dawson Dias

On Sat, Mar 10, 2018 at 11:32 AM, Dawson Dias <
thexerothermicscleroderm...@gmail.com> wrote:

> Got it. Attachments next time.
>
> I started a git bisect but noticed there were updates pushed to the tree,
> so I built HEAD instead (d1eeebbd78fd185988c3c90e3dab304cc8b86c4e). The
> stuttering is now gone!
>
> -Dawson Dias
>
> On Fri, Mar 9, 2018 at 7:36 PM, Michel Dänzer  wrote:
>
>> On 2018-03-09 12:30 PM, Dawson Dias wrote:
>> > Hello
>> >
>> > I'm experiencing extreme stuttering in X on my Ryzen 2400G. This
>> > stuttering can be noticed even while only moving the mouse.
>> > Said stuttering does not exist under Wayland.
>> >
>> > This constant stuttering started on 2018-03-07 with the patches that
>> > were pushed on that day. Stuttering occurs on both branches
>> > drm-next-4.17 (f6c3b601bd490eda08c27b03607448abd4b4841b) and
>> > drm-next-4.17-wip (6896a66bc6d0fcb69b6be564fa43f02c09348b72).
>> >
>> > dmesg.log 
>> > journalctl.log 
>>
>> In the future, please attach files directly instead of referencing a
>> paste site.
>>
>>
>> > What sort of information do we require to pinpoint the source of this
>> > regression and fix it?
>>
>> Ideal would be if you can use git bisect to isolate the individual
>> commit which introduced the stuttering.
>>
>>
>> --
>> Earthling Michel Dänzer   |   http://www.amd.com
>> Libre software enthusiast | Mesa and X developer
>>
>
>
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re: How to enable Radeon Pro Duo with mesa

[Lvzhihong (ReJohn)]

> What are you trying to do?  A large desktop spread across both chips?
> Use the chips independently?  There is no support for crossfire on Linux.  If 
> you want to use a desktop across multiple chips or select which chip is used 
> for rendering, you can use xrandr and the prime support in X:
> https://wiki.archlinux.org/index.php/PRIME

I want to select one chip to render for my application. And now I know how to 
select which chip: after set env DRI_PRIME=1 , the second chip will be used. 
But there is another problem: the second chip's performance is very bad , only 
1/4 of the first chip. 

xrandr --listproviders:
Providers: number : 2
Provider 0: id: 0x7f cap: 0x9, Source Output, Sink Offload crtcs: 6 outputs: 4 
associated providers: 1 name:AMD Radeon (TM) Pro WX 7100 Graphics @ 
pci:000d:33:00.0 Provider 1: id: 0x45 cap: 0x6, Sink Output, Source Offload 
crtcs: 6 outputs: 0 associated providers: 1 name:AMD Radeon (TM) Pro WX 7100 
Graphics @ pci:000d:34:00.0

Here is the results of running glxgears: 
DRI_PRIME=1 vblank_mode=0  glxgears
ATTENTION: default value of option vblank_mode overridden by environment.
5486 frames in 5.0 seconds = 1097.200 FPS

DRI_PRIME=0 vblank_mode=0  glxgears
ATTENTION: default value of option vblank_mode overridden by environment.
19846 frames in 5.0 seconds = 3969.058 FPS

How to resolve this?


> On Wed, Mar 14, 2018 at 5:41 AM, Lvzhihong (ReJohn)  
> wrote:
> Hi All ,
>
> Does mesa support Radeon Pro Duo? I don’t know how to configure 
> xorg.conf to use two WX7100 card of DUO , and now I can only use the first 
> card of DUO.
>
> What are you trying to do?  A large desktop spread across both chips?
> Use the chips independently?  There is no support for crossfire on Linux.  If 
> you want to use a desktop across multiple chips or select which chip is used 
> for rendering, you can use xrandr and the prime support in X:
> https://wiki.archlinux.org/index.php/PRIME
>
> Alex


>
> Installed software packages: xserver-xorg  xfce4  xinit
>
> Mesa version: 17.2.8  kernel version: 4.15
>
>
>
> Pci information:
>
> 000d:31:00.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port 
> PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)
>
> 000d:32:08.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port 
> PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)
>
> 000d:32:10.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port 
> PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)
>
> 000d:33:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
> [AMD/ATI] Ellesmere [Radeon Pro WX 7100]
>
> 000d:33:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] 
> Device
> aaf0
>
> 000d:34:00.0 Display controller: Advanced Micro Devices, Inc. 
> [AMD/ATI] Ellesmere [Radeon Pro WX 7100]
>
>
>
> My xorg.conf:
>
> Section "Device"
>
>Identifier "AMD"
>
>Driver "amdgpu"
>
>BusID "pci:51@13:00:00"
>
> EndSection
>
> Section "Monitor"
>
> Identifier "monitor0"
>
> Option "enable" "true"
>
> EndSection
>
> Section "Screen"
>
> Identifier "screen0"
>
> Device "AMD"
>
> Monitor "monitor0"
>
> DefaultDepth 24
>
> SubSection "Display"
>
> Depth 24
>
> EndSubSection
>
> EndSection
>
>
>
> I use “startx” to start desktop , and only the first WX7100(PCI Bus ID:
> 000d:33:00.0) being used , the second WX7100(PCI Bus ID: 000d:34:00.0) 
> has no load .
>
>  Even if I set BusID as "pci:52@13:00:00" (the second WX7100), 
> it still only the first WX7100 being used.
>
>
>
>   So , How to enable Radeon Pro Duo with opensource driver , does 
> my xorg.conf is wrong or mesa doesn’t support Radeon Pro Duo?
>
>
>
>
>
>
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[PATCH] drm/amd/pp: Remove the cgs wrapper for notify smu version on APU

[Rex Zhu]

Refine the commit f49e9bac191b066060a53d994f9c964fb71454f2
drm/amd/pp: Get and save Rv smu version

Change-Id: Iea668cc2161e5fcf339b408eb7eca1b028e26df2
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 -
 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 6 ++
 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c  | 6 +++---
 3 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index f2dd98d..37098c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -654,11 +654,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device 
*cgs_device,
else
strcpy(fw_name, 
"amdgpu/vega10_smc.bin");
break;
-   case CHIP_CARRIZO:
-   case CHIP_STONEY:
-   case CHIP_RAVEN:
-   adev->pm.fw_version = info->version;
-   return 0;
default:
DRM_ERROR("SMC firmware not supported\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index 6ee9822..bed229e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -247,13 +247,11 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
 
 static int smu10_start_smu(struct pp_hwmgr *hwmgr)
 {
-   struct cgs_firmware_info info = {0};
+   struct amdgpu_device *adev = hwmgr->adev;
 
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
-   info.version = hwmgr->smu_version >> 8;
-
-   cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+   adev->pm.fw_version = hwmgr->smu_version >> 8;
 
if (smu10_verify_smc_interface(hwmgr))
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
index 480deb2..8c49704 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
@@ -698,7 +698,8 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
 {
int ret = 0;
uint32_t fw_to_check = 0;
-   struct cgs_firmware_info info = {0};
+   struct amdgpu_device *adev = hwmgr->adev;
+
uint32_t index = SMN_MP1_SRAM_START_ADDR +
 SMU8_FIRMWARE_HEADER_LOCATION +
 offsetof(struct SMU8_Firmware_Header, Version);
@@ -709,8 +710,7 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
 
cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
hwmgr->smu_version = cgs_read_register(hwmgr->device, 
mmMP0PUB_IND_DATA);
-   info.version = hwmgr->smu_version >> 8;
-   cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+   adev->pm.fw_version = hwmgr->smu_version >> 8;
 
fw_to_check = UCODE_ID_RLC_G_MASK |
UCODE_ID_SDMA0_MASK |
-- 
1.9.1

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