[PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Junwei Zhang]

[  632.679861] BUG: unable to handle kernel NULL pointer dereference at (null)
[  632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]

[  632.680011] Call Trace:
[  632.680082]  amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[  632.680092]  ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[  632.680098]  amdttm_tt_bind+0x52/0x60 [amdttm]
[  632.680106]  ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[  632.680112]  ? find_next_bit+0xb/0x10
[  632.680119]  amdttm_bo_validate+0x11d/0x130 [amdttm]
[  632.680176]  amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[  632.680232]  amdgpu_cs_validate+0x41/0x270 [amdgpu]
[  632.680288]  amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[  632.680343]  amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[  632.680401]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680416]  drm_ioctl_kernel+0x6b/0xb0 [drm]
[  632.680431]  drm_ioctl+0x3e4/0x450 [drm]
[  632.680485]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680537]  amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[  632.680542]  do_vfs_ioctl+0xa4/0x600
[  632.680546]  ? SyS_futex+0x7f/0x180
[  632.680549]  SyS_ioctl+0x79/0x90
[  632.680554]  entry_SYSCALL_64_fastpath+0x24/0xab

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct 
ttm_buffer_object *bo,
gtt->ttm.ttm.func = _backend_func;
 
/* allocate space for the uninitialized page entries */
-   if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+   if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
kfree(gtt);
return NULL;
}
-- 
1.9.1

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drm/amdgpu: Add helper function to get buffer domain

[Deepak Sharma]

Move logic of getting supported domain to a helper
function

Signed-off-by: Deepak Sharma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 10 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 16 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  2 +-
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 63758db5e2ea..1e9cfbfa9c2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -750,19 +750,15 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct amdgpu_device *adev = dev->dev_private;
struct drm_gem_object *gobj;
uint32_t handle;
-   u32 domain = amdgpu_display_supported_domains(adev);
+   u32 domain;
int r;
 
args->pitch = amdgpu_align_pitch(adev, args->width,
 DIV_ROUND_UP(args->bpp, 8), 0);
args->size = (u64)args->pitch * args->height;
args->size = ALIGN(args->size, PAGE_SIZE);
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
-
+   domain = amdgpu_bo_get_domain(adev,
+ amdgpu_display_supported_domains(adev));
r = amdgpu_gem_object_create(adev, args->size, 0, domain,
 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 false, NULL, );
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6a9e46ae7f0a..8acffd9990d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -703,11 +703,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
/* This assumes only APU display buffers are pinned with (VRAM|GTT).
 * See function amdgpu_display_supported_domains()
 */
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
+   domain = amdgpu_bo_get_domain(adev, domain);
 
if (bo->pin_count) {
uint32_t mem_type = bo->tbo.mem.mem_type;
@@ -1066,3 +1062,13 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 
return bo->tbo.offset;
 }
+
+uint32_t amdgpu_bo_get_domain(struct amdgpu_device *adev, uint32_t domain)
+{
+   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
+   domain = AMDGPU_GEM_DOMAIN_VRAM;
+   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
+   domain = AMDGPU_GEM_DOMAIN_GTT;
+   }
+   return domain;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 540e03fa159f..89e05e1f0029 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -289,7 +289,7 @@ int amdgpu_bo_restore_from_shadow(struct amdgpu_device 
*adev,
  struct reservation_object *resv,
  struct dma_fence **fence,
  bool direct);
-
+uint32_t amdgpu_bo_get_domain(struct amdgpu_device *adev, uint32_t domain);
 
 /*
  * sub allocation
-- 
2.15.1

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Re: [PATCH 2/2] drm/amdgpu: add kernel doc for memory domains.

[Alex Deucher]

On Thu, May 24, 2018 at 4:35 PM, Samuel Li  wrote:

Please add a patch description.  E.g.,
Document the GEM domains exposed to userspace.

A few comments below.

> Signed-off-by: Samuel Li 
> ---
>  include/uapi/drm/amdgpu_drm.h | 19 +++
>  1 file changed, 19 insertions(+)
>
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 5b007fa..a2ae752 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -75,6 +75,25 @@ extern "C" {
>  #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + 
> DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
>  #define DRM_IOCTL_AMDGPU_FREESYNC  DRM_IOWR(DRM_COMMAND_BASE + 
> DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
>
> +/**
> + * memory domains

This should be:
 * DOC: Memory Domains

> + *
> + * %AMDGPU_GEM_DOMAIN_CPU  System memory

System memory that is not GPU accessible.  Memory in this pool could
be swapped out to disk if there is pressure.

> + *
> + * %AMDGPU_GEM_DOMAIN_GTT  Gart memory linearizes non-contiguous pages of
> + * system memory, allows GPU access system memory in a linezrized fashion

GPU accessible system memory.  System memory mapped into the GPU's
virtual address space.

> + *
> + * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
> + * carved out by BIOS

For APUs, it is system memory carved out by the BIOS.

> + *
> + * %AMDGPU_GEM_DOMAIN_GDS  Global on-chip data storage used to share data
> + *

Global on-chip shader storage used to share data across shader threads.

> + * %AMDGPU_GEM_DOMAIN_GWS  Global wave sync, used to synchronize the
> + * execution of all the waves on a device
> + *
> + * %AMDGPU_GEM_DOMAIN_OA   Ordered append, used by 3D or Compute engines
> + * for appending data
> + */
>  #define AMDGPU_GEM_DOMAIN_CPU  0x1
>  #define AMDGPU_GEM_DOMAIN_GTT  0x2
>  #define AMDGPU_GEM_DOMAIN_VRAM 0x4
> --
> 2.7.4
>
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[PATCH] drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC

[Tom Stellard]

This is an important message, so it should be visible to users without
having to enable extra debugging.

Signed-off-by: Tom Stellard 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 4d36203ffb11..c18a332e790b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -93,7 +93,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
break;
default:
-   dev_dbg(adev->dev, "kfd not supported on this ASIC\n");
+   dev_info(adev->dev, "kfd not supported on this ASIC\n");
return;
}
 
-- 
2.17.0

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Re: [PATCH 1/2] drm/amdgpu: add kernel doc for amdgpu_object.c

[Alex Deucher]

On Thu, May 24, 2018 at 4:35 PM, Samuel Li  wrote:

Please add a patch description.  Something like:

Document the amdgpu buffer object API.

A few additional comments inline below.

> v2: Add a DOC section and some more clarification.
> Signed-off-by: Samuel Li 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 266 
> +
>  1 file changed, 266 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 6a9e46a..c3a7b11 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -38,6 +38,18 @@
>  #include "amdgpu_trace.h"
>  #include "amdgpu_amdkfd.h"
>
> +/**
> + * DOC: amdgpu_object
> + *
> + * This defines the interfaces to operate on an _bo buffer object. The

An amdgpu_bo represents GPU accessible memory (VRAM, system memory, etc.).

> + * driver provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these
> + * interfaces to create/destroy/set buffer object which are then managed by
> + * the kernel TTM memory manager.
> + * The interfaces are also used internally by kernel clients, including gfx,
> + * uvd, etc.

for kernel managed allocations used by the GPU.

> + *
> + */
> +
>  static bool amdgpu_need_backup(struct amdgpu_device *adev)
>  {
> if (adev->flags & AMD_IS_APU)
> @@ -73,6 +85,15 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object 
> *tbo)
> kfree(bo);
>  }
>
> +/**
> + * amdgpu_ttm_bo_is_amdgpu_bo - check if the buffer object is an _bo
> + * @bo: buffer object to be checked
> + *
> + * Uses destroy function associated with the object to determine if this is
> + * an _bo.
> + *
> + * Returns true if the object belongs to _bo, false if not.
> + */
>  bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
>  {
> if (bo->destroy == _ttm_bo_destroy)
> @@ -80,6 +101,14 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object 
> *bo)
> return false;
>  }
>
> +/**
> + * amdgpu_ttm_placement_from_domain - set buffer's placement
> + * @abo: _bo buffer object whose placement is to be set
> + * @domain: requested domain
> + *
> + * Sets buffer's placement according to requested domain and the buffer's
> + * flags.
> + */
>  void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
>  {
> struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
> @@ -498,6 +527,19 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device 
> *adev,
> return r;
>  }
>
> +/**
> + * amdgpu_bo_create - create an _bo buffer object
> + * @adev: amdgpu device object
> + * @bp: parameters to be used for the buffer object
> + * @bo_ptr: pointer to the buffer object pointer
> + *
> + * Creates an _bo buffer object; and if requested, also creates a
> + * shadow object.
> + * Shadow object is used to backup the original buffer object, and is always
> + * in GTT.
> + *
> + * Returns 0 for success or a negative error code on failure.
> + */
>  int amdgpu_bo_create(struct amdgpu_device *adev,
>  struct amdgpu_bo_param *bp,
>  struct amdgpu_bo **bo_ptr)
> @@ -527,6 +569,20 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
> return r;
>  }
>
> +/**
> + * amdgpu_bo_backup_to_shadow - Backs up an _bo buffer object
> + * @adev: amdgpu device object
> + * @ring: amdgpu_ring for the engine handling the buffer operations
> + * @bo: _bo buffer to be backed up
> + * @resv: reservation object with embedded fence
> + * @fence: dma_fence associated with the operation
> + * @direct: whether to submit the job directly
> + *
> + * Copies an _bo buffer object to its shadow object.
> + * Not used for now.
> + *
> + * Returns 0 for success or a negative error code on failure.
> + */
>  int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
>struct amdgpu_ring *ring,
>struct amdgpu_bo *bo,
> @@ -559,6 +615,17 @@ int amdgpu_bo_backup_to_shadow(struct amdgpu_device 
> *adev,
> return r;
>  }
>
> +/**
> + * amdgpu_bo_validate - validate an _bo buffer object
> + * @bo: pointer to the buffer object
> + *
> + * Sets placement according to domain; and changes placement and caching
> + * policy of the buffer object according to the placement.
> + * This is used for validating shadow bos.  It calls ttm_bo_validate() to
> + * make sure the buffer is resident where it needs to be.
> + *
> + * Returns 0 for success or a negative error code on failure.
> + */
>  int amdgpu_bo_validate(struct amdgpu_bo *bo)
>  {
> struct ttm_operation_ctx ctx = { false, false };
> @@ -581,6 +648,21 @@ int amdgpu_bo_validate(struct amdgpu_bo *bo)
> return r;
>  }
>
> +/**
> + * amdgpu_bo_restore_from_shadow - restore an _bo buffer object
> + * @adev: amdgpu device object
> + * @ring: amdgpu_ring for the engine handling the buffer operations
> + * @bo: _bo buffer 

[PATCH] gpu: Consistently use octal not symbolic permissions

[Joe Perches]

There is currently a mixture of octal and symbolic permissions uses
in files in drivers/gpu/drm and one file in drivers/gpu.

There are ~270 existing octal uses and ~115 S_ uses.

Convert all the S_ symbolic permissions to their octal equivalents
as using octal and not symbolic permissions is preferred by many as more
readable.

see: https://lkml.org/lkml/2016/8/2/1945

Done with automated conversion via:
$ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 

Miscellanea:

o Wrapped modified multi-line calls to a single line where appropriate
o Realign modified multi-line calls to open parenthesis
o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
  debug permission for "reset" - perhaps that should be modified

Signed-off-by: Joe Perches 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
 drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
 drivers/gpu/drm/drm_debugfs.c  |  6 +-
 drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
 drivers/gpu/drm/drm_sysfs.c|  2 +-
 drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
 drivers/gpu/drm/i915/i915_perf.c   |  2 +-
 drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
 drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c  |  5 +-
 drivers/gpu/drm/msm/msm_perf.c |  4 +-
 drivers/gpu/drm/msm/msm_rd.c   |  4 +-
 drivers/gpu/drm/nouveau/nouveau_debugfs.c  |  2 +-
 drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c| 11 ++-
 .../drm/omapdrm/displays/panel-sony-acx565akm.c|  6 +-
 .../drm/omapdrm/displays/panel-tpo-td043mtea1.c| 10 +--
 drivers/gpu/drm/radeon/radeon_pm.c | 26 +++---
 drivers/gpu/drm/radeon/radeon_ttm.c|  4 +-
 drivers/gpu/drm/sti/sti_drv.c  |  2 +-
 drivers/gpu/drm/tinydrm/mipi-dbi.c |  4 +-
 drivers/gpu/drm/ttm/ttm_bo.c   |  2 +-
 drivers/gpu/drm/ttm/ttm_memory.c   | 12 +--
 drivers/gpu/drm/ttm/ttm_page_alloc.c   |  6 +-
 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c   |  6 +-
 drivers/gpu/drm/udl/udl_fb.c   |  4 +-
 drivers/gpu/host1x/debug.c | 12 +--
 30 files changed, 138 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index f5fb93795a69..7b29febff511 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -830,7 +830,7 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
 
for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
ent = debugfs_create_file(debugfs_regs_names[i],
- S_IFREG | S_IRUGO, root,
+ S_IFREG | 0444, root,
  adev, debugfs_regs[i]);
if (IS_ERR(ent)) {
for (j = 0; j < i; j++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b455da487782..fa55d7e9e784 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -905,39 +905,39 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
return -EINVAL;
 }
 
-static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
-static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
+static DEVICE_ATTR(power_dpm_state, 0644, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
+static DEVICE_ATTR(power_dpm_force_performance_level, 0644,
   amdgpu_get_dpm_forced_performance_level,
   amdgpu_set_dpm_forced_performance_level);
-static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
-static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
-static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_force_state,
-   amdgpu_set_pp_force_state);
-static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_table,
-   amdgpu_set_pp_table);
-static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_sclk,
-   amdgpu_set_pp_dpm_sclk);
-static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_mclk,
-   amdgpu_set_pp_dpm_mclk);
-static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_pcie,
-   

[PATCH 2/2] drm/amdgpu: add kernel doc for memory domains.

[Samuel Li]

Signed-off-by: Samuel Li 
---
 include/uapi/drm/amdgpu_drm.h | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 5b007fa..a2ae752 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -75,6 +75,25 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + 
DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
 #define DRM_IOCTL_AMDGPU_FREESYNC  DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
 
+/**
+ * memory domains
+ *
+ * %AMDGPU_GEM_DOMAIN_CPU  System memory
+ *
+ * %AMDGPU_GEM_DOMAIN_GTT  Gart memory linearizes non-contiguous pages of
+ * system memory, allows GPU access system memory in a linezrized fashion
+ *
+ * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
+ * carved out by BIOS
+ *
+ * %AMDGPU_GEM_DOMAIN_GDS  Global on-chip data storage used to share data
+ *
+ * %AMDGPU_GEM_DOMAIN_GWS  Global wave sync, used to synchronize the
+ * execution of all the waves on a device
+ *
+ * %AMDGPU_GEM_DOMAIN_OA   Ordered append, used by 3D or Compute engines
+ * for appending data
+ */
 #define AMDGPU_GEM_DOMAIN_CPU  0x1
 #define AMDGPU_GEM_DOMAIN_GTT  0x2
 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
-- 
2.7.4

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[PATCH 1/2] drm/amdgpu: add kernel doc for amdgpu_object.c

[Samuel Li]

v2: Add a DOC section and some more clarification.
Signed-off-by: Samuel Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 266 +
 1 file changed, 266 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6a9e46a..c3a7b11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -38,6 +38,18 @@
 #include "amdgpu_trace.h"
 #include "amdgpu_amdkfd.h"
 
+/**
+ * DOC: amdgpu_object
+ *
+ * This defines the interfaces to operate on an _bo buffer object. The
+ * driver provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these
+ * interfaces to create/destroy/set buffer object which are then managed by
+ * the kernel TTM memory manager.
+ * The interfaces are also used internally by kernel clients, including gfx,
+ * uvd, etc.
+ *
+ */
+
 static bool amdgpu_need_backup(struct amdgpu_device *adev)
 {
if (adev->flags & AMD_IS_APU)
@@ -73,6 +85,15 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object 
*tbo)
kfree(bo);
 }
 
+/**
+ * amdgpu_ttm_bo_is_amdgpu_bo - check if the buffer object is an _bo
+ * @bo: buffer object to be checked
+ *
+ * Uses destroy function associated with the object to determine if this is
+ * an _bo.
+ *
+ * Returns true if the object belongs to _bo, false if not.
+ */
 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 {
if (bo->destroy == _ttm_bo_destroy)
@@ -80,6 +101,14 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object 
*bo)
return false;
 }
 
+/**
+ * amdgpu_ttm_placement_from_domain - set buffer's placement
+ * @abo: _bo buffer object whose placement is to be set
+ * @domain: requested domain
+ *
+ * Sets buffer's placement according to requested domain and the buffer's
+ * flags.
+ */
 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
@@ -498,6 +527,19 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device 
*adev,
return r;
 }
 
+/**
+ * amdgpu_bo_create - create an _bo buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @bo_ptr: pointer to the buffer object pointer
+ *
+ * Creates an _bo buffer object; and if requested, also creates a
+ * shadow object.
+ * Shadow object is used to backup the original buffer object, and is always
+ * in GTT.
+ *
+ * Returns 0 for success or a negative error code on failure.
+ */
 int amdgpu_bo_create(struct amdgpu_device *adev,
 struct amdgpu_bo_param *bp,
 struct amdgpu_bo **bo_ptr)
@@ -527,6 +569,20 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
return r;
 }
 
+/**
+ * amdgpu_bo_backup_to_shadow - Backs up an _bo buffer object
+ * @adev: amdgpu device object
+ * @ring: amdgpu_ring for the engine handling the buffer operations
+ * @bo: _bo buffer to be backed up
+ * @resv: reservation object with embedded fence
+ * @fence: dma_fence associated with the operation
+ * @direct: whether to submit the job directly
+ *
+ * Copies an _bo buffer object to its shadow object.
+ * Not used for now.
+ *
+ * Returns 0 for success or a negative error code on failure.
+ */
 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
   struct amdgpu_ring *ring,
   struct amdgpu_bo *bo,
@@ -559,6 +615,17 @@ int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
return r;
 }
 
+/**
+ * amdgpu_bo_validate - validate an _bo buffer object
+ * @bo: pointer to the buffer object
+ *
+ * Sets placement according to domain; and changes placement and caching
+ * policy of the buffer object according to the placement.
+ * This is used for validating shadow bos.  It calls ttm_bo_validate() to
+ * make sure the buffer is resident where it needs to be.
+ *
+ * Returns 0 for success or a negative error code on failure.
+ */
 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 {
struct ttm_operation_ctx ctx = { false, false };
@@ -581,6 +648,21 @@ int amdgpu_bo_validate(struct amdgpu_bo *bo)
return r;
 }
 
+/**
+ * amdgpu_bo_restore_from_shadow - restore an _bo buffer object
+ * @adev: amdgpu device object
+ * @ring: amdgpu_ring for the engine handling the buffer operations
+ * @bo: _bo buffer to be restored
+ * @resv: reservation object with embedded fence
+ * @fence: dma_fence associated with the operation
+ * @direct: whether to submit the job directly
+ *
+ * Copies a buffer object's shadow content back to the object.
+ * This is used for recovering a buffer from its shadow in case of a gpu
+ * reset where vram context may be lost.
+ *
+ * Returns 0 for success or a negative error code on failure.
+ */
 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
  struct amdgpu_ring *ring,
  

Re: [PATCH xf86-video-amdgpu 00/13] Enabling Color Management - Round 2

[Leo Li]

On 2018-05-18 04:10 AM, Michel Dänzer wrote:

On 2018-05-17 11:43 PM, Leo Li wrote:

On 2018-05-16 01:06 PM, Michel Dänzer wrote:

On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:


3. The three color management properties (Degamma LUT, Color
Transform Matrix
     (CTM), and Gamma LUT) are hard-coded into the DDX driver, to be
listed (as
     disabled) regardless of whether a CRTC is attached on the output,
or whether
     the kernel driver supports it.

  * If kernel driver does not support color management, the
properties will
    remain disabled. A `xrandr --set` will then error.


Is it really useful to expose these properties to clients if the kernel
doesn't support them?



I left them exposed mainly for simplicity. I can see how it would
confuse a client.

It should be simpler to hide these properties once the color property
IDs are cached somewhere (maybe on the AMDGPUInfo struct?)


drmmode_crtc_private_rec seems better.



Doesn't that mean we're caching duplicate DRM property IDs on each CRTC
object? I think we only need to cache one copy.

Looking at DRM code, the IDs identify DRM property "types", not the 
actual property data, and are created during kernel driver load. Storing 
one copy is enough, since the types are the same regardless of CRTC.


I was thinking we can fetch these id's in drmmode_pre_init because of 
that, but I'm not sure of the implications. Wouldn't that be better?


Leo




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[PATCH 13/17] drm/amdgpu: add vcn jpeg ib test

[boyuan.zhang]

From: Boyuan Zhang 

Add an ib test for vcn jpeg

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 86 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   |  2 +-
 3 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 123ad5d..ab5970b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -652,3 +652,89 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring 
*ring)
 
return r;
 }
+
+static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
+   struct dma_fence **fence)
+{
+   struct amdgpu_device *adev = ring->adev;
+   struct amdgpu_job *job;
+   struct amdgpu_ib *ib;
+   struct dma_fence *f = NULL;
+   const unsigned ib_size_dw = 16;
+   int i, r;
+
+   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   if (r)
+   return r;
+
+   ib = >ibs[0];
+
+   ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH), 0, 0, 
PACKETJ_TYPE0);
+   ib->ptr[1] = 0xDEADBEEF;
+   for (i = 2; i < 16; i += 2) {
+   ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
+   ib->ptr[i+1] = 0;
+   }
+   ib->length_dw = 16;
+
+   r = amdgpu_ib_schedule(ring, 1, ib, NULL, );
+   job->fence = dma_fence_get(f);
+   if (r)
+   goto err;
+
+   amdgpu_job_free(job);
+   if (fence)
+   *fence = dma_fence_get(f);
+   dma_fence_put(f);
+
+   return 0;
+
+err:
+   amdgpu_job_free(job);
+   return r;
+}
+
+int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+   struct amdgpu_device *adev = ring->adev;
+   uint32_t tmp = 0;
+   unsigned i;
+   struct dma_fence *fence = NULL;
+   long r = 0;
+
+   r = amdgpu_vcn_jpeg_set_reg(ring, 1, );
+   if (r) {
+   DRM_ERROR("amdgpu: failed to set jpeg register (%ld).\n", r);
+   goto error;
+   }
+
+   r = dma_fence_wait_timeout(fence, false, timeout);
+   if (r == 0) {
+   DRM_ERROR("amdgpu: IB test timed out.\n");
+   r = -ETIMEDOUT;
+   goto error;
+   } else if (r < 0) {
+   DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+   goto error;
+   } else
+   r = 0;
+
+   for (i = 0; i < adev->usec_timeout; i++) {
+   tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH));
+   if (tmp == 0xDEADBEEF)
+   break;
+   DRM_UDELAY(1);
+   }
+
+   if (i < adev->usec_timeout)
+   DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
+   else {
+   DRM_ERROR("ib test failed (0x%08X)\n", tmp);
+   r = -EINVAL;
+   }
+
+   dma_fence_put(fence);
+
+error:
+   return r;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index c746dae..294f8d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -77,5 +77,6 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
+int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 5654771..be397ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1557,7 +1557,7 @@ static const struct amdgpu_ring_funcs 
vcn_v1_0_jpeg_ring_vm_funcs = {
.emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
.emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
.test_ring = amdgpu_vcn_jpeg_ring_test_ring,
-   //.test_ib
+   .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
.insert_nop = vcn_v1_0_jpeg_ring_nop,
.insert_start = vcn_v1_0_jpeg_ring_insert_start,
.insert_end = vcn_v1_0_jpeg_ring_insert_end,
-- 
2.7.4

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[PATCH 16/17] drm/amdgpu: add AMDGPU_HW_IP_VCN_JPEG to info query

[boyuan.zhang]

From: Boyuan Zhang 

Add AMDGPU_HW_IP_VCN_JPEG to info query

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 51a4b08..dfe4399 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -359,6 +359,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
ib_size_alignment = 1;
break;
+   case AMDGPU_HW_IP_VCN_JPEG:
+   type = AMD_IP_BLOCK_TYPE_VCN;
+   ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
+   ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+   ib_size_alignment = 16;
+   break;
default:
return -EINVAL;
}
@@ -403,6 +409,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
break;
case AMDGPU_HW_IP_VCN_DEC:
case AMDGPU_HW_IP_VCN_ENC:
+   case AMDGPU_HW_IP_VCN_JPEG:
type = AMD_IP_BLOCK_TYPE_VCN;
break;
default:
-- 
2.7.4

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[PATCH 12/17] drm/amdgpu: add vcn jpeg ring test

[boyuan.zhang]

From: Boyuan Zhang 

Add a ring test for vcn jpeg

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 40 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   |  2 +-
 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 190728f..123ad5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -612,3 +612,43 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, 
long timeout)
dma_fence_put(fence);
return r;
 }
+
+int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+   uint32_t tmp = 0;
+   unsigned i;
+   int r;
+
+   WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+   r = amdgpu_ring_alloc(ring, 3);
+
+   if (r) {
+   DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+ ring->idx, r);
+   return r;
+   }
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0, 0, 0));
+   amdgpu_ring_write(ring, 0xDEADBEEF);
+   amdgpu_ring_commit(ring);
+
+   for (i = 0; i < adev->usec_timeout; i++) {
+   tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+   if (tmp == 0xDEADBEEF)
+   break;
+   DRM_UDELAY(1);
+   }
+
+   if (i < adev->usec_timeout) {
+   DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
+ ring->idx, i);
+   } else {
+   DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
+ ring->idx, tmp);
+   r = -EINVAL;
+   }
+
+   return r;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 648f662..c746dae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -76,4 +76,6 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, 
long timeout);
 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
+int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2e4bd26..5654771 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1556,7 +1556,7 @@ static const struct amdgpu_ring_funcs 
vcn_v1_0_jpeg_ring_vm_funcs = {
.emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
.emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
.emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
-   //.test_ring
+   .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
//.test_ib
.insert_nop = vcn_v1_0_jpeg_ring_nop,
.insert_start = vcn_v1_0_jpeg_ring_insert_start,
-- 
2.7.4

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[PATCH 17/17] drm/amdgpu: add AMDGPU_HW_IP_VCN_JPEG to queue mgr

[boyuan.zhang]

From: Boyuan Zhang 

Add AMDGPU_HW_IP_VCN_JPEG to queue mgr

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index 262c126..a0c7e92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -91,6 +91,9 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
case AMDGPU_HW_IP_VCN_ENC:
*out_ring = >vcn.ring_enc[ring];
break;
+   case AMDGPU_HW_IP_VCN_JPEG:
+   *out_ring = >vcn.ring_jpeg;
+   break;
default:
*out_ring = NULL;
DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip);
@@ -254,6 +257,9 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
case AMDGPU_HW_IP_VCN_ENC:
ip_num_rings = adev->vcn.num_enc_rings;
break;
+   case AMDGPU_HW_IP_VCN_JPEG:
+   ip_num_rings = 1;
+   break;
default:
DRM_DEBUG("unknown ip type: %d\n", hw_ip);
return -EINVAL;
@@ -281,6 +287,7 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
case AMDGPU_HW_IP_UVD_ENC:
case AMDGPU_HW_IP_VCN_DEC:
case AMDGPU_HW_IP_VCN_ENC:
+   case AMDGPU_HW_IP_VCN_JPEG:
r = amdgpu_identity_map(adev, mapper, ring, out_ring);
break;
case AMDGPU_HW_IP_DMA:
-- 
2.7.4

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[PATCH 08/17] drm/amdgpu: initialize vcn jpeg ring

[boyuan.zhang]

From: Boyuan Zhang 

Add implementations for vcn jpeg ring initialization

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 9a04a9a..34699f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -116,6 +116,12 @@ static int vcn_v1_0_sw_init(void *handle)
return r;
}
 
+   ring = >vcn.ring_jpeg;
+   sprintf(ring->name, "vcn_jpeg");
+   r = amdgpu_ring_init(adev, ring, 512, >vcn.irq, 0);
+   if (r)
+   return r;
+
return r;
 }
 
@@ -175,6 +181,14 @@ static int vcn_v1_0_hw_init(void *handle)
}
}
 
+   ring = >vcn.ring_jpeg;
+   ring->ready = true;
+   r = amdgpu_ring_test_ring(ring);
+   if (r) {
+   ring->ready = false;
+   goto done;
+   }
+
 done:
if (!r)
DRM_INFO("VCN decode and encode initialized successfully.\n");
@@ -655,6 +669,15 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 
+   ring = >vcn.ring_jpeg;
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+   WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x0001L | 0x0002L));
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 
lower_32_bits(ring->gpu_addr));
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 
upper_32_bits(ring->gpu_addr));
+   WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
+   WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
+   WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x0002L);
+
return 0;
 }
 
-- 
2.7.4

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[PATCH 03/17] drm/amdgpu: add jpeg packet defines to soc15d.h

[boyuan.zhang]

From: Boyuan Zhang 

Add new packet for vcn jpeg, including condition checks, types and packet

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/soc15d.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h 
b/drivers/gpu/drm/amd/amdgpu/soc15d.h
index 7f408f8..7f208e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
@@ -53,6 +53,29 @@
 
 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
 
+#definePACKETJ_CONDITION_CHECK00
+#definePACKETJ_CONDITION_CHECK11
+#definePACKETJ_CONDITION_CHECK22
+#definePACKETJ_CONDITION_CHECK33
+#definePACKETJ_CONDITION_CHECK44
+#definePACKETJ_CONDITION_CHECK55
+#definePACKETJ_CONDITION_CHECK66
+#definePACKETJ_CONDITION_CHECK77
+
+#definePACKETJ_TYPE0   0
+#definePACKETJ_TYPE1   1
+#definePACKETJ_TYPE2   2
+#definePACKETJ_TYPE3   3
+#definePACKETJ_TYPE4   4
+#definePACKETJ_TYPE5   5
+#definePACKETJ_TYPE6   6
+#definePACKETJ_TYPE7   7
+
+#define PACKETJ(reg, r, cond, type)((reg & 0x3) |  
\
+((r & 0x3F) << 18) |   \
+((cond & 0xF) << 24) | \
+((type & 0xF) << 28))
+
 /* Packet 3 types */
 #definePACKET3_NOP 0x10
 #definePACKET3_SET_BASE0x11
-- 
2.7.4

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[PATCH 09/17] drm/amdgpu: implement patch for fixing a known bug

[boyuan.zhang]

From: Boyuan Zhang 

Implement a patch to maunally reset read pointer

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 43 +++
 1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 34699f8..dcd1a9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -41,6 +41,7 @@ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device 
*adev);
 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring);
 
 /**
  * vcn_v1_0_early_init - set function pointers
@@ -1339,6 +1340,48 @@ static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring 
*ring, uint32_t count)
}
 }
 
+static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   uint32_t reg, val, mask, i;
+
+   reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
+   val = lower_32_bits(ring->gpu_addr);
+   vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+   reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
+   val = upper_32_bits(ring->gpu_addr);
+   vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+   for (i = 0; i <= 2; i++)
+   vcn_v1_0_jpeg_ring_mem_read(ring);
+
+   reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+   val = 0x13;
+   vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+   reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
+   val = 0x1;
+   vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+   reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+   val = 0x1;
+   mask = 0x1;
+   vcn_v1_0_jpeg_ring_emit_reg_wait(ring, reg, val, mask);
+
+   for (i = 0; i <= 12; i++)
+   vcn_v1_0_jpeg_ring_nop(ring, 2);
+
+   reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
+   val = 0;
+   vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+   reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+   val = 0x12;
+   vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+}
+
 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
-- 
2.7.4

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[PATCH 11/17] drm/amdgpu: add vcn jpeg sw init and fini

[boyuan.zhang]

From: Boyuan Zhang 

Add software initializationa and finish for vcn jpeg ring

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 58e4953..190728f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -120,6 +120,15 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r;
}
 
+   ring = >vcn.ring_jpeg;
+   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+   r = drm_sched_entity_init(>sched, >vcn.entity_jpeg,
+ rq, amdgpu_sched_jobs, NULL);
+   if (r != 0) {
+   DRM_ERROR("Failed setting up VCN jpeg run queue.\n");
+   return r;
+   }
+
return 0;
 }
 
@@ -133,6 +142,8 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 
drm_sched_entity_fini(>vcn.ring_enc[0].sched, 
>vcn.entity_enc);
 
+   drm_sched_entity_fini(>vcn.ring_jpeg.sched, 
>vcn.entity_jpeg);
+
amdgpu_bo_free_kernel(>vcn.vcpu_bo,
  >vcn.gpu_addr,
  (void **)>vcn.cpu_addr);
@@ -142,6 +153,8 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_enc_rings; ++i)
amdgpu_ring_fini(>vcn.ring_enc[i]);
 
+   amdgpu_ring_fini(>vcn.ring_jpeg);
+
release_firmware(adev->vcn.fw);
 
return 0;
-- 
2.7.4

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[PATCH 15/17] uapi/drm: add AMDGPU_HW_IP_VCN_JPEG for jpeg CS

[boyuan.zhang]

From: Boyuan Zhang 

Add AMDGPU_HW_IP_VCN_JPEG define for jpeg CS

Signed-off-by: Boyuan Zhang 
---
 include/uapi/drm/amdgpu_drm.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 393d183..4381dcc 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -476,7 +476,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_HW_IP_UVD_ENC  5
 #define AMDGPU_HW_IP_VCN_DEC  6
 #define AMDGPU_HW_IP_VCN_ENC  7
-#define AMDGPU_HW_IP_NUM  8
+#define AMDGPU_HW_IP_VCN_JPEG 8
+#define AMDGPU_HW_IP_NUM  9
 
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 
-- 
2.7.4

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[PATCH 14/17] drm/amdgpu: enable vcn jpeg ib test

[boyuan.zhang]

From: Boyuan Zhang 

Enable vcn jpeg ib ring test in amdgpu_ib.c

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 311589e..04164a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -349,7 +349,8 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
-   ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
+   ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
+   ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
tmo = tmo_mm;
else
tmo = tmo_gfx;
-- 
2.7.4

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[PATCH 10/17] drm/amdgpu: add patch for fixing a known bug

[boyuan.zhang]

From: Boyuan Zhang 

Allocate extra space in vcn jpeg ring buffer and store the jpeg ring patch

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index dcd1a9a..2e4bd26 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -119,7 +119,8 @@ static int vcn_v1_0_sw_init(void *handle)
 
ring = >vcn.ring_jpeg;
sprintf(ring->name, "vcn_jpeg");
-   r = amdgpu_ring_init(adev, ring, 512, >vcn.irq, 0);
+   /* allocate extra dw in ring buffer for storing patch commands */
+   r = amdgpu_ring_init(adev, ring, 512 + 64, >vcn.irq, 0);
if (r)
return r;
 
@@ -679,6 +680,30 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x0002L);
 
+   /* set wptr to the extra allocated space in ring buffer */
+   ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+   ring->wptr += ring->max_dw * amdgpu_sched_hw_submission;
+
+   /* increase mask to allow to write to the extra space */
+   ring->buf_mask += 64 * 4;
+   ring->ptr_mask += 64 * 4;
+
+   /* allocate extra space */
+   r = amdgpu_ring_alloc(ring, 64);
+   if (r) {
+   DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+ ring->idx, r);
+   return r;
+   }
+
+   /* copy patch commands to the extra space */
+   vcn_v1_0_jpeg_ring_set_patch_ring(ring);
+
+   /* reset wptr and mask */
+   ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+   ring->buf_mask -= 0x100;
+   ring->ptr_mask -= 0x100;
+
return 0;
 }
 
-- 
2.7.4

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[PATCH 07/17] drm/amdgpu: add vcn jpeg irq support

[boyuan.zhang]

From: Boyuan Zhang 

Add vcn jpeg irq support

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 0dde424..9a04a9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -89,6 +89,11 @@ static int vcn_v1_0_sw_init(void *handle)
return r;
}
 
+   /* VCN JPEG TRAP */
+   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, >vcn.irq);
+   if (r)
+   return r;
+
r = amdgpu_vcn_sw_init(adev);
if (r)
return r;
@@ -1335,6 +1340,9 @@ static int vcn_v1_0_process_interrupt(struct 
amdgpu_device *adev,
case 120:
amdgpu_fence_process(>vcn.ring_enc[1]);
break;
+   case 126:
+   amdgpu_fence_process(>vcn.ring_jpeg);
+   break;
default:
DRM_ERROR("Unhandled interrupt: %d %d\n",
  entry->src_id, entry->src_data[0]);
-- 
2.7.4

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[PATCH 06/17] drm/amdgpu: set jpeg ring functions

[boyuan.zhang]

From: Boyuan Zhang 

Set all vcn jpeg ring function pointers

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 3ddab07..0dde424 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -39,6 +39,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev);
 static int vcn_v1_0_stop(struct amdgpu_device *adev);
 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
 
 /**
@@ -56,6 +57,7 @@ static int vcn_v1_0_early_init(void *handle)
 
vcn_v1_0_set_dec_ring_funcs(adev);
vcn_v1_0_set_enc_ring_funcs(adev);
+   vcn_v1_0_set_jpeg_ring_funcs(adev);
vcn_v1_0_set_irq_funcs(adev);
 
return 0;
@@ -147,6 +149,7 @@ static int vcn_v1_0_hw_init(void *handle)
int i, r;
 
r = vcn_v1_0_start(adev);
+
if (r)
goto done;
 
@@ -1434,6 +1437,38 @@ static const struct amdgpu_ring_funcs 
vcn_v1_0_enc_ring_vm_funcs = {
.emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
 };
 
+static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
+   .type = AMDGPU_RING_TYPE_VCN_JPEG,
+   .align_mask = 0xf,
+   .nop = PACKET0(0x81ff, 0),
+   .support_64bit_ptrs = false,
+   .vmhub = AMDGPU_MMHUB,
+   .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
+   .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
+   .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
+   .emit_frame_size =
+   6 + 6 + /* hdp invalidate / flush */
+   SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+   SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+   8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
+   14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
+   6,
+   .emit_ib_size = 22, /* vcn_v1_0_dec_ring_emit_ib */
+   .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
+   .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
+   .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
+   //.test_ring
+   //.test_ib
+   .insert_nop = vcn_v1_0_jpeg_ring_nop,
+   .insert_start = vcn_v1_0_jpeg_ring_insert_start,
+   .insert_end = vcn_v1_0_jpeg_ring_insert_end,
+   .pad_ib = amdgpu_ring_generic_pad_ib,
+   .begin_use = amdgpu_vcn_ring_begin_use,
+   .end_use = amdgpu_vcn_ring_end_use,
+   .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
+   .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
+};
+
 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 {
adev->vcn.ring_dec.funcs = _v1_0_dec_ring_vm_funcs;
@@ -1450,6 +1485,12 @@ static void vcn_v1_0_set_enc_ring_funcs(struct 
amdgpu_device *adev)
DRM_INFO("VCN encode is enabled in VM mode\n");
 }
 
+static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+{
+   adev->vcn.ring_jpeg.funcs = _v1_0_jpeg_ring_vm_funcs;
+   DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+}
+
 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
.set = vcn_v1_0_set_interrupt_state,
.process = vcn_v1_0_process_interrupt,
-- 
2.7.4

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[PATCH 04/17] drm/amdgpu: add more jpeg register offset headers

[boyuan.zhang]

From: Boyuan Zhang 

Add more jpeg registers defines that are needed for jpeg ring functions

Signed-off-by: Boyuan Zhang 
---
 .../drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h| 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
index 18a3247..fe0cbaa 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
@@ -89,6 +89,8 @@
 #define mmUVD_JPEG_RB_SIZE_BASE_IDX
1
 #define mmUVD_JPEG_ADDR_CONFIG 
0x021f
 #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX
1
+#define mmUVD_JPEG_PITCH   
0x0222
+#define mmUVD_JPEG_PITCH_BASE_IDX  
1
 #define mmUVD_JPEG_GPCOM_CMD   
0x022c
 #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX  
1
 #define mmUVD_JPEG_GPCOM_DATA0 
0x022d
@@ -203,6 +205,8 @@
 #define mmUVD_RB_WPTR4_BASE_IDX
1
 #define mmUVD_JRBC_RB_RPTR 
0x0457
 #define mmUVD_JRBC_RB_RPTR_BASE_IDX
1
+#define mmUVD_LMI_JPEG_VMID
0x045d
+#define mmUVD_LMI_JPEG_VMID_BASE_IDX   
1
 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
0x045e
 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX   
1
 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 
0x045f
@@ -231,6 +235,8 @@
 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX  
1
 #define mmUVD_LMI_JRBC_IB_VMID 
0x0507
 #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX
1
+#define mmUVD_LMI_JRBC_RB_VMID 
0x0508
+#define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX
1
 #define mmUVD_JRBC_RB_WPTR 
0x0509
 #define mmUVD_JRBC_RB_WPTR_BASE_IDX
1
 #define mmUVD_JRBC_RB_CNTL 
0x050a
@@ -239,6 +245,20 @@
 #define mmUVD_JRBC_IB_SIZE_BASE_IDX
1
 #define mmUVD_JRBC_LMI_SWAP_CNTL   
0x050d
 #define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX  
1
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 
0x050e
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX
1
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
0x050f
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX   
1
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 
0x0510
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX
1
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
0x0511
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX   
1
+#define mmUVD_JRBC_RB_REF_DATA 
0x0512
+#define mmUVD_JRBC_RB_REF_DATA_BASE_IDX
1
+#define mmUVD_JRBC_RB_COND_RD_TIMER
0x0513
+#define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX   
1
+#define mmUVD_JRBC_EXTERNAL_REG_BASE   

[PATCH 02/17] drm/amdgpu: add vcn jpeg ring

[boyuan.zhang]

From: Boyuan Zhang 

Add jpeg to amdgpu_vcn

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2fd7db8..648f662 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -55,9 +55,11 @@ struct amdgpu_vcn {
const struct firmware   *fw;/* VCN firmware */
struct amdgpu_ring  ring_dec;
struct amdgpu_ring  ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+   struct amdgpu_ring  ring_jpeg;
struct amdgpu_irq_src   irq;
struct drm_sched_entity entity_dec;
struct drm_sched_entity entity_enc;
+   struct drm_sched_entity entity_jpeg;
unsignednum_enc_rings;
 };
 
-- 
2.7.4

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[PATCH 05/17] drm/amdgpu: implement jpeg ring functions

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 293 ++
 1 file changed, 293 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 8c13267..3ddab07 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1015,6 +1015,299 @@ static void vcn_v1_0_enc_ring_emit_wreg(struct 
amdgpu_ring *ring,
amdgpu_ring_write(ring, val);
 }
 
+
+/**
+ * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware read pointer
+ */
+static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
+}
+
+/**
+ * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware write pointer
+ */
+static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+}
+
+/**
+ * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the write pointer to the hardware
+ */
+static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+}
+
+/**
+ * vcn_v1_0_jpeg_ring_insert_start - insert a start command
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Write a start command to the ring.
+ */
+static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 
0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, 0x68e04);
+
+   amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, 0x8001);
+}
+
+/**
+ * vcn_v1_0_jpeg_ring_insert_end - insert a end command
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Write a end command to the ring.
+ */
+static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 
0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, 0x68e04);
+
+   amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, 0x0001);
+}
+
+/**
+ * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
+ *
+ * @ring: amdgpu_ring pointer
+ * @fence: fence to emit
+ *
+ * Write a fence and a trap command to the ring.
+ */
+static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 
u64 seq,
+unsigned flags)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, 
PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, seq);
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, 
PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, seq);
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, lower_32_bits(addr));
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, upper_32_bits(addr));
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, 
PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, 0x8);
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 
PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
+   amdgpu_ring_write(ring, 0);
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 
0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, 0x01400200);
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, 
PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, seq);
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, lower_32_bits(addr));
+
+   amdgpu_ring_write(ring,
+   PACKETJ(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+   amdgpu_ring_write(ring, 

[PATCH 2/3] Revert "drm/amdgpu: add new device to use atpx quirk"

[Alex Deucher]

This reverts commit 6c24a85d236eb2348d2e221993769fd93c168f65.

This was a workaround for a bug in the HDA driver that prevented
the HDA audio chip from going into runtime pm which prevented
the GPU from going into runtime pm.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106597
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index daa06e7c5bb7..f09cc2577956 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -568,7 +568,6 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] 
= {
/* HG _PR3 doesn't seem to work on this A+A weston board */
{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
-   { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
{ 0, 0, 0, 0, 0 },
 };
 
-- 
2.13.6

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[PATCH 1/3] Revert "drm/amdgpu: Add an ATPX quirk for hybrid laptop"

[Alex Deucher]

This reverts commit 13b40935cf64f59b93cf1c716a2033488e5a228c.

This was a workaround for a bug in the HDA driver that prevented
the HDA audio chip from going into runtime pm which prevented
the GPU from going into runtime pm.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106597
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index 1bcb2b247335..daa06e7c5bb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -569,7 +569,6 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] 
= {
{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
-   { 0x1002, 0x67DF, 0x1028, 0x0774, AMDGPU_PX_QUIRK_FORCE_ATPX },
{ 0, 0, 0, 0, 0 },
 };
 
-- 
2.13.6

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[PATCH 3/3] Partially revert: drm/amdgpu: add atpx quirk handling (v2)

[Alex Deucher]

Remove the platform specific quirks, but leave the quirk
infrastructure in place.

This was a workaround for a bug in the HDA driver that prevented
the HDA audio chip from going into runtime pm which prevented
the GPU from going into runtime pm.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106597
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index f09cc2577956..9c493e8a48a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -565,9 +565,6 @@ static const struct vga_switcheroo_handler 
amdgpu_atpx_handler = {
 };
 
 static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
-   /* HG _PR3 doesn't seem to work on this A+A weston board */
-   { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
-   { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
{ 0, 0, 0, 0, 0 },
 };
 
-- 
2.13.6

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Re: [PATCH xf86-video-amdgpu 10/13] Push staged color properties when DPMS state toggles On

[Leo Li]

On 2018-05-18 04:01 AM, Michel Dänzer wrote:

On 2018-05-17 11:44 PM, Leo Li wrote:

On 2018-05-16 01:10 PM, Michel Dänzer wrote:

On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:

From: "Leo (Sunpeng) Li" 

This will persist color management properties on a CRTC across DPMS
state changes.

Signed-off-by: Leo (Sunpeng) Li 
---
   src/drmmode_display.c | 6 ++
   1 file changed, 6 insertions(+)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 45c582c..06ae902 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1294,6 +1294,7 @@ drmmode_do_crtc_dpms(xf86CrtcPtr crtc, int mode)
   AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
   CARD64 ust;
   int ret;
+    int i;
     if (drmmode_crtc->dpms_mode == DPMSModeOn && mode !=
DPMSModeOn) {
   uint32_t seq;
@@ -1341,6 +1342,11 @@ drmmode_do_crtc_dpms(xf86CrtcPtr crtc, int mode)
   drmmode_crtc->interpolated_vblanks += delta_seq;
   }
   +    for (i = 0; i < CM_NUM_PROPS; i++) {
+    if (i == CM_GAMMA_LUT_SIZE || i == CM_DEGAMMA_LUT_SIZE)
+    continue;
+    drmmode_crtc_push_cm_prop(crtc, i);
+    }
   }
   drmmode_crtc->dpms_mode = mode;
   }



This and patch 11 smell like workarounds for a kernel issue. The kernel
should preserve the property values regardless of DPMS state.

This probably explains something I just discovered: the legacy gamma LUT
becomes ineffective after turning a CRTC off and on again with DC,
whereas it's preserved without DC.


That's indeed a kernel issue, will look into it. This patch can be
dropped once the kernel persists the properties across dpms.

In terms of Patch 11, which persists the properties across hotplugs, is
it even a valid use-case? I tested with i915 and amdgpu non-dc drivers.
Both don't seem to persist legacy gamma across hotplugs, or xrandr
--output --off/--auto.


It persists for me (without this series) with amdgpu without DC on
xrandr --output --off/--auto, or explicitly moving an output between
different CRTCs. Those are definitely expected.

Not sure about hotplug; it's possible that something explicitly
re-initializes the legacy gamma in that case. But other than that, each
CRTC should preserve its values unless they are explicitly modified.



Just patched up the kernel to fix this, and the properties indeed
persist like you've described (hotplug as well). Makes sense, since the
properties don't change on the DRM states. We just have to update DC on
these events.

Thanks for your responses, moving on to v3 now.

Leo




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Re: [PATCH libdrm 3/3] amdgpu: Destroy fd_hash table when the last device is removed.

[Jan Vesely]

On Fri, 2018-05-18 at 13:00 -0400, Jan Vesely wrote:
> Fixes memory leak on module unload.
> Analogous to mesa commit of the same name.
> Signed-off-by: Jan Vesely 
> ---
>  amdgpu/amdgpu_device.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
> index e23dd3b3..34ac95b8 100644
> --- a/amdgpu/amdgpu_device.c
> +++ b/amdgpu/amdgpu_device.c
> @@ -128,6 +128,10 @@ static void 
> amdgpu_device_free_internal(amdgpu_device_handle dev)
>  {
>   pthread_mutex_lock(_mutex);
>   util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd));
> + if (util_hash_table_count(fd_tab) == 0) {
> + util_hash_table_destroy(fd_tab);
> + fd_tab = NULL;
> + }
>   close(dev->fd);
>   if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
>   close(dev->flink_fd);

gentle ping.

Jan

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[pull] amdgpu, sched drm-next-4.18

[Alex Deucher]

Hi Dave,

Last feature request for 4.18.  Mostly vega20 support.
- Vega20 support
- clock and powergating for VCN
- misc bug fixes


The following changes since commit 315852b422972e6ebb1dfddaadada09e46a2681a:

  drm: rcar-du: Fix build failure (2018-05-17 15:03:40 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.18

for you to fetch changes up to b8f3439fa5358ac84d29fa2f4afa115500dec74c:

  drm/amd/display: Remove use of division operator for long longs (2018-05-24 
10:07:56 -0500)


Alex Deucher (16):
  drm/amdgpu/atomfirmware: add new gfx_info data table v2.4 (v2)
  drm/amdgpu/atomfirmware: add parser for gfx_info table
  drm/amdgpu: Use vbios table for gpu info on vega20
  drm/amdgpu: add df 3.6 headers
  drm/amdgpu: flag Vega20 as experimental
  drm/amdgpu/display: remove VEGAM config option
  drm/amdgpu/display: remove VEGA20 config option
  drm/amdgpu/display: fix vega12/20 handling in dal_asic_id.h
  drm/amdgpu: count fences from all uvd instances in idle handler
  drm/amdgpu: Take uvd encode rings into account in idle work (v2)
  drm/amdgpu: Take vcn encode rings into account in idle work
  drm/amdgpu: add new DF 1.7 register defs
  drm/amdgpu: add new DF callback for ECC setup
  drm/amdgpu: add a df 1.7 implementation of enable_ecc_force_par_wr_rmw
  drm/amdgpu/gmc9: disable partial wr rmw if ECC is not enabled
  drm/amdgpu/pp: remove duplicate assignment

Andrey Grodzovsky (3):
  drm/amdgpu: Skip drm_sched_entity related ops for KIQ ring.
  drm/scheduler: Remove obsolete spinlock.
  Remove calls to suspend/resume atomic helpers from 
amdgpu_device_gpu_recover. (v2)

Anthony Koo (7):
  drm/amd/display: Cleanup unused SetPlaneConfig
  drm/amd/display: Make DisplayStats work with just DC DisplayStats minor
  drm/amd/display: Fix up dm logging functionality
  drm/amd/display: use macro for logs
  drm/amd/display: Add fullscreen transitions to log
  drm/amd/display: fix bug with index check
  drm/amd/display: fix memory leaks

Charlene Liu (1):
  drm/amd/display: underflow/blankscreen recovery

Christian König (7):
  drm/amdgpu: remove unused member
  drm/amdgpu: rework VM state machine lock handling v2
  drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2
  drm/amdgpu: further optimize amdgpu_vm_handle_moved
  drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories
  drm/amdgpu: consistenly use VM moved flag
  drm/amdgpu: move VM BOs on LRU again

Dan Carpenter (1):
  drm/amd/pp: missing curly braces in smu7_enable_sclk_mclk_dpm()

David Francis (1):
  drm/amd/display: Remove use of division operator for long longs

Dmytro Laktyushkin (7):
  drm/amd/display: get rid of 32.32 unsigned fixed point
  drm/amd/display: inline more of fixed point code
  drm/amd/display: add fixed point fractional bit truncation function
  drm/amd/display: truncate scaling ratios and inits to 19 bit precision
  drm/amd/display: fix 31_32_fixpt shift functions
  drm/amd/display: fix a 32 bit shift meant to be 64 warning
  drm/amd/display: update dml to allow sync with DV

Emily Deng (1):
  drm/sched: add rcu_barrier after entity fini

Eric Bernstein (2):
  drm/amd/display: Update HW sequencer initialization
  drm/amd/display: DCN1 link encoder

Evan Quan (3):
  drm/amd/powerplay: new framework to honour DAL clock limits
  drm/amd/powerplay: add a framework for perfroming pre display 
configuration change settings
  drm/amd/powerplay: update vega20 cg flags (v2)

Feifei Xu (37):
  drm/amdgpu/gfx9: Update golden setting for gfx9_0.
  drm/amdgpu: Drop the unused header files in soc15.c.
  drm/amdgpu: Fix hardcoded base offset of vram pages
  drm/amd: Add vega20_ip_offset.h headerfile for vega20. (v2)
  drm/amdgpu: Add vega20 to asic_type enum.
  drm/amdgpu: Add gpu_info firmware for vega20. (v2)
  drm/amdgpu: set asic family for vega20.
  drm/amdgpu: Add smu firmware support for vega20
  drm/amdgpu/powerplay: Add initial vega20 support v2
  drm/amdgpu/psp: Add initial psp support for vega20
  drm/amdgpu: Add vega20 ucode loading method
  drm/amdgpu: Specify vega20 uvd firmware
  drm/amdgpu: Specify vega20 vce firmware
  drm/amdgpu/virtual_dce: Add vega20 support
  drm/amdgpu/gmc9: Add vega20 support
  drm/amdgpu/mmhub: Add clockgating support for vega20
  drm/amdgpu/sdma4: Specify vega20 firmware
  drm/amdgpu/sdma4: Add vega20 golden settings (v3)
  drm/amdgpu/sdma4: Add clockgating support for vega20
  drm/amdgpu/gfx9: Add support for vega20 firmware
  drm/amdgpu/gfx9: Add vega20 golden settings (v3)
  drm/amdgpu/gfx9: Add gfx config for vega20. (v4)
  drm/amdgpu/gfx9: Add support for vega20
  drm/amdgpu/gfx9: Add 

[PATCH v2] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

[Harry Wentland]

This is required so we use the correct minimum clocks for Vega. Without
this pplib will never be able to enter the lowest clock states.

Signed-off-by: Harry Wentland 
Acked-by: Alex Deucher 
---
 .../display/amdgpu_dm/amdgpu_dm_services.c| 46 ++-
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 0229c7edb8ad..ead3d21545b1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -234,6 +234,34 @@ static void pp_to_dc_clock_levels(
}
 }
 
+static void pp_to_dc_clock_levels_with_latency(
+   const struct pp_clock_levels_with_latency *pp_clks,
+   struct dm_pp_clock_levels_with_latency *clk_level_info,
+   enum dm_pp_clock_type dc_clk_type)
+{
+   uint32_t i;
+
+   if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
+   DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d 
exceeds maximum of %d!\n",
+   DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
+   pp_clks->num_levels,
+   DM_PP_MAX_CLOCK_LEVELS);
+
+   clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
+   } else
+   clk_level_info->num_levels = pp_clks->num_levels;
+
+   DRM_DEBUG("DM_PPLIB: values for %s clock\n",
+   DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
+
+   for (i = 0; i < clk_level_info->num_levels; i++) {
+   DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
+   /* translate 10kHz to kHz */
+   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz;
+   clk_level_info->data[i].latency_in_us = 
pp_clks->data[i].clocks_in_khz;
+   }
+}
+
 bool dm_pp_get_clock_levels_by_type(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
@@ -311,8 +339,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels_with_latency *clk_level_info)
 {
-   /* TODO: to be implemented */
-   return false;
+   struct amdgpu_device *adev = ctx->driver_context;
+   void *pp_handle = adev->powerplay.pp_handle;
+   struct pp_clock_levels_with_latency pp_clks = { 0 };
+   const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+   if (!pp_funcs->get_clock_by_type_with_latency)
+   return false;
+
+   if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
+
dc_to_pp_clock_type(clk_type),
+_clks))
+   return false;
+
+   pp_to_dc_clock_levels_with_latency(_clks, clk_level_info, clk_type);
+
+   return true;
 }
 
 bool dm_pp_get_clock_levels_by_type_with_voltage(
-- 
2.17.0

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Re: [PATCH] drm/amd/display: Remove use of division operator for long longs

[Alex Deucher]

On Thu, May 24, 2018 at 10:40 AM,   wrote:
> From: David Francis 
>
> In fixed31_32.h, in dc_fixpt_shl,'/' was used for division of one long
> long int by another long long int.  As there is no inbuilt long long
> int division function in c, gcc inserted its own.  However, gcc does not
> link the library that contains this function.  To avoid this, use
> bitwise operators instead of /
>
> Signed-off-by: David Francis 
> Reviewed-by: Dmytro Laktyushkin 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/include/fixed31_32.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
> b/drivers/gpu/drm/amd/display/include/fixed31_32.h
> index 76f64e9..bb0d4eb 100644
> --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
> +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
> @@ -209,7 +209,7 @@ static inline struct fixed31_32 dc_fixpt_clamp(
>  static inline struct fixed31_32 dc_fixpt_shl(struct fixed31_32 arg, unsigned 
> char shift)
>  {
> ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
> -   ((arg.value < 0) && (arg.value >= (LLONG_MIN / (1LL << 
> shift);
> +   ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift;
>
> arg.value = arg.value << shift;
>
> --
> 2.7.4
>
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[PATCH] drm/amd/display: Remove use of division operator for long longs

[sunpeng.li]

From: David Francis 

In fixed31_32.h, in dc_fixpt_shl,'/' was used for division of one long
long int by another long long int.  As there is no inbuilt long long
int division function in c, gcc inserted its own.  However, gcc does not
link the library that contains this function.  To avoid this, use
bitwise operators instead of /

Signed-off-by: David Francis 
Reviewed-by: Dmytro Laktyushkin 
---
 drivers/gpu/drm/amd/display/include/fixed31_32.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 76f64e9..bb0d4eb 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -209,7 +209,7 @@ static inline struct fixed31_32 dc_fixpt_clamp(
 static inline struct fixed31_32 dc_fixpt_shl(struct fixed31_32 arg, unsigned 
char shift)
 {
ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-   ((arg.value < 0) && (arg.value >= (LLONG_MIN / (1LL << 
shift);
+   ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift;
 
arg.value = arg.value << shift;
 
-- 
2.7.4

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Re: [PATCH xf86-video-amdgpu 1/2] Call drmmode_do_crtc_dpms from drmmode_crtc_dpms as well

[Leo Li]

On 2018-05-18 06:33 AM, Michel Dänzer wrote:

From: Michel Dänzer 

Leo pointed out that drmmode_do_crtc_dpms wasn't getting called when
turning off an output with

  xrandr --output  --off

This meant that the vblank sequence number and timestamp wouldn't be
saved before turning off the CRTC in this case.

Reported-by: Leo (Sunpeng) Li 
Signed-off-by: Michel Dänzer 


Series is
Reviewed-by: Leo (Sunpeng) Li 


---
  src/drmmode_display.c | 3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 0ee89961a..5d4627810 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -342,8 +342,7 @@ drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode)
  
  	/* Disable unused CRTCs and enable/disable active CRTCs */

if (!crtc->enabled || mode != DPMSModeOn) {
-   drmmode_crtc_wait_pending_event(drmmode_crtc, pAMDGPUEnt->fd,
-   drmmode_crtc->flip_pending);
+   drmmode_do_crtc_dpms(crtc, DPMSModeOff);
drmModeSetCrtc(pAMDGPUEnt->fd, drmmode_crtc->mode_crtc->crtc_id,
   0, 0, 0, NULL, 0, NULL);
drmmode_fb_reference(pAMDGPUEnt->fd, _crtc->fb, NULL);


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[PATCH umr] Update disasm CPU names to match what mesa uses

[Tom St Denis]

Updates the CPU names for vega12/vegam/raven1.

Signed-off-by: Tom St Denis 
---
 src/lib/umr_llvm_disasm.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/lib/umr_llvm_disasm.c b/src/lib/umr_llvm_disasm.c
index 40e31774457f..f772db2eff29 100644
--- a/src/lib/umr_llvm_disasm.c
+++ b/src/lib/umr_llvm_disasm.c
@@ -46,12 +46,14 @@ int umr_llvm_disasm(struct umr_asic *asic,
 
// cpuname based on mesa usage
cpuname = asic->asicname;
-   if (asic->family > FAMILY_VI)
+   if (asic->family == FAMILY_RV)
+   cpuname = "gfx902";
+   else if (asic->family > FAMILY_VI)
cpuname = "gfx900";
-   if (!strcmp(cpuname, "polaris12"))
-   cpuname = "polaris11";
-   if (!strcmp(cpuname, "vegam"))
+   else if (!strcmp(cpuname, "polaris12") || !strcmp(cpuname, "vegam"))
cpuname = "polaris11";
+   else if (!strcmp(cpuname, "vega12"))
+   cpuname = "gfx902";
 
disasm_ref = LLVMCreateDisasmCPU(
"amdgcn-mesa-mesa3d", cpuname,
-- 
2.14.3

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Re: GPU hang trying to run OpenCL kernels on x86_64

[Luís Mendes]

Additional update...

I was able to boot and enter X by installing an NVIDIA GTX 1050 Ti as the
primary display card and using an AMD RX 550 as the secondary card on the
Tyan S7025 with the same Ubuntu 18.04 and the same Linux kernel 4.17-rc6.
However once I try to run an OpenCL kernel on RX 550 I get a sdma1 timeout
and the GPU hangs, which likely what is happening when I boot with RX 550
as the single GPU card on the system.

This means it is not an issue introduced in 4.17-rc6, it just means that I
didn't notice the effect of the system with the two GPUs vs system with
single AMD GPU.

The dmesg log follows attached.

Luís

On Thu, May 24, 2018 at 10:13 AM, Luís Mendes 
wrote:

> Hi Michel,
>
> I also work as a researcher at a university and we are considering buying
> AMD cards to do OpenCL computations for numerical modelling, but currently
> I am unable to give a try at the AMD cards I have at home.
> I couldn't find any working driver for them... also amdgpu-pro drivers
> don't work, or at least I have been unable to make them work.
>
> Regards,
> Luís
>
> On Thu, May 24, 2018 at 10:01 AM, Luís Mendes 
> wrote:
>
>> Hi Michel,
>>
>> So summarizing with Linux kernel 4.17-rc6 on Ubuntu 18.04 using AMD RX
>> 460/RX 550 I am not able to enter X.
>> The same system with AMD Radeon R7 240 not only enters X as also runs the
>> OpenCL kernel that RX 460 / RX 550 are unable to run for all the kernels
>> that I have tested.
>> Could this also be a Mesa issue, regarding OpenCL on RX 460?
>>
>> Regards,
>> Luís
>>
>> On Thu, May 24, 2018 at 9:55 AM, Luís Mendes 
>> wrote:
>>
>>> Hi Michel,
>>>
>>> I will have to check previous rc releases of 4.17 to see if it wasn't
>>> already happening, before trying any possible git bisect.
>>> As an update I can say that an AMD Radeon R7 240 works fine on the same
>>> system with the same kernel and I am able to run the OpenCL kernels, that I
>>> couldn't with RX 460/RX 550.
>>>
>>> Regards,
>>> Luís
>>>
>>> On Thu, May 24, 2018 at 9:30 AM, Michel Dänzer 
>>> wrote:
>>>
 On 2018-05-24 12:06 AM, Luís Mendes wrote:
 > I've tried Linux 4.17-rc6 with Ubuntu 18.04 on Tyan S7002 and I am
 not even
 > able see lightdm/gdm3 as system hangs when starting X.
 > Having SR-IOV enabled or disabled makes no difference.
 > Tested with AMD RX 460.
 > When X is supposed to start the system hangs and only a rectangular
 region
 > on the top left corner screen remains with console text messages from
 the
 > boot process while the remaining of the screen is just black. I am
 unable
 > to do anything with the keyboard, switching to console does not work,
 > ctrl-alt-del also doesn't work. I've to do a cold reset.

 Can you isolate which change introduced this new issue with git bisect?


 --
 Earthling Michel Dänzer   |
 http://www.amd.com
 Libre software enthusiast | Mesa and X developer

>>>
>>>
>>
>
[0.00] KERNEL supported cpus:
[0.00]   Intel GenuineIntel
[0.00]   AMD AuthenticAMD
[0.00]   Centaur CentaurHauls
[0.00] x86/fpu: x87 FPU will use FXSAVE
[0.00] e820: BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x0009d3ff] usable
[0.00] BIOS-e820: [mem 0x0009d400-0x0009] reserved
[0.00] BIOS-e820: [mem 0x000e-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0xbf76] usable
[0.00] BIOS-e820: [mem 0xbf77-0xbf77dfff] ACPI data
[0.00] BIOS-e820: [mem 0xbf77e000-0xbf7c] ACPI NVS
[0.00] BIOS-e820: [mem 0xbf7d-0xbf7d] reserved
[0.00] BIOS-e820: [mem 0xbf7ec000-0xbfff] reserved
[0.00] BIOS-e820: [mem 0xe000-0xefff] reserved
[0.00] BIOS-e820: [mem 0xfee0-0xfee00fff] reserved
[0.00] BIOS-e820: [mem 0xffa0-0x] reserved
[0.00] BIOS-e820: [mem 0x0001-0x000c3fff] usable
[0.00] NX (Execute Disable) protection: active
[0.00] SMBIOS 2.6 present.
[0.00] DMI: TYAN empty/S7025, BIOS 'V1.09A' 06/19/2012
[0.00] e820: update [mem 0x-0x0fff] usable ==> reserved
[0.00] e820: remove [mem 0x000a-0x000f] usable
[0.00] e820: last_pfn = 0xc4 max_arch_pfn = 0x4
[0.00] MTRR default type: uncachable
[0.00] MTRR fixed ranges enabled:
[0.00]   0-9 write-back
[0.00]   A-B uncachable
[0.00]   C-C write-protect
[0.00]   D-D uncachable
[0.00]   E-E3FFF write-protect
[0.00]   E4000-E write-through
[0.00]   

Re: GPU hang trying to run OpenCL kernels on x86_64

[Michel Dänzer]

On 2018-05-24 12:06 AM, Luís Mendes wrote:
> I've tried Linux 4.17-rc6 with Ubuntu 18.04 on Tyan S7002 and I am not even
> able see lightdm/gdm3 as system hangs when starting X.
> Having SR-IOV enabled or disabled makes no difference.
> Tested with AMD RX 460.
> When X is supposed to start the system hangs and only a rectangular region
> on the top left corner screen remains with console text messages from the
> boot process while the remaining of the screen is just black. I am unable
> to do anything with the keyboard, switching to console does not work,
> ctrl-alt-del also doesn't work. I've to do a cold reset.

Can you isolate which change introduced this new issue with git bisect?


-- 
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Libre software enthusiast | Mesa and X developer
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Re: GPU hang trying to run OpenCL kernels on x86_64

[Luís Mendes]

Hi Michel,

So summarizing with Linux kernel 4.17-rc6 on Ubuntu 18.04 using AMD RX
460/RX 550 I am not able to enter X.
The same system with AMD Radeon R7 240 not only enters X as also runs the
OpenCL kernel that RX 460 / RX 550 are unable to run for all the kernels
that I have tested.
Could this also be a Mesa issue, regarding OpenCL on RX 460?

Regards,
Luís

On Thu, May 24, 2018 at 9:55 AM, Luís Mendes 
wrote:

> Hi Michel,
>
> I will have to check previous rc releases of 4.17 to see if it wasn't
> already happening, before trying any possible git bisect.
> As an update I can say that an AMD Radeon R7 240 works fine on the same
> system with the same kernel and I am able to run the OpenCL kernels, that I
> couldn't with RX 460/RX 550.
>
> Regards,
> Luís
>
> On Thu, May 24, 2018 at 9:30 AM, Michel Dänzer  wrote:
>
>> On 2018-05-24 12:06 AM, Luís Mendes wrote:
>> > I've tried Linux 4.17-rc6 with Ubuntu 18.04 on Tyan S7002 and I am not
>> even
>> > able see lightdm/gdm3 as system hangs when starting X.
>> > Having SR-IOV enabled or disabled makes no difference.
>> > Tested with AMD RX 460.
>> > When X is supposed to start the system hangs and only a rectangular
>> region
>> > on the top left corner screen remains with console text messages from
>> the
>> > boot process while the remaining of the screen is just black. I am
>> unable
>> > to do anything with the keyboard, switching to console does not work,
>> > ctrl-alt-del also doesn't work. I've to do a cold reset.
>>
>> Can you isolate which change introduced this new issue with git bisect?
>>
>>
>> --
>> Earthling Michel Dänzer   |   http://www.amd.com
>> Libre software enthusiast | Mesa and X developer
>>
>
>
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Re: GPU hang trying to run OpenCL kernels on x86_64

[Luís Mendes]

Hi Michel,

I will have to check previous rc releases of 4.17 to see if it wasn't
already happening, before trying any possible git bisect.
As an update I can say that an AMD Radeon R7 240 works fine on the same
system with the same kernel and I am able to run the OpenCL kernels, that I
couldn't with RX 460/RX 550.

Regards,
Luís

On Thu, May 24, 2018 at 9:30 AM, Michel Dänzer  wrote:

> On 2018-05-24 12:06 AM, Luís Mendes wrote:
> > I've tried Linux 4.17-rc6 with Ubuntu 18.04 on Tyan S7002 and I am not
> even
> > able see lightdm/gdm3 as system hangs when starting X.
> > Having SR-IOV enabled or disabled makes no difference.
> > Tested with AMD RX 460.
> > When X is supposed to start the system hangs and only a rectangular
> region
> > on the top left corner screen remains with console text messages from the
> > boot process while the remaining of the screen is just black. I am unable
> > to do anything with the keyboard, switching to console does not work,
> > ctrl-alt-del also doesn't work. I've to do a cold reset.
>
> Can you isolate which change introduced this new issue with git bisect?
>
>
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
>
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Re: GPU hang trying to run OpenCL kernels on x86_64

[Luís Mendes]

Hi Michel,

I also work as a researcher at a university and we are considering buying
AMD cards to do OpenCL computations for numerical modelling, but currently
I am unable to give a try at the AMD cards I have at home.
I couldn't find any working driver for them... also amdgpu-pro drivers
don't work, or at least I have been unable to make them work.

Regards,
Luís

On Thu, May 24, 2018 at 10:01 AM, Luís Mendes 
wrote:

> Hi Michel,
>
> So summarizing with Linux kernel 4.17-rc6 on Ubuntu 18.04 using AMD RX
> 460/RX 550 I am not able to enter X.
> The same system with AMD Radeon R7 240 not only enters X as also runs the
> OpenCL kernel that RX 460 / RX 550 are unable to run for all the kernels
> that I have tested.
> Could this also be a Mesa issue, regarding OpenCL on RX 460?
>
> Regards,
> Luís
>
> On Thu, May 24, 2018 at 9:55 AM, Luís Mendes 
> wrote:
>
>> Hi Michel,
>>
>> I will have to check previous rc releases of 4.17 to see if it wasn't
>> already happening, before trying any possible git bisect.
>> As an update I can say that an AMD Radeon R7 240 works fine on the same
>> system with the same kernel and I am able to run the OpenCL kernels, that I
>> couldn't with RX 460/RX 550.
>>
>> Regards,
>> Luís
>>
>> On Thu, May 24, 2018 at 9:30 AM, Michel Dänzer 
>> wrote:
>>
>>> On 2018-05-24 12:06 AM, Luís Mendes wrote:
>>> > I've tried Linux 4.17-rc6 with Ubuntu 18.04 on Tyan S7002 and I am not
>>> even
>>> > able see lightdm/gdm3 as system hangs when starting X.
>>> > Having SR-IOV enabled or disabled makes no difference.
>>> > Tested with AMD RX 460.
>>> > When X is supposed to start the system hangs and only a rectangular
>>> region
>>> > on the top left corner screen remains with console text messages from
>>> the
>>> > boot process while the remaining of the screen is just black. I am
>>> unable
>>> > to do anything with the keyboard, switching to console does not work,
>>> > ctrl-alt-del also doesn't work. I've to do a cold reset.
>>>
>>> Can you isolate which change introduced this new issue with git bisect?
>>>
>>>
>>> --
>>> Earthling Michel Dänzer   |   http://www.amd.com
>>> Libre software enthusiast | Mesa and X developer
>>>
>>
>>
>
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Re: drm/amdgpu: Use GTT for dumb buffer if sg display enabled (v2)

[Christian König]

Am 23.05.2018 um 20:14 schrieb Deepak Sharma:



On 05/23/2018 12:31 AM, Christian König wrote:

Am 23.05.2018 um 00:31 schrieb Deepak Sharma:

When vram size <= THRESHOLD(256M) lets use GTT for dumb buffer
allocation. As SG will be enabled with vram size <= 256M
scan out will not be an issue.

v2: Use amdgpu_display_supported_domains to get supported domain.

Signed-off-by: Deepak Sharma 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 --
  1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

index 2c8e27370284..63758db5e2ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -30,6 +30,7 @@
  #include 
  #include 
  #include "amdgpu.h"
+#include "amdgpu_display.h"
  void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  {
@@ -749,15 +750,20 @@ int amdgpu_mode_dumb_create(struct drm_file 
*file_priv,

  struct amdgpu_device *adev = dev->dev_private;
  struct drm_gem_object *gobj;
  uint32_t handle;
+    u32 domain = amdgpu_display_supported_domains(adev);
  int r;
  args->pitch = amdgpu_align_pitch(adev, args->width,
   DIV_ROUND_UP(args->bpp, 8), 0);
  args->size = (u64)args->pitch * args->height;
  args->size = ALIGN(args->size, PAGE_SIZE);
+    if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
+    domain = AMDGPU_GEM_DOMAIN_VRAM;
+    if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
+    domain = AMDGPU_GEM_DOMAIN_GTT;
+    }


As Michel suggested as well better make that an helper in 
amdgpu_object.c.


Apart from that looks good to me,
Christian.


I can push another patch to create helper function and use that here 
as well as in amdgpu_bo_pin_restricted.


otherwise I can push v3 if you want that change in this patch itself.


Since this is just a minor cleanup either way works with me. Use 
whatever approach suits you better.


Thanks,
Christian.



Thanks,
Deepak




-    r = amdgpu_gem_object_create(adev, args->size, 0,
- AMDGPU_GEM_DOMAIN_VRAM,
+    r = amdgpu_gem_object_create(adev, args->size, 0, domain,
   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
   false, NULL, );
  if (r)



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Re: [PATCH] drm/amdgpu: Remove unused variable in amdgpu_device_gpu_recover

[Christian König]

Reviewed-by: Christian König  as well.

Christian.

Am 23.05.2018 um 19:11 schrieb Andrey Grodzovsky:

Reviewed-by: Andrey Grodzovsky 

Andrey


On 05/23/2018 01:08 PM, Harry Wentland wrote:

It throws an unused variable warning.

Signed-off-by: Harry Wentland 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index c1654a4dfd82..57a4f393ada3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3179,7 +3179,6 @@ static int amdgpu_device_reset_sriov(struct 
amdgpu_device *adev,

  int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
    struct amdgpu_job *job, bool force)
  {
-    struct drm_atomic_state *state = NULL;
  int i, r, resched;
    if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {


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