Re: drm/amdgpu: Add helper function to get buffer domain

[Deepak Sharma]

If look fine , please give rb for this and 
https://patchwork.freedesktop.org/patch/224850/


Thanks,
Deepak

On 05/25/2018 05:12 PM, Deepak Sharma wrote:

Move logic of getting supported domain to a helper
function

Signed-off-by: Deepak Sharma 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 10 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 17 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  3 ++-
  3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 63758db5e2ea..556406a44da3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -750,19 +750,15 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct amdgpu_device *adev = dev->dev_private;
struct drm_gem_object *gobj;
uint32_t handle;
-   u32 domain = amdgpu_display_supported_domains(adev);
+   u32 domain;
int r;
  
  	args->pitch = amdgpu_align_pitch(adev, args->width,

 DIV_ROUND_UP(args->bpp, 8), 0);
args->size = (u64)args->pitch * args->height;
args->size = ALIGN(args->size, PAGE_SIZE);
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
-
+   domain = amdgpu_bo_get_preferred_pin_domain(adev,
+   amdgpu_display_supported_domains(adev));
r = amdgpu_gem_object_create(adev, args->size, 0, domain,
 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 false, NULL, );
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6a9e46ae7f0a..5e4e1bd90383 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -703,11 +703,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
/* This assumes only APU display buffers are pinned with (VRAM|GTT).
 * See function amdgpu_display_supported_domains()
 */
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
+   domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
  
  	if (bo->pin_count) {

uint32_t mem_type = bo->tbo.mem.mem_type;
@@ -1066,3 +1062,14 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
  
  	return bo->tbo.offset;

  }
+
+uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
+   uint32_t domain)
+{
+   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
+   domain = AMDGPU_GEM_DOMAIN_VRAM;
+   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
+   domain = AMDGPU_GEM_DOMAIN_GTT;
+   }
+   return domain;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 540e03fa159f..731748033878 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -289,7 +289,8 @@ int amdgpu_bo_restore_from_shadow(struct amdgpu_device 
*adev,
  struct reservation_object *resv,
  struct dma_fence **fence,
  bool direct);
-
+uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
+   uint32_t domain);
  
  /*

   * sub allocation


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drm/amdgpu: Add helper function to get buffer domain

[Deepak Sharma]

Move logic of getting supported domain to a helper
function

Signed-off-by: Deepak Sharma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 10 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 17 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  3 ++-
 3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 63758db5e2ea..556406a44da3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -750,19 +750,15 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct amdgpu_device *adev = dev->dev_private;
struct drm_gem_object *gobj;
uint32_t handle;
-   u32 domain = amdgpu_display_supported_domains(adev);
+   u32 domain;
int r;
 
args->pitch = amdgpu_align_pitch(adev, args->width,
 DIV_ROUND_UP(args->bpp, 8), 0);
args->size = (u64)args->pitch * args->height;
args->size = ALIGN(args->size, PAGE_SIZE);
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
-
+   domain = amdgpu_bo_get_preferred_pin_domain(adev,
+   amdgpu_display_supported_domains(adev));
r = amdgpu_gem_object_create(adev, args->size, 0, domain,
 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 false, NULL, );
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6a9e46ae7f0a..5e4e1bd90383 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -703,11 +703,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
/* This assumes only APU display buffers are pinned with (VRAM|GTT).
 * See function amdgpu_display_supported_domains()
 */
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
+   domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
 
if (bo->pin_count) {
uint32_t mem_type = bo->tbo.mem.mem_type;
@@ -1066,3 +1062,14 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 
return bo->tbo.offset;
 }
+
+uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
+   uint32_t domain)
+{
+   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
+   domain = AMDGPU_GEM_DOMAIN_VRAM;
+   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
+   domain = AMDGPU_GEM_DOMAIN_GTT;
+   }
+   return domain;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 540e03fa159f..731748033878 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -289,7 +289,8 @@ int amdgpu_bo_restore_from_shadow(struct amdgpu_device 
*adev,
  struct reservation_object *resv,
  struct dma_fence **fence,
  bool direct);
-
+uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
+   uint32_t domain);
 
 /*
  * sub allocation
-- 
2.15.1

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[PATCH v2 07/13] drm/amdgpu/dc: Stop updating plane->fb

[Ville Syrjala]

From: Ville Syrjälä 

We want to get rid of plane->fb on atomic drivers. Stop setting it.

Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "David (ChunMing) Zhou" 
Cc: Harry Wentland 
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Ville Syrjälä 
Reviewed-by: Maarten Lankhorst 
Reviewed-by: Harry Wentland 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1ce10bc2d37b..82bac02fffd7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3927,8 +3927,6 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
 
/* Flip */
spin_lock_irqsave(>dev->event_lock, flags);
-   /* update crtc fb */
-   crtc->primary->fb = fb;
 
WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
WARN_ON(!acrtc_state->stream);
-- 
2.16.1

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[PATCH v2 00/13] drm: Eliminate plane->fb/crtc usage for atomic drivers

[Ville Syrjala]

From: Ville Syrjälä 

Here are again the last (?) bits of eliminating the plane->fb/crtc
usage for atomic drivers. I've pushed everything else (thanks to
everyone who reviewed them). 

Deepak said he'd tested the vmwgfx stuff, so I think it should be
safe to land. Just missing a bit of review...

Cc: Alex Deucher 
Cc: amd-gfx@lists.freedesktop.org
Cc: "Christian König" 
Cc: Daniel Vetter 
Cc: David Airlie 
Cc: "David (ChunMing) Zhou" 
Cc: Deepak Rawat 
Cc: Eric Anholt 
Cc: freedr...@lists.freedesktop.org
Cc: Gerd Hoffmann 
Cc: Harry Wentland 
Cc: Inki Dae 
Cc: Joonyoung Shim 
Cc: Kyungmin Park 
Cc: linux-arm-...@vger.kernel.org
Cc: Rob Clark 
Cc: Seung-Woo Kim 
Cc: Sinclair Yeh 
Cc: Thomas Hellstrom 
Cc: virtualizat...@lists.linux-foundation.org
Cc: VMware Graphics 

Ville Syrjälä (13):
  drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()
  drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()
  drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()
  drm/vmwgfx: Stop updating plane->fb
  drm/vmwgfx: Stop using plane->fb in atomic_enable()
  drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc
  drm/amdgpu/dc: Stop updating plane->fb
  drm/i915: Stop updating plane->fb/crtc
  drm/exynos: Stop updating plane->crtc
  drm/msm: Stop updating plane->fb/crtc
  drm/virtio: Stop updating plane->crtc
  drm/vc4: Stop updating plane->fb/crtc
  drm: Stop updating plane->crtc/fb/old_fb on atomic drivers

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 -
 drivers/gpu/drm/drm_atomic.c  | 55 +++
 drivers/gpu/drm/drm_atomic_helper.c   | 15 +--
 drivers/gpu/drm/drm_crtc.c|  8 +++-
 drivers/gpu/drm/drm_fb_helper.c   |  7 ---
 drivers/gpu/drm/drm_framebuffer.c |  5 ---
 drivers/gpu/drm/drm_plane.c   | 14 +++---
 drivers/gpu/drm/drm_plane_helper.c|  4 +-
 drivers/gpu/drm/exynos/exynos_drm_plane.c |  2 -
 drivers/gpu/drm/i915/intel_atomic_plane.c | 12 -
 drivers/gpu/drm/i915/intel_display.c  |  7 ++-
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c |  1 -
 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c|  2 -
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c |  1 -
 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c|  2 -
 drivers/gpu/drm/vc4/vc4_crtc.c|  3 --
 drivers/gpu/drm/virtio/virtgpu_display.c  |  2 -
 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c| 24 --
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c   | 24 +++---
 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c  |  2 -
 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c  |  5 +--
 include/drm/drm_atomic.h  |  3 --
 22 files changed, 46 insertions(+), 154 deletions(-)

-- 
2.16.1
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[PATCH 29/34] drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag

[Harry Wentland]

From: Samson Tam 

Signed-off-by: Samson Tam 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 125 +++---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  34 +
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   6 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   2 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  38 +-
 5 files changed, 123 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fdcac0fb2e5f..c88f6612bfb6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1210,6 +1210,9 @@ static enum surface_update_type 
check_update_surfaces_for_stream(
 
if (stream_update->abm_level)
return UPDATE_TYPE_FULL;
+
+   if (stream_update->dpms_off)
+   return UPDATE_TYPE_FULL;
}
 
for (i = 0 ; i < surface_count; i++) {
@@ -1264,6 +1267,71 @@ static struct dc_stream_status *stream_get_status(
 static const enum surface_update_type update_surface_trace_level = 
UPDATE_TYPE_FULL;
 
 
+static void commit_planes_do_stream_update(struct dc *dc,
+   struct dc_stream_state *stream,
+   struct dc_stream_update *stream_update,
+   enum surface_update_type update_type,
+   struct dc_state *context)
+{
+   int j;
+
+   // Stream updates
+   for (j = 0; j < dc->res_pool->pipe_count; j++) {
+   struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
+
+   if (!pipe_ctx->top_pipe &&
+   pipe_ctx->stream &&
+   pipe_ctx->stream == stream) {
+
+   /* Fast update*/
+   // VRR program can be done as part of FAST UPDATE
+   if (stream_update->adjust)
+   dc->hwss.set_drr(_ctx, 1,
+   stream_update->adjust->v_total_min,
+   stream_update->adjust->v_total_max);
+
+   /* Full fe update*/
+   if (update_type == UPDATE_TYPE_FAST)
+   continue;
+
+   if (stream_update->dpms_off) {
+   if (*stream_update->dpms_off) {
+   core_link_disable_stream(pipe_ctx, 
KEEP_ACQUIRED_RESOURCE);
+   
dc->hwss.pplib_apply_display_requirements(
+   dc, dc->current_state);
+   } else {
+   
dc->hwss.pplib_apply_display_requirements(
+   dc, dc->current_state);
+   
core_link_enable_stream(dc->current_state, pipe_ctx);
+   }
+   }
+
+   if (stream_update->abm_level && 
pipe_ctx->stream_res.abm) {
+   if (pipe_ctx->stream_res.tg->funcs->is_blanked) 
{
+   // if otg funcs defined check if 
blanked before programming
+   if 
(!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
+   
pipe_ctx->stream_res.abm->funcs->set_abm_level(
+   
pipe_ctx->stream_res.abm, stream->abm_level);
+   } else
+   
pipe_ctx->stream_res.abm->funcs->set_abm_level(
+   pipe_ctx->stream_res.abm, 
stream->abm_level);
+   }
+
+   if (stream_update->periodic_fn_vsync_delta &&
+   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
+   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
+   pipe_ctx->stream_res.tg, 
_ctx->stream->timing,
+   
pipe_ctx->stream->periodic_fn_vsync_delta);
+
+   if (stream_update->hdr_static_metadata ||
+   stream_update->vrr_infopacket) {
+   resource_build_info_frame(pipe_ctx);
+   dc->hwss.update_info_frame(pipe_ctx);
+   }
+   }
+   }
+}
+
 static void commit_planes_for_stream(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
@@ -1280,15 +1348,20 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
  

[PATCH 31/34] drm/amd/display: fix dscl_manual_ratio_init

[Harry Wentland]

From: Dmytro Laktyushkin 

This change will fix wb and display scaling when ratios of
4 or more are involved

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c| 5 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  | 3 +--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h  | 6 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 8 
 drivers/gpu/drm/amd/display/include/fixed31_32.h  | 2 ++
 5 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c 
b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index e61dd97d0928..f28989860fd8 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -449,6 +449,11 @@ static inline unsigned int clamp_ux_dy(
return min_clamp;
 }
 
+unsigned int dc_fixpt_u3d19(struct fixed31_32 arg)
+{
+   return ux_dy(arg.value, 3, 19);
+}
+
 unsigned int dc_fixpt_u2d19(struct fixed31_32 arg)
 {
return ux_dy(arg.value, 2, 19);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 46a35c7f01df..c69fa4bfab0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -132,8 +132,7 @@ void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
 
 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
 
-
-bool dpp_get_optimal_number_of_taps(
+static bool dpp_get_optimal_number_of_taps(
struct dpp *dpp,
struct scaler_data *scl_data,
const struct scaling_taps *in_taps)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 5944a3ba0409..e862cafa6501 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1424,12 +1424,8 @@ void dpp1_set_degamma(
enum ipp_degamma_mode mode);
 
 void dpp1_set_degamma_pwl(struct dpp *dpp_base,
-const struct 
pwl_params *params);
+   const struct pwl_params *params);
 
-bool dpp_get_optimal_number_of_taps(
-   struct dpp *dpp,
-   struct scaler_data *scl_data,
-   const struct scaling_taps *in_taps);
 
 void dpp_read_state(struct dpp *dpp_base,
struct dcn_dpp_state *s);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index 4ddd6273d5a5..f862fd148cca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -565,16 +565,16 @@ static void dpp1_dscl_set_manual_ratio_init(
uint32_t init_int = 0;
 
REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
-   SCL_H_SCALE_RATIO, dc_fixpt_u2d19(data->ratios.horz) << 
5);
+   SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 
5);
 
REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
-   SCL_V_SCALE_RATIO, dc_fixpt_u2d19(data->ratios.vert) << 
5);
+   SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 
5);
 
REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
-   SCL_H_SCALE_RATIO_C, 
dc_fixpt_u2d19(data->ratios.horz_c) << 5);
+   SCL_H_SCALE_RATIO_C, 
dc_fixpt_u3d19(data->ratios.horz_c) << 5);
 
REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
-   SCL_V_SCALE_RATIO_C, 
dc_fixpt_u2d19(data->ratios.vert_c) << 5);
+   SCL_V_SCALE_RATIO_C, 
dc_fixpt_u3d19(data->ratios.vert_c) << 5);
 
/*
 * 0.24 format for fraction, first five bits zeroed
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 2b1b29f6c794..52a73332befb 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -503,6 +503,8 @@ static inline int dc_fixpt_ceil(struct fixed31_32 arg)
  * fractional
  */
 
+unsigned int dc_fixpt_u3d19(struct fixed31_32 arg);
+
 unsigned int dc_fixpt_u2d19(struct fixed31_32 arg);
 
 unsigned int dc_fixpt_u0d19(struct fixed31_32 arg);
-- 
2.17.0

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[PATCH 30/34] drm/amd/display: add dentist frequency to resource pool

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index a94942d4e66b..4beddca0180c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -148,6 +148,7 @@ struct resource_pool {
unsigned int underlay_pipe_index;
unsigned int stream_enc_count;
unsigned int ref_clock_inKhz;
+   unsigned int dentist_vco_freq_khz;
unsigned int timing_generator_count;
 
/*
-- 
2.17.0

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[PATCH 34/34] drm/amd/display: dal 3.1.47

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 74fc4f6d9cdf..be0dee18e09f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.46"
+#define DC_VER "3.1.47"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.17.0

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[PATCH 27/34] drm/amd/display: Prefix TIMING_STANDARD entries with DC_

[Harry Wentland]

From: Reza Amini 

Signed-off-by: Reza Amini 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  | 34 +--
 drivers/gpu/drm/amd/display/dc/dc_types.h | 18 +-
 .../gpu/drm/amd/display/include/fixed31_32.h  |  7 
 5 files changed, 35 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 06ec24cb6a91..fdcac0fb2e5f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1587,7 +1587,7 @@ struct dc_sink *dc_link_add_remote_sink(
struct dc_sink *dc_sink;
enum dc_edid_status edid_status;
 
-   if (len > MAX_EDID_BUFFER_SIZE) {
+   if (len > DC_MAX_EDID_BUFFER_SIZE) {
dm_error("Max EDID buffer size breached!\n");
return NULL;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
index e1affeb5cc51..ee04812b4492 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
@@ -109,7 +109,7 @@ struct ddc_service {
 
uint32_t address;
uint32_t edid_buf_len;
-   uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
+   uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE];
 };
 
 #endif /* DC_DDC_TYPES_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 4a05df3850ba..7e5a41fc8adc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -567,25 +567,25 @@ struct scaling_taps {
 };
 
 enum dc_timing_standard {
-   TIMING_STANDARD_UNDEFINED,
-   TIMING_STANDARD_DMT,
-   TIMING_STANDARD_GTF,
-   TIMING_STANDARD_CVT,
-   TIMING_STANDARD_CVT_RB,
-   TIMING_STANDARD_CEA770,
-   TIMING_STANDARD_CEA861,
-   TIMING_STANDARD_HDMI,
-   TIMING_STANDARD_TV_NTSC,
-   TIMING_STANDARD_TV_NTSC_J,
-   TIMING_STANDARD_TV_PAL,
-   TIMING_STANDARD_TV_PAL_M,
-   TIMING_STANDARD_TV_PAL_CN,
-   TIMING_STANDARD_TV_SECAM,
-   TIMING_STANDARD_EXPLICIT,
+   DC_TIMING_STANDARD_UNDEFINED,
+   DC_TIMING_STANDARD_DMT,
+   DC_TIMING_STANDARD_GTF,
+   DC_TIMING_STANDARD_CVT,
+   DC_TIMING_STANDARD_CVT_RB,
+   DC_TIMING_STANDARD_CEA770,
+   DC_TIMING_STANDARD_CEA861,
+   DC_TIMING_STANDARD_HDMI,
+   DC_TIMING_STANDARD_TV_NTSC,
+   DC_TIMING_STANDARD_TV_NTSC_J,
+   DC_TIMING_STANDARD_TV_PAL,
+   DC_TIMING_STANDARD_TV_PAL_M,
+   DC_TIMING_STANDARD_TV_PAL_CN,
+   DC_TIMING_STANDARD_TV_SECAM,
+   DC_TIMING_STANDARD_EXPLICIT,
/*!< For explicit timings from EDID, VBIOS, etc.*/
-   TIMING_STANDARD_USER_OVERRIDE,
+   DC_TIMING_STANDARD_USER_OVERRIDE,
/*!< For mode timing override by user*/
-   TIMING_STANDARD_MAX
+   DC_TIMING_STANDARD_MAX
 };
 
 enum dc_color_depth {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index f5308715358d..f463d3a8ef62 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -98,7 +98,7 @@ struct dc_context {
 };
 
 
-#define MAX_EDID_BUFFER_SIZE 512
+#define DC_MAX_EDID_BUFFER_SIZE 512
 #define EDID_BLOCK_SIZE 128
 #define MAX_SURFACE_NUM 4
 #define NUM_PIXEL_FORMATS 10
@@ -137,13 +137,13 @@ enum plane_stereo_format {
  */
 
 enum dc_edid_connector_type {
-   EDID_CONNECTOR_UNKNOWN = 0,
-   EDID_CONNECTOR_ANALOG = 1,
-   EDID_CONNECTOR_DIGITAL = 10,
-   EDID_CONNECTOR_DVI = 11,
-   EDID_CONNECTOR_HDMIA = 12,
-   EDID_CONNECTOR_MDDI = 14,
-   EDID_CONNECTOR_DISPLAYPORT = 15
+   DC_EDID_CONNECTOR_UNKNOWN = 0,
+   DC_EDID_CONNECTOR_ANALOG = 1,
+   DC_EDID_CONNECTOR_DIGITAL = 10,
+   DC_EDID_CONNECTOR_DVI = 11,
+   DC_EDID_CONNECTOR_HDMIA = 12,
+   DC_EDID_CONNECTOR_MDDI = 14,
+   DC_EDID_CONNECTOR_DISPLAYPORT = 15
 };
 
 enum dc_edid_status {
@@ -169,7 +169,7 @@ struct dc_cea_audio_mode {
 
 struct dc_edid {
uint32_t length;
-   uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
+   uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
 };
 
 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index bb0d4ebba9f0..2b1b29f6c794 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -26,6 +26,13 @@
 #ifndef __DAL_FIXED31_32_H__
 #define __DAL_FIXED31_32_H__
 
+#ifndef LLONG_MAX
+#define LLONG_MAX 9223372036854775807ll
+#endif
+#ifndef LLONG_MIN
+#define 

[PATCH 07/34] drm/amd/display: dal 3.1.45

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 9cfde0ccf4e9..f01c6c1711d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.44"
+#define DC_VER "3.1.45"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.17.0

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[PATCH 10/34] drm/amd/display: AUX will exit when HPD LOW detected

[Harry Wentland]

From: Hersen Wu 

This change shorten wait time when HPD LOW. With HPD LOW, without this
change, AUX routine delay is 450us. With this change, it is 42us.

Signed-off-by: Hersen Wu 
Reviewed-by: Tony Cheng 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/dc/i2caux/aux_engine.c| 16 ++
 .../drm/amd/display/dc/i2caux/aux_engine.h|  5 -
 .../dc/i2caux/dce110/aux_engine_dce110.c  | 22 ++-
 .../gpu/drm/amd/display/dc/i2caux/engine.h|  3 ++-
 .../amd/display/include/ddc_service_types.h   |  3 ++-
 5 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
index bb526ad326e5..1d7309611978 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
@@ -157,6 +157,10 @@ static void process_read_reply(
ctx->operation_succeeded = false;
}
break;
+   case AUX_TRANSACTION_REPLY_HPD_DISCON:
+   ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
+   ctx->operation_succeeded = false;
+   break;
default:
ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
ctx->operation_succeeded = false;
@@ -215,6 +219,10 @@ static void process_read_request(
 * so we should not wait here */
}
break;
+   case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
+   ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
+   ctx->operation_succeeded = false;
+   break;
default:
ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
ctx->operation_succeeded = false;
@@ -370,6 +378,10 @@ static void process_write_reply(
ctx->operation_succeeded = false;
}
break;
+   case AUX_TRANSACTION_REPLY_HPD_DISCON:
+   ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
+   ctx->operation_succeeded = false;
+   break;
default:
ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
ctx->operation_succeeded = false;
@@ -422,6 +434,10 @@ static void process_write_request(
 * so we should not wait here */
}
break;
+   case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
+   ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
+   ctx->operation_succeeded = false;
+   break;
default:
ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
ctx->operation_succeeded = false;
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h 
b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
index 8e71324ccb10..b9e35d0474c6 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
@@ -51,6 +51,8 @@ enum aux_transaction_reply {
AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
 
+   AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40,
+
AUX_TRANSACTION_REPLY_INVALID = 0xFF
 };
 
@@ -64,7 +66,8 @@ enum aux_channel_operation_result {
AUX_CHANNEL_OPERATION_SUCCEEDED,
AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
-   AUX_CHANNEL_OPERATION_FAILED_TIMEOUT
+   AUX_CHANNEL_OPERATION_FAILED_TIMEOUT,
+   AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
 };
 
 struct aux_engine;
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
index 90535787a461..2b927f25937b 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
@@ -291,6 +291,12 @@ static void process_channel_reply(
value = REG_GET(AUX_SW_STATUS,
AUX_SW_REPLY_BYTE_COUNT, _replied);
 
+   /* in case HPD is LOW, exit AUX transaction */
+   if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
+   reply->status = AUX_TRANSACTION_REPLY_HPD_DISCON;
+   return;
+   }
+
if (bytes_replied) {
uint32_t reply_result;
 
@@ -347,8 +353,10 @@ static void process_channel_reply(
 * because there was surely an error that was asserted
 * that should have been handled
 * for hot plug case, this could happens*/
-   if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
+   if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
+   reply->status = AUX_TRANSACTION_REPLY_INVALID;
ASSERT_CRITICAL(false);
+   

[PATCH 23/34] drm/amd/display: Added documentation for some DC interface functions

[Harry Wentland]

From: Yasir Al Shekerchi 

Signed-off-by: Yasir Al Shekerchi 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 16 
 drivers/gpu/drm/amd/display/dc/core/dc_link.c| 16 
 drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 11 +++
 3 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 33149ed779eb..06ec24cb6a91 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -169,6 +169,22 @@ static bool create_links(
return false;
 }
 
+/**
+ *
+ *  Function: dc_stream_adjust_vmin_vmax
+ *
+ *  @brief
+ * Looks up the pipe context of dc_stream_state and updates the
+ * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
+ * Rate, which is a power-saving feature that targets reducing panel
+ * refresh rate while the screen is static
+ *
+ *  @param [in] dc: dc reference
+ *  @param [in] stream: Initial dc stream state
+ *  @param [in] adjust: Updated parameters for vertical_total_min and
+ *  vertical_total_max
+ *
+ */
 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state *stream,
struct dc_crtc_timing_adjust *adjust)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a9485c10fd77..08b7ee526f0f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2433,6 +2433,22 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, 
bool enable)
core_dc->hwss.set_avmute(pipe_ctx, enable);
 }
 
+/**
+ *
+ *  Function: dc_link_enable_hpd_filter
+ *
+ *  @brief
+ * If enable is true, programs HPD filter on associated HPD line using
+ * delay_on_disconnect/delay_on_connect values dependent on
+ * link->connector_signal
+ *
+ * If enable is false, programs HPD filter on associated HPD line with no
+ * delays on connect or disconnect
+ *
+ *  @param [in] link: pointer to the dc link
+ *  @param [in] enable: boolean specifying whether to enable hbd
+ *
+ */
 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
 {
struct gpio *hpd;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index 68a71adeb12e..815dfb50089b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -84,6 +84,17 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
return plane_state;
 }
 
+/**
+ *
+ *  Function: dc_plane_get_status
+ *
+ *  @brief
+ * Looks up the pipe context of plane_state and updates the pending status
+ * of the pipe context. Then returns plane_state->status
+ *
+ *  @param [in] plane_state: pointer to the plane_state to get the status of
+ *
+ */
 const struct dc_plane_status *dc_plane_get_status(
const struct dc_plane_state *plane_state)
 {
-- 
2.17.0

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[PATCH 17/34] drm/amd/display: Default log masks should include all connectivity events

[Harry Wentland]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Jun Lei 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/basics/log_helpers.c   |  2 +
 .../gpu/drm/amd/display/dc/basics/logger.c| 83 ++-
 .../amd/display/include/logger_interface.h|  2 +
 3 files changed, 46 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c 
b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 021451549ff7..f6c00a51d51a 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -78,6 +78,8 @@ void dc_conn_log(struct dc_context *ctx,
if (i == NUM_ELEMENTS(signal_type_info_tbl))
goto fail;
 
+   dm_logger_append_heading();
+
dm_logger_append(, "[%s][ConnIdx:%d] ",
signal_type_info_tbl[i].name,
link->link_index);
diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c 
b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index 738a818d58d1..733bc5bd760b 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -32,8 +32,9 @@
 static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_ERROR, "Error"},
{LOG_WARNING,   "Warning"},
-   {LOG_DEBUG, "Debug"},
+   {LOG_DEBUG, "Debug"},
{LOG_DC,"DC_Interface"},
+   {LOG_DTN,   "DTN"},
{LOG_SURFACE,   "Surface"},
{LOG_HW_HOTPLUG,"HW_Hotplug"},
{LOG_HW_LINK_TRAINING,  "HW_LKTN"},
@@ -60,7 +61,7 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_EVENT_LINK_LOSS,   "LinkLoss"},
{LOG_EVENT_UNDERFLOW,   "Underflow"},
{LOG_IF_TRACE,  "InterfaceTrace"},
-   {LOG_DTN,   "DTN"},
+   {LOG_PERF_TRACE,"PerfTrace"},
{LOG_DISPLAYSTATS,  "DisplayStats"}
 };
 
@@ -128,8 +129,45 @@ uint32_t dal_logger_destroy(struct dal_logger **logger)
 }
 
 /*  */
+void dm_logger_append_heading(struct log_entry *entry)
+{
+   int j;
+
+   for (j = 0; j < NUM_ELEMENTS(log_type_info_tbl); j++) {
 
+   const struct dc_log_type_info *info = _type_info_tbl[j];
 
+   if (info->type == entry->type)
+   dm_logger_append(entry, "[%s]\t", info->name);
+   }
+}
+
+
+/* Print everything unread existing in log_buffer to debug console*/
+void dm_logger_flush_buffer(struct dal_logger *logger, bool should_warn)
+{
+   char *string_start = >log_buffer[logger->buffer_read_offset];
+
+   if (should_warn)
+   dm_output_to_console(
+   " FLUSHING LOG BUFFER 
\n");
+   while (logger->buffer_read_offset < logger->buffer_write_offset) {
+
+   if (logger->log_buffer[logger->buffer_read_offset] == '\0') {
+   dm_output_to_console("%s", string_start);
+   string_start = logger->log_buffer + 
logger->buffer_read_offset + 1;
+   }
+   logger->buffer_read_offset++;
+   }
+   if (should_warn)
+   dm_output_to_console(
+   "-- END FLUSHING LOG BUFFER 
--\n\n");
+}
+/*  */
+
+/* Warning: Be careful that 'msg' is null terminated and the total size is
+ * less than DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE (256) including '\0'
+ */
 static bool dal_logger_should_log(
struct dal_logger *logger,
enum dc_log_type log_type)
@@ -159,26 +197,6 @@ static void log_to_debug_console(struct log_entry *entry)
}
 }
 
-/* Print everything unread existing in log_buffer to debug console*/
-void dm_logger_flush_buffer(struct dal_logger *logger, bool should_warn)
-{
-   char *string_start = >log_buffer[logger->buffer_read_offset];
-
-   if (should_warn)
-   dm_output_to_console(
-   " FLUSHING LOG BUFFER 
\n");
-   while (logger->buffer_read_offset < logger->buffer_write_offset) {
-
-   if (logger->log_buffer[logger->buffer_read_offset] == '\0') {
-   dm_output_to_console("%s", string_start);
-   string_start = logger->log_buffer + 
logger->buffer_read_offset + 1;
-   }
-   logger->buffer_read_offset++;
-   }
-   if (should_warn)
-   dm_output_to_console(
-

[PATCH 24/34] drm/amd/display: dal 3.1.46

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7a70a24ef736..74fc4f6d9cdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.45"
+#define DC_VER "3.1.46"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.17.0

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[PATCH 04/34] drm/amd/display: Do not program interrupt status on disabled crtc

[Harry Wentland]

From: Mikita Lipski 

Prevent interrupt programming of a crtc on which the stream is disabled and
it doesn't have an OTG to reference.

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 4be21bf54749..a910f01838ab 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -555,6 +555,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
return 0;
}
 
+   if (acrtc->otg_inst == -1)
+   return 0;
+
irq_source = dal_irq_type + acrtc->otg_inst;
 
st = (state == AMDGPU_IRQ_STATE_ENABLE);
-- 
2.17.0

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[PATCH 33/34] drm/amd/display: Do not limit color depth to 8bpc

[Harry Wentland]

From: Mikita Lipski 

Delete if statement that would force any display's color depth higher
than 8 bpc to 8

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fcc3265c..21f3ad1d66cb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2137,12 +2137,6 @@ convert_color_depth_from_display_info(const struct 
drm_connector *connector)
 {
uint32_t bpc = connector->display_info.bpc;
 
-   /* Limited color depth to 8bit
-* TODO: Still need to handle deep color
-*/
-   if (bpc > 8)
-   bpc = 8;
-
switch (bpc) {
case 0:
/* Temporary Work around, DRM don't parse color depth for
-- 
2.17.0

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[PATCH 16/34] drm/amd/display: Read DP_SINK_COUNT_ESI range on HPD for DP 1.4

[Harry Wentland]

From: Nikola Cornij 

DP 1.4 compliance now requires that registers at DP_SINK_COUNT_ESI range
(0x2002-0x2003, 0x200c-0x200f) are read instead of DP_SINK_COUNT range
(0x200-0x2005.

Signed-off-by: Nikola Cornij 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 35 ---
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0acc14f572ef..9b66634994e8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1630,17 +1630,42 @@ static enum dc_status read_hpd_rx_irq_data(
struct dc_link *link,
union hpd_irq_data *irq_data)
 {
+   static enum dc_status retval;
+
/* The HW reads 16 bytes from 200h on HPD,
 * but if we get an AUX_DEFER, the HW cannot retry
 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
 * fail, so we now explicitly read 6 bytes which is
 * the req from the above mentioned test cases.
+*
+* For DP 1.4 we need to read those from 2002h range.
 */
-   return core_link_read_dpcd(
-   link,
-   DP_SINK_COUNT,
-   irq_data->raw,
-   sizeof(union hpd_irq_data));
+   if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
+   retval = core_link_read_dpcd(
+   link,
+   DP_SINK_COUNT,
+   irq_data->raw,
+   sizeof(union hpd_irq_data));
+   else {
+   /* Read 2 bytes at this location,... */
+   retval = core_link_read_dpcd(
+   link,
+   DP_SINK_COUNT_ESI,
+   irq_data->raw,
+   2);
+
+   if (retval != DC_OK)
+   return retval;
+
+   /* ... then read remaining 4 at the other location */
+   retval = core_link_read_dpcd(
+   link,
+   DP_LANE0_1_STATUS_ESI,
+   _data->raw[2],
+   4);
+   }
+
+   return retval;
 }
 
 static bool allow_hpd_rx_irq(const struct dc_link *link)
-- 
2.17.0

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[PATCH 20/34] drm/amd/display: Refactor audio programming

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  24 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   | 256 ++
 .../display/dc/dce110/dce110_hw_sequencer.h   |   4 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  16 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   5 +
 5 files changed, 163 insertions(+), 142 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2fa521812d23..a9485c10fd77 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1861,28 +1861,6 @@ static enum dc_status enable_link(
break;
}
 
-   if (pipe_ctx->stream_res.audio && status == DC_OK) {
-   struct dc *core_dc = pipe_ctx->stream->ctx->dc;
-   /* notify audio driver for audio modes of monitor */
-   struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;
-   unsigned int i, num_audio = 1;
-   for (i = 0; i < MAX_PIPES; i++) {
-   /*current_state not updated yet*/
-   if 
(core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
-   num_audio++;
-   }
-
-   
pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
-
-   if (num_audio == 1 && pp_smu != NULL && 
pp_smu->set_pme_wa_enable != NULL)
-   /*this is the first audio. apply the PME w/a in order 
to wake AZ from D3*/
-   pp_smu->set_pme_wa_enable(_smu->pp_smu);
-   /* un-mute audio */
-   /* TODO: audio should be per stream rather than per link */
-   pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-   pipe_ctx->stream_res.stream_enc, false);
-   }
-
return status;
 }
 
@@ -2415,6 +2393,8 @@ void core_link_enable_stream(
}
}
 
+   core_dc->hwss.enable_audio_stream(pipe_ctx);
+
/* turn off otg test pattern if enable */

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8301ca484099..6ffabd2c7625 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -972,19 +972,35 @@ void hwss_edp_backlight_control(
edp_receiver_ready_T9(link);
 }
 
-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
 {
-   struct dc_stream_state *stream = pipe_ctx->stream;
-   struct dc_link *link = stream->sink->link;
-   struct dc *dc = pipe_ctx->stream->ctx->dc;
+   struct dc *core_dc = pipe_ctx->stream->ctx->dc;
+   /* notify audio driver for audio modes of monitor */
+   struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;
+   unsigned int i, num_audio = 1;
 
-   if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
-   pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
-   pipe_ctx->stream_res.stream_enc);
+   if (pipe_ctx->stream_res.audio) {
+   for (i = 0; i < MAX_PIPES; i++) {
+   /*current_state not updated yet*/
+   if 
(core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
+   num_audio++;
+   }
 
-   if (dc_is_dp_signal(pipe_ctx->stream->signal))
-   pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
-   pipe_ctx->stream_res.stream_enc);
+   
pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
+
+   if (num_audio == 1 && pp_smu != NULL && 
pp_smu->set_pme_wa_enable != NULL)
+   /*this is the first audio. apply the PME w/a in order 
to wake AZ from D3*/
+   pp_smu->set_pme_wa_enable(_smu->pp_smu);
+   /* un-mute audio */
+   /* TODO: audio should be per stream rather than per link */
+   pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
+   pipe_ctx->stream_res.stream_enc, false);
+   }
+}
+
+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+{
+   struct dc *dc = pipe_ctx->stream->ctx->dc;
 
pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
pipe_ctx->stream_res.stream_enc, true);
@@ -1015,7 +1031,23 @@ void 

[PATCH 15/34] drm/amd/display: Fix indentation in dcn10 resource constructor

[Harry Wentland]

From: Hersen Wu 

Signed-off-by: Hersen Wu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index df5cb2d1d164..99c223bcad71 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1004,7 +1004,8 @@ static bool construct(
 
ctx->dc_bios->regs = _regs;
 
-   pool->base.res_cap = _cap;
+   pool->base.res_cap = _cap;
+
pool->base.funcs = _res_pool_funcs;
 
/*
-- 
2.17.0

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[PATCH 14/34] drm/amd/display: add config for sending VSIF

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c   | 1 +
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 3 ++-
 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h  | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 90f5a842360e..0483d33bcf6d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4645,6 +4645,7 @@ void set_freesync_on_stream(struct amdgpu_display_manager 
*dm,
aconnector->min_vfreq * 100;
config.max_refresh_in_uhz =
aconnector->max_vfreq * 100;
+   config.vsif_supported = true;
}
 
mod_freesync_build_vrr_params(dm->freesync_module,
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 769f46777a1d..e1688902a1b0 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -492,7 +492,7 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync 
*mod_freesync,
/* Check if Freesync is supported. Return if false. If true,
 * set the corresponding bit in the info packet
 */
-   if (!vrr->supported)
+   if (!vrr->supported || !vrr->send_vsif)
return;
 
if (dc_is_hdmi_signal(stream->signal)) {
@@ -634,6 +634,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
return;
 
in_out_vrr->state = in_config->state;
+   in_out_vrr->send_vsif = in_config->vsif_supported;
 
if (in_config->state == VRR_STATE_UNSUPPORTED) {
in_out_vrr->state = VRR_STATE_UNSUPPORTED;
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index 85c98afe9375..a0f32cde721c 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -78,6 +78,7 @@ enum mod_vrr_state {
 
 struct mod_freesync_config {
enum mod_vrr_state state;
+   bool vsif_supported;
bool ramping;
bool btr;
unsigned int min_refresh_in_uhz;
@@ -103,6 +104,7 @@ struct mod_vrr_params_fixed_refresh {
 
 struct mod_vrr_params {
bool supported;
+   bool send_vsif;
enum mod_vrr_state state;
 
uint32_t min_refresh_in_uhz;
-- 
2.17.0

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[PATCH 32/34] drm/amd/display: check if audio clk enable is applicable

[Harry Wentland]

From: Roman Li 

Fixing warning on dce10 with HDMI display.

Signed-off-by: Roman Li 
Reviewed-by: Charlene Liu 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index c0631756cd89..c0e813c7ddd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -720,7 +720,8 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
const uint32_t *content =
(const uint32_t *) _frame->avi.sb[0];
/*we need turn on clock before programming AFMT block*/
-   REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+   if (REG(AFMT_CNTL))
+   REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 
REG_WRITE(AFMT_AVI_INFO0, content[0]);
 
-- 
2.17.0

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[PATCH 21/34] drm/amd/display: HLG support

[Harry Wentland]

From: Vitaly Prosyak 

Low level calculation methods.

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h   |   2 +
 .../amd/display/modules/color/color_gamma.c   | 137 ++
 2 files changed, 139 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 22d113eca452..7a70a24ef736 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -378,6 +378,8 @@ enum dc_transfer_func_predefined {
TRANSFER_FUNCTION_PQ,
TRANSFER_FUNCTION_LINEAR,
TRANSFER_FUNCTION_UNITY,
+   TRANSFER_FUNCTION_HLG,
+   TRANSFER_FUNCTION_HLG12
 };
 
 struct dc_transfer_func {
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index e803b375e835..fa9a199d5639 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -131,6 +131,63 @@ static void compute_de_pq(struct fixed31_32 in_x, struct 
fixed31_32 *out_y)
dc_fixpt_div(dc_fixpt_one, m1));
 
 }
+
+/*de gamma, none linear to linear*/
+static void compute_hlg_oetf(struct fixed31_32 in_x, bool is_light0_12, struct 
fixed31_32 *out_y)
+{
+   struct fixed31_32 a;
+   struct fixed31_32 b;
+   struct fixed31_32 c;
+   struct fixed31_32 threshold;
+   struct fixed31_32 reference_white_level;
+
+   a = dc_fixpt_from_fraction(17883277, 1);
+   if (is_light0_12) {
+   /*light 0-12*/
+   b = dc_fixpt_from_fraction(28466892, 1);
+   c = dc_fixpt_from_fraction(55991073, 1);
+   threshold = dc_fixpt_one;
+   reference_white_level = dc_fixpt_half;
+   } else {
+   /*light 0-1*/
+   b = dc_fixpt_from_fraction(2372241, 1);
+   c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 
1));
+   threshold = dc_fixpt_from_fraction(1, 12);
+   reference_white_level = dc_fixpt_pow(dc_fixpt_from_fraction(3, 
1), dc_fixpt_half);
+   }
+   if (dc_fixpt_lt(threshold, in_x))
+   *out_y = dc_fixpt_add(c, dc_fixpt_mul(a, 
dc_fixpt_log(dc_fixpt_sub(in_x, b;
+   else
+   *out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, dc_fixpt_half), 
reference_white_level);
+}
+
+/*re gamma, linear to none linear*/
+static void compute_hlg_eotf(struct fixed31_32 in_x, bool is_light0_12, struct 
fixed31_32 *out_y)
+{
+   struct fixed31_32 a;
+   struct fixed31_32 b;
+   struct fixed31_32 c;
+   struct fixed31_32 reference_white_level;
+
+   a = dc_fixpt_from_fraction(17883277, 1);
+   if (is_light0_12) {
+   /*light 0-12*/
+   b = dc_fixpt_from_fraction(28466892, 1);
+   c = dc_fixpt_from_fraction(55991073, 1);
+   reference_white_level = dc_fixpt_from_fraction(4, 1);
+   } else {
+   /*light 0-1*/
+   b = dc_fixpt_from_fraction(2372241, 1);
+   c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 
1));
+   reference_white_level = dc_fixpt_from_fraction(1, 3);
+   }
+   if (dc_fixpt_lt(dc_fixpt_half, in_x))
+   *out_y = 
dc_fixpt_add(dc_fixpt_exp(dc_fixpt_div(dc_fixpt_sub(in_x, c), a)), b);
+   else
+   *out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, 
dc_fixpt_from_fraction(2, 1)), reference_white_level);
+}
+
+
 /* one-time pre-compute PQ values - only for sdr_white_level 80 */
 void precompute_pq(void)
 {
@@ -691,6 +748,48 @@ static void build_degamma(struct pwl_float_data_ex *curve,
}
 }
 
+static void build_hlg_degamma(struct pwl_float_data_ex *degamma,
+   uint32_t hw_points_num,
+   const struct hw_x_point *coordinate_x, bool is_light0_12)
+{
+   uint32_t i;
+
+   struct pwl_float_data_ex *rgb = degamma;
+   const struct hw_x_point *coord_x = coordinate_x;
+
+   i = 0;
+
+   while (i != hw_points_num + 1) {
+   compute_hlg_oetf(coord_x->x, is_light0_12, >r);
+   rgb->g = rgb->r;
+   rgb->b = rgb->r;
+   ++coord_x;
+   ++rgb;
+   ++i;
+   }
+}
+
+static void build_hlg_regamma(struct pwl_float_data_ex *regamma,
+   uint32_t hw_points_num,
+   const struct hw_x_point *coordinate_x, bool is_light0_12)
+{
+   uint32_t i;
+
+   struct pwl_float_data_ex *rgb = regamma;
+   const struct hw_x_point *coord_x = coordinate_x;
+
+   i = 0;
+
+   while (i != hw_points_num + 1) {
+   compute_hlg_eotf(coord_x->x, is_light0_12, >r);
+   rgb->g = rgb->r;
+  

[PATCH 28/34] drm/amd/display: DP YCbCr 4:2:0 support

[Harry Wentland]

From: Eric Bernstein 

Update MSA MISC1 bit 6 programming to handle YCbCr 4:2:0
and BT2020 cases.

Signed-off-by: Eric Bernstein 
Reviewed-by: Hersen Wu 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dcn10/dcn10_stream_encoder.c| 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index c928ee4cd382..147f61416fa5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -298,9 +298,20 @@ void enc1_stream_encoder_dp_set_stream_attribute(
}
 
misc1 = REG_READ(DP_MSA_MISC);
+   /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
+* When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to 
indicate the
+* Pixel Encoding/Colorimetry Format and that a Sink device shall 
ignore MISC1, bit 7,
+* and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become 
“don’t care”).
+*/
+   if ((crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
+   (output_color_space == COLOR_SPACE_2020_YCBCR) ||
+   (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 
||
+   (output_color_space == 
COLOR_SPACE_2020_RGB_LIMITEDRANGE))
+   misc1 = misc1 | 0x40;
+   else
+   misc1 = misc1 & ~0x40;
 
/* set color depth */
-
switch (crtc_timing->display_color_depth) {
case COLOR_DEPTH_666:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
@@ -354,7 +365,6 @@ void enc1_stream_encoder_dp_set_stream_attribute(
 
switch (output_color_space) {
case COLOR_SPACE_SRGB:
-   misc0 = misc0 | 0x0;
misc1 = misc1 & ~0x80; /* bit7 = 0*/
dynamic_range_rgb = 0; /*full range*/
break;
-- 
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[PATCH 18/34] drm/amd/display: Optimize DP_SINK_STATUS_ESI range read on HPD

[Harry Wentland]

From: Nikola Cornij 

DP_SINK_STATUS_ESI range data is not continual, but rather than
getting it in two AUX reads, it's quicker to read more bytes in a
AUX read and then memcpy the required fields (it's only 8 more
bytes to read).

Signed-off-by: Nikola Cornij 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 22 +++
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9b66634994e8..72a8a55565c8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1647,22 +1647,26 @@ static enum dc_status read_hpd_rx_irq_data(
irq_data->raw,
sizeof(union hpd_irq_data));
else {
-   /* Read 2 bytes at this location,... */
+   /* Read 14 bytes in a single read and then copy only the 
required fields.
+* This is more efficient than doing it in two separate AUX 
reads. */
+
+   uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
+
retval = core_link_read_dpcd(
link,
DP_SINK_COUNT_ESI,
-   irq_data->raw,
-   2);
+   tmp,
+   sizeof(tmp));
 
if (retval != DC_OK)
return retval;
 
-   /* ... then read remaining 4 at the other location */
-   retval = core_link_read_dpcd(
-   link,
-   DP_LANE0_1_STATUS_ESI,
-   _data->raw[2],
-   4);
+   irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - 
DP_SINK_COUNT_ESI];
+   irq_data->bytes.device_service_irq.raw = 
tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
+   irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - 
DP_SINK_COUNT_ESI];
+   irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - 
DP_SINK_COUNT_ESI];
+   irq_data->bytes.lane_status_updated.raw = 
tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
+   irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - 
DP_SINK_COUNT_ESI];
}
 
return retval;
-- 
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[PATCH 25/34] drm/amd/display: Set TMZ and DCC for secondary surface

[Harry Wentland]

From: Eric Bernstein 

Add register programming to support TMZ and DCC on
secondary surfaces.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 14 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  8 
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index d2ab78b35a7a..c28085be39ff 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -396,11 +396,15 @@ bool hubp1_program_surface_flip_and_addr(
if (address->grph_stereo.right_addr.quad_part == 0)
break;
 
-   REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+   REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_TMZ, address->tmz_surface,
PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
-   PRIMARY_META_SURFACE_TMZ_C, 
address->tmz_surface);
+   PRIMARY_META_SURFACE_TMZ_C, 
address->tmz_surface,
+   SECONDARY_SURFACE_TMZ, address->tmz_surface,
+   SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
+   SECONDARY_META_SURFACE_TMZ, 
address->tmz_surface,
+   SECONDARY_META_SURFACE_TMZ_C, 
address->tmz_surface);
 
if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 
@@ -459,9 +463,11 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,
uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
-   REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
+   REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, dcc_en,
-   PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
+   PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
+   SECONDARY_SURFACE_DCC_EN, dcc_en,
+   SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 }
 
 void hubp1_program_surface_config(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index af384034398f..d901d5092969 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -312,6 +312,12 @@
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, 
mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, 
mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, 
PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
+   HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, 
mask_sh),\
+   HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, 
mask_sh),\
+   HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, 
mask_sh),\
+   HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, 
mask_sh),\
+   HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, 
mask_sh),\
+   HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, 
SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, 
mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
@@ -489,6 +495,8 @@
type SECONDARY_META_SURFACE_TMZ_C;\
type PRIMARY_SURFACE_DCC_EN;\
type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
+   type SECONDARY_SURFACE_DCC_EN;\
+   type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
type DET_BUF_PLANE1_BASE_ADDRESS;\
type CROSSBAR_SRC_CB_B;\
type CROSSBAR_SRC_CR_R;\
-- 
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[PATCH 22/34] drm/amd/display: DP component depth 16 bpc

[Harry Wentland]

From: Eric Bernstein 

Add register programming to support 16bpc component
depth for DP.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 653b7b2efe2e..c928ee4cd382 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -319,6 +319,10 @@ void enc1_stream_encoder_dp_set_stream_attribute(
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_PIXEL_DEPTH_12BPC);
break;
+   case COLOR_DEPTH_161616:
+   REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+   DP_COMPONENT_PIXEL_DEPTH_16BPC);
+   break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_PIXEL_DEPTH_6BPC);
-- 
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[PATCH 19/34] drm/amd/display: Dynamic HDR metadata mem buffer

[Harry Wentland]

From: Krunoslav Kovac 

Basic framework:
- caps for reporting dynamic HDR metadata support
- allocation of frame buffer memory and storage

Signed-off-by: Krunoslav Kovac 
Reviewed-by: Tony Cheng 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h| 1 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index f01c6c1711d7..22d113eca452 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -68,6 +68,7 @@ struct dc_caps {
uint32_t max_planes;
uint32_t max_downscale_ratio;
uint32_t i2c_speed_in_khz;
+   uint32_t dmdata_alloc_size;
unsigned int max_cursor_size;
unsigned int max_video_width;
int linear_pitch_alignment;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 046e87aa699a..e2424c8eb20e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -65,6 +65,8 @@ struct dc_stream_state {
struct audio_info audio_info;
 
struct dc_info_packet hdr_static_metadata;
+   PHYSICAL_ADDRESS_LOC dmdata_address;
+
struct dc_transfer_func *out_transfer_func;
struct colorspace_transform gamut_remap_matrix;
struct dc_csc_transform csc_color_matrix;
-- 
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[PATCH 26/34] drm/amd/display: Destroy connector state on reset

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

When a DRM mode reset is called on resume, the connector state's
destructor is not called. This leaves a dangling reference on the CRTC
commit object, which was obtained by the connector state during commit
setup.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0483d33bcf6d..fcc3265c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2773,6 +2773,9 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector 
*connector)
struct dm_connector_state *state =
to_dm_connector_state(connector->state);
 
+   if (connector->state)
+   __drm_atomic_helper_connector_destroy_state(connector->state);
+
kfree(state);
 
state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -2783,8 +2786,7 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector 
*connector)
state->underscan_hborder = 0;
state->underscan_vborder = 0;
 
-   connector->state = >base;
-   connector->state->connector = connector;
+   __drm_atomic_helper_connector_reset(connector, >base);
}
 }
 
-- 
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[PATCH 13/34] drm/amd/display: add DPCD read for Sink ieee OUI

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 163c88779722..0acc14f572ef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2280,6 +2280,7 @@ static bool retrieve_link_cap(struct dc_link *link)
 {
uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
 
+   struct dp_device_vendor_id sink_id;
union down_stream_port_count down_strm_port_count;
union edp_configuration_cap edp_config_cap;
union dp_downstream_port_present ds_port = { 0 };
@@ -2369,6 +2370,17 @@ static bool retrieve_link_cap(struct dc_link *link)
>dpcd_caps.sink_count.raw,
sizeof(link->dpcd_caps.sink_count.raw));
 
+   /* read sink ieee oui */
+   core_link_read_dpcd(link,
+   DP_SINK_OUI,
+   (uint8_t *)(_id),
+   sizeof(sink_id));
+
+   link->dpcd_caps.sink_dev_id =
+   (sink_id.ieee_oui[0] << 16) +
+   (sink_id.ieee_oui[1] << 8) +
+   (sink_id.ieee_oui[2]);
+
/* Connectivity log: detection */
CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
 
-- 
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[PATCH 03/34] drm/amd/display: add register offset != 0 check.

[Harry Wentland]

From: Charlene Liu 

Signed-off-by: Charlene Liu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 0a6d483dc046..c0631756cd89 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -72,7 +72,8 @@ static void dce110_update_generic_info_packet(
uint32_t max_retries = 50;
 
/*we need turn on clock before programming AFMT block*/
-   REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+   if (REG(AFMT_CNTL))
+   REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 
if (REG(AFMT_VBI_PACKET_CONTROL1)) {
if (packet_index >= 8)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 58ebc9c3e17d..8301ca484099 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1004,9 +1004,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int 
option)
/*don't free audio if it is from retrain or internal disable 
stream*/
if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio 
== true) {
/*we have to dynamic arbitrate the audio endpoints*/
-   pipe_ctx->stream_res.audio = NULL;
/*we free the resource, need reset is_audio_acquired*/
update_audio_usage(>current_state->res_ctx, 
dc->res_pool, pipe_ctx->stream_res.audio, false);
+   pipe_ctx->stream_res.audio = NULL;
}
 
/* TODO: notify audio driver for if audio modes list changed
-- 
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[PATCH 06/34] drm/amd/display: upgrade scaler math

[Harry Wentland]

From: Dmytro Laktyushkin 

This change will allow the viewport overlap to apply to rotated/
mirrored surfaces. Viewport overlap results in extra pixels being
added to viewport allowing the first few pixels to be scaled as
if there is no cut-off(mpo or pipe split) and allows us to get matching
crc's between scaled split and unsplit outputs of the same thing.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 419 --
 1 file changed, 289 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6d0e869f0270..41385174578d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -522,13 +522,12 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
}
 }
 
-static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view 
*recout_skip)
+static void calculate_recout(struct pipe_ctx *pipe_ctx, struct rect 
*recout_full)
 {
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
const struct dc_stream_state *stream = pipe_ctx->stream;
struct rect surf_src = plane_state->src_rect;
struct rect surf_clip = plane_state->clip_rect;
-   int recout_full_x, recout_full_y;
bool pri_split = pipe_ctx->bottom_pipe &&
pipe_ctx->bottom_pipe->plane_state == 
pipe_ctx->plane_state;
bool sec_split = pipe_ctx->top_pipe &&
@@ -597,20 +596,22 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, 
struct view *recout_skip
}
}
/* Unclipped recout offset = stream dst offset + ((surf dst offset - 
stream surf_src offset)
-*  * 1/ stream scaling ratio) - (surf 
surf_src offset * 1/ full scl
-*  ratio)
+*  * 1/ stream scaling ratio) - (surf surf_src 
offset * 1/ full scl
+*  ratio)
 */
-   recout_full_x = stream->dst.x + (plane_state->dst_rect.x - 
stream->src.x)
+   recout_full->x = stream->dst.x + (plane_state->dst_rect.x - 
stream->src.x)
* stream->dst.width / stream->src.width 
-
surf_src.x * plane_state->dst_rect.width / 
surf_src.width
* stream->dst.width / stream->src.width;
-   recout_full_y = stream->dst.y + (plane_state->dst_rect.y - 
stream->src.y)
+   recout_full->y = stream->dst.y + (plane_state->dst_rect.y - 
stream->src.y)
* stream->dst.height / 
stream->src.height -
surf_src.y * plane_state->dst_rect.height / 
surf_src.height
* stream->dst.height / 
stream->src.height;
 
-   recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - 
recout_full_x;
-   recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - 
recout_full_y;
+   recout_full->width = plane_state->dst_rect.width
+   * stream->dst.width / stream->src.width;
+   recout_full->height = plane_state->dst_rect.height
+   * stream->dst.height / 
stream->src.height;
 }
 
 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
@@ -662,7 +663,7 @@ static void calculate_scaling_ratios(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 }
 
-static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view 
*recout_skip)
+static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct rect 
*recout_full)
 {
struct scaler_data *data = _ctx->plane_res.scl_data;
struct rect src = pipe_ctx->plane_state->src_rect;
@@ -680,15 +681,14 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx, struct view *r
flip_vert_scan_dir = true;
else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
flip_horz_scan_dir = true;
-   if (pipe_ctx->plane_state->horizontal_mirror)
-   flip_horz_scan_dir = !flip_horz_scan_dir;
 
if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
rect_swap_helper();
rect_swap_helper(>viewport_c);
rect_swap_helper(>viewport);
-   }
+   } else if (pipe_ctx->plane_state->horizontal_mirror)
+   flip_horz_scan_dir = !flip_horz_scan_dir;
 
/*
 * Init calculated according to formula:
@@ -708,127 +708,286 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 

[PATCH 12/34] drm/amd/display: replace msleep with udelay in fbc path

[Harry Wentland]

From: Roman Li 

FBC enabling and disabling path has msleep which leads to
BUG hit when called in atomic context, hence this patch
replaces msleeps with udelays appropriately.

Signed-off-by: Shirish S 
Signed-off-by: Roman Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 9150d2694450..e2994d337044 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -121,10 +121,10 @@ static void reset_lb_on_vblank(struct dc_context *ctx)
frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT);
 
 
-   for (retry = 100; retry > 0; retry--) {
+   for (retry = 1; retry > 0; retry--) {
if (frame_count != dm_read_reg(ctx, 
mmCRTC_STATUS_FRAME_COUNT))
break;
-   msleep(1);
+   udelay(10);
}
if (!retry)
dm_error("Frame count did not increase for 100ms.\n");
@@ -147,14 +147,14 @@ static void wait_for_fbc_state_changed(
uint32_t addr = mmFBC_STATUS;
uint32_t value;
 
-   while (counter < 10) {
+   while (counter < 1000) {
value = dm_read_reg(cp110->base.ctx, addr);
if (get_reg_field_value(
value,
FBC_STATUS,
FBC_ENABLE_STATUS) == enabled)
break;
-   msleep(10);
+   udelay(100);
counter++;
}
 
-- 
2.17.0

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[PATCH 01/34] drm/amd/display: Release fake sink

[Harry Wentland]

From: Mikita Lipski 

If connector doesn't have a sink, fake sink is created, but
never released as it assumed that its destroyed with the
stream it is used for. But now sink is released before the
stream maintaing refcount consistency.

This way we also avoid assigning anything to connector keeping
all the operation local.

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ++-
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 72f9a4682f50..90f5a842360e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2358,27 +2358,22 @@ decide_crtc_timing_for_drm_display_mode(struct 
drm_display_mode *drm_mode,
}
 }
 
-static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
+static struct dc_sink *
+create_fake_sink(struct amdgpu_dm_connector *aconnector)
 {
-   struct dc_sink *sink = NULL;
struct dc_sink_init_data sink_init_data = { 0 };
-
+   struct dc_sink *sink = NULL;
sink_init_data.link = aconnector->dc_link;
sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
 
sink = dc_sink_create(_init_data);
if (!sink) {
DRM_ERROR("Failed to create sink!\n");
-   return -ENOMEM;
+   return NULL;
}
-
sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
-   aconnector->fake_enable = true;
 
-   aconnector->dc_sink = sink;
-   aconnector->dc_link->local_sink = sink;
-
-   return 0;
+   return sink;
 }
 
 static void set_multisync_trigger_params(
@@ -2441,7 +2436,7 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
struct dc_stream_state *stream = NULL;
struct drm_display_mode mode = *drm_mode;
bool native_mode_found = false;
-
+   struct dc_sink *sink = NULL;
if (aconnector == NULL) {
DRM_ERROR("aconnector is NULL!\n");
return stream;
@@ -2459,15 +2454,18 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
return stream;
}
 
-   if (create_fake_sink(aconnector))
+   sink = create_fake_sink(aconnector);
+   if (!sink)
return stream;
+   } else {
+   sink = aconnector->dc_sink;
}
 
-   stream = dc_create_stream_for_sink(aconnector->dc_sink);
+   stream = dc_create_stream_for_sink(sink);
 
if (stream == NULL) {
DRM_ERROR("Failed to create stream for sink!\n");
-   return stream;
+   goto finish;
}
 
list_for_each_entry(preferred_mode, >base.modes, head) {
@@ -2506,12 +2504,15 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
fill_audio_info(
>audio_info,
drm_connector,
-   aconnector->dc_sink);
+   sink);
 
update_stream_signal(stream);
 
if (dm_state && dm_state->freesync_capable)
stream->ignore_msa_timing_param = true;
+finish:
+   if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
+   dc_sink_release(sink);
 
return stream;
 }
-- 
2.17.0

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[PATCH 00/34] DC Patches May 24, 2018

[Harry Wentland]

Important fixes here:
 * Audio endpoint fix (Charlene)
 * Fix mem leak (Leo)
 * Fix hotplug MST after unplug SST (Mikita)
 * Fix issues using udelay in FBC path (Roman)

Anthony Koo (4):
  drm/amd/display: Prefix event prints with ==Event==
  drm/amd/display: add DPCD read for Sink ieee OUI
  drm/amd/display: add config for sending VSIF
  drm/amd/display: Refactor audio programming

Aric Cyr (1):
  drm/amd/display: Default log masks should include all connectivity
events

Charlene Liu (2):
  drm/amd/display: add register offset != 0 check.
  drm/amd/display: Clean up submit_channel_request

Dmytro Laktyushkin (3):
  drm/amd/display: upgrade scaler math
  drm/amd/display: add dentist frequency to resource pool
  drm/amd/display: fix dscl_manual_ratio_init

Eric Bernstein (5):
  drm/amd/display: pass pipe_ctx straight to blank_pixel_data
  drm/amd/display: Add function to get optc active size
  drm/amd/display: DP component depth 16 bpc
  drm/amd/display: Set TMZ and DCC for secondary surface
  drm/amd/display: DP YCbCr 4:2:0 support

Hersen Wu (2):
  drm/amd/display: AUX will exit when HPD LOW detected
  drm/amd/display: Fix indentation in dcn10 resource constructor

Krunoslav Kovac (1):
  drm/amd/display: Dynamic HDR metadata mem buffer

Leo (Sunpeng) Li (1):
  drm/amd/display: Destroy connector state on reset

Mikita Lipski (3):
  drm/amd/display: Release fake sink
  drm/amd/display: Do not program interrupt status on disabled crtc
  drm/amd/display: Do not limit color depth to 8bpc

Nikola Cornij (3):
  drm/amd/display: Read DPCD link caps up to and including
DP_ADAPTER_CAP
  drm/amd/display: Read DP_SINK_COUNT_ESI range on HPD for DP 1.4
  drm/amd/display: Optimize DP_SINK_STATUS_ESI range read on HPD

Reza Amini (1):
  drm/amd/display: Prefix TIMING_STANDARD entries with DC_

Roman Li (2):
  drm/amd/display: replace msleep with udelay in fbc path
  drm/amd/display: check if audio clk enable is applicable

Samson Tam (1):
  drm/amd/display: decouple front and backend pgm using dpms_off as
backend enable flag

Tony Cheng (3):
  drm/amd/display: dal 3.1.45
  drm/amd/display: dal 3.1.46
  drm/amd/display: dal 3.1.47

Vitaly Prosyak (1):
  drm/amd/display: HLG support

Yasir Al Shekerchi (1):
  drm/amd/display: Added documentation for some DC interface functions

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  44 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c |   3 +
 .../drm/amd/display/dc/basics/fixpt31_32.c|   5 +
 .../drm/amd/display/dc/basics/log_helpers.c   |   2 +
 .../gpu/drm/amd/display/dc/basics/logger.c|  83 ++--
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 143 --
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  74 ++-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  53 ++-
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 425 --
 .../gpu/drm/amd/display/dc/core/dc_surface.c  |  11 +
 drivers/gpu/drm/amd/display/dc/dc.h   |   5 +-
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h |   2 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |  34 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   4 +
 drivers/gpu/drm/amd/display/dc/dc_types.h |  18 +-
 .../amd/display/dc/dce/dce_stream_encoder.c   |   6 +-
 .../amd/display/dc/dce110/dce110_compressor.c |   8 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   | 296 ++--
 .../display/dc/dce110/dce110_hw_sequencer.h   |   4 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h  |   6 +-
 .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |   8 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  14 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |   8 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  26 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  32 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   4 +
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |   3 +-
 .../display/dc/dcn10/dcn10_stream_encoder.c   |  18 +-
 .../drm/amd/display/dc/i2caux/aux_engine.c|  16 +
 .../drm/amd/display/dc/i2caux/aux_engine.h|   5 +-
 .../dc/i2caux/dce110/aux_engine_dce110.c  |  56 ++-
 .../gpu/drm/amd/display/dc/i2caux/engine.h|   3 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   1 +
 .../amd/display/dc/inc/hw/timing_generator.h  |   3 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   8 +-
 .../amd/display/include/ddc_service_types.h   |   3 +-
 .../gpu/drm/amd/display/include/fixed31_32.h  |   9 +
 .../amd/display/include/logger_interface.h|   2 +
 .../amd/display/modules/color/color_gamma.c   | 137 ++
 .../amd/display/modules/freesync/freesync.c   |   3 +-
 .../amd/display/modules/inc/mod_freesync.h|   2 +
 .../gpu/drm/amd/display/modules/stats/stats.c |   2 +-
 43 files changed, 1080 insertions(+), 512 deletions(-)

-- 
2.17.0

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[PATCH 08/34] drm/amd/display: Prefix event prints with ==Event==

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/modules/stats/stats.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index 3f7d47fdc367..fa0665d09075 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -240,7 +240,7 @@ void mod_stats_dump(struct mod_stats *mod_stats)
for (int i = 0; i < core_stats->entry_id; i++) {
if (event_index < core_stats->event_index &&
i == events[event_index].entry_id) {
-   DISPLAY_STATS("%s\n", events[event_index].event_string);
+   DISPLAY_STATS("==Event==%s\n", 
events[event_index].event_string);
event_index++;
} else if (time_index < core_stats->index &&
i == time[time_index].entry_id) {
-- 
2.17.0

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[PATCH 02/34] drm/amd/display: pass pipe_ctx straight to blank_pixel_data

[Harry Wentland]

From: Eric Bernstein 

Signed-off-by: Eric Bernstein 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 10 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  3 +--
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c40993a59ca4..b7ff538998b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2078,12 +2078,13 @@ static void update_dchubp_dpp(
 
 static void dcn10_blank_pixel_data(
struct dc *dc,
-   struct stream_resource *stream_res,
-   struct dc_stream_state *stream,
+   struct pipe_ctx *pipe_ctx,
bool blank)
 {
enum dc_color_space color_space;
struct tg_color black_color = {0};
+   struct stream_resource *stream_res = _ctx->stream_res;
+   struct dc_stream_state *stream = pipe_ctx->stream;
 
/* program otg blank color */
color_space = stream->output_color_space;
@@ -2142,8 +2143,7 @@ static void program_all_pipe_in_tree(
pipe_ctx->stream_res.tg->funcs->program_global_sync(
pipe_ctx->stream_res.tg);
 
-   dc->hwss.blank_pixel_data(dc, _ctx->stream_res,
-   pipe_ctx->stream, blank);
+   dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
}
 
if (pipe_ctx->plane_state != NULL) {
@@ -2262,7 +2262,7 @@ static void dcn10_apply_ctx_for_surface(
 
if (num_planes == 0) {
/* OTG blank before remove all front end */
-   dc->hwss.blank_pixel_data(dc, _pipe_to_program->stream_res, 
top_pipe_to_program->stream, true);
+   dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
}
 
/* Disconnect unused mpcc */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 63fc6c499789..52db80fbe987 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -160,8 +160,7 @@ struct hw_sequencer_funcs {
bool lock);
void (*blank_pixel_data)(
struct dc *dc,
-   struct stream_resource *stream_res,
-   struct dc_stream_state *stream,
+   struct pipe_ctx *pipe_ctx,
bool blank);
 
void (*set_bandwidth)(
-- 
2.17.0

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[PATCH 11/34] drm/amd/display: Add function to get optc active size

[Harry Wentland]

From: Eric Bernstein 

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 32 +++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  4 +++
 .../amd/display/dc/inc/hw/timing_generator.h  |  3 ++
 3 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index f2fbce0e3fc5..e6a3ade154b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -1257,6 +1257,37 @@ void optc1_read_otg_state(struct optc *optc1,
OPTC_UNDERFLOW_OCCURRED_STATUS, 
>underflow_occurred_status);
 }
 
+bool optc1_get_otg_active_size(struct timing_generator *optc,
+   uint32_t *otg_active_width,
+   uint32_t *otg_active_height)
+{
+   uint32_t otg_enabled;
+   uint32_t v_blank_start;
+   uint32_t v_blank_end;
+   uint32_t h_blank_start;
+   uint32_t h_blank_end;
+   struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+
+   REG_GET(OTG_CONTROL,
+   OTG_MASTER_EN, _enabled);
+
+   if (otg_enabled == 0)
+   return false;
+
+   REG_GET_2(OTG_V_BLANK_START_END,
+   OTG_V_BLANK_START, _blank_start,
+   OTG_V_BLANK_END, _blank_end);
+
+   REG_GET_2(OTG_H_BLANK_START_END,
+   OTG_H_BLANK_START, _blank_start,
+   OTG_H_BLANK_END, _blank_end);
+
+   *otg_active_width = v_blank_start - v_blank_end;
+   *otg_active_height = h_blank_start - h_blank_end;
+   return true;
+}
+
 void optc1_clear_optc_underflow(struct timing_generator *optc)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -1305,6 +1336,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs 
= {
.get_position = optc1_get_position,
.get_frame_count = optc1_get_vblank_counter,
.get_scanoutpos = optc1_get_crtc_scanoutpos,
+   .get_otg_active_size = optc1_get_otg_active_size,
.set_early_control = optc1_set_early_control,
/* used by enable_timing_synchronization. Not need for FPGA */
.wait_for_state = optc1_wait_for_state,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index c62052f46460..59ed272e0c49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -507,4 +507,8 @@ bool optc1_is_optc_underflow_occurred(struct 
timing_generator *optc);
 
 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool 
enable);
 
+bool optc1_get_otg_active_size(struct timing_generator *optc,
+   uint32_t *otg_active_width,
+   uint32_t *otg_active_height);
+
 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 69cb0a105300..af700c7dac50 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -156,6 +156,9 @@ struct timing_generator_funcs {
uint32_t *v_blank_end,
uint32_t *h_position,
uint32_t *v_position);
+   bool (*get_otg_active_size)(struct timing_generator *optc,
+   uint32_t *otg_active_width,
+   uint32_t *otg_active_height);
void (*set_early_control)(struct timing_generator *tg,
   uint32_t early_cntl);
void (*wait_for_state)(struct timing_generator *tg,
-- 
2.17.0

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[PATCH 09/34] drm/amd/display: Read DPCD link caps up to and including DP_ADAPTER_CAP

[Harry Wentland]

From: Nikola Cornij 

DP 1.4 compliance requires 16 bytes to be read when reading link caps,
i.e. it requires DP_ADAPTER_CAP to be included. Included it for all DP
versions because reading more than required won't fail.

Signed-off-by: Nikola Cornij 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cb376cf3228f..163c88779722 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2278,7 +2278,7 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, 
uint8_t *dpcd_data,
 
 static bool retrieve_link_cap(struct dc_link *link)
 {
-   uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1];
+   uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
 
union down_stream_port_count down_strm_port_count;
union edp_configuration_cap edp_config_cap;
-- 
2.17.0

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[PATCH 05/34] drm/amd/display: Clean up submit_channel_request

[Harry Wentland]

From: Charlene Liu 

Signed-off-by: Charlene Liu 
Reviewed-by: Vitaly Prosyak 
Acked-by: Harry Wentland 
---
 .../dc/i2caux/dce110/aux_engine_dce110.c  | 34 +--
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
index 5f47f6c007ac..90535787a461 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
@@ -198,27 +198,27 @@ static void submit_channel_request(
((request->type == AUX_TRANSACTION_TYPE_I2C) &&
((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
+   if (REG(AUXN_IMPCAL)) {
+   /* clear_aux_error */
+   REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
+   1,
+   0);
 
-   /* clear_aux_error */
-   REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
-   1,
-   0);
-
-   REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
-   1,
-   0);
-
-   /* force_default_calibrate */
-   REG_UPDATE_1BY1_2(AUXN_IMPCAL,
-   AUXN_IMPCAL_ENABLE, 1,
-   AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
+   REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
+   1,
+   0);
 
-   /* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles 
OVERRIDE? */
+   /* force_default_calibrate */
+   REG_UPDATE_1BY1_2(AUXN_IMPCAL,
+   AUXN_IMPCAL_ENABLE, 1,
+   AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
 
-   REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
-   1,
-   0);
+   /* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P 
toggles OVERRIDE? */
 
+   REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
+   1,
+   0);
+   }
/* set the delay and the number of bytes to write */
 
/* The length include
-- 
2.17.0

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Re: [PATCH 10/17] drm/amdgpu: add patch for fixing a known bug

[Boyuan Zhang]

On 2018-05-25 05:07 AM, Christian König wrote:

Am 24.05.2018 um 22:15 schrieb boyuan.zh...@amd.com:

From: Boyuan Zhang 

Allocate extra space in vcn jpeg ring buffer and store the jpeg ring 
patch


Signed-off-by: Boyuan Zhang 
---
  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 ++-
  1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

index dcd1a9a..2e4bd26 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -119,7 +119,8 @@ static int vcn_v1_0_sw_init(void *handle)
    ring = >vcn.ring_jpeg;
  sprintf(ring->name, "vcn_jpeg");
-    r = amdgpu_ring_init(adev, ring, 512, >vcn.irq, 0);
+    /* allocate extra dw in ring buffer for storing patch commands */
+    r = amdgpu_ring_init(adev, ring, 512 + 64, >vcn.irq, 0);
  if (r)
  return r;
  @@ -679,6 +680,30 @@ static int vcn_v1_0_start(struct amdgpu_device 
*adev)

  WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
  WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x0002L);
  +    /* set wptr to the extra allocated space in ring buffer */
+    ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+    ring->wptr += ring->max_dw * amdgpu_sched_hw_submission;
+
+    /* increase mask to allow to write to the extra space */
+    ring->buf_mask += 64 * 4;
+    ring->ptr_mask += 64 * 4;


Well that is rather ugly. buf_mask and ptr_mask are bit masks, you 
could set them to 0x but what you do here might not work as 
expected.


OK, so maybe setting both mask to 0x temporarily to allow 
writing to extra space as mu as needed, then later on set them back?





+
+    /* allocate extra space */
+    r = amdgpu_ring_alloc(ring, 64);
+    if (r) {
+    DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+  ring->idx, r);
+    return r;
+    }
+
+    /* copy patch commands to the extra space */
+    vcn_v1_0_jpeg_ring_set_patch_ring(ring);


Can't vcn_v1_0_jpeg_ring_set_patch_ring() just patch the command 
directly to he end of the ring buffer?


In other words why do we need to use amdgpu_ring_write() in 
vcn_v1_0_jpeg_ring_set_patch_ring()?


Christian.


Could you give me some more detailed info on how to do that? I thought 
amdgpu_ring_write() is the best way to write commands to the ring, what 
is the other/better way to do it in this case? Could you point me to a 
simple example how to write command directly to the end of ring (without 
ring_write)?


Thanks,
Boyuan




+
+    /* reset wptr and mask */
+    ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+    ring->buf_mask -= 0x100;
+    ring->ptr_mask -= 0x100;
+
  return 0;
  }




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[PATCH] drm/amdgpu: remove unnecessary scheduler entity for VCN

[Leo Liu]

It should be stateless, and no need for scheduler to take care

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 51 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 --
 2 files changed, 10 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e5d234c..6ceac17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -49,8 +49,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work);
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 {
-   struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
unsigned long bo_size;
const char *fw_name;
const struct common_firmware_header *hdr;
@@ -102,24 +100,6 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r;
}
 
-   ring = >vcn.ring_dec;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>sched, >vcn.entity_dec,
- rq, NULL);
-   if (r != 0) {
-   DRM_ERROR("Failed setting up VCN dec run queue.\n");
-   return r;
-   }
-
-   ring = >vcn.ring_enc[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>sched, >vcn.entity_enc,
- rq, NULL);
-   if (r != 0) {
-   DRM_ERROR("Failed setting up VCN enc run queue.\n");
-   return r;
-   }
-
return 0;
 }
 
@@ -129,10 +109,6 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 
kfree(adev->vcn.saved_bo);
 
-   drm_sched_entity_fini(>vcn.ring_dec.sched, >vcn.entity_dec);
-
-   drm_sched_entity_fini(>vcn.ring_enc[0].sched, 
>vcn.entity_enc);
-
amdgpu_bo_free_kernel(>vcn.vcpu_bo,
  >vcn.gpu_addr,
  (void **)>vcn.cpu_addr);
@@ -271,7 +247,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 }
 
 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
-  struct amdgpu_bo *bo, bool direct,
+  struct amdgpu_bo *bo,
   struct dma_fence **fence)
 {
struct amdgpu_device *adev = ring->adev;
@@ -299,19 +275,12 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring 
*ring,
}
ib->length_dw = 16;
 
-   if (direct) {
-   r = amdgpu_ib_schedule(ring, 1, ib, NULL, );
-   job->fence = dma_fence_get(f);
-   if (r)
-   goto err_free;
+   r = amdgpu_ib_schedule(ring, 1, ib, NULL, );
+   job->fence = dma_fence_get(f);
+   if (r)
+   goto err_free;
 
-   amdgpu_job_free(job);
-   } else {
-   r = amdgpu_job_submit(job, ring, >vcn.entity_dec,
- AMDGPU_FENCE_OWNER_UNDEFINED, );
-   if (r)
-   goto err_free;
-   }
+   amdgpu_job_free(job);
 
amdgpu_bo_fence(bo, f, false);
amdgpu_bo_unreserve(bo);
@@ -363,11 +332,11 @@ static int amdgpu_vcn_dec_get_create_msg(struct 
amdgpu_ring *ring, uint32_t hand
for (i = 14; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
 
-   return amdgpu_vcn_dec_send_msg(ring, bo, true, fence);
+   return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 }
 
 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t 
handle,
-  bool direct, struct dma_fence **fence)
+  struct dma_fence **fence)
 {
struct amdgpu_device *adev = ring->adev;
struct amdgpu_bo *bo = NULL;
@@ -389,7 +358,7 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t han
for (i = 6; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
 
-   return amdgpu_vcn_dec_send_msg(ring, bo, direct, fence);
+   return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 }
 
 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
@@ -403,7 +372,7 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, 
long timeout)
goto error;
}
 
-   r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, true, );
+   r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, );
if (r) {
DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
goto error;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2fd7db8..f934796 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -56,8 +56,6 @@ struct amdgpu_vcn {
struct amdgpu_ring  ring_dec;
struct amdgpu_ring  ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
struct amdgpu_irq_src   irq;
-   

Re: [PATCH 02/17] drm/amdgpu: add vcn jpeg ring

[Leo Liu]

On 05/25/2018 05:08 AM, Christian König wrote:

Am 24.05.2018 um 22:15 schrieb boyuan.zh...@amd.com:

From: Boyuan Zhang 

Add jpeg to amdgpu_vcn

Signed-off-by: Boyuan Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

index 2fd7db8..648f662 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -55,9 +55,11 @@ struct amdgpu_vcn {
  const struct firmware    *fw;    /* VCN firmware */
  struct amdgpu_ring    ring_dec;
  struct amdgpu_ring    ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+    struct amdgpu_ring    ring_jpeg;
  struct amdgpu_irq_src    irq;
  struct drm_sched_entity entity_dec;
  struct drm_sched_entity entity_enc;
+    struct drm_sched_entity entity_jpeg;


Why do you need the entity here? I thought the JPEG ring is stateles?
Right. We don't even need them for dec and enc. I think there is a 
copy-over from legacy UVD/VCE stuff with handles limitation, for that we 
need scheduler involved to send a destroy message.


I will come up a patch to remove those entities for dec and enc.

Regards,
Leo




Christian.


  unsigned    num_enc_rings;
  };




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Re: [PATCH v3 1/3] drm/prime: Iterate SG DMA addresses separately

[Robin Murphy]

On 30/04/18 18:59, Sinan Kaya wrote:

On 4/30/2018 9:54 AM, Robin Murphy wrote:

For dma_map_sg(), DMA API implementations are free to merge consecutive
segments into a single DMA mapping if conditions are suitable, thus the
resulting DMA addresses which drm_prime_sg_to_page_addr_arrays()
iterates over may be packed into fewer entries than sgt->nents implies.

The current implementation does not account for this, meaning that its
callers either have to reject the 0 < count < nents case or risk getting
bogus DMA addresses beyond the first segment. Fortunately this is quite
easy to handle without having to rejig structures to also store the
mapped count, since the total DMA length should still be equal to the
total buffer length. All we need is a second scatterlist cursor to
iterate through the DMA addresses independently of the page addresses.

Reviewed-by: Christian König 
Signed-off-by: Robin Murphy 
---


Much better

Tested-by: Sinan Kaya 

for the first two patches. (1/3 and 2/3)


Cheers Sinan.

Alex, Christian, David; is the AMD GPU tree the right target for these 
patches, or is there a wider audience I should consider resending them 
to? (before I forget about them again...)


Thanks,
Robin.
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Re: [PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Christian König]

Am 25.05.2018 um 11:51 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 05:35 PM, Christian König wrote:

Am 25.05.2018 um 10:23 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 03:54 PM, Christian König wrote:

Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom but not the underlying 
problem.


Somebody is accessing the page array when it should never be 
accessed.


If prime import as GTT bo by default(now it's CPU bo), it would 
happens

quickly when GTT sg bo creation rather than next cs validation.

Since ttm_sg_tt_init() only allocates gtt->ttm.dma_address if sg 
bo is

created, it would fail to access ttm->pages when ttm populate.


And exactly that's the problem, and imported BO should never populate.



current error happens in ttm populate from cs validation, the sg 
bo is

imported from exporter.



How did you manage to trigger this?


PRI_PRIME=1 with Unigine heaven.


Going to give that a try, but the last time I check that worked as 
expected.


FYI.
PRI_PRIME=1 glxinfo will not trigger that, but the game does.


Just tested and it works perfectly fine.

Is that on the closed stack or the open stack?


I used unified driver(latest 18.20 build) + drm-next kernel, installed 
as all open stack on A+A platform.

(issue was found by 18.20 build, all open stack(dkms driver))

BTW, How did you get the UMD? apt-get or build by yourself?


That's self build Mesa+libdrm.

Do you have the apt url and/or package versions at hand you used for the 
test?


Christian.




Jerry


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Re: GPU hang trying to run OpenCL kernels on x86_64

[Luís Mendes]

I've just tested Ubuntu 18.04 with kernel 4.17-rc6 using libdrm-2.4.92 and
mesa-18.1.0.
Now both sdma0 and sdma1 timeout as can be seen in the attached logs.

~agd5f -b drm-next-4.18 doesn't improve also.

I have also tried amdgpu-pro 18.20 both on Ubuntu 18.04 and 16.04, but no
improvements.
I have tried amdgpu-pro 18.10 and 17.50 and also no improvements.

./amdgpu-pro-install -opencl=legacy,pal --headless

On Thu, May 24, 2018 at 11:18 AM, Luís Mendes 
wrote:

> Additional update...
>
> I was able to boot and enter X by installing an NVIDIA GTX 1050 Ti as the
> primary display card and using an AMD RX 550 as the secondary card on the
> Tyan S7025 with the same Ubuntu 18.04 and the same Linux kernel 4.17-rc6.
> However once I try to run an OpenCL kernel on RX 550 I get a sdma1 timeout
> and the GPU hangs, which likely what is happening when I boot with RX 550
> as the single GPU card on the system.
>
> This means it is not an issue introduced in 4.17-rc6, it just means that I
> didn't notice the effect of the system with the two GPUs vs system with
> single AMD GPU.
>
> The dmesg log follows attached.
>
> Luís
>
> On Thu, May 24, 2018 at 10:13 AM, Luís Mendes 
> wrote:
>
>> Hi Michel,
>>
>> I also work as a researcher at a university and we are considering buying
>> AMD cards to do OpenCL computations for numerical modelling, but currently
>> I am unable to give a try at the AMD cards I have at home.
>> I couldn't find any working driver for them... also amdgpu-pro drivers
>> don't work, or at least I have been unable to make them work.
>>
>> Regards,
>> Luís
>>
>> On Thu, May 24, 2018 at 10:01 AM, Luís Mendes 
>> wrote:
>>
>>> Hi Michel,
>>>
>>> So summarizing with Linux kernel 4.17-rc6 on Ubuntu 18.04 using AMD RX
>>> 460/RX 550 I am not able to enter X.
>>> The same system with AMD Radeon R7 240 not only enters X as also runs
>>> the OpenCL kernel that RX 460 / RX 550 are unable to run for all the
>>> kernels that I have tested.
>>> Could this also be a Mesa issue, regarding OpenCL on RX 460?
>>>
>>> Regards,
>>> Luís
>>>
>>> On Thu, May 24, 2018 at 9:55 AM, Luís Mendes 
>>> wrote:
>>>
 Hi Michel,

 I will have to check previous rc releases of 4.17 to see if it wasn't
 already happening, before trying any possible git bisect.
 As an update I can say that an AMD Radeon R7 240 works fine on the same
 system with the same kernel and I am able to run the OpenCL kernels, that I
 couldn't with RX 460/RX 550.

 Regards,
 Luís

 On Thu, May 24, 2018 at 9:30 AM, Michel Dänzer 
 wrote:

> On 2018-05-24 12:06 AM, Luís Mendes wrote:
> > I've tried Linux 4.17-rc6 with Ubuntu 18.04 on Tyan S7002 and I am
> not even
> > able see lightdm/gdm3 as system hangs when starting X.
> > Having SR-IOV enabled or disabled makes no difference.
> > Tested with AMD RX 460.
> > When X is supposed to start the system hangs and only a rectangular
> region
> > on the top left corner screen remains with console text messages
> from the
> > boot process while the remaining of the screen is just black. I am
> unable
> > to do anything with the keyboard, switching to console does not work,
> > ctrl-alt-del also doesn't work. I've to do a cold reset.
>
> Can you isolate which change introduced this new issue with git bisect?
>
>
> --
> Earthling Michel Dänzer   |
> http://www.amd.com
> Libre software enthusiast | Mesa and X
> developer
>


>>>
>>
>
[0.00] Linux version 4.17.0-rc6 (lpnm@lpnm-empty) (gcc version 7.3.0 
(Ubuntu 7.3.0-16ubuntu3)) #1 SMP Mon May 21 00:03:25 WEST 2018
[0.00] Command line: BOOT_IMAGE=/boot/vmlinuz-4.17.0-rc6 
root=UUID=1fd09015-7f74-4838-bbbd-00bb887c940f ro quiet splash vt.handoff=1
[0.00] KERNEL supported cpus:
[0.00]   Intel GenuineIntel
[0.00]   AMD AuthenticAMD
[0.00]   Centaur CentaurHauls
[0.00] x86/fpu: x87 FPU will use FXSAVE
[0.00] e820: BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x0009d3ff] usable
[0.00] BIOS-e820: [mem 0x0009d400-0x0009] reserved
[0.00] BIOS-e820: [mem 0x000e-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0xbf78] usable
[0.00] BIOS-e820: [mem 0xbf79-0xbf79dfff] ACPI data
[0.00] BIOS-e820: [mem 0xbf79e000-0xbf7c] ACPI NVS
[0.00] BIOS-e820: [mem 0xbf7d-0xbf7d] reserved
[0.00] BIOS-e820: [mem 0xbf7ec000-0xbfff] reserved
[0.00] BIOS-e820: [mem 0xe000-0xefff] reserved
[0.00] BIOS-e820: [mem 

Re: [PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Zhang, Jerry (Junwei)]

On 05/25/2018 05:35 PM, Christian König wrote:

Am 25.05.2018 um 10:23 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 03:54 PM, Christian König wrote:

Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 02:44 PM, Christian König wrote:

NAK, that probably just fixed the symptom but not the underlying problem.

Somebody is accessing the page array when it should never be accessed.


If prime import as GTT bo by default(now it's CPU bo), it would happens
quickly when GTT sg bo creation rather than next cs validation.

Since ttm_sg_tt_init() only allocates gtt->ttm.dma_address if sg bo is
created, it would fail to access ttm->pages when ttm populate.


And exactly that's the problem, and imported BO should never populate.



current error happens in ttm populate from cs validation, the sg bo is
imported from exporter.



How did you manage to trigger this?


PRI_PRIME=1 with Unigine heaven.


Going to give that a try, but the last time I check that worked as expected.


FYI.
PRI_PRIME=1 glxinfo will not trigger that, but the game does.


Just tested and it works perfectly fine.

Is that on the closed stack or the open stack?


I used unified driver(latest 18.20 build) + drm-next kernel, installed as all 
open stack on A+A platform.

(issue was found by 18.20 build, all open stack(dkms driver))

BTW, How did you get the UMD? apt-get or build by yourself?


Jerry



Christian.



Jerry



Thanks,
Christian.



Regards,
Jerry



Regards,
Christian.

Am 25.05.2018 um 07:41 schrieb Junwei Zhang:

[  632.679861] BUG: unable to handle kernel NULL pointer dereference at
(null)
[  632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]

[  632.680011] Call Trace:
[  632.680082]  amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[  632.680092]  ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[  632.680098]  amdttm_tt_bind+0x52/0x60 [amdttm]
[  632.680106]  ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[  632.680112]  ? find_next_bit+0xb/0x10
[  632.680119]  amdttm_bo_validate+0x11d/0x130 [amdttm]
[  632.680176]  amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[  632.680232]  amdgpu_cs_validate+0x41/0x270 [amdgpu]
[  632.680288]  amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[  632.680343]  amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[  632.680401]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680416]  drm_ioctl_kernel+0x6b/0xb0 [drm]
[  632.680431]  drm_ioctl+0x3e4/0x450 [drm]
[  632.680485]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680537]  amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[  632.680542]  do_vfs_ioctl+0xa4/0x600
[  632.680546]  ? SyS_futex+0x7f/0x180
[  632.680549]  SyS_ioctl+0x79/0x90
[  632.680554]  entry_SYSCALL_64_fastpath+0x24/0xab

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct
ttm_buffer_object *bo,
  gtt->ttm.ttm.func = _backend_func;
  /* allocate space for the uninitialized page entries */
-if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
  kfree(gtt);
  return NULL;
  }







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Re: [PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Christian König]

Am 25.05.2018 um 10:23 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 03:54 PM, Christian König wrote:

Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom but not the underlying 
problem.


Somebody is accessing the page array when it should never be accessed.


If prime import as GTT bo by default(now it's CPU bo), it would happens
quickly when GTT sg bo creation rather than next cs validation.

Since ttm_sg_tt_init() only allocates gtt->ttm.dma_address if sg bo is
created, it would fail to access ttm->pages when ttm populate.


And exactly that's the problem, and imported BO should never populate.



current error happens in ttm populate from cs validation, the sg bo is
imported from exporter.



How did you manage to trigger this?


PRI_PRIME=1 with Unigine heaven.


Going to give that a try, but the last time I check that worked as 
expected.


FYI.
PRI_PRIME=1 glxinfo will not trigger that, but the game does.


Just tested and it works perfectly fine.

Is that on the closed stack or the open stack?

Christian.



Jerry



Thanks,
Christian.



Regards,
Jerry



Regards,
Christian.

Am 25.05.2018 um 07:41 schrieb Junwei Zhang:
[  632.679861] BUG: unable to handle kernel NULL pointer 
dereference at (null)

[  632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]

[  632.680011] Call Trace:
[  632.680082]  amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[  632.680092]  ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[  632.680098]  amdttm_tt_bind+0x52/0x60 [amdttm]
[  632.680106]  ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[  632.680112]  ? find_next_bit+0xb/0x10
[  632.680119]  amdttm_bo_validate+0x11d/0x130 [amdttm]
[  632.680176]  amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[  632.680232]  amdgpu_cs_validate+0x41/0x270 [amdgpu]
[  632.680288]  amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[  632.680343]  amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[  632.680401]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680416]  drm_ioctl_kernel+0x6b/0xb0 [drm]
[  632.680431]  drm_ioctl+0x3e4/0x450 [drm]
[  632.680485]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680537]  amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[  632.680542]  do_vfs_ioctl+0xa4/0x600
[  632.680546]  ? SyS_futex+0x7f/0x180
[  632.680549]  SyS_ioctl+0x79/0x90
[  632.680554]  entry_SYSCALL_64_fastpath+0x24/0xab

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt 
*amdgpu_ttm_tt_create(struct

ttm_buffer_object *bo,
  gtt->ttm.ttm.func = _backend_func;
  /* allocate space for the uninitialized page entries */
-    if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+    if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
  kfree(gtt);
  return NULL;
  }






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Re: [PATCH 02/17] drm/amdgpu: add vcn jpeg ring

[Christian König]

Am 24.05.2018 um 22:15 schrieb boyuan.zh...@amd.com:

From: Boyuan Zhang 

Add jpeg to amdgpu_vcn

Signed-off-by: Boyuan Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2fd7db8..648f662 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -55,9 +55,11 @@ struct amdgpu_vcn {
const struct firmware   *fw;/* VCN firmware */
struct amdgpu_ring  ring_dec;
struct amdgpu_ring  ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+   struct amdgpu_ring  ring_jpeg;
struct amdgpu_irq_src   irq;
struct drm_sched_entity entity_dec;
struct drm_sched_entity entity_enc;
+   struct drm_sched_entity entity_jpeg;


Why do you need the entity here? I thought the JPEG ring is stateles?

Christian.


unsignednum_enc_rings;
  };
  


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Re: [PATCH 10/17] drm/amdgpu: add patch for fixing a known bug

[Christian König]

Am 24.05.2018 um 22:15 schrieb boyuan.zh...@amd.com:

From: Boyuan Zhang 

Allocate extra space in vcn jpeg ring buffer and store the jpeg ring patch

Signed-off-by: Boyuan Zhang 
---
  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 ++-
  1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index dcd1a9a..2e4bd26 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -119,7 +119,8 @@ static int vcn_v1_0_sw_init(void *handle)
  
  	ring = >vcn.ring_jpeg;

sprintf(ring->name, "vcn_jpeg");
-   r = amdgpu_ring_init(adev, ring, 512, >vcn.irq, 0);
+   /* allocate extra dw in ring buffer for storing patch commands */
+   r = amdgpu_ring_init(adev, ring, 512 + 64, >vcn.irq, 0);
if (r)
return r;
  
@@ -679,6 +680,30 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x0002L);
  
+	/* set wptr to the extra allocated space in ring buffer */

+   ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+   ring->wptr += ring->max_dw * amdgpu_sched_hw_submission;
+
+   /* increase mask to allow to write to the extra space */
+   ring->buf_mask += 64 * 4;
+   ring->ptr_mask += 64 * 4;


Well that is rather ugly. buf_mask and ptr_mask are bit masks, you could 
set them to 0x but what you do here might not work as expected.



+
+   /* allocate extra space */
+   r = amdgpu_ring_alloc(ring, 64);
+   if (r) {
+   DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+ ring->idx, r);
+   return r;
+   }
+
+   /* copy patch commands to the extra space */
+   vcn_v1_0_jpeg_ring_set_patch_ring(ring);


Can't vcn_v1_0_jpeg_ring_set_patch_ring() just patch the command 
directly to he end of the ring buffer?


In other words why do we need to use amdgpu_ring_write() in 
vcn_v1_0_jpeg_ring_set_patch_ring()?


Christian.


+
+   /* reset wptr and mask */
+   ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+   ring->buf_mask -= 0x100;
+   ring->ptr_mask -= 0x100;
+
return 0;
  }
  


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Re: [PATCH 1/2] drm/amdgpu: add kernel doc for amdgpu_object.c

[Christian König]

With Alex comments addressed the series is Reviewed-by: Christian König 
.


Regards,
Christian.

Am 24.05.2018 um 22:35 schrieb Samuel Li:

v2: Add a DOC section and some more clarification.
Signed-off-by: Samuel Li 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 266 +
  1 file changed, 266 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6a9e46a..c3a7b11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -38,6 +38,18 @@
  #include "amdgpu_trace.h"
  #include "amdgpu_amdkfd.h"
  
+/**

+ * DOC: amdgpu_object
+ *
+ * This defines the interfaces to operate on an _bo buffer object. The
+ * driver provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these
+ * interfaces to create/destroy/set buffer object which are then managed by
+ * the kernel TTM memory manager.
+ * The interfaces are also used internally by kernel clients, including gfx,
+ * uvd, etc.
+ *
+ */
+
  static bool amdgpu_need_backup(struct amdgpu_device *adev)
  {
if (adev->flags & AMD_IS_APU)
@@ -73,6 +85,15 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object 
*tbo)
kfree(bo);
  }
  
+/**

+ * amdgpu_ttm_bo_is_amdgpu_bo - check if the buffer object is an _bo
+ * @bo: buffer object to be checked
+ *
+ * Uses destroy function associated with the object to determine if this is
+ * an _bo.
+ *
+ * Returns true if the object belongs to _bo, false if not.
+ */
  bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  {
if (bo->destroy == _ttm_bo_destroy)
@@ -80,6 +101,14 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object 
*bo)
return false;
  }
  
+/**

+ * amdgpu_ttm_placement_from_domain - set buffer's placement
+ * @abo: _bo buffer object whose placement is to be set
+ * @domain: requested domain
+ *
+ * Sets buffer's placement according to requested domain and the buffer's
+ * flags.
+ */
  void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
@@ -498,6 +527,19 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device 
*adev,
return r;
  }
  
+/**

+ * amdgpu_bo_create - create an _bo buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @bo_ptr: pointer to the buffer object pointer
+ *
+ * Creates an _bo buffer object; and if requested, also creates a
+ * shadow object.
+ * Shadow object is used to backup the original buffer object, and is always
+ * in GTT.
+ *
+ * Returns 0 for success or a negative error code on failure.
+ */
  int amdgpu_bo_create(struct amdgpu_device *adev,
 struct amdgpu_bo_param *bp,
 struct amdgpu_bo **bo_ptr)
@@ -527,6 +569,20 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
return r;
  }
  
+/**

+ * amdgpu_bo_backup_to_shadow - Backs up an _bo buffer object
+ * @adev: amdgpu device object
+ * @ring: amdgpu_ring for the engine handling the buffer operations
+ * @bo: _bo buffer to be backed up
+ * @resv: reservation object with embedded fence
+ * @fence: dma_fence associated with the operation
+ * @direct: whether to submit the job directly
+ *
+ * Copies an _bo buffer object to its shadow object.
+ * Not used for now.
+ *
+ * Returns 0 for success or a negative error code on failure.
+ */
  int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
   struct amdgpu_ring *ring,
   struct amdgpu_bo *bo,
@@ -559,6 +615,17 @@ int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
return r;
  }
  
+/**

+ * amdgpu_bo_validate - validate an _bo buffer object
+ * @bo: pointer to the buffer object
+ *
+ * Sets placement according to domain; and changes placement and caching
+ * policy of the buffer object according to the placement.
+ * This is used for validating shadow bos.  It calls ttm_bo_validate() to
+ * make sure the buffer is resident where it needs to be.
+ *
+ * Returns 0 for success or a negative error code on failure.
+ */
  int amdgpu_bo_validate(struct amdgpu_bo *bo)
  {
struct ttm_operation_ctx ctx = { false, false };
@@ -581,6 +648,21 @@ int amdgpu_bo_validate(struct amdgpu_bo *bo)
return r;
  }
  
+/**

+ * amdgpu_bo_restore_from_shadow - restore an _bo buffer object
+ * @adev: amdgpu device object
+ * @ring: amdgpu_ring for the engine handling the buffer operations
+ * @bo: _bo buffer to be restored
+ * @resv: reservation object with embedded fence
+ * @fence: dma_fence associated with the operation
+ * @direct: whether to submit the job directly
+ *
+ * Copies a buffer object's shadow content back to the object.
+ * This is used for recovering a buffer from its shadow in case of a gpu
+ * reset where vram context may be lost.
+ *
+ * Returns 0 for success or 

Re: [PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Zhang, Jerry (Junwei)]

On 05/25/2018 03:54 PM, Christian König wrote:

Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 02:44 PM, Christian König wrote:

NAK, that probably just fixed the symptom but not the underlying problem.

Somebody is accessing the page array when it should never be accessed.


If prime import as GTT bo by default(now it's CPU bo), it would happens
quickly when GTT sg bo creation rather than next cs validation.

Since ttm_sg_tt_init() only allocates gtt->ttm.dma_address if sg bo is
created, it would fail to access ttm->pages when ttm populate.


And exactly that's the problem, and imported BO should never populate.



current error happens in ttm populate from cs validation, the sg bo is
imported from exporter.



How did you manage to trigger this?


PRI_PRIME=1 with Unigine heaven.


Going to give that a try, but the last time I check that worked as expected.


FYI.
PRI_PRIME=1 glxinfo will not trigger that, but the game does.

Jerry



Thanks,
Christian.



Regards,
Jerry



Regards,
Christian.

Am 25.05.2018 um 07:41 schrieb Junwei Zhang:

[  632.679861] BUG: unable to handle kernel NULL pointer dereference at (null)
[  632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]

[  632.680011] Call Trace:
[  632.680082]  amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[  632.680092]  ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[  632.680098]  amdttm_tt_bind+0x52/0x60 [amdttm]
[  632.680106]  ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[  632.680112]  ? find_next_bit+0xb/0x10
[  632.680119]  amdttm_bo_validate+0x11d/0x130 [amdttm]
[  632.680176]  amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[  632.680232]  amdgpu_cs_validate+0x41/0x270 [amdgpu]
[  632.680288]  amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[  632.680343]  amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[  632.680401]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680416]  drm_ioctl_kernel+0x6b/0xb0 [drm]
[  632.680431]  drm_ioctl+0x3e4/0x450 [drm]
[  632.680485]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680537]  amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[  632.680542]  do_vfs_ioctl+0xa4/0x600
[  632.680546]  ? SyS_futex+0x7f/0x180
[  632.680549]  SyS_ioctl+0x79/0x90
[  632.680554]  entry_SYSCALL_64_fastpath+0x24/0xab

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct
ttm_buffer_object *bo,
  gtt->ttm.ttm.func = _backend_func;
  /* allocate space for the uninitialized page entries */
-if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
  kfree(gtt);
  return NULL;
  }





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Re: [PATCH] gpu: Consistently use octal not symbolic permissions

[Joe Perches]

On Fri, 2018-05-25 at 09:41 +0300, Jani Nikula wrote:
> On Thu, 24 May 2018, Joe Perches  wrote:
> > There is currently a mixture of octal and symbolic permissions uses
> > in files in drivers/gpu/drm and one file in drivers/gpu.
> > 
> > There are ~270 existing octal uses and ~115 S_ uses.
> > 
> > Convert all the S_ symbolic permissions to their octal equivalents
> > as using octal and not symbolic permissions is preferred by many as more
> > readable.
> > 
> > see: https://lkml.org/lkml/2016/8/2/1945
> > 
> > Done with automated conversion via:
> > $ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 
> > 
> > Miscellanea:
> > 
> > o Wrapped modified multi-line calls to a single line where appropriate
> > o Realign modified multi-line calls to open parenthesis
> > o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
> >   debug permission for "reset" - perhaps that should be modified
> > Signed-off-by: Joe Perches 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 
> > +++---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
> >  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
> >  drivers/gpu/drm/drm_debugfs.c  |  6 +-
> >  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
> >  drivers/gpu/drm/drm_sysfs.c|  2 +-
> >  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
> >  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
> >  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
> >  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
> >  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
> 
> Please send at least i915 changes separately. There's zero reason to
> make our lives harder for this change.

The idea is to avoid unnecessary multiple patches for
individual trees.

But you could do that via something like:

$ git am --include='drivers/gpu/drm/i915/*' 

cheers, Joe

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Re: [PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Christian König]

Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):

On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom but not the underlying 
problem.


Somebody is accessing the page array when it should never be accessed.


If prime import as GTT bo by default(now it's CPU bo), it would 
happens quickly when GTT sg bo creation rather than next cs validation.


Since ttm_sg_tt_init() only allocates gtt->ttm.dma_address if sg bo is 
created, it would fail to access ttm->pages when ttm populate.


And exactly that's the problem, and imported BO should never populate.



current error happens in ttm populate from cs validation, the sg bo is 
imported from exporter.




How did you manage to trigger this?


PRI_PRIME=1 with Unigine heaven.


Going to give that a try, but the last time I check that worked as expected.

Thanks,
Christian.



Regards,
Jerry



Regards,
Christian.

Am 25.05.2018 um 07:41 schrieb Junwei Zhang:
[  632.679861] BUG: unable to handle kernel NULL pointer dereference 
at (null)

[  632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]

[  632.680011] Call Trace:
[  632.680082]  amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[  632.680092]  ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[  632.680098]  amdttm_tt_bind+0x52/0x60 [amdttm]
[  632.680106]  ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[  632.680112]  ? find_next_bit+0xb/0x10
[  632.680119]  amdttm_bo_validate+0x11d/0x130 [amdttm]
[  632.680176]  amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[  632.680232]  amdgpu_cs_validate+0x41/0x270 [amdgpu]
[  632.680288]  amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[  632.680343]  amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[  632.680401]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680416]  drm_ioctl_kernel+0x6b/0xb0 [drm]
[  632.680431]  drm_ioctl+0x3e4/0x450 [drm]
[  632.680485]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680537]  amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[  632.680542]  do_vfs_ioctl+0xa4/0x600
[  632.680546]  ? SyS_futex+0x7f/0x180
[  632.680549]  SyS_ioctl+0x79/0x90
[  632.680554]  entry_SYSCALL_64_fastpath+0x24/0xab

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct
ttm_buffer_object *bo,
  gtt->ttm.ttm.func = _backend_func;
  /* allocate space for the uninitialized page entries */
-    if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+    if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
  kfree(gtt);
  return NULL;
  }




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Re: [PATCH xf86-video-amdgpu 00/13] Enabling Color Management - Round 2

[Michel Dänzer]

On 2018-05-24 10:29 PM, Leo Li wrote:
> On 2018-05-18 04:10 AM, Michel Dänzer wrote:
>> On 2018-05-17 11:43 PM, Leo Li wrote:
>>> On 2018-05-16 01:06 PM, Michel Dänzer wrote:
 On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
>
> 3. The three color management properties (Degamma LUT, Color
> Transform Matrix
>  (CTM), and Gamma LUT) are hard-coded into the DDX driver, to be
> listed (as
>  disabled) regardless of whether a CRTC is attached on the output,
> or whether
>  the kernel driver supports it.
>
>   * If kernel driver does not support color management, the
> properties will
>     remain disabled. A `xrandr --set` will then error.

 Is it really useful to expose these properties to clients if the kernel
 doesn't support them?

>>>
>>> I left them exposed mainly for simplicity. I can see how it would
>>> confuse a client.
>>>
>>> It should be simpler to hide these properties once the color property
>>> IDs are cached somewhere (maybe on the AMDGPUInfo struct?)
>>
>> drmmode_crtc_private_rec seems better.
>>
> 
> Doesn't that mean we're caching duplicate DRM property IDs on each CRTC
> object? I think we only need to cache one copy.
> 
> Looking at DRM code, the IDs identify DRM property "types", not the
> actual property data, and are created during kernel driver load. Storing
> one copy is enough, since the types are the same regardless of CRTC.
> 
> I was thinking we can fetch these id's in drmmode_pre_init because of
> that, but I'm not sure of the implications. Wouldn't that be better?

If the IDs are the same for all CRTCs, they should be stored in struct
drmmode_rec.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Zhang, Jerry (Junwei)]

On 05/25/2018 02:44 PM, Christian König wrote:

NAK, that probably just fixed the symptom but not the underlying problem.

Somebody is accessing the page array when it should never be accessed.


If prime import as GTT bo by default(now it's CPU bo), it would happens quickly 
when GTT sg bo creation rather than next cs validation.


Since ttm_sg_tt_init() only allocates gtt->ttm.dma_address if sg bo is created, 
it would fail to access ttm->pages when ttm populate.


current error happens in ttm populate from cs validation, the sg bo is imported 
from exporter.




How did you manage to trigger this?


PRI_PRIME=1 with Unigine heaven.

Regards,
Jerry



Regards,
Christian.

Am 25.05.2018 um 07:41 schrieb Junwei Zhang:

[  632.679861] BUG: unable to handle kernel NULL pointer dereference at (null)
[  632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]

[  632.680011] Call Trace:
[  632.680082]  amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[  632.680092]  ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[  632.680098]  amdttm_tt_bind+0x52/0x60 [amdttm]
[  632.680106]  ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[  632.680112]  ? find_next_bit+0xb/0x10
[  632.680119]  amdttm_bo_validate+0x11d/0x130 [amdttm]
[  632.680176]  amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[  632.680232]  amdgpu_cs_validate+0x41/0x270 [amdgpu]
[  632.680288]  amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[  632.680343]  amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[  632.680401]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680416]  drm_ioctl_kernel+0x6b/0xb0 [drm]
[  632.680431]  drm_ioctl+0x3e4/0x450 [drm]
[  632.680485]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680537]  amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[  632.680542]  do_vfs_ioctl+0xa4/0x600
[  632.680546]  ? SyS_futex+0x7f/0x180
[  632.680549]  SyS_ioctl+0x79/0x90
[  632.680554]  entry_SYSCALL_64_fastpath+0x24/0xab

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct
ttm_buffer_object *bo,
  gtt->ttm.ttm.func = _backend_func;
  /* allocate space for the uninitialized page entries */
-if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
  kfree(gtt);
  return NULL;
  }



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Re: [PATCH] gpu: Consistently use octal not symbolic permissions

[Jani Nikula]

On Thu, 24 May 2018, Joe Perches  wrote:
> On Fri, 2018-05-25 at 09:41 +0300, Jani Nikula wrote:
>> On Thu, 24 May 2018, Joe Perches  wrote:
>> > There is currently a mixture of octal and symbolic permissions uses
>> > in files in drivers/gpu/drm and one file in drivers/gpu.
>> > 
>> > There are ~270 existing octal uses and ~115 S_ uses.
>> > 
>> > Convert all the S_ symbolic permissions to their octal equivalents
>> > as using octal and not symbolic permissions is preferred by many as more
>> > readable.
>> > 
>> > see: https://lkml.org/lkml/2016/8/2/1945
>> > 
>> > Done with automated conversion via:
>> > $ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 
>> > 
>> > 
>> > Miscellanea:
>> > 
>> > o Wrapped modified multi-line calls to a single line where appropriate
>> > o Realign modified multi-line calls to open parenthesis
>> > o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
>> >   debug permission for "reset" - perhaps that should be modified
>> > Signed-off-by: Joe Perches 
>> > ---
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 
>> > +++---
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
>> >  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
>> >  drivers/gpu/drm/drm_debugfs.c  |  6 +-
>> >  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
>> >  drivers/gpu/drm/drm_sysfs.c|  2 +-
>> >  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
>> >  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
>> >  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
>> >  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
>> >  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
>> 
>> Please send at least i915 changes separately. There's zero reason to
>> make our lives harder for this change.
>
> The idea is to avoid unnecessary multiple patches for
> individual trees.

You're changing like a dozen trees. And apparently maintainers of
different trees also have different opinions on whether this is a good
idea or not. Mass changes like this go nowhere, and if they do, will
cause unnecessary conflicts that could have been trivially avoided.

BR,
Jani.

> But you could do that via something like:
>
> $ git am --include='drivers/gpu/drm/i915/*' 
>
> cheers, Joe
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: drm/amdgpu: Add helper function to get buffer domain

[Christian König]

Am 25.05.2018 um 02:15 schrieb Deepak Sharma:

Move logic of getting supported domain to a helper
function

Signed-off-by: Deepak Sharma 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 10 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 16 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  2 +-
  3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 63758db5e2ea..1e9cfbfa9c2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -750,19 +750,15 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct amdgpu_device *adev = dev->dev_private;
struct drm_gem_object *gobj;
uint32_t handle;
-   u32 domain = amdgpu_display_supported_domains(adev);
+   u32 domain;
int r;
  
  	args->pitch = amdgpu_align_pitch(adev, args->width,

 DIV_ROUND_UP(args->bpp, 8), 0);
args->size = (u64)args->pitch * args->height;
args->size = ALIGN(args->size, PAGE_SIZE);
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
-
+   domain = amdgpu_bo_get_domain(adev,
+ amdgpu_display_supported_domains(adev));
r = amdgpu_gem_object_create(adev, args->size, 0, domain,
 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 false, NULL, );
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6a9e46ae7f0a..8acffd9990d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -703,11 +703,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
/* This assumes only APU display buffers are pinned with (VRAM|GTT).
 * See function amdgpu_display_supported_domains()
 */
-   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
-   domain = AMDGPU_GEM_DOMAIN_VRAM;
-   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
-   domain = AMDGPU_GEM_DOMAIN_GTT;
-   }
+   domain = amdgpu_bo_get_domain(adev, domain);
  
  	if (bo->pin_count) {

uint32_t mem_type = bo->tbo.mem.mem_type;
@@ -1066,3 +1062,13 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
  
  	return bo->tbo.offset;

  }
+
+uint32_t amdgpu_bo_get_domain(struct amdgpu_device *adev, uint32_t domain)


That needs a better name. Something like 
amdgpu_bo_get_preferred_pin_domain() or something like that.


Apart from that looks good to me,
Christian.


+{
+   if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
+   domain = AMDGPU_GEM_DOMAIN_VRAM;
+   if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
+   domain = AMDGPU_GEM_DOMAIN_GTT;
+   }
+   return domain;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 540e03fa159f..89e05e1f0029 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -289,7 +289,7 @@ int amdgpu_bo_restore_from_shadow(struct amdgpu_device 
*adev,
  struct reservation_object *resv,
  struct dma_fence **fence,
  bool direct);
-
+uint32_t amdgpu_bo_get_domain(struct amdgpu_device *adev, uint32_t domain);
  
  /*

   * sub allocation


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Re: [PATCH] gpu: Consistently use octal not symbolic permissions

[Christian König]

Well I think we rejected that multiple times now.

At least I find the symbolic permissions easier to read and I absolutely 
don't see any reason why we should only use one form.


Christian.

Am 24.05.2018 um 22:22 schrieb Joe Perches:

There is currently a mixture of octal and symbolic permissions uses
in files in drivers/gpu/drm and one file in drivers/gpu.

There are ~270 existing octal uses and ~115 S_ uses.

Convert all the S_ symbolic permissions to their octal equivalents
as using octal and not symbolic permissions is preferred by many as more
readable.

see: https://lkml.org/lkml/2016/8/2/1945

Done with automated conversion via:
$ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 

Miscellanea:

o Wrapped modified multi-line calls to a single line where appropriate
o Realign modified multi-line calls to open parenthesis
o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
   debug permission for "reset" - perhaps that should be modified

Signed-off-by: Joe Perches 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
  drivers/gpu/drm/drm_debugfs.c  |  6 +-
  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
  drivers/gpu/drm/drm_sysfs.c|  2 +-
  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
  drivers/gpu/drm/msm/adreno/a5xx_debugfs.c  |  5 +-
  drivers/gpu/drm/msm/msm_perf.c |  4 +-
  drivers/gpu/drm/msm/msm_rd.c   |  4 +-
  drivers/gpu/drm/nouveau/nouveau_debugfs.c  |  2 +-
  drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c| 11 ++-
  .../drm/omapdrm/displays/panel-sony-acx565akm.c|  6 +-
  .../drm/omapdrm/displays/panel-tpo-td043mtea1.c| 10 +--
  drivers/gpu/drm/radeon/radeon_pm.c | 26 +++---
  drivers/gpu/drm/radeon/radeon_ttm.c|  4 +-
  drivers/gpu/drm/sti/sti_drv.c  |  2 +-
  drivers/gpu/drm/tinydrm/mipi-dbi.c |  4 +-
  drivers/gpu/drm/ttm/ttm_bo.c   |  2 +-
  drivers/gpu/drm/ttm/ttm_memory.c   | 12 +--
  drivers/gpu/drm/ttm/ttm_page_alloc.c   |  6 +-
  drivers/gpu/drm/ttm/ttm_page_alloc_dma.c   |  6 +-
  drivers/gpu/drm/udl/udl_fb.c   |  4 +-
  drivers/gpu/host1x/debug.c | 12 +--
  30 files changed, 138 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index f5fb93795a69..7b29febff511 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -830,7 +830,7 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
  
  	for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {

ent = debugfs_create_file(debugfs_regs_names[i],
- S_IFREG | S_IRUGO, root,
+ S_IFREG | 0444, root,
  adev, debugfs_regs[i]);
if (IS_ERR(ent)) {
for (j = 0; j < i; j++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b455da487782..fa55d7e9e784 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -905,39 +905,39 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
return -EINVAL;
  }
  
-static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);

-static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
+static DEVICE_ATTR(power_dpm_state, 0644, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
+static DEVICE_ATTR(power_dpm_force_performance_level, 0644,
   amdgpu_get_dpm_forced_performance_level,
   amdgpu_set_dpm_forced_performance_level);
-static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
-static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
-static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_force_state,
-   amdgpu_set_pp_force_state);
-static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_table,
-   amdgpu_set_pp_table);
-static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_sclk,
- 

Re: [PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1

[Christian König]

NAK, that probably just fixed the symptom but not the underlying problem.

Somebody is accessing the page array when it should never be accessed.

How did you manage to trigger this?

Regards,
Christian.

Am 25.05.2018 um 07:41 schrieb Junwei Zhang:

[  632.679861] BUG: unable to handle kernel NULL pointer dereference at (null)
[  632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]

[  632.680011] Call Trace:
[  632.680082]  amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[  632.680092]  ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[  632.680098]  amdttm_tt_bind+0x52/0x60 [amdttm]
[  632.680106]  ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[  632.680112]  ? find_next_bit+0xb/0x10
[  632.680119]  amdttm_bo_validate+0x11d/0x130 [amdttm]
[  632.680176]  amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[  632.680232]  amdgpu_cs_validate+0x41/0x270 [amdgpu]
[  632.680288]  amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[  632.680343]  amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[  632.680401]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680416]  drm_ioctl_kernel+0x6b/0xb0 [drm]
[  632.680431]  drm_ioctl+0x3e4/0x450 [drm]
[  632.680485]  ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[  632.680537]  amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[  632.680542]  do_vfs_ioctl+0xa4/0x600
[  632.680546]  ? SyS_futex+0x7f/0x180
[  632.680549]  SyS_ioctl+0x79/0x90
[  632.680554]  entry_SYSCALL_64_fastpath+0x24/0xab

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct 
ttm_buffer_object *bo,
gtt->ttm.ttm.func = _backend_func;
  
  	/* allocate space for the uninitialized page entries */

-   if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+   if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
kfree(gtt);
return NULL;
}


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Re: [PATCH] gpu: Consistently use octal not symbolic permissions

[Jani Nikula]

On Thu, 24 May 2018, Joe Perches  wrote:
> There is currently a mixture of octal and symbolic permissions uses
> in files in drivers/gpu/drm and one file in drivers/gpu.
>
> There are ~270 existing octal uses and ~115 S_ uses.
>
> Convert all the S_ symbolic permissions to their octal equivalents
> as using octal and not symbolic permissions is preferred by many as more
> readable.
>
> see: https://lkml.org/lkml/2016/8/2/1945
>
> Done with automated conversion via:
> $ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 
>
> Miscellanea:
>
> o Wrapped modified multi-line calls to a single line where appropriate
> o Realign modified multi-line calls to open parenthesis
> o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
>   debug permission for "reset" - perhaps that should be modified
>
> Signed-off-by: Joe Perches 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 
> +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
>  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
>  drivers/gpu/drm/drm_debugfs.c  |  6 +-
>  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
>  drivers/gpu/drm/drm_sysfs.c|  2 +-
>  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
>  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
>  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
>  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
>  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-

Please send at least i915 changes separately. There's zero reason to
make our lives harder for this change.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
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