Re: [PATCH 1/4] drm/amdgpu/pp/smu7: use a local variable for toc indexing

[Christian König]

Am 12.07.2018 um 16:39 schrieb Alex Deucher:

Rather than using the index variable stored in vram.  If
the device fails to come back online after a resume cycle,
reads from vram will return all 1s which will cause a
segfault. Based on a patch from Thomas Martitz .
This avoids the segfault, but we still need to sort out
why the GPU does not come back online after a resume.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org


Acked-by: Christian König  for the series.


---
  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 23 +++---
  1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index d644a9bb9078..9f407c48d4f0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -381,6 +381,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
uint32_t fw_to_load;
int result = 0;
struct SMU_DRAMData_TOC *toc;
+   uint32_t num_entries = 0;
  
  	if (!hwmgr->reload_fw) {

pr_info("skip reloading...\n");
@@ -422,41 +423,41 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
}
  
  	toc = (struct SMU_DRAMData_TOC *)smu_data->header;

-   toc->num_entries = 0;
toc->structure_version = 1;
  
  	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

-   UCODE_ID_RLC_G, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_RLC_G, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_CE, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_CE, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_PFP, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_PFP, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_ME, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_ME, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_MEC, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC_JT1, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_MEC_JT1, 
&toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC_JT2, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_MEC_JT2, 
&toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_SDMA0, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_SDMA0, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_SDMA1, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_SDMA1, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
if (!hwmgr->not_vf)
PP_ASSERT_WITH_CODE(0 == 
smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_MEC_STORAGE, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_MEC_STORAGE, 
&toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
  
+	toc->num_entries = num_entries;

smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, 
upper_32_bits(smu_data->header_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, 
lower_32_bits(smu_data->header_buffer.mc_addr));
  

Re: [PATCH v2 1/3] drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

[Christian König]

Am 12.07.2018 um 16:37 schrieb Michel Dänzer:

From: Michel Dänzer 

Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

v2:
* Also change amdgpu_vram_mgr_bo_invisible_size to
   amdgpu_vram_mgr_bo_visible_size, allowing further simplification
   (Christian König)

Cc: sta...@vger.kernel.org
Signed-off-by: Michel Dänzer 


Nice, that makes the code even more cleaner than I thought it would :)

All three are Reviewed-by: Christian König .

Thanks,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c  |  5 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 20 
  5 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f4db10..77ab06bf26d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1593,7 +1593,7 @@ struct amdgpu_device {
  
  	/* tracking pinned memory */

u64 vram_pin_size;
-   u64 invisible_pin_size;
+   u64 visible_pin_size;
u64 gart_pin_size;
  
  	/* amdkfd interface */

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d041dddaad0c..b1ea43ee8b87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -504,7 +504,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
vram_gtt.vram_size = adev->gmc.real_vram_size;
vram_gtt.vram_size -= adev->vram_pin_size;
vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
-   vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - 
adev->invisible_pin_size);
+   vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= adev->gart_pin_size;
@@ -525,8 +525,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
mem.cpu_accessible_vram.total_heap_size =
adev->gmc.visible_vram_size;
mem.cpu_accessible_vram.usable_heap_size =
-   adev->gmc.visible_vram_size -
-   (adev->vram_pin_size - adev->invisible_pin_size);
+   adev->gmc.visible_vram_size - adev->visible_pin_size;
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9ee678d63890..f0239feceab4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -917,7 +917,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
adev->vram_pin_size += amdgpu_bo_size(bo);
-   adev->invisible_pin_size += 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size += amdgpu_vram_mgr_bo_visible_size(bo);
} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
adev->gart_pin_size += amdgpu_bo_size(bo);
}
@@ -969,7 +969,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
  
  	if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {

adev->vram_pin_size -= amdgpu_bo_size(bo);
-   adev->invisible_pin_size -= 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size -= amdgpu_vram_mgr_bo_visible_size(bo);
} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
adev->gart_pin_size -= amdgpu_bo_size(bo);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index e5da4654b630..8b3cc6687769 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -73,7 +73,7 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
  uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
  int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
  
-u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo);

+u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
  uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
  uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

index f7a4bd5885a3..9cfa8a9ada92 100644
--- a/drivers/gpu/drm/amd/amdgpu/am

Re: [PATCH xf86-video-amdgpu 1/3] modesetting: Record non-desktop kernel property at PreInit time

[Yu, Qiang]

Hi Michel,

Could randrproto >= 1.6.0 also be optional? randrproto 1.6 is pretty new so
most old xserver doesn't compile with it. When compile latest ddx with
various OS we support, it will fail.

Maybe we can define RR_PROPERTY_NON_DESKTOP in ddx if not yet.

Regards,
Qiang


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Tuesday, July 10, 2018 12:20:46 AM
To: Keith Packard
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH xf86-video-amdgpu 1/3] modesetting: Record non-desktop 
kernel property at PreInit time

On 2018-07-09 06:14 PM, Keith Packard wrote:
> Michel Dänzer  writes:
>
>> From: Keith Packard 
>>
>> Save any value of the kernel non-desktop property in the xf86Output
>> structure to avoid non-desktop outputs in the default configuration.
>>
>> [Also bump randrproto requirement to a version that defines
>> RR_PROPERTY_NON_DESKTOP - ajax]
>>
>> Signed-off-by: Keith Packard 
>> (Ported from xserver commit b91c787c4cd2d20685db69426c539938c556128a)
>> Signed-off-by: Michel Dänzer 
>
> Thanks for porting this and making it compile on older server versions;
> I notice that you switched from xallocarray to calloc -- seems fine to
> me as it avoids some extra configure.ac goop.

Yep, didn't see the point of that, as ncrtc + noutput needs to be
explicitly checked for overflow anyway.


> For the series:
> Reviewed-by: Keith Packard 

Thanks!


--
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer

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Re: [PATCH 0/6] Raven support for KFD

[Mike Lothian]

Hi

I'm happy to test this out, just wondering what userspace I should pair it
with

Cheers

Mike

On Thu, 12 Jul 2018 at 22:25 Felix Kuehling  wrote:

> Raven refers to Ryzen APUs with integrated GFXv9 GPU.
> This patch series completes Raven support for KFD:
>
> * fix up memory banks info from CRAT
> * support different number of SDMA engines
> * workaround IOMMUv2 PPR issues
> * add device info
>
> Yong Zhao (6):
>   drm/amdkfd: Consolidate duplicate memory banks info in topology
>   drm/amdkfd: Make SDMA engine number an ASIC-dependent variable
>   drm/amdkfd: Avoid flooding dmesg on Raven due to IOMMU issues
>   drm/amdkfd: Workaround to accommodate Raven too many PPR issue
>   drm/amdkfd: Optimize out some duplicated code in
> kfd_signal_iommu_event()
>   drm/amdkfd: Enable Raven for KFD
>
>  drivers/gpu/drm/amd/amdkfd/kfd_crat.c  | 57
> +-
>  drivers/gpu/drm/amd/amdkfd/kfd_device.c| 28 +++
>  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 29 +++
>  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  6 +--
>  drivers/gpu/drm/amd/amdkfd/kfd_events.c| 47 ++
>  drivers/gpu/drm/amd/amdkfd/kfd_iommu.c |  2 +-
>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  1 +
>  .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  3 +-
>  8 files changed, 126 insertions(+), 47 deletions(-)
>
> --
> 2.7.4
>
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[PATCH 5/6] drm/amdkfd: Optimize out some duplicated code in kfd_signal_iommu_event()

[Felix Kuehling]

From: Yong Zhao 

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_events.c | 26 +++---
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 4dcacce..e9f0e0a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -911,22 +911,18 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned 
int pasid,
memory_exception_data.failure.NotPresent = 1;
memory_exception_data.failure.NoExecute = 0;
memory_exception_data.failure.ReadOnly = 0;
-   if (vma) {
-   if (vma->vm_start > address) {
-   memory_exception_data.failure.NotPresent = 1;
-   memory_exception_data.failure.NoExecute = 0;
+   if (vma && address >= vma->vm_start) {
+   memory_exception_data.failure.NotPresent = 0;
+
+   if (is_write_requested && !(vma->vm_flags & VM_WRITE))
+   memory_exception_data.failure.ReadOnly = 1;
+   else
memory_exception_data.failure.ReadOnly = 0;
-   } else {
-   memory_exception_data.failure.NotPresent = 0;
-   if (is_write_requested && !(vma->vm_flags & VM_WRITE))
-   memory_exception_data.failure.ReadOnly = 1;
-   else
-   memory_exception_data.failure.ReadOnly = 0;
-   if (is_execute_requested && !(vma->vm_flags & VM_EXEC))
-   memory_exception_data.failure.NoExecute = 1;
-   else
-   memory_exception_data.failure.NoExecute = 0;
-   }
+
+   if (is_execute_requested && !(vma->vm_flags & VM_EXEC))
+   memory_exception_data.failure.NoExecute = 1;
+   else
+   memory_exception_data.failure.NoExecute = 0;
}
 
up_read(&mm->mmap_sem);
-- 
2.7.4

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[PATCH 6/6] drm/amdkfd: Enable Raven for KFD

[Felix Kuehling]

From: Yong Zhao 

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 572235c..1b04871 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -70,6 +70,21 @@ static const struct kfd_device_info carrizo_device_info = {
.needs_pci_atomics = false,
.num_sdma_engines = 2,
 };
+
+static const struct kfd_device_info raven_device_info = {
+   .asic_family = CHIP_RAVEN,
+   .max_pasid_bits = 16,
+   .max_no_of_hqd  = 24,
+   .doorbell_size  = 8,
+   .ih_ring_entry_size = 8 * sizeof(uint32_t),
+   .event_interrupt_class = &event_interrupt_class_v9,
+   .num_of_watch_points = 4,
+   .mqd_size_aligned = MQD_SIZE_ALIGNED,
+   .supports_cwsr = true,
+   .needs_iommu_device = true,
+   .needs_pci_atomics = true,
+   .num_sdma_engines = 1,
+};
 #endif
 
 static const struct kfd_device_info hawaii_device_info = {
@@ -259,6 +274,7 @@ static const struct kfd_deviceid supported_devices[] = {
{ 0x9875, &carrizo_device_info },   /* Carrizo */
{ 0x9876, &carrizo_device_info },   /* Carrizo */
{ 0x9877, &carrizo_device_info },   /* Carrizo */
+   { 0x15DD, &raven_device_info }, /* Raven */
 #endif
{ 0x67A0, &hawaii_device_info },/* Hawaii */
{ 0x67A1, &hawaii_device_info },/* Hawaii */
-- 
2.7.4

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[PATCH 4/6] drm/amdkfd: Workaround to accommodate Raven too many PPR issue

[Felix Kuehling]

From: Yong Zhao 

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_events.c | 21 -
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 820133c..4dcacce 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -932,13 +932,24 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned 
int pasid,
up_read(&mm->mmap_sem);
mmput(mm);
 
-   mutex_lock(&p->event_mutex);
+   pr_debug("notpresent %d, noexecute %d, readonly %d\n",
+   memory_exception_data.failure.NotPresent,
+   memory_exception_data.failure.NoExecute,
+   memory_exception_data.failure.ReadOnly);
 
-   /* Lookup events by type and signal them */
-   lookup_events_by_type_and_signal(p, KFD_EVENT_TYPE_MEMORY,
-   &memory_exception_data);
+   /* Workaround on Raven to not kill the process when memory is freed
+* before IOMMU is able to finish processing all the excessive PPRs
+*/
+   if (dev->device_info->asic_family != CHIP_RAVEN) {
+   mutex_lock(&p->event_mutex);
+
+   /* Lookup events by type and signal them */
+   lookup_events_by_type_and_signal(p, KFD_EVENT_TYPE_MEMORY,
+   &memory_exception_data);
+
+   mutex_unlock(&p->event_mutex);
+   }
 
-   mutex_unlock(&p->event_mutex);
kfd_unref_process(p);
 }
 #endif /* KFD_SUPPORT_IOMMU_V2 */
-- 
2.7.4

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[PATCH 2/6] drm/amdkfd: Make SDMA engine number an ASIC-dependent variable

[Felix Kuehling]

From: Yong Zhao 

On Raven there is only one SDMA engine instead of previously assumed two,
so we need to adapt our code to this new scenario.

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 12 +
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 29 +++---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  6 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  1 +
 .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  3 +--
 5 files changed, 36 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 8faa8db..572235c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -52,6 +52,7 @@ static const struct kfd_device_info kaveri_device_info = {
.supports_cwsr = false,
.needs_iommu_device = true,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info carrizo_device_info = {
@@ -67,6 +68,7 @@ static const struct kfd_device_info carrizo_device_info = {
.supports_cwsr = true,
.needs_iommu_device = true,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 #endif
 
@@ -83,6 +85,7 @@ static const struct kfd_device_info hawaii_device_info = {
.supports_cwsr = false,
.needs_iommu_device = false,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info tonga_device_info = {
@@ -97,6 +100,7 @@ static const struct kfd_device_info tonga_device_info = {
.supports_cwsr = false,
.needs_iommu_device = false,
.needs_pci_atomics = true,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info tonga_vf_device_info = {
@@ -111,6 +115,7 @@ static const struct kfd_device_info tonga_vf_device_info = {
.supports_cwsr = false,
.needs_iommu_device = false,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info fiji_device_info = {
@@ -125,6 +130,7 @@ static const struct kfd_device_info fiji_device_info = {
.supports_cwsr = true,
.needs_iommu_device = false,
.needs_pci_atomics = true,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info fiji_vf_device_info = {
@@ -139,6 +145,7 @@ static const struct kfd_device_info fiji_vf_device_info = {
.supports_cwsr = true,
.needs_iommu_device = false,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 
 
@@ -154,6 +161,7 @@ static const struct kfd_device_info polaris10_device_info = 
{
.supports_cwsr = true,
.needs_iommu_device = false,
.needs_pci_atomics = true,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info polaris10_vf_device_info = {
@@ -168,6 +176,7 @@ static const struct kfd_device_info 
polaris10_vf_device_info = {
.supports_cwsr = true,
.needs_iommu_device = false,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info polaris11_device_info = {
@@ -182,6 +191,7 @@ static const struct kfd_device_info polaris11_device_info = 
{
.supports_cwsr = true,
.needs_iommu_device = false,
.needs_pci_atomics = true,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info vega10_device_info = {
@@ -196,6 +206,7 @@ static const struct kfd_device_info vega10_device_info = {
.supports_cwsr = true,
.needs_iommu_device = false,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 
 static const struct kfd_device_info vega10_vf_device_info = {
@@ -210,6 +221,7 @@ static const struct kfd_device_info vega10_vf_device_info = 
{
.supports_cwsr = true,
.needs_iommu_device = false,
.needs_pci_atomics = false,
+   .num_sdma_engines = 2,
 };
 
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 97c9f10..ace94d6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -101,6 +101,17 @@ unsigned int get_pipes_per_mec(struct device_queue_manager 
*dqm)
return dqm->dev->shared_resources.num_pipe_per_mec;
 }
 
+static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
+{
+   return dqm->dev->device_info->num_sdma_engines;
+}
+
+unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
+{
+   return dqm->dev->device_info->num_sdma_engines
+   * KFD_SDMA_QUEUES_PER_ENGINE;
+}
+
 void program_sh_mem_settings(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
 {
@@ -855,7 +866,7 @@ static int initialize_nocpsch(struct d

[PATCH 1/6] drm/amdkfd: Consolidate duplicate memory banks info in topology

[Felix Kuehling]

From: Yong Zhao 

If there are several memory banks that has the same properties in CRAT,
we aggregate them into one memory bank. This cleans up memory banks on
APUs (e.g. Raven) where the CRAT reports each memory channel as a
separate bank. This only confuses user mode, which only deals with
virtual memory.

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 57 ---
 1 file changed, 46 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 296b3f2..ee49960 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -189,6 +189,21 @@ static int kfd_parse_subtype_cu(struct 
crat_subtype_computeunit *cu,
return 0;
 }
 
+static struct kfd_mem_properties *
+find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width,
+   struct kfd_topology_device *dev)
+{
+   struct kfd_mem_properties *props;
+
+   list_for_each_entry(props, &dev->mem_props, list) {
+   if (props->heap_type == heap_type
+   && props->flags == flags
+   && props->width == width)
+   return props;
+   }
+
+   return NULL;
+}
 /* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct
  * topology device present in the device_list
  */
@@ -197,36 +212,56 @@ static int kfd_parse_subtype_mem(struct 
crat_subtype_memory *mem,
 {
struct kfd_mem_properties *props;
struct kfd_topology_device *dev;
+   uint32_t heap_type;
+   uint64_t size_in_bytes;
+   uint32_t flags = 0;
+   uint32_t width;
 
pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
mem->proximity_domain);
list_for_each_entry(dev, device_list, list) {
if (mem->proximity_domain == dev->proximity_domain) {
-   props = kfd_alloc_struct(props);
-   if (!props)
-   return -ENOMEM;
-
/* We're on GPU node */
if (dev->node_props.cpu_cores_count == 0) {
/* APU */
if (mem->visibility_type == 0)
-   props->heap_type =
+   heap_type =
HSA_MEM_HEAP_TYPE_FB_PRIVATE;
/* dGPU */
else
-   props->heap_type = mem->visibility_type;
+   heap_type = mem->visibility_type;
} else
-   props->heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
+   heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
 
if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
-   props->flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
+   flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
-   props->flags |= HSA_MEM_FLAGS_NON_VOLATILE;
+   flags |= HSA_MEM_FLAGS_NON_VOLATILE;
 
-   props->size_in_bytes =
+   size_in_bytes =
((uint64_t)mem->length_high << 32) +
mem->length_low;
-   props->width = mem->width;
+   width = mem->width;
+
+   /* Multiple banks of the same type are aggregated into
+* one. User mode doesn't care about multiple physical
+* memory segments. It's managed as a single virtual
+* heap for user mode.
+*/
+   props = find_subtype_mem(heap_type, flags, width, dev);
+   if (props) {
+   props->size_in_bytes += size_in_bytes;
+   break;
+   }
+
+   props = kfd_alloc_struct(props);
+   if (!props)
+   return -ENOMEM;
+
+   props->heap_type = heap_type;
+   props->flags = flags;
+   props->size_in_bytes = size_in_bytes;
+   props->width = width;
 
dev->node_props.mem_banks_count++;
list_add_tail(&props->list, &dev->mem_props);
-- 
2.7.4

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[PATCH 0/6] Raven support for KFD

[Felix Kuehling]

Raven refers to Ryzen APUs with integrated GFXv9 GPU.
This patch series completes Raven support for KFD:

* fix up memory banks info from CRAT
* support different number of SDMA engines
* workaround IOMMUv2 PPR issues
* add device info

Yong Zhao (6):
  drm/amdkfd: Consolidate duplicate memory banks info in topology
  drm/amdkfd: Make SDMA engine number an ASIC-dependent variable
  drm/amdkfd: Avoid flooding dmesg on Raven due to IOMMU issues
  drm/amdkfd: Workaround to accommodate Raven too many PPR issue
  drm/amdkfd: Optimize out some duplicated code in
kfd_signal_iommu_event()
  drm/amdkfd: Enable Raven for KFD

 drivers/gpu/drm/amd/amdkfd/kfd_crat.c  | 57 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 28 +++
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 29 +++
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  6 +--
 drivers/gpu/drm/amd/amdkfd/kfd_events.c| 47 ++
 drivers/gpu/drm/amd/amdkfd/kfd_iommu.c |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  1 +
 .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  3 +-
 8 files changed, 126 insertions(+), 47 deletions(-)

-- 
2.7.4

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[PATCH 3/6] drm/amdkfd: Avoid flooding dmesg on Raven due to IOMMU issues

[Felix Kuehling]

From: Yong Zhao 

On Raven Invalid PPRs can be reported because multiple PPRs can be
still queued when memory is freed. Apply a rate limit to avoid
flooding the log in this case.

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
index c718179..7a61f38 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
@@ -190,7 +190,7 @@ static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int 
pasid,
 {
struct kfd_dev *dev;
 
-   dev_warn(kfd_device,
+   dev_warn_ratelimited(kfd_device,
"Invalid PPR device %x:%x.%x pasid %d address 0x%lX 
flags 0x%X",
PCI_BUS_NUM(pdev->devfn),
PCI_SLOT(pdev->devfn),
-- 
2.7.4

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[PATCH 3/3] drm/amdgpu/pp: switch smu callback type for get_argument()

[Alex Deucher]

return a uint32_t rather than an int to properly reflect
what the function does.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h   | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h  | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c  | 4 ++--
 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c  | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h  | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c   | 2 +-
 7 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index b3363f26039a..d3d96260f440 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -194,7 +194,7 @@ struct pp_smumgr_func {
int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);
int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,
uint32_t firmware);
-   int (*get_argument)(struct pp_hwmgr  *hwmgr);
+   uint32_t (*get_argument)(struct pp_hwmgr  *hwmgr);
int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);
int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,
  uint16_t msg, uint32_t parameter);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 89dfbf53c7e6..82550a8a3a3f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -80,7 +80,7 @@ enum SMU10_TABLE_ID {
SMU10_CLOCKTABLE,
 };
 
-extern int smum_get_argument(struct pp_hwmgr *hwmgr);
+extern uint32_t smum_get_argument(struct pp_hwmgr *hwmgr);
 
 extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index 0a563f6fe9ea..bb07d43f3874 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -68,7 +68,7 @@ static int smu10_send_msg_to_smc_without_waiting(struct 
pp_hwmgr *hwmgr,
return 0;
 }
 
-static int smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
+static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
 {
struct amdgpu_device *adev = hwmgr->adev;
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
index c861d3023474..f7e3bc22bb93 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
@@ -52,10 +52,10 @@ static const enum smu8_scratch_entry firmware_list[] = {
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G,
 };
 
-static int smu8_get_argument(struct pp_hwmgr *hwmgr)
+static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr)
 {
if (hwmgr == NULL || hwmgr->device == NULL)
-   return -EINVAL;
+   return 0;
 
return cgs_read_register(hwmgr->device,
mmSMU_MP1_SRBM2P_ARG_0);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c
index aad8f077f33c..079fc8e8f709 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c
@@ -142,7 +142,7 @@ int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr 
*hwmgr,
return 0;
 }
 
-int smu9_get_argument(struct pp_hwmgr *hwmgr)
+uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr)
 {
struct amdgpu_device *adev = hwmgr->adev;
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h
index a8da2815bd89..1462279ca128 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h
@@ -27,6 +27,6 @@ bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr);
 int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
 int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
-int smu9_get_argument(struct pp_hwmgr *hwmgr);
+uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index c9837935f0f5..99d5e4f98f49 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -96,7 +96,7 @@ int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
return 0;
 }
 
-int smum_get_argument(struct pp_hwmgr *hwmgr)
+uint32_t smum_get_argument(struct pp_hwmgr *hwmgr)
 {
if (NULL != hwmgr->smumgr_funcs->get_argument)
return hwmgr->smumgr_funcs->get_argument(hwmgr);
-- 
2.13.6

_

[PATCH 2/3] drm/amdgpu/pp: split out common smumgr smu9 code

[Alex Deucher]

Split out the shared smumgr code for vega10 and 12
so we don't have duplicate code for both.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c |  44 ++---
 .../gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c   |   8 +-
 drivers/gpu/drm/amd/powerplay/smumgr/Makefile  |   2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c | 150 
 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h |  32 
 .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c   | 168 ++
 .../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c   | 191 +++--
 .../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h   |   1 -
 8 files changed, 242 insertions(+), 354 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index ed17c560b5ef..3a57e53e04b0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -472,7 +472,7 @@ static int vega12_get_number_of_dpm_level(struct pp_hwmgr 
*hwmgr,
"[GetNumOfDpmLevel] failed to get dpm levels!",
return ret);
 
-   vega12_read_arg_from_smc(hwmgr, num_of_levels);
+   *num_of_levels = smum_get_argument(hwmgr);
PP_ASSERT_WITH_CODE(*num_of_levels > 0,
"[GetNumOfDpmLevel] number of clk levels is invalid!",
return -EINVAL);
@@ -494,11 +494,7 @@ static int vega12_get_dpm_frequency_by_index(struct 
pp_hwmgr *hwmgr,
"[GetDpmFrequencyByIndex] Failed to get dpm frequency from 
SMU!",
return -EINVAL);
 
-   result = vega12_read_arg_from_smc(hwmgr, clock);
-
-   PP_ASSERT_WITH_CODE(*clock != 0,
-   "[GetDPMFrequencyByIndex] Failed to get dpm frequency by 
index.!",
-   return -EINVAL);
+   *clock = smum_get_argument(hwmgr);
 
return result;
 }
@@ -879,21 +875,21 @@ static int vega12_get_all_clock_ranges_helper(struct 
pp_hwmgr *hwmgr,
smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0,
"[GetClockRanges] Failed to get max ac clock from SMC!",
return -EINVAL);
-   vega12_read_arg_from_smc(hwmgr, &(clock->ACMax));
+   clock->ACMax = smum_get_argument(hwmgr);
 
/* AC Min */
PP_ASSERT_WITH_CODE(
smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0,
"[GetClockRanges] Failed to get min ac clock from SMC!",
return -EINVAL);
-   vega12_read_arg_from_smc(hwmgr, &(clock->ACMin));
+   clock->ACMin = smum_get_argument(hwmgr);
 
/* DC Max */
PP_ASSERT_WITH_CODE(
smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0,
"[GetClockRanges] Failed to get max dc clock from SMC!",
return -EINVAL);
-   vega12_read_arg_from_smc(hwmgr, &(clock->DCMax));
+   clock->DCMax = smum_get_argument(hwmgr);
 
return 0;
 }
@@ -1214,7 +1210,7 @@ static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, 
uint32_t *query)
"Failed to get current package power!",
return -EINVAL);
 
-   vega12_read_arg_from_smc(hwmgr, &value);
+   value = smum_get_argument(hwmgr);
/* power value is an integer */
*query = value << 8;
 #endif
@@ -1230,11 +1226,8 @@ static int vega12_get_current_gfx_clk_freq(struct 
pp_hwmgr *hwmgr, uint32_t *gfx
PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0,
"[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK 
Frequency Failed!",
-   return -1);
-   PP_ASSERT_WITH_CODE(
-   vega12_read_arg_from_smc(hwmgr, &gfx_clk) == 0,
-   "[GetCurrentGfxClkFreq] Attempt to read arg from SMC 
Failed",
-   return -1);
+   return -EINVAL);
+   gfx_clk = smum_get_argument(hwmgr);
 
*gfx_freq = gfx_clk * 100;
 
@@ -1250,11 +1243,8 @@ static int vega12_get_current_mclk_freq(struct pp_hwmgr 
*hwmgr, uint32_t *mclk_f
PP_ASSERT_WITH_CODE(
smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,
"[GetCurrentMClkFreq] Attempt to get Current MCLK 
Frequency Failed!",
-   return -1);
-   PP_ASSERT_WITH_CODE(
-   vega12_read_arg_from_smc(hwmgr, &mem_clk) == 0,
-   "[GetCurrentMClkFreq] Attempt to read arg from SMC 
Failed",
-   retu

[PATCH 1/3] drm/amdgpu/pp: remove dead vega12 code

[Alex Deucher]

Commented out.

Signed-off-by: Alex Deucher 
---
 .../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c   | 29 --
 1 file changed, 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
index 7d9b40e8b1bf..508a262fb328 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
@@ -343,29 +343,6 @@ static int vega12_set_tools_address(struct pp_hwmgr *hwmgr)
return 0;
 }
 
-#if 0 /* tentatively remove */
-static int vega12_verify_smc_interface(struct pp_hwmgr *hwmgr)
-{
-   uint32_t smc_driver_if_version;
-
-   PP_ASSERT_WITH_CODE(!vega12_send_msg_to_smc(hwmgr,
-   PPSMC_MSG_GetDriverIfVersion),
-   "Attempt to get SMC IF Version Number Failed!",
-   return -EINVAL);
-   vega12_read_arg_from_smc(hwmgr, &smc_driver_if_version);
-
-   if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
-   pr_err("Your firmware(0x%x) doesn't match \
-   SMU9_DRIVER_IF_VERSION(0x%x). \
-   Please update your firmware!\n",
-   smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
-   return -EINVAL;
-   }
-
-   return 0;
-}
-#endif
-
 static int vega12_smu_init(struct pp_hwmgr *hwmgr)
 {
struct vega12_smumgr *priv;
@@ -517,12 +494,6 @@ static int vega12_start_smu(struct pp_hwmgr *hwmgr)
"SMC is not running!",
return -EINVAL);
 
-#if 0 /* tentatively remove */
-   PP_ASSERT_WITH_CODE(!vega12_verify_smc_interface(hwmgr),
-   "Failed to verify SMC interface!",
-   return -EINVAL);
-#endif
-
vega12_set_tools_address(hwmgr);
 
return 0;
-- 
2.13.6

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[PATCH 10/10] drm/amd/display: Fix some checkpatch.pl errors and warnings in dc_link_dp.c

[sunpeng.li]

From: Harry Wentland 

[Why]
Any Linux kernel code should pass checkpatch.pl with no errors and
little, if any, warning.

[How]
Fixing some spacing errors and warnings.

Change-Id: I44d2da7be3a02a9644cbdfb3382566e562e7ea24
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 35 
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 00cab78..8fbb999 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -39,7 +39,7 @@ static bool decide_fallback_link_setting(
struct dc_link_settings initial_link_settings,
struct dc_link_settings *current_link_setting,
enum link_training_result training_result);
-static struct dc_link_settings get_common_supported_link_settings (
+static struct dc_link_settings get_common_supported_link_settings(
struct dc_link_settings link_setting_a,
struct dc_link_settings link_setting_b);
 
@@ -94,8 +94,8 @@ static void dpcd_set_link_settings(
uint8_t rate = (uint8_t)
(lt_settings->link_settings.link_rate);
 
-   union down_spread_ctrl downspread = {{0}};
-   union lane_count_set lane_count_set = {{0}};
+   union down_spread_ctrl downspread = { {0} };
+   union lane_count_set lane_count_set = { {0} };
uint8_t link_set_buffer[2];
 
downspread.raw = (uint8_t)
@@ -165,11 +165,11 @@ static void dpcd_set_lt_pattern_and_lane_settings(
const struct link_training_settings *lt_settings,
enum hw_dp_training_pattern pattern)
 {
-   union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
+   union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
const uint32_t dpcd_base_lt_offset =
DP_TRAINING_PATTERN_SET;
uint8_t dpcd_lt_buffer[5] = {0};
-   union dpcd_training_pattern dpcd_pattern = {{0}};
+   union dpcd_training_pattern dpcd_pattern = { {0} };
uint32_t lane;
uint32_t size_in_bytes;
bool edp_workaround = false; /* TODO link_prop.INTERNAL */
@@ -233,7 +233,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
link,
DP_TRAINING_PATTERN_SET,
&dpcd_pattern.raw,
-   sizeof(dpcd_pattern.raw) );
+   sizeof(dpcd_pattern.raw));
 
core_link_write_dpcd(
link,
@@ -247,7 +247,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
link,
dpcd_base_lt_offset,
dpcd_lt_buffer,
-   size_in_bytes + sizeof(dpcd_pattern.raw) );
+   size_in_bytes + sizeof(dpcd_pattern.raw));
 
link->cur_lane_setting = lt_settings->lane_settings[0];
 }
@@ -429,8 +429,8 @@ static void get_lane_status_and_drive_settings(
struct link_training_settings *req_settings)
 {
uint8_t dpcd_buf[6] = {0};
-   union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {{{0}}};
-   struct link_training_settings request_settings = {{0}};
+   union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+   struct link_training_settings request_settings = { {0} };
uint32_t lane;
 
memset(req_settings, '\0', sizeof(struct link_training_settings));
@@ -652,7 +652,7 @@ static bool perform_post_lt_adj_req_sequence(
 
if (req_drv_setting_changed) {
update_drive_settings(
-   lt_settings,req_settings);
+   lt_settings, req_settings);
 
dc_link_dp_set_drive_settings(link,
lt_settings);
@@ -725,8 +725,8 @@ static enum link_training_result 
perform_channel_equalization_sequence(
enum hw_dp_training_pattern hw_tr_pattern;
uint32_t retries_ch_eq;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-   union lane_align_status_updated dpcd_lane_status_updated = {{0}};
-   union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};
+   union lane_align_status_updated dpcd_lane_status_updated = { {0} };
+   union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 
hw_tr_pattern = get_supported_tp(link);
 
@@ -1186,7 +1186,7 @@ bool dp_hbr_verify_link_cap(
return success;
 }
 
-static struct dc_link_settings get_common_supported_link_settings (
+static struct dc_link_settings get_common_supported_link_settings(
struct dc_link_settings link_setting_a,
struct dc_link_settings link

[PATCH 09/10] drm/amd/display: Null ptr check for set_sdr_white_level

[sunpeng.li]

From: Krunoslav Kovac 

[Why&How]
Cursor boosting can only be done on DCN+
Check for nullptr since DCE doesn't implement it.

Change-Id: Ifd191103f58214038355c41ccd89fc9cf4a95b3e
Signed-off-by: Krunoslav Kovac 
Reviewed-by: Sivapiriyan Kumarasamy 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 4717330..fdcc8ab 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -214,7 +214,8 @@ bool dc_stream_set_cursor_attributes(
}
 
core_dc->hwss.set_cursor_attribute(pipe_ctx);
-   core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
+   if (core_dc->hwss.set_cursor_sdr_white_level)
+   core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
}
 
if (pipe_to_program)
-- 
2.7.4

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[PATCH 08/10] drm/amd/display: dal 3.1.56

[sunpeng.li]

From: Harry Wentland 

Change-Id: I59cb2ad47b74e8aa48bc71bd532e02a1723a308e
Signed-off-by: Harry Wentland 
Reviewed-by: Steven Chiu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index f74ad8e..b10dc17 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.55"
+#define DC_VER "3.1.56"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.7.4

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[PATCH 07/10] drm/amd/display: add new dc debug structure to track debug data

[sunpeng.li]

From: Jun Lei 

[why]
Some DTN tests still failing @ 2%  Need to reduce.

[how]
add instrumentation code to driver so we can get more information from failed 
runs.

Change-Id: I6c4ead8e28100cbe951a06dcde85dd6dbd5aa321
Signed-off-by: Jun Lei 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dc.h  | 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 49f465e..00cab78 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1028,6 +1028,9 @@ enum link_training_result 
dc_link_dp_perform_link_training(
lt_settings.lane_settings[0].VOLTAGE_SWING,
lt_settings.lane_settings[0].PRE_EMPHASIS);
 
+   if (status != LINK_TRAINING_SUCCESS)
+   link->ctx->dc->debug.debug_data.ltFailCount++;
+
return status;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 85f5ddd..f74ad8e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -259,6 +259,11 @@ struct dc_debug {
bool scl_reset_length10;
bool hdmi20_disable;
 
+   struct {
+   uint32_t ltFailCount;
+   uint32_t i2cErrorCount;
+   uint32_t auxErrorCount;
+   } debug_data;
 };
 struct dc_state;
 struct resource_pool;
-- 
2.7.4

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[PATCH 05/10] drm/amd/display: Add hook for MST root branch info

[sunpeng.li]

From: Nikola Cornij 

This allows DM to do any necessary updates before MST discovery starts.

Change-Id: I106b56b0ffe1c0e00a27c81fcee3776c69e17575
Signed-off-by: Nikola Cornij 
Reviewed-by: Nikola Cornij 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 
 drivers/gpu/drm/amd/display/dc/dm_helpers.h   | 8 
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 59b113d..8403b6a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -169,6 +169,11 @@ static void get_payload_table(
mutex_unlock(&mst_mgr->payload_lock);
 }
 
+void dm_helpers_dp_update_branch_info(
+   struct dc_context *ctx,
+   const struct dc_link *link)
+{}
+
 /*
  * Writes payload allocation table in immediate downstream device.
  */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index bbe43fd..4de68fa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -529,6 +529,10 @@ static bool detect_dp(
if (reason == DETECT_REASON_BOOT)
boot = true;
 
+   dm_helpers_dp_update_branch_info(
+   link->ctx,
+   link);
+
if (!dm_helpers_dp_mst_start_top_mgr(
link->ctx,
link, boot)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h 
b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 7e6b9f5..5d4527d 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -40,6 +40,14 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
const struct dc_edid *edid,
struct dc_edid_caps *edid_caps);
 
+
+/*
+ * Update DP branch info
+ */
+void dm_helpers_dp_update_branch_info(
+   struct dc_context *ctx,
+   const struct dc_link *link);
+
 /*
  * Writes payload allocation table in immediate downstream device.
  */
-- 
2.7.4

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[PATCH 06/10] drm/amd/display: Move address tracking out of HUBP

[sunpeng.li]

From: Tony Cheng 

[Why]
We sometime require remapping of FB address space to UMA

[How]
Move address tracking up a layer before we apply address translation

Change-Id: I60a979662c07c3be8f798a517ba9d30322b2cc8a
Signed-off-by: Tony Cheng 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  4 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 19 +++
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |  1 -
 3 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 833d52b..deae210 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -471,9 +471,6 @@ bool hubp1_program_surface_flip_and_addr(
 
hubp->request_address = *address;
 
-   if (flip_immediate)
-   hubp->current_address = *address;
-
return true;
 }
 
@@ -709,7 +706,6 @@ bool hubp1_is_flip_pending(struct hubp *hubp)
if (earliest_inuse_address.grph.addr.quad_part != 
hubp->request_address.grph.addr.quad_part)
return true;
 
-   hubp->current_address = hubp->request_address;
return false;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 689aebf..8535d87 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1172,12 +1172,19 @@ static void dcn10_update_plane_addr(const struct dc 
*dc, struct pipe_ctx *pipe_c
 
if (plane_state == NULL)
return;
+
addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
+
pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
pipe_ctx->plane_res.hubp,
&plane_state->address,
plane_state->flip_immediate);
+
plane_state->status.requested_address = plane_state->address;
+
+   if (plane_state->flip_immediate)
+   plane_state->status.current_address = plane_state->address;
+
if (addr_patched)
pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 }
@@ -2556,16 +2563,20 @@ static void dcn10_update_pending_status(struct pipe_ctx 
*pipe_ctx)
 {
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct timing_generator *tg = pipe_ctx->stream_res.tg;
+   bool flip_pending;
 
if (plane_state == NULL)
return;
 
-   plane_state->status.is_flip_pending =
-   pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
+   flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
pipe_ctx->plane_res.hubp);
 
-   plane_state->status.current_address = 
pipe_ctx->plane_res.hubp->current_address;
-   if (pipe_ctx->plane_res.hubp->current_address.type == 
PLN_ADDR_TYPE_GRPH_STEREO &&
+   plane_state->status.is_flip_pending = flip_pending;
+
+   if (!flip_pending)
+   plane_state->status.current_address = 
plane_state->status.requested_address;
+
+   if (plane_state->status.current_address.type == 
PLN_ADDR_TYPE_GRPH_STEREO &&
tg->funcs->is_stereo_left_eye) {
plane_state->status.is_right_eye =

!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 5b7976f..4f3f9e6 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -46,7 +46,6 @@ struct hubp {
const struct hubp_funcs *funcs;
struct dc_context *ctx;
struct dc_plane_address request_address;
-   struct dc_plane_address current_address;
int inst;
 
/* run time states */
-- 
2.7.4

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[PATCH 04/10] drm/amd/display: add HDR visual confirm

[sunpeng.li]

From: Gloria Li 

[Why]
Testing team wants a way to tell if HDR is on or not

[How]
Program the overscan color to visually indicate the HDR state of the top-most 
plane

Change-Id: I5bd04d68586461f2da81be99f5e92a6cdfa17d8b
Signed-off-by: Gloria Li 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h| 11 -
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c |  2 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  2 +-
 .../drm/amd/display/dc/dce110/dce110_transform_v.c |  2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |  7 ++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 50 --
 6 files changed, 63 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2085783..85f5ddd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -169,6 +169,12 @@ struct dc_config {
bool disable_disp_pll_sharing;
 };
 
+enum visual_confirm {
+   VISUAL_CONFIRM_DISABLE = 0,
+   VISUAL_CONFIRM_SURFACE = 1,
+   VISUAL_CONFIRM_HDR = 2,
+};
+
 enum dcc_option {
DCC_ENABLE = 0,
DCC_DISABLE = 1,
@@ -202,7 +208,7 @@ struct dc_clocks {
 };
 
 struct dc_debug {
-   bool surface_visual_confirm;
+   enum visual_confirm visual_confirm;
bool sanity_checks;
bool max_disp_clk;
bool surface_trace;
@@ -387,7 +393,8 @@ enum dc_transfer_func_predefined {
TRANSFER_FUNCTION_LINEAR,
TRANSFER_FUNCTION_UNITY,
TRANSFER_FUNCTION_HLG,
-   TRANSFER_FUNCTION_HLG12
+   TRANSFER_FUNCTION_HLG12,
+   TRANSFER_FUNCTION_GAMMA22
 };
 
 struct dc_transfer_func {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index a02e719..ab63d0d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -155,7 +155,7 @@ static void program_overscan(
int overscan_bottom = data->v_active
- data->recout.y - data->recout.height;
 
-   if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) {
+   if (xfm_dce->base.ctx->dc->debug.visual_confirm != 
VISUAL_CONFIRM_DISABLE) {
overscan_bottom += 2;
overscan_right += 2;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index a964dd0c..2202c17 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1256,7 +1256,7 @@ static void program_scaler(const struct dc *dc,
return;
 #endif
 
-   if (dc->debug.surface_visual_confirm)
+   if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
get_surface_visual_confirm_color(pipe_ctx, &color);
else
color_space_to_black_color(dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index a7dce06..aa8d6b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -235,7 +235,7 @@ static void program_overscan(
int overscan_right = data->h_active - data->recout.x - 
data->recout.width;
int overscan_bottom = data->v_active - data->recout.y - 
data->recout.height;
 
-   if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) {
+   if (xfm_dce->base.ctx->dc->debug.visual_confirm != 
VISUAL_CONFIRM_DISABLE) {
overscan_bottom += 2;
overscan_right += 2;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index f0cc975..4a863a5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -621,6 +621,10 @@ static void dpp1_dscl_set_manual_ratio_init(
 static void dpp1_dscl_set_recout(
struct dcn10_dpp *dpp, const struct rect *recout)
 {
+   int visual_confirm_on = 0;
+   if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
+   visual_confirm_on = 1;
+
REG_SET_2(RECOUT_START, 0,
/* First pixel of RECOUT */
 RECOUT_START_X, recout->x,
@@ -632,8 +636,7 @@ static void dpp1_dscl_set_recout(
 RECOUT_WIDTH, recout->width,
/* Number of RECOUT vertical lines */
 RECOUT_HEIGHT, recout->height
-- dpp->base.ctx->dc->debug.surface_visual_confirm * 4 *
-(dpp->base.inst + 1));
+- visual_confirm_on * 4 * (dpp->base.inst + 1));
 }
 
 /* Main function to program scaler and line bu

[PATCH 03/10] drm/amd/display: Handle HDR meta update as fast update

[sunpeng.li]

From: Krunoslav Kovac 

[Why]
Vesa DPMS tool sends different HDR meta in OS flips without changing output
parameters. We don't properly update HDR info frame:
- we label HDR meta update as fast update
- when updating HW info frame, we only do it if full update

[How]
It should still be fast update, so when doing HW infoframe update,
do it always no matter the update type.
Also, don't request passive flip for HDR meta update only without output
transfer function or color space changed.

Change-Id: I666566c887d3a5c33bcdd2d1950c0a50c7e845bf
Signed-off-by: Krunoslav Kovac 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f02d92c..8fbe586 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1345,6 +1345,13 @@ static void commit_planes_do_stream_update(struct dc *dc,
pipe_ctx->stream_res.tg, 
&pipe_ctx->stream->timing,

pipe_ctx->stream->periodic_fn_vsync_delta);
 
+   if (stream_update->hdr_static_metadata ||
+   stream_update->vrr_infopacket ||
+   stream_update->vsc_infopacket) {
+   resource_build_info_frame(pipe_ctx);
+   dc->hwss.update_info_frame(pipe_ctx);
+   }
+
/* Full fe update*/
if (update_type == UPDATE_TYPE_FAST)
continue;
@@ -1371,13 +1378,6 @@ static void commit_planes_do_stream_update(struct dc *dc,

pipe_ctx->stream_res.abm->funcs->set_abm_level(
pipe_ctx->stream_res.abm, 
stream->abm_level);
}
-
-   if (stream_update->hdr_static_metadata ||
-   stream_update->vrr_infopacket ||
-   stream_update->vsc_infopacket) {
-   resource_build_info_frame(pipe_ctx);
-   dc->hwss.update_info_frame(pipe_ctx);
-   }
}
}
 }
-- 
2.7.4

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[PATCH 02/10] drm/amd/display: Refactor SDR cursor boosting in HDR mode

[sunpeng.li]

From: Krunoslav Kovac 

[Why]
Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP
Previous commit was implementing it in HUBP functions,
and also breaking diags tests.

[How]
1. Undo original commit as well as Eric's diags test fix, almost completely
2. Move programming to DPP and call via new dc_stream function
3. Also removing cur_rom_en from dpp_cursor_attributes and programming
as part of normal cursor attributes as it depends on cursor color format

Change-Id: I3bb62e8f0d67f314c79176af5ec067cc8de35b3e
Signed-off-by: Krunoslav Kovac 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|  1 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  5 
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  2 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 13 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 14 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  | 15 ---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h  | 12 +++--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 30 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h|  3 +++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  1 +
 10 files changed, 70 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 0223f48..4717330 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -214,6 +214,7 @@ bool dc_stream_set_cursor_attributes(
}
 
core_dc->hwss.set_cursor_attribute(pipe_ctx);
+   core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
}
 
if (pipe_to_program)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index e1c0af7..e9c1ec5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -500,6 +500,11 @@ struct dc_cursor_attributes {
union dc_cursor_attribute_flags attribute_flags;
 };
 
+struct dpp_cursor_attributes {
+   int bias;
+   int scale;
+};
+
 /* OPP */
 
 enum dc_color_space {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 532b2af..790beb5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -107,6 +107,7 @@ struct dc_stream_state {
 
struct dc_cursor_attributes cursor_attributes;
struct dc_cursor_position cursor_position;
+   uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
 
/* from stream struct */
struct kref refcount;
@@ -267,6 +268,7 @@ bool dc_stream_set_cursor_position(
struct dc_stream_state *stream,
const struct dc_cursor_position *position);
 
+
 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state *stream,
struct dc_crtc_timing_adjust *adjust);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index a558efa..bf8b68f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -459,6 +459,18 @@ void dpp1_set_cursor_position(
 
 }
 
+void dpp1_cnv_set_optional_cursor_attributes(
+   struct dpp *dpp_base,
+   struct dpp_cursor_attributes *attr)
+{
+   struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
+   if (attr) {
+   REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr->bias);
+   REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr->scale);
+   }
+}
+
 void dpp1_dppclk_control(
struct dpp *dpp_base,
bool dppclk_div,
@@ -499,6 +511,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
.dpp_full_bypass= dpp1_full_bypass,
.set_cursor_attributes = dpp1_set_cursor_attributes,
.set_cursor_position = dpp1_set_cursor_position,
+   .set_optional_cursor_attributes = 
dpp1_cnv_set_optional_cursor_attributes,
.dpp_dppclk_control = dpp1_dppclk_control,
.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index e862caf..e2889e6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -119,6 +119,7 @@
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
+   SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
SRI(DPP_CONTROL, DPP_TOP, id), \
SRI(CM_HDR_MULT_COEF, CM, id)
 
@@ -324,6 +325,8 @@

[PATCH 01/10] drm/amd/display: Add headers for hardcoded 1d luts.

[sunpeng.li]

From: Vitaly Prosyak 

Hard-coded luts are needed since complex algorithms are used for
color and tone mapping. Add the headers for future use.

Change-Id: Ida4288a0ded7dc21182b23d108aa1df38681d6f0
Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/modules/color/luts_1d.h| 51 ++
 1 file changed, 51 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/modules/color/luts_1d.h

diff --git a/drivers/gpu/drm/amd/display/modules/color/luts_1d.h 
b/drivers/gpu/drm/amd/display/modules/color/luts_1d.h
new file mode 100644
index 000..66b1fad
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/color/luts_1d.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef LUTS_1D_H
+#define LUTS_1D_H
+
+#include "hw_shared.h"
+
+struct point_config {
+   uint32_t custom_float_x;
+   uint32_t custom_float_y;
+   uint32_t custom_float_slope;
+};
+
+struct lut_point {
+   uint32_t red;
+   uint32_t green;
+   uint32_t blue;
+   uint32_t delta_red;
+   uint32_t delta_green;
+   uint32_t delta_blue;
+};
+
+struct pwl_1dlut_parameter {
+   struct gamma_curve  arr_curve_points[34];
+   struct point_config arr_points[2];
+   struct lut_point rgb_resulted[256];
+   uint32_t hw_points_num;
+};
+#endif // LUTS_1D_H
-- 
2.7.4

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[PATCH 00/10] DC Patches Jul 12, 2018

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

Summary of change:
* HDR debugging features
* Small bug fixes and minor cleanups

Gloria Li (1):
  drm/amd/display: add HDR visual confirm

Harry Wentland (2):
  drm/amd/display: dal 3.1.56
  drm/amd/display: Fix some checkpatch.pl errors and warnings in
dc_link_dp.c

Jun Lei (1):
  drm/amd/display: add new dc debug structure to track debug data

Krunoslav Kovac (3):
  drm/amd/display: Refactor SDR cursor boosting in HDR mode
  drm/amd/display: Handle HDR meta update as fast update
  drm/amd/display: Null ptr check for set_sdr_white_level

Nikola Cornij (1):
  drm/amd/display: Add hook for MST root branch info

Tony Cheng (1):
  drm/amd/display: Move address tracking out of HUBP

Vitaly Prosyak (1):
  drm/amd/display: Add headers for hardcoded 1d luts.

 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |  5 ++
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 14 +--
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  4 +
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 38 +
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|  2 +
 drivers/gpu/drm/amd/display/dc/dc.h| 18 +++-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  5 ++
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  2 +
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c |  2 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  2 +-
 .../drm/amd/display/dc/dce110/dce110_transform_v.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 13 +++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 14 ++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |  7 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  | 19 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h  | 12 +--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 99 --
 drivers/gpu/drm/amd/display/dc/dm_helpers.h|  8 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h|  3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h   |  1 -
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  1 +
 .../gpu/drm/amd/display/modules/color/luts_1d.h| 51 +++
 22 files changed, 251 insertions(+), 71 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/modules/color/luts_1d.h

-- 
2.7.4

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Re: [PATCH 3/3] drm/scheduler: modify args of drm_sched_entity_init

[Eric Anholt]

Nayan Deshmukh  writes:
> diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c 
> b/drivers/gpu/drm/scheduler/gpu_scheduler.c
> index 3dc1a4f07e3f..b2dbd1c1ba69 100644
> --- a/drivers/gpu/drm/scheduler/gpu_scheduler.c
> +++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
> @@ -162,26 +162,32 @@ drm_sched_rq_select_entity(struct drm_sched_rq *rq)
>   * drm_sched_entity_init - Init a context entity used by scheduler when
>   * submit to HW ring.
>   *
> - * @sched: scheduler instance
>   * @entity: scheduler entity to init
> - * @rq: the run queue this entity belongs
> + * @rq_list: the list of run queue on which jobs from this
> + *   entity can be submitted
> + * @num_rq_list: number of run queue in rq_list
>   * @guilty: atomic_t set to 1 when a job on this queue
>   *  is found to be guilty causing a timeout
>   *
> + * Note: the rq_list should have atleast one element to schedule
> + *   the entity
> + *
>   * Returns 0 on success or a negative error code on failure.
>  */
> -int drm_sched_entity_init(struct drm_gpu_scheduler *sched,
> -   struct drm_sched_entity *entity,
> -   struct drm_sched_rq *rq,
> +int drm_sched_entity_init(struct drm_sched_entity *entity,
> +   struct drm_sched_rq **rq_list,
> +   unsigned int num_rq_list,
> atomic_t *guilty)
>  {
> - if (!(sched && entity && rq))
> + if (!(entity && rq_list && num_rq_list > 0 && rq_list[0]))
>   return -EINVAL;
>  
>   memset(entity, 0, sizeof(struct drm_sched_entity));
>   INIT_LIST_HEAD(&entity->list);
> - entity->rq = rq;
> - entity->sched = sched;
> + entity->rq_list = NULL;
> + entity->rq = rq_list[0];
> + entity->sched = rq_list[0]->sched;
> + entity->num_rq_list = num_rq_list;

The API change makes sense as prep work, but I don't really like adding
the field to the struct (and changing the struct's docs for the existing
rq field) if it's going to always be NULL until a future change.

Similarly, I'd rather see patch 2 as part of a series that uses the
value.

That said, while I don't currently have a usecase for load-balancing
between entities, I may in the future, so thanks for working on this!


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Re: [PATCH 1/3] drm/scheduler: add a pointer to scheduler in the rq

[Eric Anholt]

Nayan Deshmukh  writes:

> Signed-off-by: Nayan Deshmukh 
> ---

Acked-by: Eric Anholt 


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Re: [PATCH libdrm] amdgpu: add amdgpu_bo_handle_type_kms_noimport

[Marek Olšák]

On Thu, Jul 12, 2018, 3:31 AM Michel Dänzer  wrote:

> On 2018-07-12 02:47 AM, Marek Olšák wrote:
> > From: Marek Olšák 
> >
> > ---
> >  amdgpu/amdgpu.h| 7 ++-
> >  amdgpu/amdgpu_bo.c | 4 
> >  2 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
> > index 36f91058..be83b457 100644
> > --- a/amdgpu/amdgpu.h
> > +++ b/amdgpu/amdgpu.h
> > @@ -77,21 +77,26 @@ struct drm_amdgpu_info_hw_ip;
> >   *
> >  */
> >  enum amdgpu_bo_handle_type {
> >   /** GEM flink name (needs DRM authentication, used by DRI2) */
> >   amdgpu_bo_handle_type_gem_flink_name = 0,
> >
> >   /** KMS handle which is used by all driver ioctls */
> >   amdgpu_bo_handle_type_kms = 1,
> >
> >   /** DMA-buf fd handle */
> > - amdgpu_bo_handle_type_dma_buf_fd = 2
> > + amdgpu_bo_handle_type_dma_buf_fd = 2,
> > +
> > + /** KMS handle, but re-importing as a DMABUF handle through
> > +  *  drmPrimeHandleToFD is forbidden. (Glamor does that)
> > +  */
> > + amdgpu_bo_handle_type_kms_noimport = 3,
> >  };
> >
> >  /** Define known types of GPU VM VA ranges */
> >  enum amdgpu_gpu_va_range
> >  {
> >   /** Allocate from "normal"/general range */
> >   amdgpu_gpu_va_range_general = 0
> >  };
> >
> >  enum amdgpu_sw_info {
> > diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
> > index 9e37b149..d29be244 100644
> > --- a/amdgpu/amdgpu_bo.c
> > +++ b/amdgpu/amdgpu_bo.c
> > @@ -234,20 +234,22 @@ int amdgpu_bo_export(amdgpu_bo_handle bo,
> >   case amdgpu_bo_handle_type_gem_flink_name:
> >   r = amdgpu_bo_export_flink(bo);
> >   if (r)
> >   return r;
> >
> >   *shared_handle = bo->flink_name;
> >   return 0;
> >
> >   case amdgpu_bo_handle_type_kms:
> >   amdgpu_add_handle_to_table(bo);
> > + /* fall through */
> > + case amdgpu_bo_handle_type_kms_noimport:
> >   *shared_handle = bo->handle;
> >   return 0;
>
> What is the rationale for this? I.e. why do you want to not store some
> handles in the hash table?


Because I have the option.

And how can code using
> amdgpu_bo_handle_type_kms_noimport be sure that the BO will never be
> re-imported via dma-buf?
>

That's for the user to decide and prove when it's safe.


> The experience with the previous patch has shown that it's hard to keep
> track of all possible ways in which BOs are imported, and that if we
> miss one, this breaks pretty spectacularly.
>

You are assuming that it will be used incorrectly based on your previous
bad experience. All I need to do is not to hand the handle to components
that would misuse it.

Marek


>
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
>
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[PATCH v2] drm/amdgpu: Allow to create BO lists in CS ioctl v3

[Andrey Grodzovsky]

This change is to support MESA performace optimization.
Modify CS IOCTL to allow its input as command buffer and an array of
buffer handles to create a temporay bo list and then destroy it
when IOCTL completes.
This saves on calling for BO_LIST create and destry IOCTLs in MESA
and by this improves performance.

v2: Avoid inserting the temp list into idr struct.

v3:
Remove idr alloation from amdgpu_bo_list_create.
Remove useless argument from amdgpu_cs_parser_fini
Minor cosmetic stuff.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 
 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 90 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 48 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 +-
 include/uapi/drm/amdgpu_drm.h   |  1 +
 5 files changed, 111 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f..44975c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -732,6 +732,16 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
 struct list_head *validated);
 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
+int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,
+ struct drm_amdgpu_bo_list_entry 
**info_param);
+
+int amdgpu_bo_list_create(struct amdgpu_device *adev,
+struct drm_file *filp,
+struct drm_amdgpu_bo_list_entry *info,
+unsigned num_entries,
+struct amdgpu_bo_list **list);
+
+void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id);
 
 /*
  * GFX stuff
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 92be7f6..13e8cdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -55,15 +55,15 @@ static void amdgpu_bo_list_release_rcu(struct kref *ref)
kfree_rcu(list, rhead);
 }
 
-static int amdgpu_bo_list_create(struct amdgpu_device *adev,
+int amdgpu_bo_list_create(struct amdgpu_device *adev,
 struct drm_file *filp,
 struct drm_amdgpu_bo_list_entry *info,
 unsigned num_entries,
-int *id)
+struct amdgpu_bo_list **list_out)
 {
-   int r;
-   struct amdgpu_fpriv *fpriv = filp->driver_priv;
struct amdgpu_bo_list *list;
+   int r;
+
 
list = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL);
if (!list)
@@ -78,20 +78,11 @@ static int amdgpu_bo_list_create(struct amdgpu_device *adev,
return r;
}
 
-   /* idr alloc should be called only after initialization of bo list. */
-   mutex_lock(&fpriv->bo_list_lock);
-   r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
-   mutex_unlock(&fpriv->bo_list_lock);
-   if (r < 0) {
-   amdgpu_bo_list_free(list);
-   return r;
-   }
-   *id = r;
-
+   *list_out = list;
return 0;
 }
 
-static void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id)
+void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id)
 {
struct amdgpu_bo_list *list;
 
@@ -263,55 +254,79 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list)
kfree(list);
 }
 
-int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
-   struct drm_file *filp)
+int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,
+ struct drm_amdgpu_bo_list_entry 
**info_param)
 {
+   const void __user *uptr = u64_to_user_ptr(in->bo_info_ptr);
const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);
-
-   struct amdgpu_device *adev = dev->dev_private;
-   struct amdgpu_fpriv *fpriv = filp->driver_priv;
-   union drm_amdgpu_bo_list *args = data;
-   uint32_t handle = args->in.list_handle;
-   const void __user *uptr = u64_to_user_ptr(args->in.bo_info_ptr);
-
struct drm_amdgpu_bo_list_entry *info;
-   struct amdgpu_bo_list *list;
-
int r;
 
-   info = kvmalloc_array(args->in.bo_number,
-sizeof(struct drm_amdgpu_bo_list_entry), 
GFP_KERNEL);
+   info = kvmalloc_array(in->bo_number, info_size, GFP_KERNEL);
if (!info)
return -ENOMEM;
 
/* copy the handle array from userspace to a kernel buffer */
r = -EFAULT;
-   if (likely(info_size == args->in.bo_info_size)) {
-   unsigned long bytes = args->in.bo_number *
-   args->in.bo_info_size;
+   if

GTT memory usage overflow

[sunnanyong]

Hi All,
 When the gtt memory is used up, application continues to use gtt , then 
the gtt will overflow,
the gtt available will be negative(cat /sys/kernel/debug/dri/1/amdgpu_gtt_mm), 
and more system memory is used as GTT, is it normal?
My kernel  is newest v4.18 master,  I add "cma=0 amdgpu.gttsize=24576" in 
kernel boot cmdline.

Please help, Thanks : )
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Re: DEBUG_LOCKS_WARN_ON(sem->owner != ((struct task_struct *)(1UL << 0)))

[Felix Kuehling]

[+Pan Xinhui]

On 2018-07-12 03:16 AM, Michel Dänzer wrote:
> On 2018-07-12 02:43 AM, Felix Kuehling wrote:
>> Kent just caught a similar backtrace in one of our KFD pre-submission
>> tests (see below)
> Yeah, looks the same.
>
>
>> Neither KFD nor AMDGPU are implied in the backtrace. Is this a
>> regression in the kernel itself? amd-kfd-staging is currently based on
>> 4.18-rc1.
> FWIW, I saw this with 4.17 based kernels already, and I didn't have
> CONFIG_DEBUG_RWSEMS enabled with older kernels, so I'm not sure it's a
> (recent) regression.

I've now also seen it on Oded's branch (4.17-rc5). It is reproduced
reliably by a new test that Pan Xinhui just added to our kfdtest
(KFDMemoryTest.MMapLarge).

Regards,
  Felix


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Re: [PATCH] drm/amdgpu: fix TTM move entity init order

[Alex Deucher]

On Thu, Jul 12, 2018 at 8:33 AM, Christian König
 wrote:
> We are initializing the entity before the scheduler is actually
> initialized.
>
> This can lead to all kind of problem, but especially NULL pointer deref
> because of Nayan's scheduler work.
>
> Signed-off-by: Christian König 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 36 
> ++---
>  1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 2a0e1b4752ff..11a12483c995 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -104,8 +104,6 @@ static void amdgpu_ttm_mem_global_release(struct 
> drm_global_reference *ref)
>  static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
>  {
> struct drm_global_reference *global_ref;
> -   struct amdgpu_ring *ring;
> -   struct drm_sched_rq *rq;
> int r;
>
> /* ensure reference is false in case init fails */
> @@ -138,21 +136,10 @@ static int amdgpu_ttm_global_init(struct amdgpu_device 
> *adev)
>
> mutex_init(&adev->mman.gtt_window_lock);
>
> -   ring = adev->mman.buffer_funcs_ring;
> -   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> -   r = drm_sched_entity_init(&adev->mman.entity,
> - &rq, 1, NULL);
> -   if (r) {
> -   DRM_ERROR("Failed setting up TTM BO move run queue.\n");
> -   goto error_entity;
> -   }
> -
> adev->mman.mem_global_referenced = true;
>
> return 0;
>
> -error_entity:
> -   drm_global_item_unref(&adev->mman.bo_global_ref.ref);
>  error_bo:
> drm_global_item_unref(&adev->mman.mem_global_ref);
>  error_mem:
> @@ -162,8 +149,6 @@ static int amdgpu_ttm_global_init(struct amdgpu_device 
> *adev)
>  static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
>  {
> if (adev->mman.mem_global_referenced) {
> -   drm_sched_entity_destroy(adev->mman.entity.sched,
> - &adev->mman.entity);
> mutex_destroy(&adev->mman.gtt_window_lock);
> drm_global_item_unref(&adev->mman.bo_global_ref.ref);
> drm_global_item_unref(&adev->mman.mem_global_ref);
> @@ -1921,10 +1906,29 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
> amdgpu_device *adev, bool enable)
>  {
> struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
> uint64_t size;
> +   int r;
>
> -   if (!adev->mman.initialized || adev->in_gpu_reset)
> +   if (!adev->mman.initialized || adev->in_gpu_reset ||
> +   adev->mman.buffer_funcs_enabled == enable)
> return;
>
> +   if (enable) {
> +   struct amdgpu_ring *ring;
> +   struct drm_sched_rq *rq;
> +
> +   ring = adev->mman.buffer_funcs_ring;
> +   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> +   r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
> +   if (r) {
> +   DRM_ERROR("Failed setting up TTM BO move entity 
> (%d)\n",
> + r);
> +   return;
> +   }
> +   } else {
> +   drm_sched_entity_destroy(adev->mman.entity.sched,
> +&adev->mman.entity);
> +   }
> +
> /* this just adjusts TTM size idea, which sets lpfn to the correct 
> value */
> if (enable)
> size = adev->gmc.real_vram_size;
> --
> 2.14.1
>
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Re: [PATCH] amd/dc/dce100: On dce100, set clocks to 0 on suspend

[Harry Wentland]

On 2018-07-12 10:29 AM, Francis, David wrote:
> Upon closer inspection, this does not match any FDO bug.  The FDO bug I 
> thought this was related to was fixed by Michel Danzer, and this fixes an 
> entirely separate issue.
> 

If I remember right we have a regression change for this. We should add that 
with the Fixes tag like so

Fixes: 308425ff39dc ("drm/amd/display: redesign dce/dcn clock voltage update 
request")

Looks like it's not in any kernel tag yet, so no need to add stable like I 
previously thought.

Harry

> --
> *From:* Michel Dänzer 
> *Sent:* July 12, 2018 10:18:34 AM
> *To:* Wentland, Harry; Francis, David; amd-gfx@lists.freedesktop.org
> *Subject:* Re: [PATCH] amd/dc/dce100: On dce100, set clocks to 0 on suspend
>  
> On 2018-07-12 04:13 PM, Harry Wentland wrote:
>> On 2018-07-12 10:07 AM, David Francis wrote:
>>> [Why]
>>> When a dce100 asic was suspended, the clocks were not set to 0.
>>> Upon resume, the new clock was compared to the existing clock,
>>> they were found to be the same, and so the clock was not set.
>>> This resulted in a pernicious blackscreen.
>>>
>>> [How]
>>> In atomic commit, check to see if there are any active pipes.
>>> If no, set clocks to 0
>>>
>> 
>> Please add Fixes: tag with link to freedesktop bugzilla bug that this fixes.
> 
> That would be
> 
> Bugzilla: https://...
> 
> (the Fixes tag is for referencing another commit which is fixed by this one)
> 
> 
> -- 
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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[PATCH 2/4] drm/amdgpu/pp/smu7: drop unused values in smu data structure

[Alex Deucher]

use kaddr directly rather than secondary variable.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 3 +--
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 2 --
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 9f407c48d4f0..0f11c5341c49 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -422,7 +422,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
   + UCODE_ID_CP_MEC_JT2_MASK;
}
 
-   toc = (struct SMU_DRAMData_TOC *)smu_data->header;
+   toc = (struct SMU_DRAMData_TOC *)smu_data->header_buffer.kaddr;
toc->structure_version = 1;
 
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
@@ -591,7 +591,6 @@ int smu7_init(struct pp_hwmgr *hwmgr)
if (r)
return -EINVAL;
 
-   smu_data->header = smu_data->header_buffer.kaddr;
smu_data->header_buffer.mc_addr = mc_addr;
 
if (!hwmgr->not_vf)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
index 39c9bfda0ab4..e6def283b731 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
@@ -37,8 +37,6 @@ struct smu7_buffer_entry {
 };
 
 struct smu7_smumgr {
-   uint8_t *header;
-   uint8_t *mec_image;
struct smu7_buffer_entry smu_buffer;
struct smu7_buffer_entry header_buffer;
 
-- 
2.13.6

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[PATCH 3/4] drm/amdgpu/pp/smu7: remove local mc_addr variable

[Alex Deucher]

use the structure member directly.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 0f11c5341c49..cb5da61f214b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -571,7 +571,6 @@ int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)
 int smu7_init(struct pp_hwmgr *hwmgr)
 {
struct smu7_smumgr *smu_data;
-   uint64_t mc_addr = 0;
int r;
/* Allocate memory for backend private data */
smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
@@ -585,14 +584,12 @@ int smu7_init(struct pp_hwmgr *hwmgr)
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&smu_data->header_buffer.handle,
-   &mc_addr,
+   &smu_data->header_buffer.mc_addr,
&smu_data->header_buffer.kaddr);
 
if (r)
return -EINVAL;
 
-   smu_data->header_buffer.mc_addr = mc_addr;
-
if (!hwmgr->not_vf)
return 0;
 
@@ -602,7 +599,7 @@ int smu7_init(struct pp_hwmgr *hwmgr)
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&smu_data->smu_buffer.handle,
-   &mc_addr,
+   &smu_data->smu_buffer.mc_addr,
&smu_data->smu_buffer.kaddr);
 
if (r) {
@@ -611,7 +608,6 @@ int smu7_init(struct pp_hwmgr *hwmgr)
&smu_data->header_buffer.kaddr);
return -EINVAL;
}
-   smu_data->smu_buffer.mc_addr = mc_addr;
 
if (smum_is_hw_avfs_present(hwmgr))
hwmgr->avfs_supported = true;
-- 
2.13.6

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[PATCH 4/4] drm/amdgpu/pp/smu7: cache smu firmware toc

[Alex Deucher]

Rather than calculating it everytime we rebuild the toc
buffer, calculate it once initially and then just copy
the cached results to the vram buffer.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 92 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h |  1 +
 2 files changed, 54 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index cb5da61f214b..a029e47c2319 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -379,9 +379,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
 {
struct smu7_smumgr *smu_data = (struct smu7_smumgr 
*)(hwmgr->smu_backend);
uint32_t fw_to_load;
-   int result = 0;
-   struct SMU_DRAMData_TOC *toc;
-   uint32_t num_entries = 0;
+   int r = 0;
 
if (!hwmgr->reload_fw) {
pr_info("skip reloading...\n");
@@ -422,49 +420,62 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
   + UCODE_ID_CP_MEC_JT2_MASK;
}
 
-   toc = (struct SMU_DRAMData_TOC *)smu_data->header_buffer.kaddr;
-   toc->structure_version = 1;
-
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_RLC_G, &toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_CE, &toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_PFP, &toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_ME, &toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC, &toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC_JT1, 
&toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC_JT2, 
&toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_SDMA0, &toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_SDMA1, &toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
-   if (!hwmgr->not_vf)
-   PP_ASSERT_WITH_CODE(0 == 
smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_MEC_STORAGE, 
&toc->entry[num_entries++]),
-   "Failed to Get Firmware Entry.", return 
-EINVAL);
+   if (!smu_data->toc) {
+   struct SMU_DRAMData_TOC *toc;
 
-   toc->num_entries = num_entries;
+   smu_data->toc = kzalloc(sizeof(struct SMU_DRAMData_TOC), 
GFP_KERNEL);
+   if (!smu_data->toc)
+   return -ENOMEM;
+   toc = smu_data->toc;
+   toc->num_entries = 0;
+   toc->structure_version = 1;
+
+   PP_ASSERT_WITH_CODE(0 == 
smu7_populate_single_firmware_entry(hwmgr,
+   UCODE_ID_RLC_G, 
&toc->entry[toc->num_entries++]),
+   "Failed to Get Firmware Entry.", r = -EINVAL; 
goto failed);
+   PP_ASSERT_WITH_CODE(0 == 
smu7_populate_single_firmware_entry(hwmgr,
+   UCODE_ID_CP_CE, 
&toc->entry[toc->num_entries++]),
+   "Failed to Get Firmware Entry.", r = -EINVAL; 
goto failed);
+   PP_ASSERT_WITH_CODE(0 == 
smu7_populate_single_firmware_entry(hwmgr,
+   UCODE_ID_CP_PFP, 
&toc->entry[toc->num_entries++]),
+   "Failed to Get Firmware Entry.", r = -EINVAL; 
goto failed);
+   PP_ASSERT_WITH_CODE(0 == 
smu7_populate_single_firmware_entry(hwmgr,
+  

[PATCH 1/4] drm/amdgpu/pp/smu7: use a local variable for toc indexing

[Alex Deucher]

Rather than using the index variable stored in vram.  If
the device fails to come back online after a resume cycle,
reads from vram will return all 1s which will cause a
segfault. Based on a patch from Thomas Martitz .
This avoids the segfault, but we still need to sort out
why the GPU does not come back online after a resume.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 23 +++---
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index d644a9bb9078..9f407c48d4f0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -381,6 +381,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
uint32_t fw_to_load;
int result = 0;
struct SMU_DRAMData_TOC *toc;
+   uint32_t num_entries = 0;
 
if (!hwmgr->reload_fw) {
pr_info("skip reloading...\n");
@@ -422,41 +423,41 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
}
 
toc = (struct SMU_DRAMData_TOC *)smu_data->header;
-   toc->num_entries = 0;
toc->structure_version = 1;
 
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_RLC_G, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_RLC_G, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_CE, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_CE, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_PFP, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_PFP, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_ME, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_ME, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_MEC, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC_JT1, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_MEC_JT1, 
&toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_CP_MEC_JT2, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_CP_MEC_JT2, 
&toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_SDMA0, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_SDMA0, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_SDMA1, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_SDMA1, &toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
if (!hwmgr->not_vf)
PP_ASSERT_WITH_CODE(0 == 
smu7_populate_single_firmware_entry(hwmgr,
-   UCODE_ID_MEC_STORAGE, 
&toc->entry[toc->num_entries++]),
+   UCODE_ID_MEC_STORAGE, 
&toc->entry[num_entries++]),
"Failed to Get Firmware Entry.", return 
-EINVAL);
 
+   toc->num_entries = num_entries;
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, 
upper_32_bits(smu_data->header_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, 
lower_32_bits(smu_data->header_buffer.mc_addr));
 
-- 
2.13.6

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[PATCH v2 3/3] drm/amdgpu: Warn and update pin_size values when destroying a pinned BO

[Michel Dänzer]

From: Michel Dänzer 

This shouldn't happen, but if it does, we'll get a backtrace of the
caller, and update the pin_size values as needed.

v2:
* Check bo->pin_count instead of placement flags (Christian König)

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 32 +-
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1fd83ed175fa..b12526ce1a9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -63,11 +63,35 @@ static bool amdgpu_need_backup(struct amdgpu_device *adev)
return true;
 }
 
+/**
+ * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting
+ *
+ * @bo: &amdgpu_bo buffer object
+ *
+ * This function is called when a BO stops being pinned, and updates the
+ * &amdgpu_device pin_size values accordingly.
+ */
+static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo)
+{
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+   if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
+   atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
+   atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
+&adev->visible_pin_size);
+   } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
+   atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
+   }
+}
+
 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
 
+   if (WARN_ON_ONCE(bo->pin_count > 0))
+   amdgpu_bo_subtract_pin_size(bo);
+
if (bo->kfd_bo)
amdgpu_amdkfd_unreserve_system_memory_limit(bo);
 
@@ -968,13 +992,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
if (bo->pin_count)
return 0;
 
-   if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
-   atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
-   atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
-&adev->visible_pin_size);
-   } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
-   atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
-   }
+   amdgpu_bo_subtract_pin_size(bo);
 
for (i = 0; i < bo->placement.num_placement; i++) {
bo->placements[i].lpfn = 0;
-- 
2.18.0

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[PATCH v2 1/3] drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

[Michel Dänzer]

From: Michel Dänzer 

Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

v2:
* Also change amdgpu_vram_mgr_bo_invisible_size to
  amdgpu_vram_mgr_bo_visible_size, allowing further simplification
  (Christian König)

Cc: sta...@vger.kernel.org
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c  |  5 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 20 
 5 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f4db10..77ab06bf26d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1593,7 +1593,7 @@ struct amdgpu_device {
 
/* tracking pinned memory */
u64 vram_pin_size;
-   u64 invisible_pin_size;
+   u64 visible_pin_size;
u64 gart_pin_size;
 
/* amdkfd interface */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d041dddaad0c..b1ea43ee8b87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -504,7 +504,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
vram_gtt.vram_size = adev->gmc.real_vram_size;
vram_gtt.vram_size -= adev->vram_pin_size;
vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
-   vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - 
adev->invisible_pin_size);
+   vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= adev->gart_pin_size;
@@ -525,8 +525,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
mem.cpu_accessible_vram.total_heap_size =
adev->gmc.visible_vram_size;
mem.cpu_accessible_vram.usable_heap_size =
-   adev->gmc.visible_vram_size -
-   (adev->vram_pin_size - adev->invisible_pin_size);
+   adev->gmc.visible_vram_size - adev->visible_pin_size;
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9ee678d63890..f0239feceab4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -917,7 +917,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
adev->vram_pin_size += amdgpu_bo_size(bo);
-   adev->invisible_pin_size += 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size += amdgpu_vram_mgr_bo_visible_size(bo);
} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
adev->gart_pin_size += amdgpu_bo_size(bo);
}
@@ -969,7 +969,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 
if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
adev->vram_pin_size -= amdgpu_bo_size(bo);
-   adev->invisible_pin_size -= 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size -= amdgpu_vram_mgr_bo_visible_size(bo);
} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
adev->gart_pin_size -= amdgpu_bo_size(bo);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index e5da4654b630..8b3cc6687769 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -73,7 +73,7 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
 uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
 int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
 
-u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo);
+u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
 uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
 uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index f7a4bd5885a3..9cfa8a9ada92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -97,33 +97,29 @@ static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device 
*adev,
 }
 
 /**
- * amdgpu_vram_mgr_bo_invisible_

[PATCH v2 2/3] drm/amdgpu: Make pin_size values atomic

[Michel Dänzer]

From: Michel Dänzer 

Concurrent execution of the non-atomic arithmetic could result in
completely bogus values.

v2:
* Rebased on v2 of the previous patch

Cc: sta...@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106872
Reviewed-by: Christian König  # v1
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 22 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 14 --
 4 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 77ab06bf26d5..f00be3d80aa4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1592,9 +1592,9 @@ struct amdgpu_device {
DECLARE_HASHTABLE(mn_hash, 7);
 
/* tracking pinned memory */
-   u64 vram_pin_size;
-   u64 visible_pin_size;
-   u64 gart_pin_size;
+   atomic64_t vram_pin_size;
+   atomic64_t visible_pin_size;
+   atomic64_t gart_pin_size;
 
/* amdkfd interface */
struct kfd_dev  *kfd;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 9881a1e55df3..5a2a5ba29f9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -262,7 +262,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct 
amdgpu_device *adev,
return;
}
 
-   total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;
+   total_vram = adev->gmc.real_vram_size - 
atomic64_read(&adev->vram_pin_size);
used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index b1ea43ee8b87..258b6f73cbdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -501,13 +501,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
case AMDGPU_INFO_VRAM_GTT: {
struct drm_amdgpu_info_vram_gtt vram_gtt;
 
-   vram_gtt.vram_size = adev->gmc.real_vram_size;
-   vram_gtt.vram_size -= adev->vram_pin_size;
-   vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
-   vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
+   vram_gtt.vram_size = adev->gmc.real_vram_size -
+   atomic64_read(&adev->vram_pin_size);
+   vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size 
-
+   atomic64_read(&adev->visible_pin_size);
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
-   vram_gtt.gtt_size -= adev->gart_pin_size;
+   vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
return copy_to_user(out, &vram_gtt,
min((size_t)size, sizeof(vram_gtt))) ? 
-EFAULT : 0;
}
@@ -516,16 +516,16 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
 
memset(&mem, 0, sizeof(mem));
mem.vram.total_heap_size = adev->gmc.real_vram_size;
-   mem.vram.usable_heap_size =
-   adev->gmc.real_vram_size - adev->vram_pin_size;
+   mem.vram.usable_heap_size = adev->gmc.real_vram_size -
+   atomic64_read(&adev->vram_pin_size);
mem.vram.heap_usage =

amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 
mem.cpu_accessible_vram.total_heap_size =
adev->gmc.visible_vram_size;
-   mem.cpu_accessible_vram.usable_heap_size =
-   adev->gmc.visible_vram_size - adev->visible_pin_size;
+   mem.cpu_accessible_vram.usable_heap_size = 
adev->gmc.visible_vram_size -
+   atomic64_read(&adev->visible_pin_size);
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
@@ -533,8 +533,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
 
mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
mem.gtt.total_heap_size *= PAGE_SIZE;
-   mem.gtt.usable_heap_size = mem.gtt.total_heap_size
-   - adev->gart_pin_size;
+   mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
+   atomic64_read(&adev->gart_pin_size);
  

Re: [PATCH] amd/dc/dce100: On dce100, set clocks to 0 on suspend

[Francis, David]

Upon closer inspection, this does not match any FDO bug.  The FDO bug I thought 
this was related to was fixed by Michel Danzer, and this fixes an entirely 
separate issue.


From: Michel Dänzer 
Sent: July 12, 2018 10:18:34 AM
To: Wentland, Harry; Francis, David; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] amd/dc/dce100: On dce100, set clocks to 0 on suspend

On 2018-07-12 04:13 PM, Harry Wentland wrote:
> On 2018-07-12 10:07 AM, David Francis wrote:
>> [Why]
>> When a dce100 asic was suspended, the clocks were not set to 0.
>> Upon resume, the new clock was compared to the existing clock,
>> they were found to be the same, and so the clock was not set.
>> This resulted in a pernicious blackscreen.
>>
>> [How]
>> In atomic commit, check to see if there are any active pipes.
>> If no, set clocks to 0
>>
>
> Please add Fixes: tag with link to freedesktop bugzilla bug that this fixes.

That would be

Bugzilla: https://...

(the Fixes tag is for referencing another commit which is fixed by this one)


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Libre software enthusiast | Mesa and X developer
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[PATCH v3] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Harry Wentland]

The driver is expecting clock frequency in kHz, while SMU returns
the values in 10kHz, which causes the bandwidth validation to fail

4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
only, which is only used by Vega. Make sure we multiply these values
by 10 here, as we do for other ASICs as powerplay assigned them
wrong. 4.19 has the proper fix in powerplay.

v2: Add Fixes tag
v3: Fixes -> Bugzilla, with simplified link

Bugzilla: https://bugs.freedesktop.org/107082

Signed-off-by: Mikita Lipski 
Signed-off-by: Harry Wentland 
Acked-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5a3346124a01..5a2e952c5bea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
for (i = 0; i < clk_level_info->num_levels; i++) {
-   DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz;
+   DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", 
pp_clks->data[i].clocks_in_khz);
+   /* translate 10kHz to kHz */
+   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz * 10;
clk_level_info->data[i].latency_in_us = 
pp_clks->data[i].latency_in_us;
}
 }
-- 
2.17.1

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Re: [PATCH v2] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Nicholas Kazlauskas]

This does get called from both dce120 and dce112, but it will also any 
fix any problems for dce112 as well. Looks fine to me.


Reviewed-by: Nicholas Kazlauskas 

Nicholas Kazlauskas

On 07/12/2018 10:09 AM, Harry Wentland wrote:

The driver is expecting clock frequency in kHz, while SMU returns
the values in 10kHz, which causes the bandwidth validation to fail

4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
only, which is only used by Vega. Make sure we multiply these values
by 10 here, as we do for other ASICs as powerplay assigned them
wrong. 4.19 has the proper fix in powerplay.

v2: Add Fixes tag

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=107082

Signed-off-by: Mikita Lipski 
Signed-off-by: Harry Wentland 
---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5a3346124a01..5a2e952c5bea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
  
  	for (i = 0; i < clk_level_info->num_levels; i++) {

-   DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz;
+   DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", 
pp_clks->data[i].clocks_in_khz);
+   /* translate 10kHz to kHz */
+   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz * 10;
clk_level_info->data[i].latency_in_us = 
pp_clks->data[i].latency_in_us;
}
  }


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Re: [PATCH v2] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Michel Dänzer]

On 2018-07-12 04:09 PM, Harry Wentland wrote:
> The driver is expecting clock frequency in kHz, while SMU returns
> the values in 10kHz, which causes the bandwidth validation to fail
> 
> 4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
> only, which is only used by Vega. Make sure we multiply these values
> by 10 here, as we do for other ASICs as powerplay assigned them
> wrong. 4.19 has the proper fix in powerplay.
> 
> v2: Add Fixes tag
> 
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=107082

Bugzilla: https://bugs.freedesktop.org/107082

With that fixed,

Acked-by: Michel Dänzer 


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Re: [PATCH] amd/dc/dce100: On dce100, set clocks to 0 on suspend

[Michel Dänzer]

On 2018-07-12 04:13 PM, Harry Wentland wrote:
> On 2018-07-12 10:07 AM, David Francis wrote:
>> [Why]
>> When a dce100 asic was suspended, the clocks were not set to 0.
>> Upon resume, the new clock was compared to the existing clock,
>> they were found to be the same, and so the clock was not set.
>> This resulted in a pernicious blackscreen.
>>
>> [How]
>> In atomic commit, check to see if there are any active pipes.
>> If no, set clocks to 0
>>
> 
> Please add Fixes: tag with link to freedesktop bugzilla bug that this fixes.

That would be

Bugzilla: https://...

(the Fixes tag is for referencing another commit which is fixed by this one)


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Re: [PATCH] amd/dc/dce100: On dce100, set clocks to 0 on suspend

[Harry Wentland]

On 2018-07-12 10:07 AM, David Francis wrote:
> [Why]
> When a dce100 asic was suspended, the clocks were not set to 0.
> Upon resume, the new clock was compared to the existing clock,
> they were found to be the same, and so the clock was not set.
> This resulted in a pernicious blackscreen.
> 
> [How]
> In atomic commit, check to see if there are any active pipes.
> If no, set clocks to 0
> 

Please add Fixes: tag with link to freedesktop bugzilla bug that this fixes.

I believe the issue is older than 4.18. Can you confirm? If so, please add

Cc: sta...@vger.kernel.org

Harry

> Signed-off-by: David Francis 
> ---
>  .../amd/display/dc/dce100/dce100_resource.c   | 19 ---
>  1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> index 8ed8eace42be..ad8ad4e1437c 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> @@ -678,9 +678,22 @@ bool dce100_validate_bandwidth(
>   struct dc  *dc,
>   struct dc_state *context)
>  {
> - /* TODO implement when needed but for now hardcode max value*/
> - context->bw.dce.dispclk_khz = 681000;
> - context->bw.dce.yclk_khz = 25 * MEMORY_TYPE_MULTIPLIER;
> + int i;
> + bool at_least_one_pipe = false;
> +
> + for (i = 0; i < dc->res_pool->pipe_count; i++) {
> + if (context->res_ctx.pipe_ctx[i].stream)
> + at_least_one_pipe = true;
> + }
> +
> + if (at_least_one_pipe) {
> + /* TODO implement when needed but for now hardcode max value*/
> + context->bw.dce.dispclk_khz = 681000;
> + context->bw.dce.yclk_khz = 25 * MEMORY_TYPE_MULTIPLIER;
> + } else {
> + context->bw.dce.dispclk_khz = 0;
> + context->bw.dce.yclk_khz = 0;
> + }
>  
>   return true;
>  }
> 
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[PATCH v2] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Harry Wentland]

The driver is expecting clock frequency in kHz, while SMU returns
the values in 10kHz, which causes the bandwidth validation to fail

4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
only, which is only used by Vega. Make sure we multiply these values
by 10 here, as we do for other ASICs as powerplay assigned them
wrong. 4.19 has the proper fix in powerplay.

v2: Add Fixes tag

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=107082

Signed-off-by: Mikita Lipski 
Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5a3346124a01..5a2e952c5bea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
for (i = 0; i < clk_level_info->num_levels; i++) {
-   DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz;
+   DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", 
pp_clks->data[i].clocks_in_khz);
+   /* translate 10kHz to kHz */
+   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz * 10;
clk_level_info->data[i].latency_in_us = 
pp_clks->data[i].latency_in_us;
}
 }
-- 
2.17.1

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[PATCH] amd/dc/dce100: On dce100, set clocks to 0 on suspend

[David Francis]

[Why]
When a dce100 asic was suspended, the clocks were not set to 0.
Upon resume, the new clock was compared to the existing clock,
they were found to be the same, and so the clock was not set.
This resulted in a pernicious blackscreen.

[How]
In atomic commit, check to see if there are any active pipes.
If no, set clocks to 0

Signed-off-by: David Francis 
---
 .../amd/display/dc/dce100/dce100_resource.c   | 19 ---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 8ed8eace42be..ad8ad4e1437c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -678,9 +678,22 @@ bool dce100_validate_bandwidth(
struct dc  *dc,
struct dc_state *context)
 {
-   /* TODO implement when needed but for now hardcode max value*/
-   context->bw.dce.dispclk_khz = 681000;
-   context->bw.dce.yclk_khz = 25 * MEMORY_TYPE_MULTIPLIER;
+   int i;
+   bool at_least_one_pipe = false;
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   if (context->res_ctx.pipe_ctx[i].stream)
+   at_least_one_pipe = true;
+   }
+
+   if (at_least_one_pipe) {
+   /* TODO implement when needed but for now hardcode max value*/
+   context->bw.dce.dispclk_khz = 681000;
+   context->bw.dce.yclk_khz = 25 * MEMORY_TYPE_MULTIPLIER;
+   } else {
+   context->bw.dce.dispclk_khz = 0;
+   context->bw.dce.yclk_khz = 0;
+   }
 
return true;
 }
-- 
2.17.1

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Re: [PATCH] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Harry Wentland]

On 2018-07-12 09:58 AM, Alex Deucher wrote:
> On Thu, Jul 12, 2018 at 9:46 AM, Harry Wentland  
> wrote:
>> Fixing Nicholas's email.
>>
>> On 2018-07-12 09:36 AM, Harry Wentland wrote:
>>> The driver is expecting clock frequency in kHz, while SMU returns
>>> the values in 10kHz, which causes the bandwidth validation to fail
>>>
>>> 4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
>>> only, which is only used by Vega. Make sure we multiply these values
>>> by 10 here, as we do for other ASICs as powerplay assigned them
>>> wrong. 4.19 has the proper fix in powerplay.
>>>
>>> Signed-off-by: Mikita Lipski 
>>> Signed-off-by: Harry Wentland 
>>> ---
>>>
>>> Alex, please pull this into drm-fixes-4.18.
> 
> I assume this fixes:
> https://bugs.freedesktop.org/show_bug.cgi?id=107082 ?
> 

Correct, sending v2.

Harry

> Thanks,
> 
> Alex
> 
>>>
>>> Harry
>>>
>>>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
>>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>>> index 5a3346124a01..5a2e952c5bea 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>>> @@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
>>>   DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
>>>
>>>   for (i = 0; i < clk_level_info->num_levels; i++) {
>>> - DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
>>> - clk_level_info->data[i].clocks_in_khz = 
>>> pp_clks->data[i].clocks_in_khz;
>>> + DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", 
>>> pp_clks->data[i].clocks_in_khz);
>>> + /* translate 10kHz to kHz */
>>> + clk_level_info->data[i].clocks_in_khz = 
>>> pp_clks->data[i].clocks_in_khz * 10;
>>>   clk_level_info->data[i].latency_in_us = 
>>> pp_clks->data[i].latency_in_us;
>>>   }
>>>  }
>>>
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Re: [PATCH] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Alex Deucher]

On Thu, Jul 12, 2018 at 9:46 AM, Harry Wentland  wrote:
> Fixing Nicholas's email.
>
> On 2018-07-12 09:36 AM, Harry Wentland wrote:
>> The driver is expecting clock frequency in kHz, while SMU returns
>> the values in 10kHz, which causes the bandwidth validation to fail
>>
>> 4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
>> only, which is only used by Vega. Make sure we multiply these values
>> by 10 here, as we do for other ASICs as powerplay assigned them
>> wrong. 4.19 has the proper fix in powerplay.
>>
>> Signed-off-by: Mikita Lipski 
>> Signed-off-by: Harry Wentland 
>> ---
>>
>> Alex, please pull this into drm-fixes-4.18.

I assume this fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=107082 ?

Thanks,

Alex

>>
>> Harry
>>
>>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>> index 5a3346124a01..5a2e952c5bea 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>> @@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
>>   DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
>>
>>   for (i = 0; i < clk_level_info->num_levels; i++) {
>> - DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
>> - clk_level_info->data[i].clocks_in_khz = 
>> pp_clks->data[i].clocks_in_khz;
>> + DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", 
>> pp_clks->data[i].clocks_in_khz);
>> + /* translate 10kHz to kHz */
>> + clk_level_info->data[i].clocks_in_khz = 
>> pp_clks->data[i].clocks_in_khz * 10;
>>   clk_level_info->data[i].latency_in_us = 
>> pp_clks->data[i].latency_in_us;
>>   }
>>  }
>>
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Re: 答复: Regression with kernel 4.18 - AMD RX 550 fails IB ring test on power-up

[Luís Mendes]

Hi Jim,

Replies in between.

Regards,
Luís

On Thu, Jul 12, 2018 at 3:16 AM, jimqu  wrote:

>
>
> On 2018年07月12日 05:27, Luís Mendes wrote:
>
> Hi Jim,
>
> I followed your suggestion and was able to bisect the kernel patches.
> The offending patch is: drm/amdgpu: defer test IBs on the rings at boot
> (V3)
> commit:
>
> 2c773de2ecb8c327f2448bd1eecad224e9227087
> 
>
> After reverting this patch the IB test succeeded with kernel v4.18-rc4 on
> both systems and the amdgpu driver was correctly loaded both on SAPPHIRE
> RX550 4GB and on SAPPHIRE RX460 2GB.
>
>
> Alex, Christian, What do you think about the patch?
>
> The GPU hang remains, however.
>  I will try to configure a remote IPMI connection to see what is happening
> with the kernel boot or setup a serial console for the Kernel.
>
>
> *You can set up remote connection by ssh, and also you can add amdgpu to
> blacklist first, and manually modprobe amdgpu.*
>
R: I was able to setup a remote serial console with console=ttyS0,11520n8
kernel parameter.
Boot log follows attached as file kernel_bisected_v4.18-rc4_log.txt.
First noticeable issue seems to be:
[6.131989] amdgpu: [powerplay]
[6.131989]  last message was failed ret is 65535
...
and later hangs with:
[   33.504100] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]]
*ERROR* [CRTC:42:crtc-0] flip_done timed out
[   43.744094] [drm:drm_atomic_helper_wait_for_dependencies
[drm_kms_helper]] *ERROR* [CRTC:42:crtc-0] flip_done timed
out
[   53.984089] [drm:drm_atomic_helper_wait_for_dependencies
[drm_kms_helper]] *ERROR* [CONNECTOR:54:HDMI-A-1] flip_done timed
out
[   64.224036] [drm:drm_atomic_helper_wait_for_dependencies
[drm_kms_helper]] *ERROR* [PLANE:40:plane-4] flip_done timed
out
[   64.224141] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
amdgpu_dm_commit_planes: acrtc 0, already
busy



> *What's about xinit? What is MESA driver version on your platform?*
>
R: I am running Ubuntu 18.04 with bisected kernel 4.18-rc4 using
libdrm-2.4.92 and mesa-18.1.0.
xinit output follows attached as xinit_log.txt


>
> Thanks & Regards,
> Luís
>
> On Wed, Jul 11, 2018 at 10:56 AM, jimqu  wrote:
>
>> HI Luis,
>>
>>
>> Let us trace the issue one by one.
>>
>>
>> IB test fail:
>>
>> This should be regression issue on 4.18, you can bisect the kernel
>> patches.
>>
>> GPU hang:
>>
>> Fix IB test fail first.
>>
>>
>> Thanks
>>
>> JimQu
>>
>>
>>
>> On 2018年07月11日 17:34, Luís Mendes wrote:
>>
>> Hi Jim,
>>
>> Thanks for your interest in this issue. Actually this is a multiple
>> issue... not only the IB ring test is failing... as I am having quite some
>> trouble getting the cards SAPPHIRE RX 550 4GB on a Tyan S7025 and SAPPHIRE
>> RX 460 2GB on a TYAN S7002 to work, both systems using same Ubuntu 18.04
>> with vanilla kernel.
>>
>> *1. May you also test earlier kernel? v4.17 or v4.16.*
>> I've tested kernels v4.17.5 and v4.16.6 with same system and both are
>> able to pass the IB ring test and system boots into X using NVIDIA as the
>> display connected card.
>> dmesg log attached for kernel 4.17.5, file TYAN_S7025_kernelv4.17.5_amdgp
>> u_IB_ring_test_OK.txt.
>>
>> *2. May you test the issue only with amdgpu?*
>> - I've tested on a TYAN S7002 system with a single SAPPHIRE RX 460 2GB,
>> on-board VGA enabled and used as primary display.
>> Kernel v4.18-rc4 fails the IB ring test, system is able to enter X
>> through the on-board VGA.
>> dmesg log attached for kernel 4.18-rc4, file
>> TYAN_S7002_kernel_v4.18-rc4_IB_ring_test_fail.txt.
>>
>> - Same TYAN S7002 system, but now with on-board VGA disabled and using RX
>> 460 as display connected card.
>> Kernels v4.17.5 and v4.16.6 are able to pass the IB ring test, but GPU
>> hangs before entering X. Don't have logs for these yet.
>>
>> Regards,
>> Luís Mendes
>> Aparapi contributor and MSc Researcher
>>
>>
>>
>>
>>
>> On Wed, Jul 11, 2018 at 3:49 AM, Qu, Jim  wrote:
>>
>>> Hi Luis,
>>>
>>> 1. May you also test earlier kernel? v4.17 or v4.16.
>>> 2. May you test the issue only with amdgpu?
>>>
>>> Thanks
>>> JimQu
>>>
>>> 
>>> 发件人: amd-gfx  代表 Luís Mendes <
>>> luis.p.men...@gmail.com>
>>> 发送时间: 2018年7月11日 6:04:00
>>> 收件人: Michel Dänzer; Koenig, Christian; amd-gfx list
>>> 主题: Re: Regression with kernel 4.18 - AMD RX 550 fails IB ring test on
>>> power-up
>>>
>>> Hi,
>>>
>>> Issue remains in kernel 4.18-rc4 using SAPPHIRE RX 550 4GB.
>>>
>>> Logs follow attached.
>>>
>>> Regards,
>>> Luis
>>>
>>> On Tue, Jun 26, 2018 at 10:08 AM, Luís Mendes >> > wrote:
>>> Hi,
>>>
>>> I've tried kernel 4.18-rc2 on a system with a NVIDIA GTX 1050 Ti and an
>>> AMD RX 550 4GB and the RX 550 card is failing the IB ring test.
>>>
>>> [5.033217] [drm:gfx_v8_0_ring_test_ib [amdgpu]] *ERROR* amdgpu: ib
>>> test failed (scratch(0xC040)=0x)
>>> [5.033264] [drm:a

Re: [PATCH] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Harry Wentland]

Fixing Nicholas's email.

On 2018-07-12 09:36 AM, Harry Wentland wrote:
> The driver is expecting clock frequency in kHz, while SMU returns
> the values in 10kHz, which causes the bandwidth validation to fail
> 
> 4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
> only, which is only used by Vega. Make sure we multiply these values
> by 10 here, as we do for other ASICs as powerplay assigned them
> wrong. 4.19 has the proper fix in powerplay.
> 
> Signed-off-by: Mikita Lipski 
> Signed-off-by: Harry Wentland 
> ---
> 
> Alex, please pull this into drm-fixes-4.18.
> 
> Harry
> 
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 5a3346124a01..5a2e952c5bea 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> @@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
>   DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
>  
>   for (i = 0; i < clk_level_info->num_levels; i++) {
> - DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
> - clk_level_info->data[i].clocks_in_khz = 
> pp_clks->data[i].clocks_in_khz;
> + DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", 
> pp_clks->data[i].clocks_in_khz);
> + /* translate 10kHz to kHz */
> + clk_level_info->data[i].clocks_in_khz = 
> pp_clks->data[i].clocks_in_khz * 10;
>   clk_level_info->data[i].latency_in_us = 
> pp_clks->data[i].latency_in_us;
>   }
>  }
> 
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[PATCH] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Harry Wentland]

The driver is expecting clock frequency in kHz, while SMU returns
the values in 10kHz, which causes the bandwidth validation to fail

4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
only, which is only used by Vega. Make sure we multiply these values
by 10 here, as we do for other ASICs as powerplay assigned them
wrong. 4.19 has the proper fix in powerplay.

Signed-off-by: Mikita Lipski 
Signed-off-by: Harry Wentland 
---

Alex, please pull this into drm-fixes-4.18.

Harry

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5a3346124a01..5a2e952c5bea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
for (i = 0; i < clk_level_info->num_levels; i++) {
-   DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz;
+   DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", 
pp_clks->data[i].clocks_in_khz);
+   /* translate 10kHz to kHz */
+   clk_level_info->data[i].clocks_in_khz = 
pp_clks->data[i].clocks_in_khz * 10;
clk_level_info->data[i].latency_in_us = 
pp_clks->data[i].latency_in_us;
}
 }
-- 
2.17.1

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[PATCH] drm/amdgpu: fix TTM move entity init order

[Christian König]

We are initializing the entity before the scheduler is actually
initialized.

This can lead to all kind of problem, but especially NULL pointer deref
because of Nayan's scheduler work.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 36 ++---
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2a0e1b4752ff..11a12483c995 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -104,8 +104,6 @@ static void amdgpu_ttm_mem_global_release(struct 
drm_global_reference *ref)
 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
 {
struct drm_global_reference *global_ref;
-   struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
int r;
 
/* ensure reference is false in case init fails */
@@ -138,21 +136,10 @@ static int amdgpu_ttm_global_init(struct amdgpu_device 
*adev)
 
mutex_init(&adev->mman.gtt_window_lock);
 
-   ring = adev->mman.buffer_funcs_ring;
-   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(&adev->mman.entity,
- &rq, 1, NULL);
-   if (r) {
-   DRM_ERROR("Failed setting up TTM BO move run queue.\n");
-   goto error_entity;
-   }
-
adev->mman.mem_global_referenced = true;
 
return 0;
 
-error_entity:
-   drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 error_bo:
drm_global_item_unref(&adev->mman.mem_global_ref);
 error_mem:
@@ -162,8 +149,6 @@ static int amdgpu_ttm_global_init(struct amdgpu_device 
*adev)
 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 {
if (adev->mman.mem_global_referenced) {
-   drm_sched_entity_destroy(adev->mman.entity.sched,
- &adev->mman.entity);
mutex_destroy(&adev->mman.gtt_window_lock);
drm_global_item_unref(&adev->mman.bo_global_ref.ref);
drm_global_item_unref(&adev->mman.mem_global_ref);
@@ -1921,10 +1906,29 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 {
struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
uint64_t size;
+   int r;
 
-   if (!adev->mman.initialized || adev->in_gpu_reset)
+   if (!adev->mman.initialized || adev->in_gpu_reset ||
+   adev->mman.buffer_funcs_enabled == enable)
return;
 
+   if (enable) {
+   struct amdgpu_ring *ring;
+   struct drm_sched_rq *rq;
+
+   ring = adev->mman.buffer_funcs_ring;
+   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+   r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
+   if (r) {
+   DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
+ r);
+   return;
+   }
+   } else {
+   drm_sched_entity_destroy(adev->mman.entity.sched,
+&adev->mman.entity);
+   }
+
/* this just adjusts TTM size idea, which sets lpfn to the correct 
value */
if (enable)
size = adev->gmc.real_vram_size;
-- 
2.14.1

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Re: 答复: Regression with kernel 4.18 - AMD RX 550 fails IB ring test on power-up

[Luís Mendes]

Hi Christian,

Sure, how can I help to fix that?

Regards,
Luís

On Thu, Jul 12, 2018 at 8:13 AM, Christian König 
wrote:

> Hi Luis,
>
> well was "drm/amdgpu: defer test IBs on the rings at boot (V3)" does is
> delaying the IB test a bit and running it async to the rest of the bootup.
>
> So what most likely happens is that some hardware feature (like power or
> clock gating) which doesn't works correctly on your system kicks in and
> lets the IB test fail.
>
> It's rather likely that this problem is also responsible for the crashes
> you expect later on. So I think we should concentrate on fixing that.
>
> Regards,
> Christian.
>
>
> Am 11.07.2018 um 23:27 schrieb Luís Mendes:
>
> Hi Jim,
>
> I followed your suggestion and was able to bisect the kernel patches.
> The offending patch is: drm/amdgpu: defer test IBs on the rings at boot
> (V3)
> commit:
>
> 2c773de2ecb8c327f2448bd1eecad224e9227087
> 
>
> After reverting this patch the IB test succeeded with kernel v4.18-rc4 on
> both systems and the amdgpu driver was correctly loaded both on SAPPHIRE
> RX550 4GB and on SAPPHIRE RX460 2GB.
>
> The GPU hang remains, however.
>  I will try to configure a remote IPMI connection to see what is happening
> with the kernel boot or setup a serial console for the Kernel.
>
> Thanks & Regards,
> Luís
>
> On Wed, Jul 11, 2018 at 10:56 AM, jimqu  wrote:
>
>> HI Luis,
>>
>>
>> Let us trace the issue one by one.
>>
>>
>> IB test fail:
>>
>> This should be regression issue on 4.18, you can bisect the kernel
>> patches.
>>
>> GPU hang:
>>
>> Fix IB test fail first.
>>
>>
>> Thanks
>>
>> JimQu
>>
>>
>>
>> On 2018年07月11日 17:34, Luís Mendes wrote:
>>
>> Hi Jim,
>>
>> Thanks for your interest in this issue. Actually this is a multiple
>> issue... not only the IB ring test is failing... as I am having quite some
>> trouble getting the cards SAPPHIRE RX 550 4GB on a Tyan S7025 and SAPPHIRE
>> RX 460 2GB on a TYAN S7002 to work, both systems using same Ubuntu 18.04
>> with vanilla kernel.
>>
>> *1. May you also test earlier kernel? v4.17 or v4.16.*
>> I've tested kernels v4.17.5 and v4.16.6 with same system and both are
>> able to pass the IB ring test and system boots into X using NVIDIA as the
>> display connected card.
>> dmesg log attached for kernel 4.17.5, file TYAN_S7025_kernelv4.17.5_amdgp
>> u_IB_ring_test_OK.txt.
>>
>> *2. May you test the issue only with amdgpu?*
>> - I've tested on a TYAN S7002 system with a single SAPPHIRE RX 460 2GB,
>> on-board VGA enabled and used as primary display.
>> Kernel v4.18-rc4 fails the IB ring test, system is able to enter X
>> through the on-board VGA.
>> dmesg log attached for kernel 4.18-rc4, file
>> TYAN_S7002_kernel_v4.18-rc4_IB_ring_test_fail.txt.
>>
>> - Same TYAN S7002 system, but now with on-board VGA disabled and using RX
>> 460 as display connected card.
>> Kernels v4.17.5 and v4.16.6 are able to pass the IB ring test, but GPU
>> hangs before entering X. Don't have logs for these yet.
>>
>> Regards,
>> Luís Mendes
>> Aparapi contributor and MSc Researcher
>>
>>
>>
>>
>>
>> On Wed, Jul 11, 2018 at 3:49 AM, Qu, Jim  wrote:
>>
>>> Hi Luis,
>>>
>>> 1. May you also test earlier kernel? v4.17 or v4.16.
>>> 2. May you test the issue only with amdgpu?
>>>
>>> Thanks
>>> JimQu
>>>
>>> 
>>> 发件人: amd-gfx  代表 Luís Mendes <
>>> luis.p.men...@gmail.com>
>>> 发送时间: 2018年7月11日 6:04:00
>>> 收件人: Michel Dänzer; Koenig, Christian; amd-gfx list
>>> 主题: Re: Regression with kernel 4.18 - AMD RX 550 fails IB ring test on
>>> power-up
>>>
>>> Hi,
>>>
>>> Issue remains in kernel 4.18-rc4 using SAPPHIRE RX 550 4GB.
>>>
>>> Logs follow attached.
>>>
>>> Regards,
>>> Luis
>>>
>>> On Tue, Jun 26, 2018 at 10:08 AM, Luís Mendes >> > wrote:
>>> Hi,
>>>
>>> I've tried kernel 4.18-rc2 on a system with a NVIDIA GTX 1050 Ti and an
>>> AMD RX 550 4GB and the RX 550 card is failing the IB ring test.
>>>
>>> [5.033217] [drm:gfx_v8_0_ring_test_ib [amdgpu]] *ERROR* amdgpu: ib
>>> test failed (scratch(0xC040)=0x)
>>> [5.033264] [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* amdgpu:
>>> failed testing IB on ring 6 (-22).
>>>
>>> Please see the attached log.
>>>
>>> Regards,
>>> Luís
>>>
>>>
>>
>>
>
>
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Re: [PATCH v2] drm/amdgpu: Allow to create BO lists in CS ioctl v2

[zhoucm1]

On 2018年07月12日 15:56, Christian König wrote:

Am 12.07.2018 um 06:21 schrieb zhoucm1:
With more thinking for you performance reason, Can we go further more 
not to create temp bo list at all? directly add them into 
parser->validated list?


You still need something which is added to the parser->validated list, 
so creating the array of BOs in unavoidable.


In fact, if bo array is very long, then overhead of bo list creation 
in CS is considerable, which will double iterate all BOs compared to 
original.


From UMD perspective, they don't create bo list for every CS, they 
could use old created bo_list for next several CS, if there is a new 
bo, they just add it.


And exactly that is the failed concept of bo_lists, it is complete 
nonsense to do this.


Either you create the list of BOs from scratch for each command 
submission like Mesa does it in which is exactly the case we try to 
support efficient here.

@Kai, do you have comments for what Christian said?



Or you use per process BOs which are always valid. Something which we 
have already implemented as well.

Yes, vulkan already use it from 4.15. But pro-ogl still use bo list.


Regards,
Christian.



Thanks,
David Zhou
On 2018年07月12日 12:02, zhoucm1 wrote:



On 2018年07月12日 11:09, Zhou, David(ChunMing) wrote:

Hi Andrey,

Could you add compatibility flag or increase kms driver version? So 
that user space can keep old path when using new one.

Sorry for noise, it's already at end of path.

Regards,
David Zhou


Regards,
David Zhou

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On 
Behalf Of zhoucm1

Sent: Thursday, July 12, 2018 10:31 AM
To: Grodzovsky, Andrey ; 
amd-gfx@lists.freedesktop.org
Cc: Olsak, Marek ; Koenig, Christian 

Subject: Re: [PATCH v2] drm/amdgpu: Allow to create BO lists in CS 
ioctl v2




On 2018年07月12日 04:57, Andrey Grodzovsky wrote:

This change is to support MESA performace optimization.
Modify CS IOCTL to allow its input as command buffer and an array of
buffer handles to create a temporay bo list and then destroy it when
IOCTL completes.
This saves on calling for BO_LIST create and destry IOCTLs in MESA 
and

by this improves performance.

v2: Avoid inserting the temp list into idr struct.

Signed-off-by: Andrey Grodzovsky 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 
   drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 86 
++---

   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 51 +++--
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 +-
   include/uapi/drm/amdgpu_drm.h   |  1 +
   5 files changed, 114 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f..9b472b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -732,6 +732,17 @@ void amdgpu_bo_list_get_list(struct 
amdgpu_bo_list *list,

    struct list_head *validated);
   void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
   void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
+int amdgpu_bo_create_list_entry_array(struct 
drm_amdgpu_bo_list_in *in,

+  struct drm_amdgpu_bo_list_entry **info_param);
+
+int amdgpu_bo_list_create(struct amdgpu_device *adev,
+ struct drm_file *filp,
+ struct drm_amdgpu_bo_list_entry *info,
+ unsigned num_entries,
+ int *id,
+ struct amdgpu_bo_list **list);
+
+void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id);
      /*
    * GFX stuff
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 92be7f6..14c7c59 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -55,11 +55,12 @@ static void amdgpu_bo_list_release_rcu(struct 
kref *ref)

   kfree_rcu(list, rhead);
   }
   -static int amdgpu_bo_list_create(struct amdgpu_device *adev,
+int amdgpu_bo_list_create(struct amdgpu_device *adev,
    struct drm_file *filp,
    struct drm_amdgpu_bo_list_entry *info,
    unsigned num_entries,
- int *id)
+ int *id,
+ struct amdgpu_bo_list **list_out)
   {
   int r;
   struct amdgpu_fpriv *fpriv = filp->driver_priv; @@ -78,20 
+79,25 @@

static int amdgpu_bo_list_create(struct amdgpu_device *adev,
   return r;
   }
   +    if (id) {
   /* idr alloc should be called only after initialization of 
bo list. */

-    mutex_lock(&fpriv->bo_list_lock);
-    r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
-    mutex_unlock(&fpriv->bo_list_lock);
-    if (r < 0) {
-    amdgpu_bo_list_free(list);
-    return r;
+    mutex_lock(&fpriv->bo_list_lock);
+    r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, 
GFP_KERNEL);

+    mutex_unlock(&fp

Re: [PATCH v2] drm/amdgpu: Allow to create BO lists in CS ioctl v2

[Christian König]

Am 12.07.2018 um 06:21 schrieb zhoucm1:
With more thinking for you performance reason, Can we go further more 
not to create temp bo list at all? directly add them into 
parser->validated list?


You still need something which is added to the parser->validated list, 
so creating the array of BOs in unavoidable.


In fact, if bo array is very long, then overhead of bo list creation 
in CS is considerable, which will double iterate all BOs compared to 
original.


From UMD perspective, they don't create bo list for every CS, they 
could use old created bo_list for next several CS, if there is a new 
bo, they just add it.


And exactly that is the failed concept of bo_lists, it is complete 
nonsense to do this.


Either you create the list of BOs from scratch for each command 
submission like Mesa does it in which is exactly the case we try to 
support efficient here.


Or you use per process BOs which are always valid. Something which we 
have already implemented as well.


Regards,
Christian.



Thanks,
David Zhou
On 2018年07月12日 12:02, zhoucm1 wrote:



On 2018年07月12日 11:09, Zhou, David(ChunMing) wrote:

Hi Andrey,

Could you add compatibility flag or increase kms driver version? So 
that user space can keep old path when using new one.

Sorry for noise, it's already at end of path.

Regards,
David Zhou


Regards,
David Zhou

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On 
Behalf Of zhoucm1

Sent: Thursday, July 12, 2018 10:31 AM
To: Grodzovsky, Andrey ; 
amd-gfx@lists.freedesktop.org
Cc: Olsak, Marek ; Koenig, Christian 

Subject: Re: [PATCH v2] drm/amdgpu: Allow to create BO lists in CS 
ioctl v2




On 2018年07月12日 04:57, Andrey Grodzovsky wrote:

This change is to support MESA performace optimization.
Modify CS IOCTL to allow its input as command buffer and an array of
buffer handles to create a temporay bo list and then destroy it when
IOCTL completes.
This saves on calling for BO_LIST create and destry IOCTLs in MESA and
by this improves performance.

v2: Avoid inserting the temp list into idr struct.

Signed-off-by: Andrey Grodzovsky 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 
   drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 86 
++---

   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 51 +++--
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 +-
   include/uapi/drm/amdgpu_drm.h   |  1 +
   5 files changed, 114 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f..9b472b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -732,6 +732,17 @@ void amdgpu_bo_list_get_list(struct 
amdgpu_bo_list *list,

    struct list_head *validated);
   void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
   void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
+int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in 
*in,

+  struct drm_amdgpu_bo_list_entry **info_param);
+
+int amdgpu_bo_list_create(struct amdgpu_device *adev,
+ struct drm_file *filp,
+ struct drm_amdgpu_bo_list_entry *info,
+ unsigned num_entries,
+ int *id,
+ struct amdgpu_bo_list **list);
+
+void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id);
      /*
    * GFX stuff
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 92be7f6..14c7c59 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -55,11 +55,12 @@ static void amdgpu_bo_list_release_rcu(struct 
kref *ref)

   kfree_rcu(list, rhead);
   }
   -static int amdgpu_bo_list_create(struct amdgpu_device *adev,
+int amdgpu_bo_list_create(struct amdgpu_device *adev,
    struct drm_file *filp,
    struct drm_amdgpu_bo_list_entry *info,
    unsigned num_entries,
- int *id)
+ int *id,
+ struct amdgpu_bo_list **list_out)
   {
   int r;
   struct amdgpu_fpriv *fpriv = filp->driver_priv; @@ -78,20 
+79,25 @@

static int amdgpu_bo_list_create(struct amdgpu_device *adev,
   return r;
   }
   +    if (id) {
   /* idr alloc should be called only after initialization of 
bo list. */

-    mutex_lock(&fpriv->bo_list_lock);
-    r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
-    mutex_unlock(&fpriv->bo_list_lock);
-    if (r < 0) {
-    amdgpu_bo_list_free(list);
-    return r;
+    mutex_lock(&fpriv->bo_list_lock);
+    r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, 
GFP_KERNEL);

+    mutex_unlock(&fpriv->bo_list_lock);
+    if (r < 0) {
+    amdgpu_bo_list_free(list);
+    return r;
+    }
+    *id = r;
   }
-    *id = r;
+
+    if (list_o

Re: [PATCH 00/25] KFD fixes, robutness enhancements and cleanups

[Christian König]

Patches which don't already have my rb are Acked-by: Christian König 
.


Regards,
Christian.

Am 12.07.2018 um 04:32 schrieb Felix Kuehling:

This series fixes some KFD issues, adds robustness enhancements and
finally a few cleanups.

Patches 1-4 are important fixes.
Patches 5-8 add handling of GPU VM faults
Patches 9-22 add handling of GPU resets and detection of HWS hangs
Patches 23-25 are various cleanups

Felix Kuehling (2):
   drm/amdkfd: Reliably prevent reclaim-FS while holding DQM lock
   drm/amdkfd: Stop using GFP_NOIO explicitly

Jay Cornwall (1):
   drm/amdkfd: Fix race between scheduler and context restore

Lan Xiao (1):
   drm/amdkfd: fix zero reading of VMID and PASID for Hawaii

Moses Reuben (1):
   drm/amdkfd: When we get KFD_EVENT_TYPE_MEMORY we send the process
 SIGSEGV

Shaoyun Liu (13):
   drm/amd: Add gpu reset interfaces between amdgpu and amdkfd
   drm/amd: Add kfd ioctl defines for hw_exception event
   drm/amdkfd: Add gpu reset interface and place holder
   drm/amdgpu: Call KFD reset handlers during GPU reset
   drm/amdkfd: Implement GPU reset handlers in KFD
   drm/amdgpu: Enable the gpu reset from KFD
   drm/amdkfd: Implement hang detection in KFD and call amdgpu
   drm/amdgpu: Don't use shadow BO for compute context
   drm/amdgpu: Check NULL pointer for job before reset job's ring
   drm/amdkfd: Fix kernel queue 64 bit doorbell offset calculation
   drm/amdgpu: Avoid invalidate tlbs when gpu is on reset
   drm/amdgpu: Avoid destroy hqd when GPU is on reset
   drm/amdkfd: Add debugfs interface to trigger HWS hang

Wei Lu (1):
   drm/amdkfd: Fix error codes in kfd_get_process

Yong Zhao (4):
   drm/amdkfd: Introduce KFD module parameter halt_if_hws_hang
   drm/amdkfd: Use module parameters noretry as the internal variable
 name
   drm/amdkfd: Replace mqd with mqd_mgr as the variable name for
 mqd_manager
   drm/amdkfd: Clean up reference of radeon

shaoyunl (2):
   drm/amdgpu: get_vm_fault implementation on amdgpu side
   drm/amdkfd: Handle VM faults in KFD

  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  27 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |   9 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |  26 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  |   8 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c  |   7 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c   |  14 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   7 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h|   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  13 +-
  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  33 +-
  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  33 +-
  drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c   |  54 ++-
  drivers/gpu/drm/amd/amdkfd/cik_int.h   |   7 +-
  drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 458 +++--
  .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm  |  18 +-
  .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm  |  16 +-
  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c   |   3 +
  drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c|   1 -
  drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h|  37 ++
  drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c   |  48 +++
  drivers/gpu/drm/amd/amdkfd/kfd_device.c|  94 -
  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 247 ++-
  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  26 +-
  .../drm/amd/amdkfd/kfd_device_queue_manager_v9.c   |   2 +-
  drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c  |   9 +-
  drivers/gpu/drm/amd/amdkfd/kfd_events.c|  71 
  drivers/gpu/drm/amd/amdkfd/kfd_events.h|   1 +
  drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c|  22 +-
  drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c |   6 +-
  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c  |  17 +-
  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h  |   2 +-
  drivers/gpu/drm/amd/amdkfd/kfd_module.c|  16 +-
  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c   |   2 +-
  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c|   4 +-
  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c|   2 +-
  drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c|  26 ++
  drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  34 +-
  drivers/gpu/drm/amd/amdkfd/kfd_process.c   |   2 +
  .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  10 +-
  drivers/gpu/drm/amd/include/kgd_kfd_interface.h|  35 ++
  include/uapi/linux/kfd_ioctl.h |  22 +-
  41 files changed, 1081 insertions(+), 390 deletions(-)



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Re: [PATCH 1/3] drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

[Michel Dänzer]

On 2018-07-12 09:38 AM, Christian König wrote:
> Am 11.07.2018 um 18:23 schrieb Michel Dänzer:
>> From: Michel Dänzer 
>>
>> Instead of CPU invisible VRAM. Preparation for the following, no
>> functional change intended.
>>
>> Cc: sta...@vger.kernel.org
>> Signed-off-by: Michel Dänzer 
>>
>> [...]
>>  
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> index 9ee678d63890..752484328665 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> @@ -917,7 +917,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo,
>> u32 domain,
>>   domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
>>   if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
>>   adev->vram_pin_size += amdgpu_bo_size(bo);
>> -    adev->invisible_pin_size +=
>> amdgpu_vram_mgr_bo_invisible_size(bo);
>> +    adev->visible_pin_size +=
>> +    amdgpu_bo_size(bo) - amdgpu_vram_mgr_bo_invisible_size(bo);
> 
> Any particular reason why we should not invert
> amdgpu_vram_mgr_bo_invisible_size() as well?

Right, that occurred to me as well in the meantime. I was planning to
send a follow-up patch for this, but since patch 3 needs a v2 anyway,
I'll do a v2 of this one as well.


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Re: [PATCH 3/3] drm/amdgpu: Warn and update pin_size values when destroying a pinned BO

[Christian König]

Am 11.07.2018 um 18:23 schrieb Michel Dänzer:

From: Michel Dänzer 

This shouldn't happen, but if it does, we'll get a backtrace of the
caller, and update the pin_size values as needed.

Signed-off-by: Michel Dänzer 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 37 +-
  1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 24d6fb87f3b6..9945f080ea7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -63,10 +63,38 @@ static bool amdgpu_need_backup(struct amdgpu_device *adev)
return true;
  }
  
+/**

+ * amdgpu_bo_subtract_pin_size - Remove BO from pin size accounting
+ *
+ * @bo: &amdgpu_bo buffer object
+ *
+ * This function is called when a BO stops being pinned, and updates the
+ * &amdgpu_device pin_size values accordingly.
+ */
+static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo)
+{
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+   if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
+   atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
+   atomic64_sub(amdgpu_bo_size(bo) -
+amdgpu_vram_mgr_bo_invisible_size(bo),
+&adev->visible_pin_size);
+   } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
+   atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
+   }
+}
+
  static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
+   int i;
+
+   for (i = 0; i < bo->placement.num_placement; i++) {
+   if (WARN_ON_ONCE(bo->placements[i].flags & 
TTM_PL_FLAG_NO_EVICT))
+   amdgpu_bo_subtract_pin_size(bo);
+   }


That would subtract the values once for each placement which is not 
something we want. I would rather take a look at bo->pin_count.


Regards,
Christian.

  
  	if (bo->kfd_bo)

amdgpu_amdkfd_unreserve_system_memory_limit(bo);
@@ -969,14 +997,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
if (bo->pin_count)
return 0;
  
-	if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {

-   atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
-   atomic64_sub(amdgpu_bo_size(bo) -
-amdgpu_vram_mgr_bo_invisible_size(bo),
-&adev->visible_pin_size);
-   } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
-   atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
-   }
+   amdgpu_bo_subtract_pin_size(bo);
  
  	for (i = 0; i < bo->placement.num_placement; i++) {

bo->placements[i].lpfn = 0;


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Re: [PATCH 2/3] drm/amdgpu: Make pin_size values atomic

[Christian König]

Am 11.07.2018 um 18:23 schrieb Michel Dänzer:

From: Michel Dänzer 

Concurrent execution of the non-atomic arithmetic could result in
completely bogus values.

Cc: sta...@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106872
Signed-off-by: Michel Dänzer 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 22 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 18 ++
  4 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 77ab06bf26d5..f00be3d80aa4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1592,9 +1592,9 @@ struct amdgpu_device {
DECLARE_HASHTABLE(mn_hash, 7);
  
  	/* tracking pinned memory */

-   u64 vram_pin_size;
-   u64 visible_pin_size;
-   u64 gart_pin_size;
+   atomic64_t vram_pin_size;
+   atomic64_t visible_pin_size;
+   atomic64_t gart_pin_size;
  
  	/* amdkfd interface */

struct kfd_dev  *kfd;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 9881a1e55df3..5a2a5ba29f9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -262,7 +262,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct 
amdgpu_device *adev,
return;
}
  
-	total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;

+   total_vram = adev->gmc.real_vram_size - 
atomic64_read(&adev->vram_pin_size);
used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

index b1ea43ee8b87..258b6f73cbdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -501,13 +501,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
case AMDGPU_INFO_VRAM_GTT: {
struct drm_amdgpu_info_vram_gtt vram_gtt;
  
-		vram_gtt.vram_size = adev->gmc.real_vram_size;

-   vram_gtt.vram_size -= adev->vram_pin_size;
-   vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
-   vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
+   vram_gtt.vram_size = adev->gmc.real_vram_size -
+   atomic64_read(&adev->vram_pin_size);
+   vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size 
-
+   atomic64_read(&adev->visible_pin_size);
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
-   vram_gtt.gtt_size -= adev->gart_pin_size;
+   vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
return copy_to_user(out, &vram_gtt,
min((size_t)size, sizeof(vram_gtt))) ? 
-EFAULT : 0;
}
@@ -516,16 +516,16 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
  
  		memset(&mem, 0, sizeof(mem));

mem.vram.total_heap_size = adev->gmc.real_vram_size;
-   mem.vram.usable_heap_size =
-   adev->gmc.real_vram_size - adev->vram_pin_size;
+   mem.vram.usable_heap_size = adev->gmc.real_vram_size -
+   atomic64_read(&adev->vram_pin_size);
mem.vram.heap_usage =

amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
  
  		mem.cpu_accessible_vram.total_heap_size =

adev->gmc.visible_vram_size;
-   mem.cpu_accessible_vram.usable_heap_size =
-   adev->gmc.visible_vram_size - adev->visible_pin_size;
+   mem.cpu_accessible_vram.usable_heap_size = 
adev->gmc.visible_vram_size -
+   atomic64_read(&adev->visible_pin_size);
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
@@ -533,8 +533,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
  
  		mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;

mem.gtt.total_heap_size *= PAGE_SIZE;
-   mem.gtt.usable_heap_size = mem.gtt.total_heap_size
-   - adev->gart_pin_size;
+   mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
+   atomic64_read(&adev->gart_pin_size);
mem.gtt.heap_usage =
  

Re: [PATCH 1/3] drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

[Christian König]

Am 11.07.2018 um 18:23 schrieb Michel Dänzer:

From: Michel Dänzer 

Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

Cc: sta...@vger.kernel.org
Signed-off-by: Michel Dänzer 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 5 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 --
  3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f4db10..77ab06bf26d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1593,7 +1593,7 @@ struct amdgpu_device {
  
  	/* tracking pinned memory */

u64 vram_pin_size;
-   u64 invisible_pin_size;
+   u64 visible_pin_size;
u64 gart_pin_size;
  
  	/* amdkfd interface */

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d041dddaad0c..b1ea43ee8b87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -504,7 +504,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
vram_gtt.vram_size = adev->gmc.real_vram_size;
vram_gtt.vram_size -= adev->vram_pin_size;
vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
-   vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - 
adev->invisible_pin_size);
+   vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= adev->gart_pin_size;
@@ -525,8 +525,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
mem.cpu_accessible_vram.total_heap_size =
adev->gmc.visible_vram_size;
mem.cpu_accessible_vram.usable_heap_size =
-   adev->gmc.visible_vram_size -
-   (adev->vram_pin_size - adev->invisible_pin_size);
+   adev->gmc.visible_vram_size - adev->visible_pin_size;
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9ee678d63890..752484328665 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -917,7 +917,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
adev->vram_pin_size += amdgpu_bo_size(bo);
-   adev->invisible_pin_size += 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size +=
+   amdgpu_bo_size(bo) - 
amdgpu_vram_mgr_bo_invisible_size(bo);


Any particular reason why we should not invert 
amdgpu_vram_mgr_bo_invisible_size() as well?


Apart from that looks good to me,
Christian.


} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
adev->gart_pin_size += amdgpu_bo_size(bo);
}
@@ -969,7 +970,8 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
  
  	if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {

adev->vram_pin_size -= amdgpu_bo_size(bo);
-   adev->invisible_pin_size -= 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size -=
+   amdgpu_bo_size(bo) - 
amdgpu_vram_mgr_bo_invisible_size(bo);
} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
adev->gart_pin_size -= amdgpu_bo_size(bo);
}


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Re: [PATCH libdrm] amdgpu: add amdgpu_bo_handle_type_kms_noimport

[Michel Dänzer]

On 2018-07-12 02:47 AM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> ---
>  amdgpu/amdgpu.h| 7 ++-
>  amdgpu/amdgpu_bo.c | 4 
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
> index 36f91058..be83b457 100644
> --- a/amdgpu/amdgpu.h
> +++ b/amdgpu/amdgpu.h
> @@ -77,21 +77,26 @@ struct drm_amdgpu_info_hw_ip;
>   *
>  */
>  enum amdgpu_bo_handle_type {
>   /** GEM flink name (needs DRM authentication, used by DRI2) */
>   amdgpu_bo_handle_type_gem_flink_name = 0,
>  
>   /** KMS handle which is used by all driver ioctls */
>   amdgpu_bo_handle_type_kms = 1,
>  
>   /** DMA-buf fd handle */
> - amdgpu_bo_handle_type_dma_buf_fd = 2
> + amdgpu_bo_handle_type_dma_buf_fd = 2,
> +
> + /** KMS handle, but re-importing as a DMABUF handle through
> +  *  drmPrimeHandleToFD is forbidden. (Glamor does that)
> +  */
> + amdgpu_bo_handle_type_kms_noimport = 3,
>  };
>  
>  /** Define known types of GPU VM VA ranges */
>  enum amdgpu_gpu_va_range
>  {
>   /** Allocate from "normal"/general range */
>   amdgpu_gpu_va_range_general = 0
>  };
>  
>  enum amdgpu_sw_info {
> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
> index 9e37b149..d29be244 100644
> --- a/amdgpu/amdgpu_bo.c
> +++ b/amdgpu/amdgpu_bo.c
> @@ -234,20 +234,22 @@ int amdgpu_bo_export(amdgpu_bo_handle bo,
>   case amdgpu_bo_handle_type_gem_flink_name:
>   r = amdgpu_bo_export_flink(bo);
>   if (r)
>   return r;
>  
>   *shared_handle = bo->flink_name;
>   return 0;
>  
>   case amdgpu_bo_handle_type_kms:
>   amdgpu_add_handle_to_table(bo);
> + /* fall through */
> + case amdgpu_bo_handle_type_kms_noimport:
>   *shared_handle = bo->handle;
>   return 0;

What is the rationale for this? I.e. why do you want to not store some
handles in the hash table? And how can code using
amdgpu_bo_handle_type_kms_noimport be sure that the BO will never be
re-imported via dma-buf?

The experience with the previous patch has shown that it's hard to keep
track of all possible ways in which BOs are imported, and that if we
miss one, this breaks pretty spectacularly.


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Re: [PATCH 0/3] drm/scheduler: preparation for load balancing

[Christian König]

Only a few more style nit picks:

Patches #1 and #2 need a commit message. A one liner why we do this 
should be fine.


On Patch #3 you have a couple of places like this:

-   r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
- rq, NULL);
+   r = drm_sched_entity_init(&adev->mman.entity,
+ &rq, 1, NULL);
If I'm not completely mistaken that could be written on one line now and 
still be shorter than 80 characters.


Those are not major issues, so patches are Reviewed-by: Christian König 
 either way.


If neither Lucas nor Eric object I'm going to pick them those patches up 
on Friday.


Thanks for the help,
Christian.

Am 12.07.2018 um 08:36 schrieb Nayan Deshmukh:

This patch series is prepration for implementing better load balancing
in the GPU scheduler. Patch #3 is the major change which modifies the
drm_sched_entity_init, the driver is now expected to provide a list of
potential run queue on which the jobs from this entity can be scheduled.

In future patches we will add functionality to scheduler to select the
run queue which has the least amount of load. To avoid making
significant changes to multiple drivers in the same patch I am not yet
sending a list to drm_sched_entity_init. I will make seprate patches for
each driver for that.

Regards,
Nayan Deshmukh

Nayan Deshmukh (3):
   drm/scheduler: add a pointer to scheduler in the rq
   drm/scheduler: add counter for total jobs in scheduler
   drm/scheduler: modify args of drm_sched_entity_init

  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|  4 ++--
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c |  4 ++--
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |  4 ++--
  drivers/gpu/drm/etnaviv/etnaviv_drv.c |  8 
  drivers/gpu/drm/scheduler/gpu_scheduler.c | 31 +--
  drivers/gpu/drm/v3d/v3d_drv.c |  7 +++
  include/drm/gpu_scheduler.h   | 17 +
  11 files changed, 55 insertions(+), 36 deletions(-)



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Re: DEBUG_LOCKS_WARN_ON(sem->owner != ((struct task_struct *)(1UL << 0)))

[Michel Dänzer]

On 2018-07-12 02:43 AM, Felix Kuehling wrote:
> Kent just caught a similar backtrace in one of our KFD pre-submission
> tests (see below)

Yeah, looks the same.


> Neither KFD nor AMDGPU are implied in the backtrace. Is this a
> regression in the kernel itself? amd-kfd-staging is currently based on
> 4.18-rc1.

FWIW, I saw this with 4.17 based kernels already, and I didn't have
CONFIG_DEBUG_RWSEMS enabled with older kernels, so I'm not sure it's a
(recent) regression.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: 答复: Regression with kernel 4.18 - AMD RX 550 fails IB ring test on power-up

[Christian König]

Hi Luis,

well was "drm/amdgpu: defer test IBs on the rings at boot (V3)" does is 
delaying the IB test a bit and running it async to the rest of the bootup.


So what most likely happens is that some hardware feature (like power or 
clock gating) which doesn't works correctly on your system kicks in and 
lets the IB test fail.


It's rather likely that this problem is also responsible for the crashes 
you expect later on. So I think we should concentrate on fixing that.


Regards,
Christian.

Am 11.07.2018 um 23:27 schrieb Luís Mendes:

Hi Jim,

I followed your suggestion and was able to bisect the kernel patches.
The offending patch is: drm/amdgpu: defer test IBs on the rings at 
boot (V3)

commit:

	2c773de2ecb8c327f2448bd1eecad224e9227087 
 




After reverting this patch the IB test succeeded with kernel v4.18-rc4 
on both systems and the amdgpu driver was correctly loaded both on 
SAPPHIRE RX550 4GB and on SAPPHIRE RX460 2GB.


The GPU hang remains, however.
 I will try to configure a remote IPMI connection to see what is 
happening with the kernel boot or setup a serial console for the Kernel.


Thanks & Regards,
Luís

On Wed, Jul 11, 2018 at 10:56 AM, jimqu > wrote:


HI Luis,


Let us trace the issue one by one.


IB test fail:

This should be regression issue on 4.18, you can bisect the kernel
patches.

GPU hang:

Fix IB test fail first.


Thanks

JimQu



On 2018年07月11日 17:34, Luís Mendes wrote:

Hi Jim,

Thanks for your interest in this issue. Actually this is a
multiple issue... not only the IB ring test is failing... as I am
having quite some trouble getting the cards SAPPHIRE RX 550 4GB
on a Tyan S7025 and SAPPHIRE RX 460 2GB on a TYAN S7002 to work,
both systems using same Ubuntu 18.04 with vanilla kernel.

*1. May you also test earlier kernel? v4.17 or v4.16.*
I've tested kernels v4.17.5 and v4.16.6 with same system and both
are able to pass the IB ring test and system boots into X using
NVIDIA as the display connected card.
dmesg log attached for kernel 4.17.5, file
TYAN_S7025_kernelv4.17.5_amdgpu_IB_ring_test_OK.txt.

*2. May you test the issue only with amdgpu?*
- I've tested on a TYAN S7002 system with a single SAPPHIRE RX
460 2GB, on-board VGA enabled and used as primary display.
Kernel v4.18-rc4 fails the IB ring test, system is able to enter
X through the on-board VGA.
dmesg log attached for kernel 4.18-rc4, file
TYAN_S7002_kernel_v4.18-rc4_IB_ring_test_fail.txt.

- Same TYAN S7002 system, but now with on-board VGA disabled and
using RX 460 as display connected card.
Kernels v4.17.5 and v4.16.6 are able to pass the IB ring test,
but GPU hangs before entering X. Don't have logs for these yet.

Regards,
Luís Mendes
Aparapi contributor and MSc Researcher





On Wed, Jul 11, 2018 at 3:49 AM, Qu, Jim mailto:jim...@amd.com>> wrote:

Hi Luis,

1. May you also test earlier kernel? v4.17 or v4.16.
2. May you test the issue only with amdgpu?

Thanks
JimQu


发件人: amd-gfx mailto:amd-gfx-boun...@lists.freedesktop.org>> 代表 Luís
Mendes mailto:luis.p.men...@gmail.com>>
发送时间: 2018年7月11日 6:04:00
收件人: Michel Dänzer; Koenig, Christian; amd-gfx list
主题: Re: Regression with kernel 4.18 - AMD RX 550 fails IB
ring test on power-up

Hi,

Issue remains in kernel 4.18-rc4 using SAPPHIRE RX 550 4GB.

Logs follow attached.

Regards,
Luis

On Tue, Jun 26, 2018 at 10:08 AM, Luís Mendes
mailto:luis.p.men...@gmail.com>>> wrote:
Hi,

I've tried kernel 4.18-rc2 on a system with a NVIDIA GTX 1050
Ti and an AMD RX 550 4GB and the RX 550 card is failing the
IB ring test.

[    5.033217] [drm:gfx_v8_0_ring_test_ib [amdgpu]] *ERROR*
amdgpu: ib test failed (scratch(0xC040)=0x)
[    5.033264] [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR*
amdgpu: failed testing IB on ring 6 (-22).

Please see the attached log.

Regards,
Luís







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Re: [PATCH v2] drm/amdgpu: Allow to create BO lists in CS ioctl v2

[Christian König]

Am 11.07.2018 um 22:57 schrieb Andrey Grodzovsky:

This change is to support MESA performace optimization.
Modify CS IOCTL to allow its input as command buffer and an array of
buffer handles to create a temporay bo list and then destroy it
when IOCTL completes.
This saves on calling for BO_LIST create and destry IOCTLs in MESA
and by this improves performance.

v2: Avoid inserting the temp list into idr struct.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 
  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 86 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 51 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 +-
  include/uapi/drm/amdgpu_drm.h   |  1 +
  5 files changed, 114 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f..9b472b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -732,6 +732,17 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
 struct list_head *validated);
  void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
  void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
+int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,
+ struct drm_amdgpu_bo_list_entry 
**info_param);
+
+int amdgpu_bo_list_create(struct amdgpu_device *adev,
+struct drm_file *filp,
+struct drm_amdgpu_bo_list_entry *info,
+unsigned num_entries,
+int *id,
+struct amdgpu_bo_list **list);
+
+void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id);
  
  /*

   * GFX stuff
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 92be7f6..14c7c59 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -55,11 +55,12 @@ static void amdgpu_bo_list_release_rcu(struct kref *ref)
kfree_rcu(list, rhead);
  }
  
-static int amdgpu_bo_list_create(struct amdgpu_device *adev,

+int amdgpu_bo_list_create(struct amdgpu_device *adev,
 struct drm_file *filp,
 struct drm_amdgpu_bo_list_entry *info,
 unsigned num_entries,
-int *id)
+int *id,
+struct amdgpu_bo_list **list_out)
  {
int r;
struct amdgpu_fpriv *fpriv = filp->driver_priv;
@@ -78,20 +79,25 @@ static int amdgpu_bo_list_create(struct amdgpu_device *adev,
return r;
}
  
+	if (id) {

/* idr alloc should be called only after initialization of bo list. */
-   mutex_lock(&fpriv->bo_list_lock);
-   r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
-   mutex_unlock(&fpriv->bo_list_lock);
-   if (r < 0) {
-   amdgpu_bo_list_free(list);
-   return r;
+   mutex_lock(&fpriv->bo_list_lock);
+   r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
+   mutex_unlock(&fpriv->bo_list_lock);
+   if (r < 0) {
+   amdgpu_bo_list_free(list);
+   return r;
+   }
+   *id = r;


Can we move that into the calling or a separate other function?

Would be cleaner to separate the functionality of creating a bo_list 
structure from inserting it into the IDR.



}
-   *id = r;
+
+   if (list_out)
+   *list_out = list;
  
  	return 0;

  }
  
-static void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id)

+void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id)
  {
struct amdgpu_bo_list *list;
  
@@ -263,53 +269,68 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list)

kfree(list);
  }
  
-int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,

-   struct drm_file *filp)
+int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,
+ struct drm_amdgpu_bo_list_entry 
**info_param)
  {
-   const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);
-
-   struct amdgpu_device *adev = dev->dev_private;
-   struct amdgpu_fpriv *fpriv = filp->driver_priv;
-   union drm_amdgpu_bo_list *args = data;
-   uint32_t handle = args->in.list_handle;
-   const void __user *uptr = u64_to_user_ptr(args->in.bo_info_ptr);
-
struct drm_amdgpu_bo_list_entry *info;
-   struct amdgpu_bo_list *list;
-
int r;
+   const void __user *uptr = u64_to_user_ptr(in->bo_info_ptr);
+   const uint32_t info_size = sizeof(struct drm_amdgpu_bo_l