RE: [PATCH 3/6] drm: add support of syncobj timeline point wait v2

2018-10-07 Thread Zhou, David(ChunMing) 
>> Another general comment (no good place to put it) is that I think we want 
>> two kinds of waits:  Wait for time point to be completed and wait for time 
>> point to become available.  The first is the usual CPU wait for completion 
>> while the second is for use by userspace drivers to wait until the first 
>> moment where they can submit work which depends on a given time point.

Hi Jason,

How about adding two new wait flags?
DRM_SYNCOBJ_WAIT_FLAGS_WAIT_COMPLETED
DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE

Thanks,
David

From: Christian König 
Sent: Tuesday, September 25, 2018 5:50 PM
To: Jason Ekstrand ; Zhou, David(ChunMing) 

Cc: amd-gfx mailing list ; Maling list - DRI 
developers 
Subject: Re: [PATCH 3/6] drm: add support of syncobj timeline point wait v2

Am 25.09.2018 um 11:22 schrieb Jason Ekstrand:
On Thu, Sep 20, 2018 at 6:04 AM Chunming Zhou 
mailto:david1.z...@amd.com>> wrote:
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.

I think ioctl structs can be extended as long as fields aren't re-ordered.  I'm 
not sure on the details of this though as I'm not a particularly experienced 
kernel developer.

Yeah, that is correct. The problem in this particular case is that we don't 
change the direct IOCTL parameter, but rather the array it points to.

We could do something like keep the existing handles array and add a separate 
optional one for the timeline points. That would also drop the need for the 
padding of the structure.


Another general comment (no good place to put it) is that I think we want two 
kinds of waits:  Wait for time point to be completed and wait for time point to 
become available.  The first is the usual CPU wait for completion while the 
second is for use by userspace drivers to wait until the first moment where 
they can submit work which depends on a given time point.

Oh, yeah that is a really good point as ell.

Christian.



Signed-off-by: Chunming Zhou mailto:david1.z...@amd.com>>
---
 drivers/gpu/drm/drm_internal.h |  2 +
 drivers/gpu/drm/drm_ioctl.c|  2 +
 drivers/gpu/drm/drm_syncobj.c  | 99 +-
 include/uapi/drm/drm.h | 14 +
 4 files changed, 103 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 0c4eb4a9ab31..566d44e3c782 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -183,6 +183,8 @@ int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, 
void *data,
   struct drm_file *file_private);
 int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data,
   struct drm_file *file_private);
+int drm_syncobj_timeline_wait_ioctl(struct drm_device *dev, void *data,
+   struct drm_file *file_private);
 int drm_syncobj_reset_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_private);
 int drm_syncobj_signal_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 6b4a633b4240..c0891614f516 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -669,6 +669,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, 
drm_syncobj_timeline_wait_ioctl,
+ DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_RESET, drm_syncobj_reset_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl,
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 67472bd77c83..a43de0e4616c 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -126,13 +126,14 @@ static void drm_syncobj_add_callback_locked(struct 
drm_syncobj *syncobj,
 }

 static int drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,
+u64 point,
 struct dma_fence **fence,
 struct drm_syncobj_cb *cb,
 drm_syncobj_func_t func)
 {
int ret;

-   ret = drm_syncobj_search_fence(syncobj, 0, 0, fence);
+   ret = drm_syncobj_search_fence(syncobj, point, 0, fence);
if (!ret)
return 1;

@@ -143,7 +144,7 @@ static int drm_syncobj_fence_get_or_add_callback(struct 
drm_syncobj *syncobj,
 */
if (!list_empty(&syncobj->signal_pt_list)) {
spin_unlock(&syncobj->lock);
-   drm_syncobj_search_fence(syncobj, 0, 0, fence);
+   drm_sync

RE: [PATCH 5/6] drm/amdgpu: add timeline support in amdgpu CS

2018-10-07 Thread Zhou, David(ChunMing) 


> -Original Message-
> From: Nicolai Hähnle 
> Sent: Wednesday, September 26, 2018 4:44 PM
> To: Zhou, David(ChunMing) ; dri-
> de...@lists.freedesktop.org
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 5/6] drm/amdgpu: add timeline support in amdgpu CS
> 
> >   static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, diff --git
> > a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index
> > 1ceec56de015..412359b446f1 100644
> > --- a/include/uapi/drm/amdgpu_drm.h
> > +++ b/include/uapi/drm/amdgpu_drm.h
> > @@ -517,6 +517,8 @@ struct drm_amdgpu_gem_va {
> >   #define AMDGPU_CHUNK_ID_SYNCOBJ_IN  0x04
> >   #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
> >   #define AMDGPU_CHUNK_ID_BO_HANDLES  0x06
> > +#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT0x07
> > +#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x08
> >
> >   struct drm_amdgpu_cs_chunk {
> > __u32   chunk_id;
> > @@ -592,6 +594,14 @@ struct drm_amdgpu_cs_chunk_sem {
> > __u32 handle;
> >   };
> >
> > +struct drm_amdgpu_cs_chunk_syncobj {
> > +   __u32 handle;
> > +   __u32 pad;
> > +   __u64 point;
> > +   __u64 flags;
> > +};
> 
> Sure it's nice to be forward-looking, but can't we just put the flags into the
> padding?

Will change.

Thanks,
David
> 
> Cheers,
> Nicolai
> 
> 
> > +
> > +
> >   #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ0
> >   #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
> >   #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD   2
> >
> 
> 
> --
> Lerne, wie die Welt wirklich ist,
> Aber vergiss niemals, wie sie sein sollte.
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RE: [PATCH 5/6] drm/amdgpu: add timeline support in amdgpu CS

2018-10-07 Thread Zhou, David(ChunMing) 


> -Original Message-
> From: Nicolai Hähnle 
> Sent: Wednesday, September 26, 2018 5:06 PM
> To: Zhou, David(ChunMing) ; dri-
> de...@lists.freedesktop.org
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 5/6] drm/amdgpu: add timeline support in amdgpu CS
> 
> Hey Chunming,
> 
> On 20.09.2018 13:03, Chunming Zhou wrote:
> > @@ -1113,48 +1117,91 @@ static int
> amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
> >   }
> >
> >   static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser
> *p,
> > -   struct amdgpu_cs_chunk *chunk)
> > +   struct amdgpu_cs_chunk *chunk,
> > +   bool timeline)
> >   {
> > unsigned num_deps;
> > int i, r;
> > -   struct drm_amdgpu_cs_chunk_sem *deps;
> >
> > -   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
> > -   num_deps = chunk->length_dw * 4 /
> > -   sizeof(struct drm_amdgpu_cs_chunk_sem);
> > +   if (!timeline) {
> > +   struct drm_amdgpu_cs_chunk_sem *deps;
> >
> > -   for (i = 0; i < num_deps; ++i) {
> > -   r = amdgpu_syncobj_lookup_and_add_to_sync(p,
> deps[i].handle);
> > +   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
> > +   num_deps = chunk->length_dw * 4 /
> > +   sizeof(struct drm_amdgpu_cs_chunk_sem);
> > +   for (i = 0; i < num_deps; ++i) {
> > +   r = amdgpu_syncobj_lookup_and_add_to_sync(p,
> deps[i].handle,
> > + 0, 0);
> > if (r)
> > return r;
> 
> The indentation looks wrong.
> 
> 
> > +   }
> > +   } else {
> > +   struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
> > +
> > +   syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj
> *)chunk->kdata;
> > +   num_deps = chunk->length_dw * 4 /
> > +   sizeof(struct drm_amdgpu_cs_chunk_syncobj);
> > +   for (i = 0; i < num_deps; ++i) {
> > +   r = amdgpu_syncobj_lookup_and_add_to_sync(p,
> syncobj_deps[i].handle,
> > +
> syncobj_deps[i].point,
> > +
> syncobj_deps[i].flags);
> > +   if (r)
> > +   return r;
> 
> Here as well.
> 
> So I'm wondering a bit about this uapi. Specifically, what happens if you try 
> to
> use timeline syncobjs here as dependencies _without_
> DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT?
> 
> My understanding is, it'll just return -EINVAL without any indication as to
> which syncobj actually failed. What's the caller supposed to do then?

How about adding a print to indicate which syncobj failed?

Thanks,
David Zhou
> 
> Cheers,
> Nicolai
> --
> Lerne, wie die Welt wirklich ist,
> Aber vergiss niemals, wie sie sein sollte.
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答复: VegaM DP dpms issue

2018-10-07 Thread Qu, Jim 
Hi,

Please give more details about the issue, such as OS, kernel version, amdgpu 
driver version, dmesg log, Xorg log.


Some suggestions:

1. Make sure that hybrid GFX has enabled on your system.
2. The important issue, make sure Which GPU is mDP phy connected. If it is from 
iGPU, that mean the dGPU is for offloading, it maybe some issue about Intel 
driver.
2. If the display is from dGPU, By default, all the rendering job is done by 
Intel. make sure you used the last modesetting DDX, I just fixed a modesetting 
PRIME sync issue for Intel + AMD/NV hybrid GFX issue.

Thanks
JimQu


发件人: amd-gfx  代表 Mike Lothian 

发送时间: 2018年10月1日 18:17:30
收件人: Louis Garcia
抄送: amd-gfx@lists.freedesktop.org
主题: Re: VegaM DP dpms issue

Hi

I'm pretty sure unless you're offloading using DRI_PRIME=1 then it'll be your 
Intel graphics that'll be driving the displays

I'd recommend you raise a bug on https://bugs.freedesktop.org/ under DRI then 
DRM/Intel

Make sure you attach your dmesg and Xorg.0.log and hopefully they'll be able to 
help

Cheers

Mike

On Sun, 30 Sep 2018 at 17:23 Louis Garcia 
mailto:louisg...@gmail.com>> wrote:
I am having an issue with intel NUC8i7HNK with AMD Vega M. I have three Dell 
U2415 monitors connected to one mDP daisychained. When the monitors go to sleep 
(dpms) trying to wake up the monitors after half hour or more fails, touching 
the keyboard and mouse. Only way is a hard reboot. Same monitors connected to 
other systems wake up fine. I seen old bug reports on this issue but seems I'm 
hitting this bug again.

If this is not the proper list please let me kno. --Thanks
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[PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6

2018-10-07 Thread Mauro Rossi 
DCE6 targets are added replicating existing DCE8 implementation.
---
 drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
 .../display/dc/bios/command_table_helper.c|   8 +
 .../display/dc/bios/command_table_helper.h|   3 +
 .../display/dc/bios/command_table_helper2.c   |   8 +
 .../display/dc/bios/command_table_helper2.h   |   3 +
 .../bios/dce60/command_table_helper_dce60.c   | 354 ++
 .../bios/dce60/command_table_helper_dce60.h   |  33 ++
 7 files changed, 418 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile 
b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 239e86bbec5a..ed6b5e9763f6 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
 
+###
+# DCE 6x
+###
+# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
+# DCE6.x is compiled.
+ifdef CONFIG_DRM_AMD_DC_SI
+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
+endif
+
 ###
 # DCE 8x
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 253bbb1eea60..48b4ef03fc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
enum dce_version dce)
 {
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   case DCE_VERSION_6_1:
+   case DCE_VERSION_6_4:
+   *h = dal_cmd_tbl_helper_dce60_get_table();
+   return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
index 4c3789df253d..dfd30aaf4032 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
@@ -26,6 +26,9 @@
 #ifndef __DAL_COMMAND_TABLE_HELPER_H__
 #define __DAL_COMMAND_TABLE_HELPER_H__
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
 #include "dce80/command_table_helper_dce80.h"
 #include "dce110/command_table_helper_dce110.h"
 #include "dce112/command_table_helper_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index bbbcef566c55..dad302564da4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
enum dce_version dce)
 {
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   case DCE_VERSION_6_1:
+   case DCE_VERSION_6_4:
+   *h = dal_cmd_tbl_helper_dce60_get_table();
+   return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
index 785fcb20a1b9..66e0a3e73768 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
@@ -26,6 +26,9 @@
 #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
 #define __DAL_COMMAND_TABLE_HELPER2_H__
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
 #include "dce80/command_table_helper_dce80.h"
 #include "dce110/command_table_helper_dce110.h"
 #include "dce112/command_table_helper2_dce112.h"
diff --git 
a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c 
b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
new file mode 100644
index ..552778ce9835
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rig

[PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6

2018-10-07 Thread Mauro Rossi 
DCE6 targets are added replicating existing DCE8 implementation.

NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c

IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |  11 +
 .../display/dc/irq/dce60/irq_service_dce60.c  | 303 ++
 .../display/dc/irq/dce60/irq_service_dce60.h  |  35 ++
 .../gpu/drm/amd/display/dc/irq/irq_service.c  |   3 +
 4 files changed, 352 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile 
b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 498515aad4a5..e38b6d8d614d 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
 
+###
+# DCE 6x
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+IRQ_DCE60 = irq_service_dce60.o
+
+AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
+endif
+
 ###
 # DCE 8x
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c 
b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
new file mode 100644
index ..107e0dcb5f80
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce60.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "dc_types.h"
+
+static bool hpd_ack(
+   struct irq_service *irq_service,
+   const struct irq_source_info *info)
+{
+   uint32_t addr = info->status_reg;
+   uint32_t value = dm_read_reg(irq_service->ctx, addr);
+   uint32_t current_status =
+   get_reg_field_value(
+   value,
+   DC_HPD1_INT_STATUS,
+   DC_HPD1_SENSE_DELAYED);
+
+   dal_irq_service_ack_generic(irq_service, info);
+
+   value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+   set_reg_field_value(
+   value,
+   current_status ? 0 : 1,
+   DC_HPD1_INT_CONTROL,
+   DC_HPD1_INT_POLARITY);
+
+   dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+   return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+   .set = NULL,
+   .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+   .set = dce110_vblank_set,
+   .ack = NULL
+};
+
+
+#define hpd_int_entry(reg_num)\
+   [DC_IRQ_SOURCE_INVALID + reg_num] = {\
+   .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+   .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MAS

[PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6

2018-10-07 Thread Mauro Rossi 
DCE6 targets are added replicating existing DCE8 implementation.
---
 drivers/gpu/drm/amd/display/dc/gpio/Makefile  |  12 +
 .../display/dc/gpio/dce60/hw_factory_dce60.c  | 174 
 .../display/dc/gpio/dce60/hw_factory_dce60.h  |  32 ++
 .../dc/gpio/dce60/hw_translate_dce60.c| 411 ++
 .../dc/gpio/dce60/hw_translate_dce60.h|  32 ++
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |  10 +
 .../drm/amd/display/dc/gpio/hw_translate.c|  10 +
 7 files changed, 681 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile 
b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 562ee189d780..122ca9991100 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
 
+###
+# DCE 6x
+###
+# all DCE6.x are derived from DCE6.0
+ifdef CONFIG_DRM_AMD_DC_SI
+GPIO_DCE60 = hw_translate_dce60.o hw_factory_dce60.o
+
+AMD_DAL_GPIO_DCE60 = $(addprefix $(AMDDALPATH)/dc/gpio/dce60/,$(GPIO_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE60)
+endif
+
 ###
 # DCE 8x
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c 
b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
new file mode 100644
index ..64afe9b48c5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+#include "hw_factory_dce60.h"
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#define REG(reg_name)\
+   mm ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define HPD_REG_LIST_DCE6(id) \
+   HPD_GPIO_REG_LIST(id), \
+   .int_status = mmDC_HPD ## id ## _INT_STATUS,\
+   .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
+
+#define HPD_MASK_SH_LIST_DCE6(mask_sh) \
+   .DC_HPD_SENSE_DELAYED = 
DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
+   .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
+   .DC_HPD_CONNECT_INT_DELAY = 
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
+   .DC_HPD_DISCONNECT_INT_DELAY = 
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
+
+#define hpd_regs(id) \
+{\
+   HPD_REG_LIST_DCE6(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+   hpd_regs(1),
+   hpd_regs(2),
+   hpd_regs(3),
+   hpd_regs(4),
+   hpd_regs(5),
+   hpd_regs(6)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+   HPD_MASK_SH_LIST_DCE6(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+   HPD_MASK_SH_LIST_DCE6(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+   .field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs[] = {
+   ddc_dat

[PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support

2018-10-07 Thread Mauro Rossi 
DCE6 targets are added replicating existing DCE8 implementation.

NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks

IMPORTANT: Coding of dce60_resource.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
 drivers/gpu/drm/amd/display/dc/Makefile   |4 +
 .../drm/amd/display/dc/dce/dce_clock_source.c |   15 +
 drivers/gpu/drm/amd/display/dc/dce60/Makefile |   34 +
 .../amd/display/dc/dce60/dce60_hw_sequencer.c |   81 +
 .../amd/display/dc/dce60/dce60_hw_sequencer.h |   36 +
 .../drm/amd/display/dc/dce60/dce60_resource.c | 1348 +
 .../drm/amd/display/dc/dce60/dce60_resource.h |   47 +
 .../display/dc/dce60/dce60_timing_generator.c |  242 +++
 .../display/dc/dce60/dce60_timing_generator.h |   39 +
 .../include/asic_reg/dce/dce_6_0_sh_mask.h|4 +
 10 files changed, 1850 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index aed538a4d1ba..d5d5acd57559 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -36,6 +36,10 @@ DC_LIBS += dce110
 DC_LIBS += dce100
 DC_LIBS += dce80
 
+ifdef CONFIG_DRM_AMD_DC_SI
+DC_LIBS += dce60
+endif
+
 AMD_DC = $(addsuffix /Makefile, $(addprefix 
$(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
 
 include $(AMD_DC)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index ca137757a69e..d96c977e451b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -580,6 +580,11 @@ static uint32_t dce110_get_pix_clk_dividers(
}
 
switch (cs->ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   case DCE_VERSION_6_1:
+   case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
@@ -941,6 +946,11 @@ static bool dce110_program_pix_clk(
bp_pc_params.signal_type = pix_clk_params->signal_type;
 
switch (clock_source->ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   case DCE_VERSION_6_1:
+   case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
@@ -1296,6 +1306,11 @@ bool dce110_clk_src_construct(
fw_info.external_clock_source_frequency_for_dp;
 
switch (clk_src->base.ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   case DCE_VERSION_6_1:
+   case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile 
b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
new file mode 100644
index ..39afd7c59a7c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
+   dce60_resource.o
+
+AMD_DAL_DCE60 =

[PATCH 09/10] drm/amdgpu: enable DC support for SI parts

2018-10-07 Thread Mauro Rossi 
This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  7 +++
 drivers/gpu/drm/amd/amdgpu/si.c| 14 ++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 43c030459af7..f479f7274412 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2250,6 +2250,13 @@ bool amdgpu_device_asic_has_dc_support(enum 
amd_asic_type asic_type)
 {
switch (asic_type) {
 #if defined(CONFIG_DRM_AMD_DC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_OLAND:
+   case CHIP_HAINAN:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c364ef94cc36..f898f548140c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -48,6 +48,8 @@
 #include "uvd/uvd_4_0_d.h"
 #include "bif/bif_3_0_d.h"
 
+#include "amdgpu_dm.h"
+
 static const u32 tahiti_golden_registers[] =
 {
mmAZALIA_SCLK_CONTROL, 0x0030, 0x0011,
@@ -2060,6 +2062,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+   else if (amdgpu_device_has_dc_support(adev))
+   amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
@@ -2074,6 +2080,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+   else if (amdgpu_device_has_dc_support(adev))
+   amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
@@ -2088,6 +2098,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+   else if (amdgpu_device_has_dc_support(adev))
+   amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
break;
-- 
2.17.1

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[PATCH 03/10] drm/amd/display: dc/core: add DCE6 support

2018-10-07 Thread Mauro Rossi 
DCE6 targets are added as branching of existing DCE8 implementation.
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ea6beccfd89d..16568e79d4b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -37,6 +37,9 @@
 #include "virtual/virtual_stream_encoder.h"
 #include "dpcd_defs.h"
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/dce60_resource.h"
+#endif
 #include "dce80/dce80_resource.h"
 #include "dce100/dce100_resource.h"
 #include "dce110/dce110_resource.h"
@@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id 
asic_id)
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
switch (asic_id.chip_family) {
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case FAMILY_SI:
+   if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
+   ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
+   ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
+   dc_version = DCE_VERSION_6_0;
+   else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
+   dc_version = DCE_VERSION_6_4;
+   else
+   dc_version = DCE_VERSION_6_1;
+   break;
+#endif
case FAMILY_CI:
dc_version = DCE_VERSION_8_0;
break;
@@ -106,6 +121,20 @@ struct resource_pool *dc_create_resource_pool(
struct resource_pool *res_pool = NULL;
 
switch (dc_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   res_pool = dce60_create_resource_pool(
+   num_virtual_links, dc);
+   break;
+   case DCE_VERSION_6_1:
+   res_pool = dce61_create_resource_pool(
+   num_virtual_links, dc);
+   break;
+   case DCE_VERSION_6_4:
+   res_pool = dce64_create_resource_pool(
+   num_virtual_links, dc);
+   break;
+#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
num_virtual_links, dc);
-- 
2.17.1

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[PATCH 01/10] drm/amd/display: add asics info for SI parts

2018-10-07 Thread Mauro Rossi 
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL

Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
 .../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
 .../gpu/drm/amd/display/include/dal_types.h   |  3 ++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h 
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 25029ed42d89..adea98e0b4b6 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -30,6 +30,34 @@
  * ASIC internal revision ID
  */
 
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
+#define SI_TAHITI_P_A00x01
+#define SI_TAHITI_P_B00x05
+#define SI_TAHITI_P_B10x06
+#define SI_PITCAIRN_PM_A0 0x14
+#define SI_PITCAIRN_PM_A1 0x15
+#define SI_CAPEVERDE_M_A0 0x28
+#define SI_CAPEVERDE_M_A1 0x29
+#define SI_OLAND_M_A0 0x3C
+#define SI_HAINAN_V_A00x46
+
+#define SI_UNKNOWN0xFF
+
+#define ASIC_REV_IS_TAHITI_P(rev) \
+   ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
+
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
+   ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
+
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
+   ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
+
+#define ASIC_REV_IS_OLAND_M(rev) \
+   ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
+
+#define ASIC_REV_IS_HAINAN_V(rev) \
+   ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
+
 /* DCE80 (based on ci_id.h in Perforce) */
 #defineCI_BONAIRE_M_A0 0x14
 #defineCI_BONAIRE_M_A1 0x15
@@ -143,12 +171,24 @@
 /*
  * ASIC chip ID
  */
+
+/* DCE60 */
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
+
 /* DCE80 */
 #define DEVICE_ID_KALINDI_9834 0x9834
 #define DEVICE_ID_TEMASH_9839 0x9839
 #define DEVICE_ID_TEMASH_983D 0x983D
 
 /* Asic Family IDs for different asic family. */
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape 
Verde (M), Oland (M), Hainan (V) */
 #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
 #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
 #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h 
b/drivers/gpu/drm/amd/display/include/dal_types.h
index 840142b65f8b..df1d3f9d8e14 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
 
 enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
+   DCE_VERSION_6_0,
+   DCE_VERSION_6_1,
+   DCE_VERSION_6_4,
DCE_VERSION_8_0,
DCE_VERSION_8_1,
DCE_VERSION_8_3,
-- 
2.17.1

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[PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6

2018-10-07 Thread Mauro Rossi 
DCE6 targets are added replicating existing DCE8 implementation.
---
 .../gpu/drm/amd/display/dc/i2caux/Makefile|  12 +
 .../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++
 .../dc/i2caux/dce60/i2c_hw_engine_dce60.h |  54 ++
 .../dc/i2caux/dce60/i2c_sw_engine_dce60.c | 173 
 .../dc/i2caux/dce60/i2c_sw_engine_dce60.h |  43 +
 .../display/dc/i2caux/dce60/i2caux_dce60.c| 284 ++
 .../display/dc/i2caux/dce60/i2caux_dce60.h|  38 +
 .../gpu/drm/amd/display/dc/i2caux/i2caux.c|  10 +
 8 files changed, 1489 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile 
b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
index 352885cb4d07..80f58a357879 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_I2CAUX = $(addprefix 
$(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
 
+###
+# DCE 6x family
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+I2CAUX_DCE60 = i2caux_dce60.o i2c_hw_engine_dce60.o \
+   i2c_sw_engine_dce60.o
+
+AMD_DAL_I2CAUX_DCE60 = $(addprefix 
$(AMDDALPATH)/dc/i2caux/dce60/,$(I2CAUX_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE60)
+endif
+
 ###
 # DCE 8x family
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
new file mode 100644
index ..a945e00ce913
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_hw_engine.h"
+#include "../i2c_generic_hw_engine.h"
+/*
+ * Header of this unit
+ */
+
+#include "i2c_hw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/*
+ * This unit
+ */
+
+enum dc_i2c_status {
+   DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
+   DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
+   DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
+};
+
+enum dc_i2c_arbitration {
+   DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+   DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
+};
+
+enum {
+   /* No timeout in HW
+* (timeout implemented in SW by querying status) */
+   I2C_SETUP_TIME_LIMIT = 255,
+   I2C_HW_BUFFER_SIZE = 144
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_hw_engine *'
+ * to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_HW_ENGINE(ptr) \
+   container_of((ptr), struct i2c_hw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast pointer to 'struct i2c_engine *'
+ * to pointer to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+   FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
+
+/*
+ * @brief
+ * Cast pointer to 'struct engine *'
+ * to

[PATCH 10/10] drm/amd/display: enable SI support in the Kconfig

2018-10-07 Thread Mauro Rossi 
CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled
---
 drivers/gpu/drm/amd/display/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index ed654a76c76a..c79afe89e6e2 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -15,6 +15,14 @@ config DRM_AMD_DC_DCN1_0
help
  RV family support for display engine
 
+config DRM_AMD_DC_SI
+   bool "AMD DC support for Southern Islands ASICs"
+   default n
+   help
+ Choose this option to enable new AMD DC support for SI asics
+ by default. This includes Tahiti, Pitcairn, Cape Verde, Oland
+ and Hainan.
+
 config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
-- 
2.17.1

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[RFC] drm/amd/display: add SI support to AMD DC

2018-10-07 Thread Mauro Rossi 
[PATCH 01/10] drm/amd/display: add asics info for SI parts
[PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
[PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
[PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
[PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
[PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
[PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
[PATCH 09/10] drm/amdgpu: enable DC support for SI parts
[PATCH 10/10] drm/amd/display: enable SI support in the Kconfig

The series adds preliminar SI support as a Proof Of Concept, 
based on the idea that DCE6 is similar to DCE8, to be reviewed and refined

Android-x86 need/motivation lies in the following chain of dependencies: 
Vulkan radv requires gbm gralloc prime_fd support,
gbm gralloc requires drm hwcomposer,
drm hwcomposer requires Atomic Display Framework, 
Atomic Display Framework requires AMD DC, currently not supporting SI.

So the goals are:
1) to get Vulkan radv working on SI parts for android-x86.
2) to remove the gap in SI (GCN 1st gen) not having atomic support. 

DCE6 specific code was implemented as a replica of existing DCE8 support
and based on how DCE8 specific code was added on top of DCE10,11 support
by adding dce60* sources, functions, macros for each existing in dce80*

CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC

During this first iteration of review, there are aspects to verify:
- dce60 code has been added mechanically, so there may be redundancies 
and space for refactoring part of the code
- dce60_resources was having too many building errors due to missing DCE6 macros
in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- gfx6 may require some ad hoc initialization, skipped for the moment
- Hainan specific code requires review, as some documentation and code paths
seem to point that famility may not have DCE6, please confirm
- video decoding blocks code have not been touched
- dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
- dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
- dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
- dc/amdgpu_dm/* changes may be incomplete
- Any other omissis to be reviewed
- Feedback on best testing strategy required

Review from an expert of the DC impacted modules is recommended

SW Layer
/===\
| DCDisplay Timing  ModeAsic|
| Interface Service Service Manager Capability* |
|   |
| Display   TopologyDisplay LinkAdapter |
| Path  Manager Capability  Service Service |
|   Service |
|---|
| GPIO* IRQ I2cAux  HW  BIOS|
|   Service**   Manager*Sequencer*  Parser* |
|   |
| Connector Encoder Audio   GPU Controller  |
|   |
\===/
HW Layer

Legend: 
*dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
**dce60 support was added using dce_8_0_{d,sh_mask}.h headers

Android-x86 preliminary tests results:

[Boots with drm gralloc]
3DMark Slingshot
GFXbench OpenGLES benchmarks OK
V1 GPU benchmark (OpenGLES) OK
Regression in Google Chrome, Youtube (app does not show up)
Regression in Olympus Rising,  Chicken Invaders (app does not show up)

[Boots with drm hwcomposer + gbm gralloc]
Google Chrome, Youtube are OK
Vulkan radv HAL API becomes available with hwc+gbm gralloc
V1 GPU benchmark (Vulkan API) OK
Sacha Willems examples OK
Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead

Kind regards

Mauro Rossi
android-x86 team

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[PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support

2018-10-07 Thread Mauro Rossi 
This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ef02d26f7151..e776ac33a857 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1638,6 +1638,13 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
 
/* Software is initialized. Now we can register interrupt handlers. */
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_OLAND:
+   case CHIP_HAINAN:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -1782,6 +1789,23 @@ static int dm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_HAINAN:
+   adev->mode_info.num_crtc = 6;
+   adev->mode_info.num_hpd = 6;
+   adev->mode_info.num_dig = 6;
+   adev->mode_info.plane_type = dm_plane_type_default;
+   break;
+   case CHIP_OLAND:
+   adev->mode_info.num_crtc = 2;
+   adev->mode_info.num_hpd = 2;
+   adev->mode_info.num_dig = 2;
+   adev->mode_info.plane_type = dm_plane_type_default;
+   break;
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
adev->mode_info.num_crtc = 6;
-- 
2.17.1

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