RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Oh, that mean I remember it reversed way, according to code looks we need to
enable ctx_switch to support WORLD SWITCH for SDMA engine
But better let Sigil confirm it ...
Hi @Ma, Sigil can you confirm it ? what's the relationship between ctx_swich
and world swich for SDMA engines ?
Ctx_switch_enable() will set "SDMA0/1_CNTL's field: AUTO_CTXSW_ENABLE" to 1,
can you tell us what's it for and how it go with SRIOV world switch ?
Thanks
/Monk
-Original Message-
From: Koenig, Christian
Sent: Tuesday, October 9, 2018 9:03 PM
To: Liu, Monk ; Huang, Ray ; Min, Frank
; Ma, Sigil
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Hi Monk,
well that doesn't make much sense to me what you say here cause context
switching certainly is already enabled under SRIOV:
> - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence
> doesn't need below to lines */
> - sdma_v4_0_ctx_switch_enable(adev, true);
> - sdma_v4_0_enable(adev, true);
> - }
The problem is that context switching as well as the gfx ring is enabled for
both SDMA0 and SDMA1 without initializing SDMA1.
That's most likely causing some unwanted consequences.
Christian.
Am 09.10.2018 um 13:45 schrieb Liu, Monk:
> Context switch is for preemption across different queues (gfx, rlc0/1,
> page) under bare-metal environment, For SRIOV we didn't need it and we didn't
> test it yet, so we just disable it to make life easier, besides since each VF
> share only 6 MS slice there is in fact no benefit to enable it for SRIOV ...
>
> + @Ma, Sigil to confirm
>
> Hi Sigil
>
> Do you think context switch could be enabled for SRIOV VF ?? I worry that the
> context switch have internal crush with preemption for world switch , thanks !
>
> /Monk
>
> -Original Message-
> From: Christian König
> Sent: Tuesday, October 9, 2018 6:57 PM
> To: Huang, Ray ; Liu, Monk ; Min,
> Frank
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
>
> Am 09.10.2018 um 11:17 schrieb Huang Rui:
>> On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
>>> [SNIP]
>>> - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>>> - r = sdma_v4_0_load_microcode(adev);
>>> + /* start the gfx rings and rlc compute queues */
>>> + for (i = 0; i < adev->sdma.num_instances; i++)
>>> + sdma_v4_0_gfx_resume(adev, i);
>>> +
>>> + if (amdgpu_sriov_vf(adev)) {
>>> + sdma_v4_0_ctx_switch_enable(adev, true);
>>> + sdma_v4_0_enable(adev, true);
>>> + } else {
>>> + r = sdma_v4_0_rlc_resume(adev);
>>> if (r)
>>> return r;
>>> }
>> + Monk, Frank,
>>
>> I probably cannot judge here, under SRIOV, I saw you disable ctx
>> switch before. Do you have any concern if we enabled it here.
> The problem was that those calls where mixed into sdma_v4_0_gfx_resume() for
> the first SDMA instance.
>
> What was happening is that SDMA0 was initialized and while doing so enabled
> both SDMA0 and SDMA1. So SDMA1 was starting up before the ring buffer was
> even set.
>
> That this doesn't crashed was pure coincident and is most likely also the
> reason why we ran into problems when ring buffers weren't initialized.
>
> Regards,
> Christian.
>
>> Others, looks good for me. Christian, may we know which kind of jobs
>> will use sdma page queue(ring), you know, we just sdma gfx queue(ring)
>> before?
>>
>> Thanks,
>> Ray
>>
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[PATCH v2] drm/amdgpu: Limit the max mc address to hole start
Replace AMDGPU_VA_HOLE_START with AMDGPU_GMC_HOLE_START, and add the comment in
code.
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..bb05d9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
{
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n");
@@ -164,7 +166,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
--
2.7.4
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[PATCH] drm/amdgpu: Limit the max mc address to hole start
Replace AMDGPU_VA_HOLE_START with AMDGPU_GMC_HOLE_START and add the comment.
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..bb05d9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
{
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n");
@@ -164,7 +166,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
--
2.7.4
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Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Ok.
BTW, Maybe we can remove the module parameter amdgpu_fw_load_type suppor .
It is only used for bring up/debug.
Best Regards
Rex
From: Deucher, Alexander
Sent: Wednesday, October 10, 2018 3:31 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Maybe just drop the warning altogether? We only support SMU loading on VI at
this point. Otherwise, we'll need to update this if we ever add a new fw
loading type.
Alex
From: amd-gfx on behalf of Rex Zhu
Sent: Tuesday, October 9, 2018 11:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Fix the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
v2: fix typo
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..01d794d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
+ if (load_type == AMDGPU_FW_LOAD_DIRECT || load_type ==
AMDGPU_FW_LOAD_PSP)
pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
--
1.9.1
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Re: [PATCH] Updated comment accuracy in PSP SOS/Sysdriver loading sequence to target bootloader instead of bootrom
On Tue, Oct 09, 2018 at 05:51:32PM -0400, John Clements wrote: > From: John Clements > Please add commit comment and signed-off in the patch. Thanks, Ray > --- > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c > index b70cfa3fe1b2..3fe30eb46d26 100644 > --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c > @@ -167,7 +167,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct > psp_context *psp) > /* Copy PSP System Driver binary to memory */ > memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); > > - /* Provide the sys driver to bootrom */ > + /* Provide the sys driver to bootloader */ > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, > (uint32_t)(psp->fw_pri_mc_addr >> 20)); > psp_gfxdrv_command_reg = 1 << 16; > @@ -208,7 +208,7 @@ static int psp_v11_0_bootloader_load_sos(struct > psp_context *psp) > /* Copy Secure OS binary to PSP memory */ > memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); > > - /* Provide the PSP secure OS to bootrom */ > + /* Provide the PSP secure OS to bootloader */ > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, > (uint32_t)(psp->fw_pri_mc_addr >> 20)); > psp_gfxdrv_command_reg = 2 << 16; > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > index e1ebf770c303..9cea0bbe4525 100644 > --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > @@ -194,7 +194,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct > psp_context *psp) > /* Copy PSP System Driver binary to memory */ > memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); > > - /* Provide the sys driver to bootrom */ > + /* Provide the sys driver to bootloader */ > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, > (uint32_t)(psp->fw_pri_mc_addr >> 20)); > psp_gfxdrv_command_reg = 1 << 16; > @@ -254,7 +254,7 @@ static int psp_v3_1_bootloader_load_sos(struct > psp_context *psp) > /* Copy Secure OS binary to PSP memory */ > memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); > > - /* Provide the PSP secure OS to bootrom */ > + /* Provide the PSP secure OS to bootloader */ > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, > (uint32_t)(psp->fw_pri_mc_addr >> 20)); > psp_gfxdrv_command_reg = 2 << 16; > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/2] drm/amd/display: Fix warning storm on Raven2
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of roman...@amd.com
> Sent: Wednesday, October 10, 2018 1:50 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Li, Sun peng (Leo) ; Wu, Hersen
> ; Wentland, Harry ;
> Li, Roman
> Subject: [PATCH 1/2] drm/amd/display: Fix warning storm on Raven2
>
> From: Roman Li
>
> [Why]
> Wrong index for pstate debug test register
>
> [How]
> Add correct index value for dcn1_01 in hubbub1_construct()
>
> Signed-off-by: Hersen Wu
> Signed-off-by: Roman Li
Thanks, Roman.
Series are also
Reviewed-by: Huang Rui
I will apply them directly to drm-next and dkms-4.18 for testing.
Thanks,
Ray
> ---
> .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 43
> +-
> 1 file changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
> index 69345ce6..4254e7e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
> @@ -133,7 +133,43 @@ bool hubbub1_verify_allow_pstate_change_high(
> forced_pstate_allow = false;
> }
>
> - /* RV1:
> + /* RV2:
> + * dchubbubdebugind, at: 0xB
> + * description
> + * 0: Pipe0 Plane0 Allow Pstate Change
> + * 1: Pipe0 Plane1 Allow Pstate Change
> + * 2: Pipe0 Cursor0 Allow Pstate Change
> + * 3: Pipe0 Cursor1 Allow Pstate Change
> + * 4: Pipe1 Plane0 Allow Pstate Change
> + * 5: Pipe1 Plane1 Allow Pstate Change
> + * 6: Pipe1 Cursor0 Allow Pstate Change
> + * 7: Pipe1 Cursor1 Allow Pstate Change
> + * 8: Pipe2 Plane0 Allow Pstate Change
> + * 9: Pipe2 Plane1 Allow Pstate Change
> + * 10:Pipe2 Cursor0 Allow Pstate Change
> + * 11:Pipe2 Cursor1 Allow Pstate Change
> + * 12:Pipe3 Plane0 Allow Pstate Change
> + * 13:Pipe3 Plane1 Allow Pstate Change
> + * 14:Pipe3 Cursor0 Allow Pstate Change
> + * 15:Pipe3 Cursor1 Allow Pstate Change
> + * 16:Pipe4 Plane0 Allow Pstate Change
> + * 17:Pipe4 Plane1 Allow Pstate Change
> + * 18:Pipe4 Cursor0 Allow Pstate Change
> + * 19:Pipe4 Cursor1 Allow Pstate Change
> + * 20:Pipe5 Plane0 Allow Pstate Change
> + * 21:Pipe5 Plane1 Allow Pstate Change
> + * 22:Pipe5 Cursor0 Allow Pstate Change
> + * 23:Pipe5 Cursor1 Allow Pstate Change
> + * 24:Pipe6 Plane0 Allow Pstate Change
> + * 25:Pipe6 Plane1 Allow Pstate Change
> + * 26:Pipe6 Cursor0 Allow Pstate Change
> + * 27:Pipe6 Cursor1 Allow Pstate Change
> + * 28:WB0 Allow Pstate Change
> + * 29:WB1 Allow Pstate Change
> + * 30:Arbiter's allow_pstate_change
> + * 31:SOC pstate change request"
> + *
> + * RV1:
>* dchubbubdebugind, at: 0x7
>* description "3-0: Pipe0 cursor0 QOS
>* 7-4: Pipe1 cursor0 QOS
> @@ -157,7 +193,6 @@ bool hubbub1_verify_allow_pstate_change_high(
>* 31:SOC pstate change request
>*/
>
> -
> REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub-
> >debug_test_index_pstate);
>
> for (i = 0; i < pstate_wait_timeout_us; i++) { @@ -819,5 +854,9 @@
> void hubbub1_construct(struct hubbub *hubbub,
> hubbub->masks = hubbub_mask;
>
> hubbub->debug_test_index_pstate = 0x7;
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + if (ctx->dce_version == DCN_VERSION_1_01)
> + hubbub->debug_test_index_pstate = 0xB; #endif
> }
>
> --
> 2.7.4
>
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RE: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of powerplay
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, October 10, 2018 3:28 AM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out
> of powerplay
>
> On Tue, Oct 9, 2018 at 8:45 AM Rex Zhu wrote:
> >
> > So there is no dependence between gfx/sdma/smu.
> > and for Vi, after IH hw_init, driver load all the smu/gfx/sdma fw. for
> > AI, fw loading is controlled by PSP, after psp hw init, we call the
> > function to check smu fw version.
> >
> > Signed-off-by: Rex Zhu
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30
> ++
> > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11
> > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 --
> > drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 20 ---
> > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
> > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 ++
> > drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5
> > 7 files changed, 32 insertions(+), 51 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 4787571..a6766b3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -1525,6 +1525,24 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> > return 0;
> > }
> >
> > +static int amdgpu_device_fw_loading(struct amdgpu_device *adev,
> > +uint32_t index) {
> > + int r = 0;
> > +
> > + if ((adev->asic_type < CHIP_VEGA10
> > +&& (adev->ip_blocks[index].version->type ==
> AMD_IP_BLOCK_TYPE_IH))
> > +|| (adev->asic_type >= CHIP_VEGA10
> > +&& (adev->ip_blocks[index].version->type ==
> > + AMD_IP_BLOCK_TYPE_PSP))) {
>
> This seems kind of fragile. If we change the order again at some point, it
> will
> break. How about we check whether hw_init/resume is done or not on the
> blocks we care about or move the checks into the callers and only call when
> we need it?
Hi Alex,
How about split hw_init to hw_init_phase1 and hw_init_phase2 as resume?
We loaded fw(call psp_hw_init and start_smu) between phase1 and phase2.
Regards
Rex
> > + if (adev->powerplay.pp_funcs->load_firmware) {
> > + r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> > + if (r) {
> > + pr_err("firmware loading failed\n");
> > + return r;
> > + }
> > + }
> > + }
> > + return 0;
> > +}
> > /**
> > * amdgpu_device_ip_init - run init for hardware IPs
> > *
> > @@ -1595,6 +1613,9 @@ static int amdgpu_device_ip_init(struct
> amdgpu_device *adev)
> > return r;
> > }
> > adev->ip_blocks[i].status.hw = true;
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> >
> > amdgpu_xgmi_add_device(adev);
> > @@ -2030,6 +2051,9 @@ static int
> amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
> > DRM_INFO("RE-INIT: %s %s\n",
> > block->version->funcs->name,
> r?"failed":"succeeded");
> > if (r)
> > return r;
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> > }
> >
> > @@ -2098,6 +2122,9 @@ static int
> amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
> >
> > adev->ip_blocks[i].version->funcs->name, r);
> > return r;
> > }
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> > }
> >
> > @@ -2134,6 +2161,9 @@ static int
> amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
> > adev->ip_blocks[i].version->funcs->name,
> > r);
> > return r;
> > }
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index 8439f9a..3d0f277 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -4175,20 +4175,9 @@ static void gfx_v8_0_rlc_start(struct
> > amdgpu_device *adev)
> >
> > static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) {
> > - int r;
> > -
> > gfx_v8_0_
RE: [PATCH 4/4] drm/amdgpu/powerplay: factor out some pptable helpers
Series is reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: 2018年10月10日 5:41
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 4/4] drm/amdgpu/powerplay: factor out some pptable
> helpers
>
> Move copy_array helpers to smu_helper.c and share between
> vega12 and vega20.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 44
>
> drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 12 +
> .../amd/powerplay/hwmgr/vega12_processpptables.c | 58 -
> -
> .../amd/powerplay/hwmgr/vega20_processpptables.c | 52 ++
> -
> 4 files changed, 70 insertions(+), 96 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> index 8ad4e6960efd..4714b5b59825 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> @@ -39,6 +39,50 @@ uint16_t convert_to_vddc(uint8_t vid)
> return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE); }
>
> +int phm_copy_clock_limits_array(
> + struct pp_hwmgr *hwmgr,
> + uint32_t **pptable_info_array,
> + const uint32_t *pptable_array,
> + uint32_t power_saving_clock_count)
> +{
> + uint32_t array_size, i;
> + uint32_t *table;
> +
> + array_size = sizeof(uint32_t) * power_saving_clock_count;
> + table = kzalloc(array_size, GFP_KERNEL);
> + if (NULL == table)
> + return -ENOMEM;
> +
> + for (i = 0; i < power_saving_clock_count; i++)
> + table[i] = le32_to_cpu(pptable_array[i]);
> +
> + *pptable_info_array = table;
> +
> + return 0;
> +}
> +
> +int phm_copy_overdrive_settings_limits_array(
> + struct pp_hwmgr *hwmgr,
> + uint32_t **pptable_info_array,
> + const uint32_t *pptable_array,
> + uint32_t od_setting_count)
> +{
> + uint32_t array_size, i;
> + uint32_t *table;
> +
> + array_size = sizeof(uint32_t) * od_setting_count;
> + table = kzalloc(array_size, GFP_KERNEL);
> + if (NULL == table)
> + return -ENOMEM;
> +
> + for (i = 0; i < od_setting_count; i++)
> + table[i] = le32_to_cpu(pptable_array[i]);
> +
> + *pptable_info_array = table;
> +
> + return 0;
> +}
> +
> uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32
> size) {
> u32 mask = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> index 5454289d5226..ad33983a8064 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> @@ -47,6 +47,18 @@ struct watermarks {
> uint32_t padding[7];
> };
>
> +int phm_copy_clock_limits_array(
> + struct pp_hwmgr *hwmgr,
> + uint32_t **pptable_info_array,
> + const uint32_t *pptable_array,
> + uint32_t power_saving_clock_count);
> +
> +int phm_copy_overdrive_settings_limits_array(
> + struct pp_hwmgr *hwmgr,
> + uint32_t **pptable_info_array,
> + const uint32_t *pptable_array,
> + uint32_t od_setting_count);
> +
> extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
> uint32_t index,
> uint32_t value, uint32_t mask);
> diff --git
> a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> index 3203cd2d2029..9817f7a5ed29 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> @@ -99,50 +99,6 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr,
> uint32_t powerplay_caps)
> return 0;
> }
>
> -static int copy_clock_limits_array(
> - struct pp_hwmgr *hwmgr,
> - uint32_t **pptable_info_array,
> - const uint32_t *pptable_array)
> -{
> - uint32_t array_size, i;
> - uint32_t *table;
> -
> - array_size = sizeof(uint32_t) * ATOM_VEGA12_PPCLOCK_COUNT;
> -
> - table = kzalloc(array_size, GFP_KERNEL);
> - if (NULL == table)
> - return -ENOMEM;
> -
> - for (i = 0; i < ATOM_VEGA12_PPCLOCK_COUNT; i++)
> - table[i] = le32_to_cpu(pptable_array[i]);
> -
> - *pptable_info_array = table;
> -
> - return 0;
> -}
> -
> -static int copy_overdrive_settings_limits_array(
> - struct pp_hwmgr *hwmgr,
> - uint32_t **pptable_info_array,
> - const uint32_t *pptable_array)
> -{
> - uint32_t array_size, i;
> - uint32_t *table;
> -
> - array_size = sizeof(uint32_t) * ATOM_VEGA12_ODSETTING_COUNT;
> -
> - table = kzalloc(array_size, GFP_KERNEL);
> - if (NULL == table)
> - return -ENOMEM;
> -
> - for (i = 0; i < ATOM_VEGA12_ODSETTING_COUNT; i++)
> - tab
Re: [PATCH 04/12] drm/amdgpu: move IV prescreening into the GMC code
I realized that most of the code in gmc_v9_0_psescreen_iv is not
actually hardware-specific. If it was not prescreening, but using an
amdgpu_iv_entry that was already parsed, I think it could just be a
generic function for processing retry faults:
* looking up the VM of a fault
* storing retry faults in a per-VM fifo
* dropping faults that have already been seen
In other words, it's just a generic top half interrupt handler for retry
faults while the bottom half (worker thread) would use the per-VM FIFOs
to handle those pending retry faults.
Regards,
Felix
On 2018-09-26 09:53 AM, Christian König wrote:
> The GMC/VM subsystem is causing the faults, so move the handling here as
> well.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 59 +
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 69
> --
> 2 files changed, 59 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 729a2c230f91..f8d69ab85fc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -244,6 +244,62 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
> amdgpu_device *adev,
> return 0;
> }
>
> +/**
> + * vega10_ih_prescreen_iv - prescreen an interrupt vector
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Returns true if the interrupt vector should be further processed.
> + */
> +static bool gmc_v9_0_prescreen_iv(struct amdgpu_device *adev,
> + struct amdgpu_iv_entry *entry,
> + uint64_t addr)
> +{
> + struct amdgpu_vm *vm;
> + u64 key;
> + int r;
> +
> + /* No PASID, can't identify faulting process */
> + if (!entry->pasid)
> + return true;
> +
> + /* Not a retry fault */
> + if (!(entry->src_data[1] & 0x80))
> + return true;
> +
> + /* Track retry faults in per-VM fault FIFO. */
> + spin_lock(&adev->vm_manager.pasid_lock);
> + vm = idr_find(&adev->vm_manager.pasid_idr, entry->pasid);
> + if (!vm) {
> + /* VM not found, process it normally */
> + spin_unlock(&adev->vm_manager.pasid_lock);
> + return true;
> + }
> +
> + key = AMDGPU_VM_FAULT(entry->pasid, addr);
> + r = amdgpu_vm_add_fault(vm->fault_hash, key);
> +
> + /* Hash table is full or the fault is already being processed,
> + * ignore further page faults
> + */
> + if (r != 0) {
> + spin_unlock(&adev->vm_manager.pasid_lock);
> + return false;
> + }
> + /* No locking required with single writer and single reader */
> + r = kfifo_put(&vm->faults, key);
> + if (!r) {
> + /* FIFO is full. Ignore it until there is space */
> + amdgpu_vm_clear_fault(vm->fault_hash, key);
> + spin_unlock(&adev->vm_manager.pasid_lock);
> + return false;
> + }
> +
> + spin_unlock(&adev->vm_manager.pasid_lock);
> + /* It's the first fault for this address, process it normally */
> + return true;
> +}
> +
> static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
> struct amdgpu_irq_src *source,
> struct amdgpu_iv_entry *entry)
> @@ -255,6 +311,9 @@ static int gmc_v9_0_process_interrupt(struct
> amdgpu_device *adev,
> addr = (u64)entry->src_data[0] << 12;
> addr |= ((u64)entry->src_data[1] & 0xf) << 44;
>
> + if (!gmc_v9_0_prescreen_iv(adev, entry, addr))
> + return 1;
> +
> if (!amdgpu_sriov_vf(adev)) {
> status = RREG32(hub->vm_l2_pro_fault_status);
> WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 0f50bef87163..0f68a0cd1fbf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -228,76 +228,7 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
> */
> static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
> {
> - u32 ring_index = adev->irq.ih.rptr >> 2;
> - u32 dw0, dw3, dw4, dw5;
> - u16 pasid;
> - u64 addr, key;
> - struct amdgpu_vm *vm;
> - int r;
> -
> - dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
> - dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
> - dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
> - dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
> -
> - /* Filter retry page faults, let only the first one pass. If
> - * there are too many outstanding faults, ignore them until
> - * some faults get cleared.
> - */
> - switch (dw0 & 0xff) {
> - case SOC15_IH_CLIENTID_VMC:
> - case SOC15_IH_CLIENTID_UTCL2:
> - break;
> - default:
> -
[PATCH] Updated comment accuracy in PSP SOS/Sysdriver loading sequence to target bootloader instead of bootrom
From: John Clements --- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index b70cfa3fe1b2..3fe30eb46d26 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -167,7 +167,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) /* Copy PSP System Driver binary to memory */ memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); - /* Provide the sys driver to bootrom */ + /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); psp_gfxdrv_command_reg = 1 << 16; @@ -208,7 +208,7 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) /* Copy Secure OS binary to PSP memory */ memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); - /* Provide the PSP secure OS to bootrom */ + /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); psp_gfxdrv_command_reg = 2 << 16; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index e1ebf770c303..9cea0bbe4525 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -194,7 +194,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) /* Copy PSP System Driver binary to memory */ memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); - /* Provide the sys driver to bootrom */ + /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); psp_gfxdrv_command_reg = 1 << 16; @@ -254,7 +254,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) /* Copy Secure OS binary to PSP memory */ memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); - /* Provide the PSP secure OS to bootrom */ + /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); psp_gfxdrv_command_reg = 2 << 16; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/4] drm/amdgpu/powerplay: factor out some pptable helpers
Move copy_array helpers to smu_helper.c and share between
vega12 and vega20.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 44
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 12 +
.../amd/powerplay/hwmgr/vega12_processpptables.c | 58 --
.../amd/powerplay/hwmgr/vega20_processpptables.c | 52 ++-
4 files changed, 70 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 8ad4e6960efd..4714b5b59825 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -39,6 +39,50 @@ uint16_t convert_to_vddc(uint8_t vid)
return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);
}
+int phm_copy_clock_limits_array(
+ struct pp_hwmgr *hwmgr,
+ uint32_t **pptable_info_array,
+ const uint32_t *pptable_array,
+ uint32_t power_saving_clock_count)
+{
+ uint32_t array_size, i;
+ uint32_t *table;
+
+ array_size = sizeof(uint32_t) * power_saving_clock_count;
+ table = kzalloc(array_size, GFP_KERNEL);
+ if (NULL == table)
+ return -ENOMEM;
+
+ for (i = 0; i < power_saving_clock_count; i++)
+ table[i] = le32_to_cpu(pptable_array[i]);
+
+ *pptable_info_array = table;
+
+ return 0;
+}
+
+int phm_copy_overdrive_settings_limits_array(
+ struct pp_hwmgr *hwmgr,
+ uint32_t **pptable_info_array,
+ const uint32_t *pptable_array,
+ uint32_t od_setting_count)
+{
+ uint32_t array_size, i;
+ uint32_t *table;
+
+ array_size = sizeof(uint32_t) * od_setting_count;
+ table = kzalloc(array_size, GFP_KERNEL);
+ if (NULL == table)
+ return -ENOMEM;
+
+ for (i = 0; i < od_setting_count; i++)
+ table[i] = le32_to_cpu(pptable_array[i]);
+
+ *pptable_info_array = table;
+
+ return 0;
+}
+
uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32
size)
{
u32 mask = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
index 5454289d5226..ad33983a8064 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
@@ -47,6 +47,18 @@ struct watermarks {
uint32_t padding[7];
};
+int phm_copy_clock_limits_array(
+ struct pp_hwmgr *hwmgr,
+ uint32_t **pptable_info_array,
+ const uint32_t *pptable_array,
+ uint32_t power_saving_clock_count);
+
+int phm_copy_overdrive_settings_limits_array(
+ struct pp_hwmgr *hwmgr,
+ uint32_t **pptable_info_array,
+ const uint32_t *pptable_array,
+ uint32_t od_setting_count);
+
extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index,
uint32_t value, uint32_t mask);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
index 3203cd2d2029..9817f7a5ed29 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
@@ -99,50 +99,6 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr,
uint32_t powerplay_caps)
return 0;
}
-static int copy_clock_limits_array(
- struct pp_hwmgr *hwmgr,
- uint32_t **pptable_info_array,
- const uint32_t *pptable_array)
-{
- uint32_t array_size, i;
- uint32_t *table;
-
- array_size = sizeof(uint32_t) * ATOM_VEGA12_PPCLOCK_COUNT;
-
- table = kzalloc(array_size, GFP_KERNEL);
- if (NULL == table)
- return -ENOMEM;
-
- for (i = 0; i < ATOM_VEGA12_PPCLOCK_COUNT; i++)
- table[i] = le32_to_cpu(pptable_array[i]);
-
- *pptable_info_array = table;
-
- return 0;
-}
-
-static int copy_overdrive_settings_limits_array(
- struct pp_hwmgr *hwmgr,
- uint32_t **pptable_info_array,
- const uint32_t *pptable_array)
-{
- uint32_t array_size, i;
- uint32_t *table;
-
- array_size = sizeof(uint32_t) * ATOM_VEGA12_ODSETTING_COUNT;
-
- table = kzalloc(array_size, GFP_KERNEL);
- if (NULL == table)
- return -ENOMEM;
-
- for (i = 0; i < ATOM_VEGA12_ODSETTING_COUNT; i++)
- table[i] = le32_to_cpu(pptable_array[i]);
-
- *pptable_info_array = table;
-
- return 0;
-}
-
static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t
*ppsmc_pptable)
{
struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table;
@@ -258,8 +214,14 @@ static int init_powerplay_table_information(
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
le32_to_cpu(powerplay_ta
[PATCH 2/4] drm/amdgpu/powerplay: endian fixes for vega12_processpptables.c
Properly swap data from vbios.
Signed-off-by: Alex Deucher
---
.../amd/powerplay/hwmgr/vega12_processpptables.c | 26 --
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
index cb3a5b1737c8..3203cd2d2029 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
@@ -114,7 +114,7 @@ static int copy_clock_limits_array(
return -ENOMEM;
for (i = 0; i < ATOM_VEGA12_PPCLOCK_COUNT; i++)
- table[i] = pptable_array[i];
+ table[i] = le32_to_cpu(pptable_array[i]);
*pptable_info_array = table;
@@ -136,7 +136,7 @@ static int copy_overdrive_settings_limits_array(
return -ENOMEM;
for (i = 0; i < ATOM_VEGA12_ODSETTING_COUNT; i++)
- table[i] = pptable_array[i];
+ table[i] = le32_to_cpu(pptable_array[i]);
*pptable_info_array = table;
@@ -250,11 +250,13 @@ static int init_powerplay_table_information(
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
- if (powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX] >
VEGA12_ENGINECLOCK_HARDMAX)
+ if
(le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX])
> VEGA12_ENGINECLOCK_HARDMAX)
hwmgr->platform_descriptor.overdriveLimit.engineClock =
VEGA12_ENGINECLOCK_HARDMAX;
else
- hwmgr->platform_descriptor.overdriveLimit.engineClock =
powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX];
- hwmgr->platform_descriptor.overdriveLimit.memoryClock =
powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX];
+ hwmgr->platform_descriptor.overdriveLimit.engineClock =
+
le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]);
+ hwmgr->platform_descriptor.overdriveLimit.memoryClock =
+
le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX]);
copy_overdrive_settings_limits_array(hwmgr,
&pptable_information->od_settings_max, powerplay_table->ODSettingsMax);
copy_overdrive_settings_limits_array(hwmgr,
&pptable_information->od_settings_min, powerplay_table->ODSettingsMin);
@@ -267,15 +269,15 @@ static int init_powerplay_table_information(
&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ACOverdriveSupport);
- pptable_information->us_small_power_limit1 =
powerplay_table->usSmallPowerLimit1;
- pptable_information->us_small_power_limit2 =
powerplay_table->usSmallPowerLimit2;
- pptable_information->us_boost_power_limit =
powerplay_table->usBoostPowerLimit;
- pptable_information->us_od_turbo_power_limit =
powerplay_table->usODTurboPowerLimit;
- pptable_information->us_od_powersave_power_limit =
powerplay_table->usODPowerSavePowerLimit;
+ pptable_information->us_small_power_limit1 =
le16_to_cpu(powerplay_table->usSmallPowerLimit1);
+ pptable_information->us_small_power_limit2 =
le16_to_cpu(powerplay_table->usSmallPowerLimit2);
+ pptable_information->us_boost_power_limit =
le16_to_cpu(powerplay_table->usBoostPowerLimit);
+ pptable_information->us_od_turbo_power_limit =
le16_to_cpu(powerplay_table->usODTurboPowerLimit);
+ pptable_information->us_od_powersave_power_limit =
le16_to_cpu(powerplay_table->usODPowerSavePowerLimit);
- pptable_information->us_software_shutdown_temp =
powerplay_table->usSoftwareShutdownTemp;
+ pptable_information->us_software_shutdown_temp =
le16_to_cpu(powerplay_table->usSoftwareShutdownTemp);
- hwmgr->platform_descriptor.TDPODLimit =
(uint16_t)powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE];
+ hwmgr->platform_descriptor.TDPODLimit =
le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]);
disable_power_control = 0;
if (!disable_power_control) {
--
2.13.6
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[PATCH 3/4] drm/amdgpu/powerplay: endian fixes for vega20_processpptables.c
Properly swap data from vbios.
Signed-off-by: Alex Deucher
---
.../amd/powerplay/hwmgr/vega20_processpptables.c | 41 +-
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
index c9b93e6487e4..956aa6aff28d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
@@ -676,7 +676,7 @@ static int copy_clock_limits_array(
return -ENOMEM;
for (i = 0; i < power_saving_clock_count; i++)
- table[i] = pptable_array[i];
+ table[i] = le32_to_cpu(pptable_array[i]);
*pptable_info_array = table;
@@ -698,7 +698,7 @@ static int copy_overdrive_settings_limits_array(
return -ENOMEM;
for (i = 0; i < od_setting_count; i++)
- table[i] = pptable_array[i];
+ table[i] = le32_to_cpu(pptable_array[i]);
*pptable_info_array = table;
@@ -721,7 +721,7 @@ static int copy_overdrive_feature_capabilities_array(
return -ENOMEM;
for (i = 0; i < od_feature_count; i++) {
- table[i] = pptable_array[i];
+ table[i] = le32_to_cpu(pptable_array[i]);
if (table[i])
od_supported = true;
}
@@ -844,10 +844,16 @@ static int init_powerplay_table_information(
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
- od_feature_count =
(powerplay_table->OverDrive8Table.ODFeatureCount > ATOM_VEGA20_ODFEATURE_COUNT)
?
- ATOM_VEGA20_ODFEATURE_COUNT :
powerplay_table->OverDrive8Table.ODFeatureCount;
- od_setting_count =
(powerplay_table->OverDrive8Table.ODSettingCount > ATOM_VEGA20_ODSETTING_COUNT)
?
- ATOM_VEGA20_ODSETTING_COUNT :
powerplay_table->OverDrive8Table.ODSettingCount;
+ od_feature_count =
+
(le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
+ATOM_VEGA20_ODFEATURE_COUNT) ?
+ ATOM_VEGA20_ODFEATURE_COUNT :
+
le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
+ od_setting_count =
+
(le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
+ATOM_VEGA20_ODSETTING_COUNT) ?
+ ATOM_VEGA20_ODSETTING_COUNT :
+
le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
copy_overdrive_feature_capabilities_array(hwmgr,
&pptable_information->od_feature_capabilities,
@@ -863,15 +869,15 @@ static int init_powerplay_table_information(
od_setting_count);
}
- pptable_information->us_small_power_limit1 =
powerplay_table->usSmallPowerLimit1;
- pptable_information->us_small_power_limit2 =
powerplay_table->usSmallPowerLimit2;
- pptable_information->us_boost_power_limit =
powerplay_table->usBoostPowerLimit;
- pptable_information->us_od_turbo_power_limit =
powerplay_table->usODTurboPowerLimit;
- pptable_information->us_od_powersave_power_limit =
powerplay_table->usODPowerSavePowerLimit;
+ pptable_information->us_small_power_limit1 =
le16_to_cpu(powerplay_table->usSmallPowerLimit1);
+ pptable_information->us_small_power_limit2 =
le16_to_cpu(powerplay_table->usSmallPowerLimit2);
+ pptable_information->us_boost_power_limit =
le16_to_cpu(powerplay_table->usBoostPowerLimit);
+ pptable_information->us_od_turbo_power_limit =
le16_to_cpu(powerplay_table->usODTurboPowerLimit);
+ pptable_information->us_od_powersave_power_limit =
le16_to_cpu(powerplay_table->usODPowerSavePowerLimit);
- pptable_information->us_software_shutdown_temp =
powerplay_table->usSoftwareShutdownTemp;
+ pptable_information->us_software_shutdown_temp =
le16_to_cpu(powerplay_table->usSoftwareShutdownTemp);
- hwmgr->platform_descriptor.TDPODLimit =
(uint16_t)powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE];
+ hwmgr->platform_descriptor.TDPODLimit =
le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
disable_power_control = 0;
if (!disable_power_control && hwmgr->platform_descriptor.TDPODLimit)
@@ -879,8 +885,11 @@ static int init_powerplay_table_information(
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerControl);
if (powerplay_table->PowerSavingClockTable.ucTableRevision == 1) {
- power_saving_clock_count =
(powerplay_table->PowerSaving
[PATCH 1/4] drm/amdgpu/powerplay: endian fixes for vega10_processpptables.c
Properly swap data from vbios.
Signed-off-by: Alex Deucher
---
.../amd/powerplay/hwmgr/vega10_processpptables.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index 16b1a9cf6cf0..b8747a5c9204 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -451,23 +451,23 @@ static int get_tdp_table(
le16_to_cpu(power_tune_table_v2->usLoadLineResistance);
} else {
power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table;
- tdp_table->usMaximumPowerDeliveryLimit =
power_tune_table_v3->usSocketPowerLimit;
- tdp_table->usTDC =
power_tune_table_v3->usTdcLimit;
- tdp_table->usEDCLimit=
power_tune_table_v3->usEdcLimit;
- tdp_table->usSoftwareShutdownTemp=
power_tune_table_v3->usSoftwareShutdownTemp;
- tdp_table->usTemperatureLimitTedge =
power_tune_table_v3->usTemperatureLimitTedge;
- tdp_table->usTemperatureLimitHotspot =
power_tune_table_v3->usTemperatureLimitHotSpot;
- tdp_table->usTemperatureLimitLiquid1 =
power_tune_table_v3->usTemperatureLimitLiquid1;
- tdp_table->usTemperatureLimitLiquid2 =
power_tune_table_v3->usTemperatureLimitLiquid2;
- tdp_table->usTemperatureLimitHBM =
power_tune_table_v3->usTemperatureLimitHBM;
- tdp_table->usTemperatureLimitVrVddc =
power_tune_table_v3->usTemperatureLimitVrSoc;
- tdp_table->usTemperatureLimitVrMvdd =
power_tune_table_v3->usTemperatureLimitVrMem;
- tdp_table->usTemperatureLimitPlx =
power_tune_table_v3->usTemperatureLimitPlx;
+ tdp_table->usMaximumPowerDeliveryLimit =
le16_to_cpu(power_tune_table_v3->usSocketPowerLimit);
+ tdp_table->usTDC =
le16_to_cpu(power_tune_table_v3->usTdcLimit);
+ tdp_table->usEDCLimit=
le16_to_cpu(power_tune_table_v3->usEdcLimit);
+ tdp_table->usSoftwareShutdownTemp=
le16_to_cpu(power_tune_table_v3->usSoftwareShutdownTemp);
+ tdp_table->usTemperatureLimitTedge =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitTedge);
+ tdp_table->usTemperatureLimitHotspot =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitHotSpot);
+ tdp_table->usTemperatureLimitLiquid1 =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid1);
+ tdp_table->usTemperatureLimitLiquid2 =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid2);
+ tdp_table->usTemperatureLimitHBM =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitHBM);
+ tdp_table->usTemperatureLimitVrVddc =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrSoc);
+ tdp_table->usTemperatureLimitVrMvdd =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrMem);
+ tdp_table->usTemperatureLimitPlx =
le16_to_cpu(power_tune_table_v3->usTemperatureLimitPlx);
tdp_table->ucLiquid1_I2C_address =
power_tune_table_v3->ucLiquid1_I2C_address;
tdp_table->ucLiquid2_I2C_address =
power_tune_table_v3->ucLiquid2_I2C_address;
- tdp_table->usBoostStartTemperature =
power_tune_table_v3->usBoostStartTemperature;
- tdp_table->usBoostStopTemperature=
power_tune_table_v3->usBoostStopTemperature;
- tdp_table->ulBoostClock =
power_tune_table_v3->ulBoostClock;
+ tdp_table->usBoostStartTemperature =
le16_to_cpu(power_tune_table_v3->usBoostStartTemperature);
+ tdp_table->usBoostStopTemperature=
le16_to_cpu(power_tune_table_v3->usBoostStopTemperature);
+ tdp_table->ulBoostClock =
le32_to_cpu(power_tune_table_v3->ulBoostClock);
get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl,
&sda);
--
2.13.6
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Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Maybe just drop the warning altogether? We only support SMU loading on VI at
this point. Otherwise, we'll need to update this if we ever add a new fw
loading type.
Alex
From: amd-gfx on behalf of Rex Zhu
Sent: Tuesday, October 9, 2018 11:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Fix the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
v2: fix typo
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..01d794d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
+ if (load_type == AMDGPU_FW_LOAD_DIRECT || load_type ==
AMDGPU_FW_LOAD_PSP)
pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
--
1.9.1
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Re: [PATCH 5/5] drm/amdgpu: Remove the direct fw loading support for sdma2.4
On Tue, Oct 9, 2018 at 8:45 AM Rex Zhu wrote:
>
> sdma2.4 is only for iceland. For Vi, we don't maintain the
> direct fw loading.
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 42
> --
> 1 file changed, 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index cd781ab..2d4770e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -504,41 +504,6 @@ static int sdma_v2_4_rlc_resume(struct amdgpu_device
> *adev)
> return 0;
> }
>
> -/**
> - * sdma_v2_4_load_microcode - load the sDMA ME ucode
> - *
> - * @adev: amdgpu_device pointer
> - *
> - * Loads the sDMA0/1 ucode.
> - * Returns 0 for success, -EINVAL if the ucode is not available.
> - */
> -static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
> -{
> - const struct sdma_firmware_header_v1_0 *hdr;
> - const __le32 *fw_data;
> - u32 fw_size;
> - int i, j;
> -
> - /* halt the MEs */
> - sdma_v2_4_enable(adev, false);
> -
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - if (!adev->sdma.instance[i].fw)
> - return -EINVAL;
> - hdr = (const struct sdma_firmware_header_v1_0
> *)adev->sdma.instance[i].fw->data;
> - amdgpu_ucode_print_sdma_hdr(&hdr->header);
> - fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> - fw_data = (const __le32 *)
> - (adev->sdma.instance[i].fw->data +
> -le32_to_cpu(hdr->header.ucode_array_offset_bytes));
> - WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
> - for (j = 0; j < fw_size; j++)
> - WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i],
> le32_to_cpup(fw_data++));
> - WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i],
> adev->sdma.instance[i].fw_version);
> - }
> -
> - return 0;
> -}
>
> /**
> * sdma_v2_4_start - setup and start the async dma engines
> @@ -552,13 +517,6 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
> {
> int r;
>
> -
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> - r = sdma_v2_4_load_microcode(adev);
> - if (r)
> - return r;
> - }
> -
> /* halt the engine before programing */
> sdma_v2_4_enable(adev, false);
>
> --
> 1.9.1
>
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Re: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of powerplay
On Tue, Oct 9, 2018 at 8:45 AM Rex Zhu wrote:
>
> So there is no dependence between gfx/sdma/smu.
> and for Vi, after IH hw_init, driver load all the smu/gfx/sdma
> fw. for AI, fw loading is controlled by PSP, after psp hw init,
> we call the function to check smu fw version.
>
> Signed-off-by: Rex Zhu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30
> ++
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 --
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 20 ---
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 ++
> drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5
> 7 files changed, 32 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 4787571..a6766b3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1525,6 +1525,24 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> return 0;
> }
>
> +static int amdgpu_device_fw_loading(struct amdgpu_device *adev, uint32_t
> index)
> +{
> + int r = 0;
> +
> + if ((adev->asic_type < CHIP_VEGA10
> +&& (adev->ip_blocks[index].version->type ==
> AMD_IP_BLOCK_TYPE_IH))
> +|| (adev->asic_type >= CHIP_VEGA10
> +&& (adev->ip_blocks[index].version->type ==
> AMD_IP_BLOCK_TYPE_PSP))) {
This seems kind of fragile. If we change the order again at some
point, it will break. How about we check whether hw_init/resume is
done or not on the blocks we care about or move the checks into the
callers and only call when we need it?
> + if (adev->powerplay.pp_funcs->load_firmware) {
> + r =
> adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
> + if (r) {
> + pr_err("firmware loading failed\n");
> + return r;
> + }
> + }
> + }
> + return 0;
> +}
> /**
> * amdgpu_device_ip_init - run init for hardware IPs
> *
> @@ -1595,6 +1613,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
> *adev)
> return r;
> }
> adev->ip_blocks[i].status.hw = true;
> + r = amdgpu_device_fw_loading(adev, i);
> + if (r)
> + return r;
> }
>
> amdgpu_xgmi_add_device(adev);
> @@ -2030,6 +2051,9 @@ static int amdgpu_device_ip_reinit_early_sriov(struct
> amdgpu_device *adev)
> DRM_INFO("RE-INIT: %s %s\n",
> block->version->funcs->name, r?"failed":"succeeded");
> if (r)
> return r;
> + r = amdgpu_device_fw_loading(adev, i);
> + if (r)
> + return r;
> }
> }
>
> @@ -2098,6 +2122,9 @@ static int amdgpu_device_ip_resume_phase1(struct
> amdgpu_device *adev)
>
> adev->ip_blocks[i].version->funcs->name, r);
> return r;
> }
> + r = amdgpu_device_fw_loading(adev, i);
> + if (r)
> + return r;
> }
> }
>
> @@ -2134,6 +2161,9 @@ static int amdgpu_device_ip_resume_phase2(struct
> amdgpu_device *adev)
> adev->ip_blocks[i].version->funcs->name, r);
> return r;
> }
> + r = amdgpu_device_fw_loading(adev, i);
> + if (r)
> + return r;
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 8439f9a..3d0f277 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4175,20 +4175,9 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device
> *adev)
>
> static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
> {
> - int r;
> -
> gfx_v8_0_rlc_stop(adev);
> gfx_v8_0_rlc_reset(adev);
> gfx_v8_0_init_pg(adev);
> -
> - if (adev->powerplay.pp_funcs->load_firmware) {
> - r =
> adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
> - if (r) {
> - pr_err("firmware loading failed\n");
> - return r;
> - }
> - }
> -
> gfx_v8_0_rlc_start(adev);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 0bdde7f..6fb3eda 100644
> --- a/drivers/gpu
Re: [PATCH 2/5] drm/amdgpu: Remove amdgpu_ucode_fini_bo
On Tue, Oct 9, 2018 at 8:44 AM Rex Zhu wrote:
>
> The variable clean is unnecessary.
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 19 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +--
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
> 4 files changed, 1 insertion(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index bd397d2..25d2f3e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -452,8 +452,6 @@ static int psp_hw_fini(void *handle)
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> return 0;
>
> - amdgpu_ucode_fini_bo(adev);
> -
> psp_ring_destroy(psp, PSP_RING_TYPE__KM);
>
> amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> index 7b6b2f4c..f2604ac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> @@ -489,22 +489,3 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
> }
> return 0;
> }
> -
> -int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
> -{
> - int i;
> - struct amdgpu_firmware_info *ucode = NULL;
> -
> - if (!adev->firmware.fw_size)
> - return 0;
> -
> - for (i = 0; i < adev->firmware.max_ucodes; i++) {
> - ucode = &adev->firmware.ucode[i];
> - if (ucode->fw) {
> - ucode->mc_addr = 0;
> - ucode->kaddr = NULL;
> - }
> - }
> -
> - return 0;
> -}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
> index 4c0e5be..05a2c46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
> @@ -276,9 +276,8 @@ struct amdgpu_firmware {
> int amdgpu_ucode_validate(const struct firmware *fw);
> bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
> uint16_t hdr_major, uint16_t hdr_minor);
> -int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
> -int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
>
> +int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
> void amdgpu_ucode_create_bo(struct amdgpu_device *adev);
> void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 6bc8e9c..75b56ae 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -109,9 +109,6 @@ static int pp_sw_fini(void *handle)
>
> hwmgr_sw_fini(hwmgr);
>
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> - amdgpu_ucode_fini_bo(adev);
> -
> release_firmware(adev->pm.fw);
> adev->pm.fw = NULL;
>
> --
> 1.9.1
>
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Re: [PATCH v2 1/5] drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
On Tue, Oct 9, 2018 at 11:36 AM Rex Zhu wrote:
>
> 1. one is for create/free bo when init/fini
> 2. one is for fill the bo before fw loading
>
> the ucode bo only need to be created when load driver
> and free when driver unload.
>
> when resume/reset, driver only need to re-fill the bo
> if the bo is allocated in vram.
>
> Suggested by Christian.
>
> v2: Return error when bo create failed.
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 58
> +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++
> 3 files changed, 36 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 94c92f5..680df05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1581,6 +1581,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
> *adev)
> }
> }
>
> + r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init
> complete*/
> + if (r)
> + return r;
> for (i = 0; i < adev->num_ip_blocks; i++) {
> if (!adev->ip_blocks[i].status.sw)
> continue;
> @@ -1803,6 +1806,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
> *adev)
> continue;
>
> if (adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_GMC) {
> + amdgpu_ucode_free_bo(adev);
> amdgpu_free_static_csa(adev);
> amdgpu_device_wb_fini(adev);
> amdgpu_device_vram_scratch_fini(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> index adfeb93..57ed384 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> @@ -422,32 +422,42 @@ static int amdgpu_ucode_patch_jt(struct
> amdgpu_firmware_info *ucode,
> return 0;
> }
>
> +int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
> +{
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
> + amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
> PAGE_SIZE,
> + amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM :
> AMDGPU_GEM_DOMAIN_GTT,
> + &adev->firmware.fw_buf,
> + &adev->firmware.fw_buf_mc,
> + &adev->firmware.fw_buf_ptr);
> + if (!adev->firmware.fw_buf) {
> + dev_err(adev->dev, "failed to create kernel buffer
> for firmware.fw_buf\n");
> + return -ENOMEM;
> + } else if (amdgpu_sriov_vf(adev)) {
> + memset(adev->firmware.fw_buf_ptr, 0,
> adev->firmware.fw_size);
> + }
> + }
> + return 0;
> +}
> +
> +void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
> +{
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
> + amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
> + &adev->firmware.fw_buf_mc,
> + &adev->firmware.fw_buf_ptr);
> +}
> +
> int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
> {
> uint64_t fw_offset = 0;
> - int i, err;
> + int i;
> struct amdgpu_firmware_info *ucode = NULL;
> const struct common_firmware_header *header = NULL;
>
> - if (!adev->firmware.fw_size) {
> - dev_warn(adev->dev, "No ip firmware need to load\n");
> + /* for baremetal, the ucode is allocated in gtt, so don't need to fill the
> bo when reset/suspend */
> + if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset ||
> adev->in_suspend))
> return 0;
> - }
> -
> - if (!adev->in_gpu_reset && !adev->in_suspend) {
> - err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
> PAGE_SIZE,
> - amdgpu_sriov_vf(adev) ?
> AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
> - &adev->firmware.fw_buf,
> - &adev->firmware.fw_buf_mc,
> - &adev->firmware.fw_buf_ptr);
> - if (err) {
> - dev_err(adev->dev, "failed to create kernel buffer
> for firmware.fw_buf\n");
> - goto failed;
> - }
> - }
> -
> - memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
> -
> /*
> * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
> * ucode info here
> @@ -479,12 +489,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
> }
> }
> return 0;
> -
> -failed:
> - if (err)
> - adev->firmware.load_type = AMDGP
Re: [PATCH 1/2] drm/amd/display: Fix warning storm on Raven2
Series is:
Acked-by: Alex Deucher
From: amd-gfx on behalf of
roman...@amd.com
Sent: Tuesday, October 9, 2018 1:50:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo); Wu, Hersen; Wentland, Harry; Li, Roman
Subject: [PATCH 1/2] drm/amd/display: Fix warning storm on Raven2
From: Roman Li
[Why]
Wrong index for pstate debug test register
[How]
Add correct index value for dcn1_01 in hubbub1_construct()
Signed-off-by: Hersen Wu
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 43 +-
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 69345ce6..4254e7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -133,7 +133,43 @@ bool hubbub1_verify_allow_pstate_change_high(
forced_pstate_allow = false;
}
- /* RV1:
+ /* RV2:
+* dchubbubdebugind, at: 0xB
+* description
+* 0: Pipe0 Plane0 Allow Pstate Change
+* 1: Pipe0 Plane1 Allow Pstate Change
+* 2: Pipe0 Cursor0 Allow Pstate Change
+* 3: Pipe0 Cursor1 Allow Pstate Change
+* 4: Pipe1 Plane0 Allow Pstate Change
+* 5: Pipe1 Plane1 Allow Pstate Change
+* 6: Pipe1 Cursor0 Allow Pstate Change
+* 7: Pipe1 Cursor1 Allow Pstate Change
+* 8: Pipe2 Plane0 Allow Pstate Change
+* 9: Pipe2 Plane1 Allow Pstate Change
+* 10:Pipe2 Cursor0 Allow Pstate Change
+* 11:Pipe2 Cursor1 Allow Pstate Change
+* 12:Pipe3 Plane0 Allow Pstate Change
+* 13:Pipe3 Plane1 Allow Pstate Change
+* 14:Pipe3 Cursor0 Allow Pstate Change
+* 15:Pipe3 Cursor1 Allow Pstate Change
+* 16:Pipe4 Plane0 Allow Pstate Change
+* 17:Pipe4 Plane1 Allow Pstate Change
+* 18:Pipe4 Cursor0 Allow Pstate Change
+* 19:Pipe4 Cursor1 Allow Pstate Change
+* 20:Pipe5 Plane0 Allow Pstate Change
+* 21:Pipe5 Plane1 Allow Pstate Change
+* 22:Pipe5 Cursor0 Allow Pstate Change
+* 23:Pipe5 Cursor1 Allow Pstate Change
+* 24:Pipe6 Plane0 Allow Pstate Change
+* 25:Pipe6 Plane1 Allow Pstate Change
+* 26:Pipe6 Cursor0 Allow Pstate Change
+* 27:Pipe6 Cursor1 Allow Pstate Change
+* 28:WB0 Allow Pstate Change
+* 29:WB1 Allow Pstate Change
+* 30:Arbiter's allow_pstate_change
+* 31:SOC pstate change request"
+*
+* RV1:
* dchubbubdebugind, at: 0x7
* description "3-0: Pipe0 cursor0 QOS
* 7-4: Pipe1 cursor0 QOS
@@ -157,7 +193,6 @@ bool hubbub1_verify_allow_pstate_change_high(
* 31:SOC pstate change request
*/
-
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);
for (i = 0; i < pstate_wait_timeout_us; i++) {
@@ -819,5 +854,9 @@ void hubbub1_construct(struct hubbub *hubbub,
hubbub->masks = hubbub_mask;
hubbub->debug_test_index_pstate = 0x7;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (ctx->dce_version == DCN_VERSION_1_01)
+ hubbub->debug_test_index_pstate = 0xB;
+#endif
}
--
2.7.4
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[PATCH 1/2] drm/amd/display: Fix warning storm on Raven2
From: Roman Li
[Why]
Wrong index for pstate debug test register
[How]
Add correct index value for dcn1_01 in hubbub1_construct()
Signed-off-by: Hersen Wu
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 43 +-
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 69345ce6..4254e7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -133,7 +133,43 @@ bool hubbub1_verify_allow_pstate_change_high(
forced_pstate_allow = false;
}
- /* RV1:
+ /* RV2:
+* dchubbubdebugind, at: 0xB
+* description
+* 0: Pipe0 Plane0 Allow Pstate Change
+* 1: Pipe0 Plane1 Allow Pstate Change
+* 2: Pipe0 Cursor0 Allow Pstate Change
+* 3: Pipe0 Cursor1 Allow Pstate Change
+* 4: Pipe1 Plane0 Allow Pstate Change
+* 5: Pipe1 Plane1 Allow Pstate Change
+* 6: Pipe1 Cursor0 Allow Pstate Change
+* 7: Pipe1 Cursor1 Allow Pstate Change
+* 8: Pipe2 Plane0 Allow Pstate Change
+* 9: Pipe2 Plane1 Allow Pstate Change
+* 10:Pipe2 Cursor0 Allow Pstate Change
+* 11:Pipe2 Cursor1 Allow Pstate Change
+* 12:Pipe3 Plane0 Allow Pstate Change
+* 13:Pipe3 Plane1 Allow Pstate Change
+* 14:Pipe3 Cursor0 Allow Pstate Change
+* 15:Pipe3 Cursor1 Allow Pstate Change
+* 16:Pipe4 Plane0 Allow Pstate Change
+* 17:Pipe4 Plane1 Allow Pstate Change
+* 18:Pipe4 Cursor0 Allow Pstate Change
+* 19:Pipe4 Cursor1 Allow Pstate Change
+* 20:Pipe5 Plane0 Allow Pstate Change
+* 21:Pipe5 Plane1 Allow Pstate Change
+* 22:Pipe5 Cursor0 Allow Pstate Change
+* 23:Pipe5 Cursor1 Allow Pstate Change
+* 24:Pipe6 Plane0 Allow Pstate Change
+* 25:Pipe6 Plane1 Allow Pstate Change
+* 26:Pipe6 Cursor0 Allow Pstate Change
+* 27:Pipe6 Cursor1 Allow Pstate Change
+* 28:WB0 Allow Pstate Change
+* 29:WB1 Allow Pstate Change
+* 30:Arbiter's allow_pstate_change
+* 31:SOC pstate change request"
+*
+* RV1:
* dchubbubdebugind, at: 0x7
* description "3-0: Pipe0 cursor0 QOS
* 7-4: Pipe1 cursor0 QOS
@@ -157,7 +193,6 @@ bool hubbub1_verify_allow_pstate_change_high(
* 31:SOC pstate change request
*/
-
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);
for (i = 0; i < pstate_wait_timeout_us; i++) {
@@ -819,5 +854,9 @@ void hubbub1_construct(struct hubbub *hubbub,
hubbub->masks = hubbub_mask;
hubbub->debug_test_index_pstate = 0x7;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (ctx->dce_version == DCN_VERSION_1_01)
+ hubbub->debug_test_index_pstate = 0xB;
+#endif
}
--
2.7.4
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[PATCH 2/2] drm/amd/display: RV2 DP MST 2nd display within daisy chain not light up
From: Hersen Wu
RV2 resource is limit to 3 pipes. Limitation should apply to all HW
blocks instead of front pipe.
Change-Id: I87e5d7084df2d60e1b2fa8a33d0d06ea73f8f71b
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 563847c..a71453a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -507,6 +507,18 @@ static const struct resource_caps res_cap = {
.num_ddc = 4,
};
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+static const struct resource_caps rv2_res_cap = {
+ .num_timing_generator = 3,
+ .num_opp = 3,
+ .num_video_plane = 3,
+ .num_audio = 3,
+ .num_stream_encoder = 3,
+ .num_pll = 3,
+ .num_ddc = 3,
+};
+#endif
+
static const struct dc_debug_options debug_defaults_drv = {
.sanity_checks = true,
.disable_dmcu = true,
@@ -1172,7 +1184,12 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
- pool->base.res_cap = &res_cap;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (ctx->dce_version == DCN_VERSION_1_01)
+ pool->base.res_cap = &rv2_res_cap;
+ else
+#endif
+ pool->base.res_cap = &res_cap;
pool->base.funcs = &dcn10_res_pool_funcs;
/*
--
2.7.4
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Re: [PATCH 3/3] drm/amdgpu: put HQD EOP buffers into VRAM
On Fri, Oct 5, 2018 at 5:01 PM Marek Olšák wrote:
>
> From: Marek Olšák
>
> This increases performance of compute queues.
> EOP events (PKT3_RELEASE_MEM) are stored into these buffers.
>
> Signed-off-by: Marek Olšák
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 0e72bc09939a..000180d79f30 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2774,21 +2774,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device
> *adev)
> bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
>
> /* take ownership of the relevant compute queues */
> amdgpu_gfx_compute_queue_acquire(adev);
>
> /* allocate space for ALL pipes (even the ones we don't own) */
> mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
> * GFX7_MEC_HPD_SIZE * 2;
>
> r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> + AMDGPU_GEM_DOMAIN_VRAM,
> &adev->gfx.mec.hpd_eop_obj,
> &adev->gfx.mec.hpd_eop_gpu_addr,
> (void **)&hpd);
> if (r) {
> dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo
> failed\n", r);
> gfx_v7_0_mec_fini(adev);
> return r;
> }
>
> /* clear memory. Not sure if this is required or not */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 191feafc3b60..8b6dae7a10bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1436,21 +1436,21 @@ static int gfx_v8_0_mec_init(struct amdgpu_device
> *adev)
> size_t mec_hpd_size;
>
> bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
>
> /* take ownership of the relevant compute queues */
> amdgpu_gfx_compute_queue_acquire(adev);
>
> mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
>
> r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> + AMDGPU_GEM_DOMAIN_VRAM,
> &adev->gfx.mec.hpd_eop_obj,
> &adev->gfx.mec.hpd_eop_gpu_addr,
> (void **)&hpd);
> if (r) {
> dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
> return r;
> }
>
> memset(hpd, 0, mec_hpd_size);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index a9d3d6a3fb41..3aaacf61d85e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1247,21 +1247,21 @@ static int gfx_v9_0_mec_init(struct amdgpu_device
> *adev)
>
> const struct gfx_firmware_header_v1_0 *mec_hdr;
>
> bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
>
> /* take ownership of the relevant compute queues */
> amdgpu_gfx_compute_queue_acquire(adev);
> mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
>
> r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> + AMDGPU_GEM_DOMAIN_VRAM,
> &adev->gfx.mec.hpd_eop_obj,
> &adev->gfx.mec.hpd_eop_gpu_addr,
> (void **)&hpd);
> if (r) {
> dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
> gfx_v9_0_mec_fini(adev);
> return r;
> }
>
> memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
> --
> 2.17.1
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers
On Fri, Oct 5, 2018 at 5:01 PM Marek Olšák wrote: > > From: Marek Olšák > > Signed-off-by: Marek Olšák > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- Any reason not to bump the size for gfx7 as well? Alex > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 77e05c19022a..191feafc3b60 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -47,21 +47,21 @@ > #include "gca/gfx_8_0_enum.h" > > #include "dce/dce_10_0_d.h" > #include "dce/dce_10_0_sh_mask.h" > > #include "smu/smu_7_1_3_d.h" > > #include "ivsrcid/ivsrcid_vislands30.h" > > #define GFX8_NUM_GFX_RINGS 1 > -#define GFX8_MEC_HPD_SIZE 2048 > +#define GFX8_MEC_HPD_SIZE 4096 > > #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 > #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 > #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 > #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 > > #define ARRAY_MODE(x) ((x) << > GB_TILE_MODE0__ARRAY_MODE__SHIFT) > #define PIPE_CONFIG(x) ((x) << > GB_TILE_MODE0__PIPE_CONFIG__SHIFT) > #define TILE_SPLIT(x) ((x) << > GB_TILE_MODE0__TILE_SPLIT__SHIFT) > #define MICRO_TILE_MODE_NEW(x) ((x) << > GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 4b020cc4bea9..a9d3d6a3fb41 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -34,21 +34,21 @@ > #include "vega10_enum.h" > #include "hdp/hdp_4_0_offset.h" > > #include "soc15_common.h" > #include "clearstate_gfx9.h" > #include "v9_structs.h" > > #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" > > #define GFX9_NUM_GFX_RINGS 1 > -#define GFX9_MEC_HPD_SIZE 2048 > +#define GFX9_MEC_HPD_SIZE 4096 > #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L > #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0xL > > #define mmPWR_MISC_CNTL_STATUS 0x0183 > #define mmPWR_MISC_CNTL_STATUS_BASE_IDX0 > #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 > #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 > #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x0001L > #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x0006L > > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Fix the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
v2: fix typo
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..01d794d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
+ if (load_type == AMDGPU_FW_LOAD_DIRECT || load_type ==
AMDGPU_FW_LOAD_PSP)
pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
--
1.9.1
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[PATCH v2 1/5] drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading
the ucode bo only need to be created when load driver
and free when driver unload.
when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.
Suggested by Christian.
v2: Return error when bo create failed.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 58 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++
3 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 94c92f5..680df05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1581,6 +1581,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init
complete*/
+ if (r)
+ return r;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw)
continue;
@@ -1803,6 +1806,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
continue;
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+ amdgpu_ucode_free_bo(adev);
amdgpu_free_static_csa(adev);
amdgpu_device_wb_fini(adev);
amdgpu_device_vram_scratch_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index adfeb93..57ed384 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -422,32 +422,42 @@ static int amdgpu_ucode_patch_jt(struct
amdgpu_firmware_info *ucode,
return 0;
}
+int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
+ amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
+ amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM :
AMDGPU_GEM_DOMAIN_GTT,
+ &adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
+ if (!adev->firmware.fw_buf) {
+ dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
+ return -ENOMEM;
+ } else if (amdgpu_sriov_vf(adev)) {
+ memset(adev->firmware.fw_buf_ptr, 0,
adev->firmware.fw_size);
+ }
+ }
+ return 0;
+}
+
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
+ amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
+}
+
int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
uint64_t fw_offset = 0;
- int i, err;
+ int i;
struct amdgpu_firmware_info *ucode = NULL;
const struct common_firmware_header *header = NULL;
- if (!adev->firmware.fw_size) {
- dev_warn(adev->dev, "No ip firmware need to load\n");
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo
when reset/suspend */
+ if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
return 0;
- }
-
- if (!adev->in_gpu_reset && !adev->in_suspend) {
- err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
PAGE_SIZE,
- amdgpu_sriov_vf(adev) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- &adev->firmware.fw_buf,
- &adev->firmware.fw_buf_mc,
- &adev->firmware.fw_buf_ptr);
- if (err) {
- dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
- goto failed;
- }
- }
-
- memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
-
/*
* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
* ucode info here
@@ -479,12 +489,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
}
}
return 0;
-
-failed:
- if (err)
- adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
-
- return err;
}
int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
@@ -503,9 +507,5 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
}
}
- amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
- &adev->firmware.fw_buf_mc,
-
RE: [PATCH 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
> -Original Message- > From: Michel Dänzer > Sent: Tuesday, October 9, 2018 9:19 PM > To: Zhu, Rex > Cc: amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 4/5] drm/amdgpu: Fix unnecessary warning in dmesg > > On 2018-10-09 2:43 p.m., Rex Zhu wrote: > > Fix the warning message: > > "-1 is not supported on VI" > > the -1 is the default fw load type, mean auto. > > > > Signed-off-by: Rex Zhu > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > > index f2604ac..e5b13b2 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > > @@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type > > case CHIP_POLARIS11: > > case CHIP_POLARIS12: > > case CHIP_VEGAM: > > - if (load_type != AMDGPU_FW_LOAD_SMU) > > + if (load_type != AMDGPU_FW_LOAD_DIRECT || load_type == > AMDGPU_FW_LOAD_PSP) > > AMDGPU_FW_LOAD_PSP == 2 != AMDGPU_FW_LOAD_DIRECT == 0 > > I suspect you meant something else here. Yes, it should be - if (load_type != AMDGPU_FW_LOAD_SMU) + if (load_type == AMDGPU_FW_LOAD_DIRECT || load_type == AMDGPU_FW_LOAD_PSP) Typo when split the patches. Thanks for pointing it out. Best Regards Rex > > -- > Earthling Michel Dänzer | http://www.amd.com > Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/radeon: ratelimit bo warnings
On 2018-10-05 7:14 p.m., Nick Alcock wrote: > On 5 Oct 2018, Michel Dänzer told this: > >> On 2018-10-04 9:58 p.m., Nick Alcock wrote: >>> So a few days ago I started getting sprays of these warnings -- >>> sorry, but because it was a few days ago I'm not sure what I was >>> running at the time (but it was probably either Stellaris or Chromium). >>> >>> Sep 25 22:06:34 mutilate err: : [ 544.718905] >>> [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc >>> Sep 25 22:06:34 mutilate err: : [ 544.718909] [drm:radeon_cs_ioctl] >>> *ERROR* Failed to parse relocation -2! >>> Sep 25 22:06:34 mutilate err: : [ 544.719710] >>> [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc >>> Sep 25 22:06:34 mutilate err: : [ 544.719714] [drm:radeon_cs_ioctl] >>> *ERROR* Failed to parse relocation -2! >>> Sep 25 22:06:34 mutilate err: : [ 544.719862] >>> [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc >>> Sep 25 22:06:34 mutilate err: : [ 544.719865] [drm:radeon_cs_ioctl] >>> *ERROR* Failed to parse relocation -2! >>> Sep 25 22:06:34 mutilate err: : [ 544.720772] >>> [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc >>> Sep 25 22:06:34 mutilate err: : [ 544.720778] [drm:radeon_cs_ioctl] >>> *ERROR* Failed to parse relocation -2! >> >> These are likely due to https://bugs.freedesktop.org/105381 , fixed in >> xf86-video-ati 18.1.0. > > This is with X server 1.20.0 and xf86-video-ati 18.0.1, so I concur. > > I'll upgrade once I'm back near the machine in question (I mean, I could > upgrade now but I'm 200 miles away so running an X server on it at > present is a bit pointless). > >>> Sep 25 22:06:34 mutilate warning: : [ 544.721415] radeon :01:00.0: vbo >>> resource seems too big for the bo >> >> Not sure this can also be caused by the above, but I guess it's possible. > > It can clearly be caused by *something*, and without anything obvious > going wrong in the user interface you can clearly get crazy log flooding > without the user being any the wiser. It doesn't really matter what > causes it, just that it is causable. :) > >>> This patch is against 4.18.11: I saw the warnings on 4.17.6 with Mesa >>> 18.1.2, but nothing much seems to have changed in this area so I bet >>> this could recur. >> >> Not sure it makes sense to have the last paragraph in the Git commit >> log, but either way: > > Yeah, I stuck it in the wrong place in the mail. (I meant to move it and > then completely forgot. Mea culpa.) > >> Reviewed-by: Michel Dänzer > > Thanks! Merged the patch for amd-staging-drm-next, will probably land for 4.20, thanks! -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
On 2018-10-09 2:43 p.m., Rex Zhu wrote: > Fix the warning message: > "-1 is not supported on VI" > the -1 is the default fw load type, mean auto. > > Signed-off-by: Rex Zhu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > index f2604ac..e5b13b2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > @@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type > case CHIP_POLARIS11: > case CHIP_POLARIS12: > case CHIP_VEGAM: > - if (load_type != AMDGPU_FW_LOAD_SMU) > + if (load_type != AMDGPU_FW_LOAD_DIRECT || load_type == > AMDGPU_FW_LOAD_PSP) AMDGPU_FW_LOAD_PSP == 2 != AMDGPU_FW_LOAD_DIRECT == 0 I suspect you meant something else here. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/5] drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
Am 09.10.2018 um 14:43 schrieb Rex Zhu:
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading
the ucode bo only need to be created when load driver
and free when driver unload.
when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.
Suggested by Christian.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 57 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++
3 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 94c92f5..4787571 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1581,6 +1581,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
+
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw)
continue;
@@ -1803,6 +1805,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
continue;
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+ amdgpu_ucode_free_bo(adev);
amdgpu_free_static_csa(adev);
amdgpu_device_wb_fini(adev);
amdgpu_device_vram_scratch_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index adfeb93..7b6b2f4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -422,32 +422,41 @@ static int amdgpu_ucode_patch_jt(struct
amdgpu_firmware_info *ucode,
return 0;
}
+void amdgpu_ucode_create_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
Better use early bailout here, e.g. in this case a return statement.
Apart from that looks good to me,
Christian.
+ amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
+ amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM :
AMDGPU_GEM_DOMAIN_GTT,
+ &adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
+ if (!adev->firmware.fw_buf) {
+ dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
+ adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
+ } else if (amdgpu_sriov_vf(adev)) {
+ memset(adev->firmware.fw_buf_ptr, 0,
adev->firmware.fw_size);
+ }
+ }
+}
+
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
+ amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
+}
+
int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
uint64_t fw_offset = 0;
- int i, err;
+ int i;
struct amdgpu_firmware_info *ucode = NULL;
const struct common_firmware_header *header = NULL;
- if (!adev->firmware.fw_size) {
- dev_warn(adev->dev, "No ip firmware need to load\n");
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo
when reset/suspend */
+ if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
return 0;
- }
-
- if (!adev->in_gpu_reset && !adev->in_suspend) {
- err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
PAGE_SIZE,
- amdgpu_sriov_vf(adev) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- &adev->firmware.fw_buf,
- &adev->firmware.fw_buf_mc,
- &adev->firmware.fw_buf_ptr);
- if (err) {
- dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
- goto failed;
- }
- }
-
- memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
-
/*
* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
* ucode info here
@@ -479,12 +488,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
}
}
return 0;
-
-failed:
- if (err)
- adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
-
- return err;
}
int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
@@ -503,9 +506,5 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
}
}
- amdgpu_bo_free_kernel(&adev->firmware.fw_b
Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Hi Monk,
well that doesn't make much sense to me what you say here cause context
switching certainly is already enabled under SRIOV:
> - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence
> doesn't need below to lines */
> - sdma_v4_0_ctx_switch_enable(adev, true);
> - sdma_v4_0_enable(adev, true);
> - }
The problem is that context switching as well as the gfx ring is enabled
for both SDMA0 and SDMA1 without initializing SDMA1.
That's most likely causing some unwanted consequences.
Christian.
Am 09.10.2018 um 13:45 schrieb Liu, Monk:
> Context switch is for preemption across different queues (gfx, rlc0/1, page)
> under bare-metal environment,
> For SRIOV we didn't need it and we didn't test it yet, so we just disable it
> to make life easier, besides since each VF share only 6 MS slice there is in
> fact no benefit to enable it for SRIOV ...
>
> + @Ma, Sigil to confirm
>
> Hi Sigil
>
> Do you think context switch could be enabled for SRIOV VF ?? I worry that the
> context switch have internal crush with preemption for world switch , thanks !
>
> /Monk
>
> -Original Message-
> From: Christian König
> Sent: Tuesday, October 9, 2018 6:57 PM
> To: Huang, Ray ; Liu, Monk ; Min, Frank
>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
>
> Am 09.10.2018 um 11:17 schrieb Huang Rui:
>> On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
>>> [SNIP]
>>> - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>>> - r = sdma_v4_0_load_microcode(adev);
>>> + /* start the gfx rings and rlc compute queues */
>>> + for (i = 0; i < adev->sdma.num_instances; i++)
>>> + sdma_v4_0_gfx_resume(adev, i);
>>> +
>>> + if (amdgpu_sriov_vf(adev)) {
>>> + sdma_v4_0_ctx_switch_enable(adev, true);
>>> + sdma_v4_0_enable(adev, true);
>>> + } else {
>>> + r = sdma_v4_0_rlc_resume(adev);
>>> if (r)
>>> return r;
>>> }
>> + Monk, Frank,
>>
>> I probably cannot judge here, under SRIOV, I saw you disable ctx
>> switch before. Do you have any concern if we enabled it here.
> The problem was that those calls where mixed into sdma_v4_0_gfx_resume() for
> the first SDMA instance.
>
> What was happening is that SDMA0 was initialized and while doing so enabled
> both SDMA0 and SDMA1. So SDMA1 was starting up before the ring buffer was
> even set.
>
> That this doesn't crashed was pure coincident and is most likely also the
> reason why we ran into problems when ring buffers weren't initialized.
>
> Regards,
> Christian.
>
>> Others, looks good for me. Christian, may we know which kind of jobs
>> will use sdma page queue(ring), you know, we just sdma gfx queue(ring)
>> before?
>>
>> Thanks,
>> Ray
>>
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[PATCH 5/5] drm/amdgpu: Remove the direct fw loading support for sdma2.4
sdma2.4 is only for iceland. For Vi, we don't maintain the
direct fw loading.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 42 --
1 file changed, 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index cd781ab..2d4770e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -504,41 +504,6 @@ static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
return 0;
}
-/**
- * sdma_v2_4_load_microcode - load the sDMA ME ucode
- *
- * @adev: amdgpu_device pointer
- *
- * Loads the sDMA0/1 ucode.
- * Returns 0 for success, -EINVAL if the ucode is not available.
- */
-static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
-{
- const struct sdma_firmware_header_v1_0 *hdr;
- const __le32 *fw_data;
- u32 fw_size;
- int i, j;
-
- /* halt the MEs */
- sdma_v2_4_enable(adev, false);
-
- for (i = 0; i < adev->sdma.num_instances; i++) {
- if (!adev->sdma.instance[i].fw)
- return -EINVAL;
- hdr = (const struct sdma_firmware_header_v1_0
*)adev->sdma.instance[i].fw->data;
- amdgpu_ucode_print_sdma_hdr(&hdr->header);
- fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
- fw_data = (const __le32 *)
- (adev->sdma.instance[i].fw->data +
-le32_to_cpu(hdr->header.ucode_array_offset_bytes));
- WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
- for (j = 0; j < fw_size; j++)
- WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i],
le32_to_cpup(fw_data++));
- WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i],
adev->sdma.instance[i].fw_version);
- }
-
- return 0;
-}
/**
* sdma_v2_4_start - setup and start the async dma engines
@@ -552,13 +517,6 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
{
int r;
-
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- r = sdma_v2_4_load_microcode(adev);
- if (r)
- return r;
- }
-
/* halt the engine before programing */
sdma_v2_4_enable(adev, false);
--
1.9.1
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[PATCH 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Fix the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index f2604ac..e5b13b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
+ if (load_type != AMDGPU_FW_LOAD_DIRECT || load_type ==
AMDGPU_FW_LOAD_PSP)
pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
--
1.9.1
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[PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of powerplay
So there is no dependence between gfx/sdma/smu.
and for Vi, after IH hw_init, driver load all the smu/gfx/sdma
fw. for AI, fw loading is controlled by PSP, after psp hw init,
we call the function to check smu fw version.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30 ++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 --
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 20 ---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 ++
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5
7 files changed, 32 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4787571..a6766b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1525,6 +1525,24 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
return 0;
}
+static int amdgpu_device_fw_loading(struct amdgpu_device *adev, uint32_t index)
+{
+ int r = 0;
+
+ if ((adev->asic_type < CHIP_VEGA10
+&& (adev->ip_blocks[index].version->type == AMD_IP_BLOCK_TYPE_IH))
+|| (adev->asic_type >= CHIP_VEGA10
+&& (adev->ip_blocks[index].version->type ==
AMD_IP_BLOCK_TYPE_PSP))) {
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+ }
+ return 0;
+}
/**
* amdgpu_device_ip_init - run init for hardware IPs
*
@@ -1595,6 +1613,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
return r;
}
adev->ip_blocks[i].status.hw = true;
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
amdgpu_xgmi_add_device(adev);
@@ -2030,6 +2051,9 @@ static int amdgpu_device_ip_reinit_early_sriov(struct
amdgpu_device *adev)
DRM_INFO("RE-INIT: %s %s\n",
block->version->funcs->name, r?"failed":"succeeded");
if (r)
return r;
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
}
@@ -2098,6 +2122,9 @@ static int amdgpu_device_ip_resume_phase1(struct
amdgpu_device *adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
}
@@ -2134,6 +2161,9 @@ static int amdgpu_device_ip_resume_phase2(struct
amdgpu_device *adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8439f9a..3d0f277 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4175,20 +4175,9 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device
*adev)
static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
{
- int r;
-
gfx_v8_0_rlc_stop(adev);
gfx_v8_0_rlc_reset(adev);
gfx_v8_0_init_pg(adev);
-
- if (adev->powerplay.pp_funcs->load_firmware) {
- r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
- if (r) {
- pr_err("firmware loading failed\n");
- return r;
- }
- }
-
gfx_v8_0_rlc_start(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 0bdde7f..6fb3eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -788,14 +788,6 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
{
int r;
- if (adev->powerplay.pp_funcs->load_firmware) {
- r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
- if (r) {
- pr_err("firmware loading failed\n");
- return r;
- }
- }
-
/* disable sdma engine before programing it */
sdma_v3_0_ctx
[PATCH 1/5] drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading
the ucode bo only need to be created when load driver
and free when driver unload.
when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.
Suggested by Christian.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 57 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++
3 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 94c92f5..4787571 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1581,6 +1581,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
+
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw)
continue;
@@ -1803,6 +1805,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
continue;
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+ amdgpu_ucode_free_bo(adev);
amdgpu_free_static_csa(adev);
amdgpu_device_wb_fini(adev);
amdgpu_device_vram_scratch_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index adfeb93..7b6b2f4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -422,32 +422,41 @@ static int amdgpu_ucode_patch_jt(struct
amdgpu_firmware_info *ucode,
return 0;
}
+void amdgpu_ucode_create_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
+ amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
+ amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM :
AMDGPU_GEM_DOMAIN_GTT,
+ &adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
+ if (!adev->firmware.fw_buf) {
+ dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
+ adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
+ } else if (amdgpu_sriov_vf(adev)) {
+ memset(adev->firmware.fw_buf_ptr, 0,
adev->firmware.fw_size);
+ }
+ }
+}
+
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
+ amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
+}
+
int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
uint64_t fw_offset = 0;
- int i, err;
+ int i;
struct amdgpu_firmware_info *ucode = NULL;
const struct common_firmware_header *header = NULL;
- if (!adev->firmware.fw_size) {
- dev_warn(adev->dev, "No ip firmware need to load\n");
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo
when reset/suspend */
+ if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
return 0;
- }
-
- if (!adev->in_gpu_reset && !adev->in_suspend) {
- err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
PAGE_SIZE,
- amdgpu_sriov_vf(adev) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- &adev->firmware.fw_buf,
- &adev->firmware.fw_buf_mc,
- &adev->firmware.fw_buf_ptr);
- if (err) {
- dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
- goto failed;
- }
- }
-
- memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
-
/*
* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
* ucode info here
@@ -479,12 +488,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
}
}
return 0;
-
-failed:
- if (err)
- adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
-
- return err;
}
int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
@@ -503,9 +506,5 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
}
}
- amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
- &adev->firmware.fw_buf_mc,
- &adev->firmware.fw_buf_ptr);
-
return 0;
}
diff
[PATCH 2/5] drm/amdgpu: Remove amdgpu_ucode_fini_bo
The variable clean is unnecessary.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 19 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +--
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
4 files changed, 1 insertion(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index bd397d2..25d2f3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -452,8 +452,6 @@ static int psp_hw_fini(void *handle)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
return 0;
- amdgpu_ucode_fini_bo(adev);
-
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 7b6b2f4c..f2604ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -489,22 +489,3 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
}
return 0;
}
-
-int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
-{
- int i;
- struct amdgpu_firmware_info *ucode = NULL;
-
- if (!adev->firmware.fw_size)
- return 0;
-
- for (i = 0; i < adev->firmware.max_ucodes; i++) {
- ucode = &adev->firmware.ucode[i];
- if (ucode->fw) {
- ucode->mc_addr = 0;
- ucode->kaddr = NULL;
- }
- }
-
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 4c0e5be..05a2c46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -276,9 +276,8 @@ struct amdgpu_firmware {
int amdgpu_ucode_validate(const struct firmware *fw);
bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
uint16_t hdr_major, uint16_t hdr_minor);
-int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
-int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
+int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
void amdgpu_ucode_create_bo(struct amdgpu_device *adev);
void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 6bc8e9c..75b56ae 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -109,9 +109,6 @@ static int pp_sw_fini(void *handle)
hwmgr_sw_fini(hwmgr);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- amdgpu_ucode_fini_bo(adev);
-
release_firmware(adev->pm.fw);
adev->pm.fw = NULL;
--
1.9.1
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Re: [PATCH v3 1/4] drm: Add vrr_capable property to the drm connector
On 10/05/2018 06:10 PM, Manasi Navare wrote:
On Fri, Oct 05, 2018 at 04:39:46PM -0400, Nicholas Kazlauskas wrote:
Modern display hardware is capable of supporting variable refresh rates.
This patch introduces the "vrr_capable" property on the connector to
allow userspace to query support for variable refresh rates.
Atomic drivers should attach this property to connectors that are
capable of driving variable refresh rates using
drm_connector_attach_vrr_capable_property().
The value should be updated based on driver and hardware capabiltiy
by using drm_connector_set_vrr_capable_property().
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/drm_connector.c | 51 +
include/drm/drm_connector.h | 15 ++
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 1e40e5decbe9..3283703b9822 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1254,6 +1254,39 @@ int drm_mode_create_scaling_mode_property(struct
drm_device *dev)
}
EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
+/**
+ * drm_connector_attach_vrr_capable_property - creates the
+ * vrr_capable property
+ * @connector: connector to create the vrr_capable property on.
+ *
+ * This is used by atomic drivers to add support for querying
+ * variable refresh rate capability for a connector.
+ *
+ * The value from &drm_connector_state.vrr_capable will reads
+ *
The sentence above looks incomplete.
Other than that this patch looks good to me. So with the kernel doc fixes:
Reviewed-by: Manasi Navare
Manasi
Thanks, looks like this line should have just been removed as part of
the immutable prop refactoring for vrr_capable.
+ * Returns:
+ * Zero on success, negative errono on failure.
+ */
+int drm_connector_attach_vrr_capable_property(
+ struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *prop;
+
+ if (!connector->vrr_capable_property) {
+ prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE,
+ "vrr_capable");
+ if (!prop)
+ return -ENOMEM;
+
+ connector->vrr_capable_property = prop;
+ drm_object_attach_property(&connector->base, prop, 0);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_vrr_capable_property);
+
/**
* drm_connector_attach_scaling_mode_property - attach atomic scaling mode
property
* @connector: connector to attach scaling mode property on.
@@ -1582,6 +1615,24 @@ void drm_connector_set_link_status_property(struct
drm_connector *connector,
}
EXPORT_SYMBOL(drm_connector_set_link_status_property);
+/**
+ * drm_connector_set_vrr_capable_property - sets the variable refresh rate
+ * capable property for a connector
+ * @connector: drm connector
+ * @capable: True if the connector is variable refresh rate capable
+ *
+ * Should be used by atomic drivers to update the indicated support for
+ * variable refresh rate over a connector.
+ */
+void drm_connector_set_vrr_capable_property(
+ struct drm_connector *connector, bool capable)
+{
+ return drm_object_property_set_value(&connector->base,
+connector->vrr_capable_property,
+capable);
+}
+EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
+
/**
* drm_connector_init_panel_orientation_property -
*initialize the connecters panel_orientation property
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 91a877fa00cb..b2263005234a 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -910,6 +910,17 @@ struct drm_connector {
*/
struct drm_property *scaling_mode_property;
+ /**
+* @vrr_capable_property: Optional property to help userspace
+* query hardware support for variable refresh rate on a connector.
+* connector. Drivers can add the property to a connector by
+* calling drm_connector_attach_vrr_capable_property().
+*
+* This should be updated only by calling
+* drm_connector_set_vrr_capable_property().
+*/
+ struct drm_property *vrr_capable_property;
+
/**
* @content_protection_property: DRM ENUM property for content
* protection. See drm_connector_attach_content_protection_property().
@@ -1183,6 +1194,8 @@ int drm_mode_create_scaling_mode_property(struct
drm_device *dev);
int drm_connector_attach_content_type_property(struct drm_connector *dev);
int drm_connector_attach_scaling_mode_property(struct drm_connector
*connector,
u32 scaling_mode_mask);
+int drm_connector_attach_vrr_capable_property(
+ struct drm_connector *connector);
int drm_connector_attach_conten
RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Context switch is for preemption across different queues (gfx, rlc0/1, page)
under bare-metal environment,
For SRIOV we didn't need it and we didn't test it yet, so we just disable it to
make life easier, besides since each VF share only 6 MS slice there is in fact
no benefit to enable it for SRIOV ...
+ @Ma, Sigil to confirm
Hi Sigil
Do you think context switch could be enabled for SRIOV VF ?? I worry that the
context switch have internal crush with preemption for world switch , thanks !
/Monk
-Original Message-
From: Christian König
Sent: Tuesday, October 9, 2018 6:57 PM
To: Huang, Ray ; Liu, Monk ; Min, Frank
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Am 09.10.2018 um 11:17 schrieb Huang Rui:
> On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
>> [SNIP]
>> -if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>> -r = sdma_v4_0_load_microcode(adev);
>> +/* start the gfx rings and rlc compute queues */
>> +for (i = 0; i < adev->sdma.num_instances; i++)
>> +sdma_v4_0_gfx_resume(adev, i);
>> +
>> +if (amdgpu_sriov_vf(adev)) {
>> +sdma_v4_0_ctx_switch_enable(adev, true);
>> +sdma_v4_0_enable(adev, true);
>> +} else {
>> +r = sdma_v4_0_rlc_resume(adev);
>> if (r)
>> return r;
>> }
> + Monk, Frank,
>
> I probably cannot judge here, under SRIOV, I saw you disable ctx
> switch before. Do you have any concern if we enabled it here.
The problem was that those calls where mixed into sdma_v4_0_gfx_resume() for
the first SDMA instance.
What was happening is that SDMA0 was initialized and while doing so enabled
both SDMA0 and SDMA1. So SDMA1 was starting up before the ring buffer was even
set.
That this doesn't crashed was pure coincident and is most likely also the
reason why we ran into problems when ring buffers weren't initialized.
Regards,
Christian.
>
> Others, looks good for me. Christian, may we know which kind of jobs
> will use sdma page queue(ring), you know, we just sdma gfx queue(ring) before?
>
> Thanks,
> Ray
>
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Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Am 09.10.2018 um 11:17 schrieb Huang Rui:
On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
[SNIP]
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- r = sdma_v4_0_load_microcode(adev);
+ /* start the gfx rings and rlc compute queues */
+ for (i = 0; i < adev->sdma.num_instances; i++)
+ sdma_v4_0_gfx_resume(adev, i);
+
+ if (amdgpu_sriov_vf(adev)) {
+ sdma_v4_0_ctx_switch_enable(adev, true);
+ sdma_v4_0_enable(adev, true);
+ } else {
+ r = sdma_v4_0_rlc_resume(adev);
if (r)
return r;
}
+ Monk, Frank,
I probably cannot judge here, under SRIOV, I saw you disable ctx switch
before. Do you have any concern if we enabled it here.
The problem was that those calls where mixed into sdma_v4_0_gfx_resume()
for the first SDMA instance.
What was happening is that SDMA0 was initialized and while doing so
enabled both SDMA0 and SDMA1. So SDMA1 was starting up before the ring
buffer was even set.
That this doesn't crashed was pure coincident and is most likely also
the reason why we ran into problems when ring buffers weren't initialized.
Regards,
Christian.
Others, looks good for me. Christian, may we know which kind of jobs will
use sdma page queue(ring), you know, we just sdma gfx queue(ring) before?
Thanks,
Ray
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Re: [PATCH] drm/amdgpu: fix AGP location with VRAM at 0x0
On Thu, Oct 04, 2018 at 11:02:10AM +0200, Christian König wrote:
> That also simplifies handling quite a bit.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 9a5b252784a1..999e15945355 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -200,16 +200,13 @@ void amdgpu_gmc_agp_location(struct amdgpu_device
> *adev, struct amdgpu_gmc *mc)
> }
>
> if (size_bf > size_af) {
> - mc->agp_start = mc->fb_start > mc->gart_start ?
> - mc->gart_end + 1 : 0;
> + mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
> mc->agp_size = size_bf;
> } else {
> - mc->agp_start = (mc->fb_start > mc->gart_start ?
> - mc->fb_end : mc->gart_end) + 1,
> + mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
> mc->agp_size = size_af;
> }
>
> - mc->agp_start = ALIGN(mc->agp_start, sixteen_gb);
> mc->agp_end = mc->agp_start + mc->agp_size - 1;
> dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
> mc->agp_size >> 20, mc->agp_start, mc->agp_end);
> --
> 2.14.1
>
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Re: [PATCH][drm-next] drm/amdgpu/powerplay: fix missing break in switch statements
On Mon, Oct 08, 2018 at 05:22:28PM +0100, Colin King wrote:
> From: Colin Ian King
>
> There are several switch statements that are missing break statements.
> Add missing breaks to handle any fall-throughs corner cases.
>
> Detected by CoverityScan, CID#1457175 ("Missing break in switch")
>
> Fixes: 18aafc59b106 ("drm/amd/powerplay: implement fw related smu interface
> for iceland.")
> Signed-off-by: Colin Ian King
Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 2 ++
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c| 2 ++
> drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 ++
> drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 ++
> drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 2 ++
> 5 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> index 18643e06bc6f..669bd0c2a16c 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> @@ -2269,11 +2269,13 @@ static uint32_t ci_get_offsetof(uint32_t type,
> uint32_t member)
> case DRAM_LOG_BUFF_SIZE:
> return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);
> }
> + break;
> case SMU_Discrete_DpmTable:
> switch (member) {
> case LowSclkInterruptThreshold:
> return offsetof(SMU7_Discrete_DpmTable,
> LowSclkInterruptT);
> }
> + break;
> }
> pr_debug("can't get the offset of type %x member %x\n", type, member);
> return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index ec14798e87b6..bddd6d09f887 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -2331,6 +2331,7 @@ static uint32_t fiji_get_offsetof(uint32_t type,
> uint32_t member)
> case DRAM_LOG_BUFF_SIZE:
> return offsetof(SMU73_SoftRegisters,
> DRAM_LOG_BUFF_SIZE);
> }
> + break;
> case SMU_Discrete_DpmTable:
> switch (member) {
> case UvdBootLevel:
> @@ -2340,6 +2341,7 @@ static uint32_t fiji_get_offsetof(uint32_t type,
> uint32_t member)
> case LowSclkInterruptThreshold:
> return offsetof(SMU73_Discrete_DpmTable,
> LowSclkInterruptThreshold);
> }
> + break;
> }
> pr_warn("can't get the offset of type %x member %x\n", type, member);
> return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index 73aa368a454e..2d4c7f167b88 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -2237,11 +2237,13 @@ static uint32_t iceland_get_offsetof(uint32_t type,
> uint32_t member)
> case DRAM_LOG_BUFF_SIZE:
> return offsetof(SMU71_SoftRegisters,
> DRAM_LOG_BUFF_SIZE);
> }
> + break;
> case SMU_Discrete_DpmTable:
> switch (member) {
> case LowSclkInterruptThreshold:
> return offsetof(SMU71_Discrete_DpmTable,
> LowSclkInterruptThreshold);
> }
> + break;
> }
> pr_warn("can't get the offset of type %x member %x\n", type, member);
> return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> index ae8378ed32ee..a2ba5b012866 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> @@ -2619,6 +2619,7 @@ static uint32_t tonga_get_offsetof(uint32_t type,
> uint32_t member)
> case DRAM_LOG_BUFF_SIZE:
> return offsetof(SMU72_SoftRegisters,
> DRAM_LOG_BUFF_SIZE);
> }
> + break;
> case SMU_Discrete_DpmTable:
> switch (member) {
> case UvdBootLevel:
> @@ -2628,6 +2629,7 @@ static uint32_t tonga_get_offsetof(uint32_t type,
> uint32_t member)
> case LowSclkInterruptThreshold:
> return offsetof(SMU72_Discrete_DpmTable,
> LowSclkInterruptThreshold);
> }
> + break;
> }
> pr_warn("can't get the offset of type %x member %x\n", type, member);
> return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> index 3d415fabbd93..9f71512b2510 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> @@ -2185,6 +2185,7 @@ sta
Re: [PATCH 8/8] drm/amdgpu: use paging queue for VM page table updates
On Mon, Oct 08, 2018 at 03:35:21PM +0200, Christian König wrote:
> Only for testing, not sure if we should keep it like this.
>
> Signed-off-by: Christian König
OK, I see. Page queue is for page table update. We might need more testing
for this change.
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index a362904d73f7..5fa80b231da3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2052,7 +2052,7 @@ static void sdma_v4_0_set_vm_pte_funcs(struct
> amdgpu_device *adev)
>
> adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - sched = &adev->sdma.instance[i].ring.sched;
> + sched = &adev->sdma.instance[i].page.sched;
> adev->vm_manager.vm_pte_rqs[i] =
> &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> }
> --
> 2.14.1
>
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Re: [PATCH 7/8] drm/amdgpu: activate paging queue on SDMA v4
On Mon, Oct 08, 2018 at 03:35:20PM +0200, Christian König wrote:
> Implement all the necessary stuff to get those extra rings working.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
We have four queue architecture, currently, if include page queue, we only
use two, is there any use case that we need also activate rlc0/rlc1?
Thanks,
Ray
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 324
> -
> 1 file changed, 274 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 55384bad7a70..a362904d73f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -427,6 +427,57 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring
> *ring)
> }
> }
>
> +/**
> + * sdma_v4_0_page_ring_get_wptr - get the current write pointer
> + *
> + * @ring: amdgpu ring pointer
> + *
> + * Get the current wptr from the hardware (VEGA10+).
> + */
> +static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + u64 wptr;
> +
> + if (ring->use_doorbell) {
> + /* XXX check if swapping is necessary on BE */
> + wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
> + } else {
> + wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
> + wptr = wptr << 32;
> + wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
> + }
> +
> + return wptr >> 2;
> +}
> +
> +/**
> + * sdma_v4_0_ring_set_wptr - commit the write pointer
> + *
> + * @ring: amdgpu ring pointer
> + *
> + * Write the wptr back to the hardware (VEGA10+).
> + */
> +static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->use_doorbell) {
> + u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
> +
> + /* XXX check if swapping is necessary on BE */
> + WRITE_ONCE(*wb, (ring->wptr << 2));
> + WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
> + } else {
> + uint64_t wptr = ring->wptr << 2;
> +
> + WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
> + lower_32_bits(wptr));
> + WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
> + upper_32_bits(wptr));
> + }
> +}
> +
> static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t
> count)
> {
> struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
> @@ -597,6 +648,35 @@ static void sdma_v4_0_rlc_stop(struct amdgpu_device
> *adev)
> /* XXX todo */
> }
>
> +/**
> + * sdma_v4_0_page_stop - stop the page async dma engines
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Stop the page async dma ring buffers (VEGA10).
> + */
> +static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
> +{
> + struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page;
> + struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page;
> + u32 rb_cntl, ib_cntl;
> + int i;
> +
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
> + RB_ENABLE, 0);
> + WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
> + ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
> + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
> + IB_ENABLE, 0);
> + WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
> + }
> +
> + sdma0->ready = false;
> + sdma1->ready = false;
> +}
> +
> /**
> * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
> *
> @@ -664,6 +744,7 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev,
> bool enable)
> if (enable == false) {
> sdma_v4_0_gfx_stop(adev);
> sdma_v4_0_rlc_stop(adev);
> + sdma_v4_0_page_stop(adev);
> }
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> @@ -673,6 +754,23 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev,
> bool enable)
> }
> }
>
> +/**
> + * sdma_v4_0_rb_cntl - get parameters for rb_cntl
> + */
> +static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
> +{
> + /* Set ring buffer size in dwords */
> + uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
> +
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
> +#ifdef __BIG_ENDIAN
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
> + RPTR_WRITEBACK_SWAP_ENABLE, 1);
> +#endif
> + return rb_cntl;
> +}
> +
> /**
> * sdma_v4_0
Re: [PATCH 6/8] drm/amdgpu: add some [WR]REG32_SDMA macros to sdma_v4_0.c
On Mon, Oct 08, 2018 at 03:35:19PM +0200, Christian König wrote:
> Significantly shortens the code.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 126
> -
> 1 file changed, 63 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 61da9b862ede..55384bad7a70 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -54,6 +54,11 @@ MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
> #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x00F8L
> #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC00L
>
> +#define WREG32_SDMA(instance, offset, value) \
> + WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
> +#define RREG32_SDMA(instance, offset) \
> + RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
> +
> static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
> static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
> static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
> @@ -367,8 +372,8 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct
> amdgpu_ring *ring)
> } else {
> u32 lowbit, highbit;
>
> - lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR)) >> 2;
> - highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
> + lowbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR) >> 2;
> + highbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI) >> 2;
>
> DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
> ring->me, highbit, lowbit);
> @@ -415,8 +420,10 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring
> *ring)
> lower_32_bits(ring->wptr << 2),
> ring->me,
> upper_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> + WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
> + lower_32_bits(ring->wptr << 2));
> + WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
> + upper_32_bits(ring->wptr << 2));
> }
> }
>
> @@ -566,12 +573,12 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device
> *adev)
> amdgpu_ttm_set_buffer_funcs_status(adev, false);
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_CNTL));
> + rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
> rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE,
> 0);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL),
> rb_cntl);
> - ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_IB_CNTL));
> + WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
> + ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
> ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE,
> 0);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL),
> ib_cntl);
> + WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
> }
>
> sdma0->ready = false;
> @@ -628,18 +635,15 @@ static void sdma_v4_0_ctx_switch_enable(struct
> amdgpu_device *adev, bool enable)
> }
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_CNTL));
> + f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
> f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> AUTO_CTXSW_ENABLE, enable ? 1 : 0);
> if (enable && amdgpu_sdma_phase_quantum) {
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_PHASE0_QUANTUM),
> -phase_quantum);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_PHASE1_QUANTUM),
> -phase_quantum);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_PHASE2_QUANTUM),
> -phase_quantum);
> + WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
> + WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
> + WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
> }
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL),
> f32_cntl);
> + WREG32_SDMA(i, mmSDMA0_CNTL,
Re: [PATCH 5/8] drm/amdgpu: remove SRIOV specific handling from sdma_v4_0_gfx_resume
On Mon, Oct 08, 2018 at 03:35:18PM +0200, Christian König wrote:
> Just use the same code path for both SRIOV and bare metal.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 1124b45d166d..61da9b862ede 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -723,11 +723,6 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device
> *adev, unsigned int i)
> /* before programing wptr to a less value, need set minor_ptr_update
> first */
> WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE),
> 1);
>
> - if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for
> wptr */
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
> lower_32_bits(ring->wptr) << 2);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
> - }
> -
> doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_DOORBELL));
> doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_DOORBELL_OFFSET));
>
> @@ -743,8 +738,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device
> *adev, unsigned int i)
> adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
> ring->doorbell_index);
>
> - if (amdgpu_sriov_vf(adev))
> - sdma_v4_0_ring_set_wptr(ring);
> + sdma_v4_0_ring_set_wptr(ring);
>
> /* set minor_ptr_update to 0 after wptr programed */
> WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE),
> 0);
> --
> 2.14.1
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 4/8] drm/amdgpu: remove non gfx specific handling from sdma_v4_0_gfx_resume
On Mon, Oct 08, 2018 at 03:35:17PM +0200, Christian König wrote:
> Needed to start using the paging queue.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 36
> +++---
> 1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 5ecf6c9252c4..1124b45d166d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -686,13 +686,10 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device
> *adev, unsigned int i)
> u32 wb_offset;
> u32 doorbell;
> u32 doorbell_offset;
> - u32 temp;
> u64 wptr_gpu_addr;
>
> wb_offset = (ring->rptr_offs * 4);
>
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
> -
> /* Set ring buffer size in dwords */
> rb_bufsz = order_base_2(ring->ring_size / 4);
> rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_CNTL));
> @@ -752,18 +749,6 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device
> *adev, unsigned int i)
> /* set minor_ptr_update to 0 after wptr programed */
> WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE),
> 0);
>
> - /* set utc l1 enable flag always to 1 */
> - temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
> - temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
> -
> - if (!amdgpu_sriov_vf(adev)) {
> - /* unhalt engine */
> - temp = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_F32_CNTL));
> - temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL),
> temp);
> - }
> -
> /* setup the wptr shadow polling */
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
> WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
> @@ -942,9 +927,28 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
> }
>
> /* start the gfx rings and rlc compute queues */
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + uint32_t temp;
> +
> + WREG32(sdma_v4_0_get_reg_offset(adev, i,
> + mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
> sdma_v4_0_gfx_resume(adev, i);
>
> + /* set utc l1 enable flag always to 1 */
> + temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
> + temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
> +
> + if (!amdgpu_sriov_vf(adev)) {
> + /* unhalt engine */
> + temp = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> + mmSDMA0_F32_CNTL));
> + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i,
> + mmSDMA0_F32_CNTL), temp);
> + }
> + }
> +
> if (amdgpu_sriov_vf(adev)) {
> sdma_v4_0_ctx_switch_enable(adev, true);
> sdma_v4_0_enable(adev, true);
> --
> 2.14.1
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 3/8] drm/amdgpu: add basics for SDMA page queue support
On Mon, Oct 08, 2018 at 03:35:16PM +0200, Christian König wrote:
> Just the common helper and a new ring in the SDMA instance.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 10 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 +
> 2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index bc9244b429ef..0fb9907494bb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -34,11 +34,9 @@ struct amdgpu_sdma_instance *
> amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
> int i;
>
> for (i = 0; i < adev->sdma.num_instances; i++)
> - if (&adev->sdma.instance[i].ring == ring)
> - break;
> + if (ring == &adev->sdma.instance[i].ring ||
> + ring == &adev->sdma.instance[i].page)
> + return &adev->sdma.instance[i];
>
> - if (i < AMDGPU_MAX_SDMA_INSTANCES)
> - return &adev->sdma.instance[i];
> - else
> - return NULL;
> + return NULL;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> index 500113ec65ca..556db42edaed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> @@ -41,6 +41,7 @@ struct amdgpu_sdma_instance {
> uint32_tfeature_version;
>
> struct amdgpu_ring ring;
> + struct amdgpu_ring page;
> boolburst_nop;
> };
>
> --
> 2.14.1
>
> ___
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
> Under SRIOV we were enabling the ring buffer before it was initialized.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 234
> -
> 1 file changed, 116 insertions(+), 118 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index c20d413f277c..5ecf6c9252c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -673,13 +673,14 @@ static void sdma_v4_0_enable(struct amdgpu_device
> *adev, bool enable)
> * sdma_v4_0_gfx_resume - setup and start the async dma engines
> *
> * @adev: amdgpu_device pointer
> + * @i: instance to resume
> *
> * Set up the gfx DMA ring buffers and enable them (VEGA10).
> * Returns 0 for success, error for failure.
> */
> -static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
> +static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
> {
> - struct amdgpu_ring *ring;
> + struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
> u32 rb_cntl, ib_cntl, wptr_poll_cntl;
> u32 rb_bufsz;
> u32 wb_offset;
> @@ -687,129 +688,108 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device
> *adev)
> u32 doorbell_offset;
> u32 temp;
> u64 wptr_gpu_addr;
> - int i, r;
>
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - ring = &adev->sdma.instance[i].ring;
> - wb_offset = (ring->rptr_offs * 4);
> + wb_offset = (ring->rptr_offs * 4);
>
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
>
> - /* Set ring buffer size in dwords */
> - rb_bufsz = order_base_2(ring->ring_size / 4);
> - rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_CNTL));
> - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE,
> rb_bufsz);
> + /* Set ring buffer size in dwords */
> + rb_bufsz = order_base_2(ring->ring_size / 4);
> + rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_CNTL));
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
> #ifdef __BIG_ENDIAN
> - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
> RB_SWAP_ENABLE, 1);
> - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
> - RPTR_WRITEBACK_SWAP_ENABLE, 1);
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
> + RPTR_WRITEBACK_SWAP_ENABLE, 1);
> #endif
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL),
> rb_cntl);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
>
> - /* Initialize the ring buffer's read and write pointers */
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR),
> 0);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_RPTR_HI), 0);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
> 0);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_WPTR_HI), 0);
> + /* Initialize the ring buffer's read and write pointers */
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
>
> - /* set the wb address whether it's enabled or not */
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_RPTR_ADDR_HI),
> -upper_32_bits(adev->wb.gpu_addr + wb_offset) &
> 0x);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
> mmSDMA0_GFX_RB_RPTR_ADDR_LO),
> -lower_32_bits(adev->wb.gpu_addr + wb_offset) &
> 0xFFFC);
> + /* set the wb address whether it's enabled or not */
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
> +upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0x);
> + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
> +lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFC);
>
> - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
> RPTR_WRITEBACK_ENABLE, 1);
> + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
> RPTR_WRITEBACK_ENABLE, 1);
>
> - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
> ring->gpu_addr >> 8);
> - WREG32(sdma_v4_0_get_reg_offset(adev, i,
[PATCH 6/6] drm/amdgpu: update version for timeline syncobj support in amdgpu
Signed-off-by: Chunming Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6870909da926..58cba492ba55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -70,9 +70,10 @@ * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. + * - 3.28.0 - Add syncobj timeline support to AMDGPU_CS. */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 27 +#define KMS_DRIVER_MINOR 28 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/6] drm: add timeline syncobj payload query ioctl v2
user mode can query timeline payload.
v2: check return value of copy_to_user
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 ++
drivers/gpu/drm/drm_ioctl.c| 2 ++
drivers/gpu/drm/drm_syncobj.c | 52 ++
include/uapi/drm/drm.h | 11 +++
4 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 566d44e3c782..9c4826411a3c 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -189,6 +189,8 @@ int drm_syncobj_reset_ioctl(struct drm_device *dev, void
*data,
struct drm_file *file_private);
int drm_syncobj_signal_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_private);
+int drm_syncobj_query_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_private);
/* drm_framebuffer.c */
void drm_framebuffer_print_info(struct drm_printer *p, unsigned int indent,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index c0891614f516..c3c0617e6372 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -675,6 +675,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_QUERY, drm_syncobj_query_ioctl,
+ DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_GET_SEQUENCE, drm_crtc_get_sequence_ioctl,
DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_QUEUE_SEQUENCE,
drm_crtc_queue_sequence_ioctl, DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_LEASE, drm_mode_create_lease_ioctl,
DRM_MASTER|DRM_UNLOCKED),
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index f3f11ac2ef28..17124d40532f 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -1304,3 +1304,55 @@ drm_syncobj_signal_ioctl(struct drm_device *dev, void
*data,
return ret;
}
+
+static void drm_syncobj_timeline_query_payload(struct drm_syncobj *syncobj,
+ uint64_t *point)
+{
+ if (syncobj->type != DRM_SYNCOBJ_TYPE_TIMELINE) {
+ DRM_ERROR("Normal syncobj cann't be queried!");
+ *point = 0;
+ return;
+ }
+ *point = syncobj->signal_point;
+}
+
+int drm_syncobj_query_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_private)
+{
+ struct drm_syncobj_timeline_query *args = data;
+ struct drm_syncobj **syncobjs;
+ uint64_t *points;
+ uint32_t i;
+ int ret;
+
+ if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+ return -ENODEV;
+
+ if (args->count_handles == 0)
+ return -EINVAL;
+
+ ret = drm_syncobj_array_find(file_private,
+u64_to_user_ptr(args->handles),
+args->count_handles,
+&syncobjs);
+ if (ret < 0)
+ return ret;
+
+
+ points = kmalloc_array(args->count_handles, sizeof(*points),
+ GFP_KERNEL);
+ if (points == NULL) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ for (i = 0; i < args->count_handles; i++)
+ drm_syncobj_timeline_query_payload(syncobjs[i], &points[i]);
+ ret = copy_to_user(u64_to_user_ptr(args->points), points,
+ sizeof(uint64_t) * args->count_handles) ? -EFAULT :
0;
+
+ kfree(points);
+out:
+ drm_syncobj_array_free(syncobjs, args->count_handles);
+
+ return ret;
+}
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index c8bc1414753d..23c4979d8a1c 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -771,6 +771,15 @@ struct drm_syncobj_array {
__u32 pad;
};
+struct drm_syncobj_timeline_query {
+ __u64 handles;
+ /* points are timeline syncobjs payloads returned by query ioctl */
+ __u64 points;
+ __u32 count_handles;
+ __u32 pad;
+};
+
+
/* Query current scanout sequence number */
struct drm_crtc_get_sequence {
__u32 crtc_id; /* requested crtc_id */
@@ -928,6 +937,8 @@ extern "C" {
#define DRM_IOCTL_MODE_REVOKE_LEASEDRM_IOWR(0xC9, struct
drm_mode_revoke_lease)
#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAITDRM_IOWR(0xCA, struct
drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERYDRM_IOWR(0xCB, struct
drm_syncobj_timeline_query)
+
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
--
2.17.1
___
[PATCH 5/6] drm/amdgpu: add timeline support in amdgpu CS v2
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 111 +
include/uapi/drm/amdgpu_drm.h | 9 ++
3 files changed, 112 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 447c4c7a36d6..6e4a3db56833 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -975,6 +975,11 @@ struct amdgpu_cs_chunk {
void*kdata;
};
+struct amdgpu_cs_syncobj_post_dep {
+ struct drm_syncobj *post_dep_syncobj;
+ u64 point;
+};
+
struct amdgpu_cs_parser {
struct amdgpu_device*adev;
struct drm_file *filp;
@@ -1003,9 +1008,8 @@ struct amdgpu_cs_parser {
/* user fence */
struct amdgpu_bo_list_entry uf_entry;
-
+ struct amdgpu_cs_syncobj_post_dep *post_dep_syncobjs;
unsigned num_post_dep_syncobjs;
- struct drm_syncobj **post_dep_syncobjs;
};
static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 412fac238575..7429e7941f4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -204,6 +204,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
case AMDGPU_CHUNK_ID_DEPENDENCIES:
case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
+ case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
+ case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
break;
default:
@@ -783,7 +785,7 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser
*parser, int error,
&parser->validated);
for (i = 0; i < parser->num_post_dep_syncobjs; i++)
- drm_syncobj_put(parser->post_dep_syncobjs[i]);
+ drm_syncobj_put(parser->post_dep_syncobjs[i].post_dep_syncobj);
kfree(parser->post_dep_syncobjs);
dma_fence_put(parser->fence);
@@ -1098,13 +1100,17 @@ static int amdgpu_cs_process_fence_dep(struct
amdgpu_cs_parser *p,
}
static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
-uint32_t handle)
+uint32_t handle, u64 point,
+u64 flags)
{
int r;
struct dma_fence *fence;
- r = drm_syncobj_find_fence(p->filp, handle, 0, 0, &fence);
- if (r)
+
+ r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
+ if (r) {
+ DRM_ERROR("syncobj %u failed to find fence!\n", handle);
return r;
+ }
r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
dma_fence_put(fence);
@@ -1115,46 +1121,108 @@ static int
amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
struct amdgpu_cs_chunk *chunk)
{
+ struct drm_amdgpu_cs_chunk_sem *deps;
unsigned num_deps;
int i, r;
- struct drm_amdgpu_cs_chunk_sem *deps;
deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
num_deps = chunk->length_dw * 4 /
sizeof(struct drm_amdgpu_cs_chunk_sem);
+ for (i = 0; i < num_deps; ++i) {
+ r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
+ 0, 0);
+ if (r)
+ return r;
+ }
+
+ return 0;
+}
+
+
+static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser
*p,
+struct amdgpu_cs_chunk
*chunk)
+{
+ struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
+ unsigned num_deps;
+ int i, r;
+ syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
+ num_deps = chunk->length_dw * 4 /
+ sizeof(struct drm_amdgpu_cs_chunk_syncobj);
for (i = 0; i < num_deps; ++i) {
- r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
+ r = amdgpu_syncobj_lookup_and_add_to_sync(p,
+
syncobj_deps[i].handle,
+ syncobj_deps[i].point,
+
syncobj_deps[i].flags);
if (r)
return r;
}
+
return 0;
}
static int amdgpu_cs_process_syncob
[PATCH 3/6] drm: add support of syncobj timeline point wait v2
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_ioctl.c| 2 +
drivers/gpu/drm/drm_syncobj.c | 118 -
include/uapi/drm/drm.h | 18 +
4 files changed, 124 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 0c4eb4a9ab31..566d44e3c782 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -183,6 +183,8 @@ int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file_private);
int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_private);
+int drm_syncobj_timeline_wait_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_private);
int drm_syncobj_reset_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_private);
int drm_syncobj_signal_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 6b4a633b4240..c0891614f516 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -669,6 +669,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT,
drm_syncobj_timeline_wait_ioctl,
+ DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_RESET, drm_syncobj_reset_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl,
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 67472bd77c83..f3f11ac2ef28 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -126,13 +126,14 @@ static void drm_syncobj_add_callback_locked(struct
drm_syncobj *syncobj,
}
static int drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,
+u64 point,
struct dma_fence **fence,
struct drm_syncobj_cb *cb,
drm_syncobj_func_t func)
{
int ret;
- ret = drm_syncobj_search_fence(syncobj, 0, 0, fence);
+ ret = drm_syncobj_search_fence(syncobj, point, 0, fence);
if (!ret)
return 1;
@@ -143,7 +144,7 @@ static int drm_syncobj_fence_get_or_add_callback(struct
drm_syncobj *syncobj,
*/
if (!list_empty(&syncobj->signal_pt_list)) {
spin_unlock(&syncobj->lock);
- drm_syncobj_search_fence(syncobj, 0, 0, fence);
+ drm_syncobj_search_fence(syncobj, point, 0, fence);
if (*fence)
return 1;
spin_lock(&syncobj->lock);
@@ -354,13 +355,17 @@ void drm_syncobj_replace_fence(struct drm_syncobj
*syncobj,
drm_syncobj_create_signal_pt(syncobj, fence, pt_value);
if (fence) {
struct drm_syncobj_cb *cur, *tmp;
+ struct list_head cb_list;
+
+ INIT_LIST_HEAD(&cb_list);
spin_lock(&syncobj->lock);
- list_for_each_entry_safe(cur, tmp, &syncobj->cb_list, node) {
+ list_splice_init(&syncobj->cb_list, &cb_list);
+ spin_unlock(&syncobj->lock);
+ list_for_each_entry_safe(cur, tmp, &cb_list, node) {
list_del_init(&cur->node);
cur->func(syncobj, cur);
}
- spin_unlock(&syncobj->lock);
}
}
EXPORT_SYMBOL(drm_syncobj_replace_fence);
@@ -856,6 +861,7 @@ struct syncobj_wait_entry {
struct dma_fence *fence;
struct dma_fence_cb fence_cb;
struct drm_syncobj_cb syncobj_cb;
+ u64point;
};
static void syncobj_wait_fence_func(struct dma_fence *fence,
@@ -873,12 +879,13 @@ static void syncobj_wait_syncobj_func(struct drm_syncobj
*syncobj,
struct syncobj_wait_entry *wait =
container_of(cb, struct syncobj_wait_entry, syncobj_cb);
- drm_syncobj_search_fence(syncobj, 0, 0, &wait->fence);
+ drm_syncobj_search_fence(syncobj, wait->point, 0, &wait->fence);
wake_up_process(wait->task);
}
static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj
**syncobjs,
+
[PATCH 2/6] drm: add syncobj timeline support v8
This patch is for VK_KHR_timeline_semaphore extension, semaphore is called
syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer payload
identifying a point in a timeline. Such timeline syncobjs support the
following operations:
* CPU query - A host operation that allows querying the payload of the
timeline syncobj.
* CPU wait - A host operation that allows a blocking wait for a
timeline syncobj to reach a specified value.
* Device wait - A device operation that allows waiting for a
timeline syncobj to reach a specified value.
* Device signal - A device operation that allows advancing the
timeline syncobj to a specified value.
v1:
Since it's a timeline, that means the front time point(PT) always is signaled
before the late PT.
a. signal PT design:
Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when
PT[N] fence is signaled,
the timeline will increase to value of PT[N].
b. wait PT design:
Wait PT fence is signaled by reaching timeline point value, when timeline is
increasing, will compare
wait PTs value with new timeline value, if PT value is lower than timeline
value, then wait PT will be
signaled, otherwise keep in list. syncobj wait operation can wait on any point
of timeline,
so need a RB tree to order them. And wait PT could ahead of signal PT, we need
a sumission fence to
perform that.
v2:
1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian)
2. move unexposed denitions to .c file. (Daniel Vetter)
3. split up the change to drm_syncobj_find_fence() in a separate patch.
(Christian)
4. split up the change to drm_syncobj_replace_fence() in a separate patch.
5. drop the submission_fence implementation and instead use wait_event() for
that. (Christian)
6. WARN_ON(point != 0) for NORMAL type syncobj case. (Daniel Vetter)
v3:
1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
a. normal syncobj signal op will create a signal PT to tail of signal pt
list.
b. normal syncobj wait op will create a wait pt with last signal point, and
this wait PT is only signaled by related signal point PT.
2. many bug fix and clean up
3. stub fence moving is moved to other patch.
v4：
1. fix RB tree loop with while(node=rb_first(...)). (Christian)
2. fix syncobj lifecycle. (Christian)
3. only enable_signaling when there is wait_pt. (Christian)
4. fix timeline path issues.
5. write a timeline test in libdrm
v5: (Christian)
1. semaphore is called syncobj in kernel side.
2. don't need 'timeline' characters in some function name.
3. keep syncobj cb.
v6: (Christian)
1. merge syncobj_timeline to syncobj structure.
2. simplify some check sentences.
3. some misc change.
4. fix CTS failed issue.
v7: (Christian)
1. error handling when creating signal pt.
2. remove timeline naming in func.
3. export flags in find_fence.
4. allow reset timeline.
v8:
1. use wait_event_interruptible without timeout
2. rename _TYPE_INDIVIDUAL to _TYPE_BINARY
individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
timeline syncobj is tested by ./amdgpu_test -s 9
Signed-off-by: Chunming Zhou
Cc: Christian Konig
Cc: Dave Airlie
Cc: Daniel Rakos
Cc: Daniel Vetter
Reviewed-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 287 ++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
include/drm/drm_syncobj.h | 65 ++---
include/uapi/drm/drm.h | 1 +
4 files changed, 281 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index f796c9fc3858..67472bd77c83 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -56,6 +56,9 @@
#include "drm_internal.h"
#include
+/* merge normal syncobj to timeline syncobj, the point interval is 1 */
+#define DRM_SYNCOBJ_BINARY_POINT 1
+
struct drm_syncobj_stub_fence {
struct dma_fence base;
spinlock_t lock;
@@ -82,6 +85,11 @@ static const struct dma_fence_ops drm_syncobj_stub_fence_ops
= {
.release = drm_syncobj_stub_fence_release,
};
+struct drm_syncobj_signal_pt {
+ struct dma_fence_array *base;
+ u64value;
+ struct list_head list;
+};
/**
* drm_syncobj_find - lookup and reference a sync object.
@@ -124,8 +132,8 @@ static int drm_syncobj_fence_get_or_add_callback(struct
drm_syncobj *syncobj,
{
int ret;
- *fence = drm_syncobj_fence_get(syncobj);
- if (*fence)
+ ret = drm_syncobj_search_fence(syncobj, 0, 0, fence);
+ if (!ret)
return 1;
spin_lock(&syncobj->lock);
@@ -133,10 +141,12 @@ static int drm_syncobj_fence_get_or_add_callback(struct
drm_syncobj *syncobj,
* have the lock, try one more time just to be sure we don't add a
* callback when a fence has already been set.
*/
- if (syncobj->fence) {
- *fence = dma_fence_get(rcu_dereference_protected(s
[PATCH 1/6] drm: add flags to drm_syncobj_find_fence
flags can be used by driver to decide whether need to block wait submission.
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/drm_syncobj.c | 4 ++--
drivers/gpu/drm/v3d/v3d_gem.c | 4 ++--
drivers/gpu/drm/vc4/vc4_gem.c | 2 +-
include/drm/drm_syncobj.h | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d9d2ede96490..412fac238575 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1102,7 +1102,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct
amdgpu_cs_parser *p,
{
int r;
struct dma_fence *fence;
- r = drm_syncobj_find_fence(p->filp, handle, 0, &fence);
+ r = drm_syncobj_find_fence(p->filp, handle, 0, 0, &fence);
if (r)
return r;
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index e9ce623d049e..f796c9fc3858 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -235,7 +235,7 @@ static int drm_syncobj_assign_null_handle(struct
drm_syncobj *syncobj)
* dma_fence_put().
*/
int drm_syncobj_find_fence(struct drm_file *file_private,
- u32 handle, u64 point,
+ u32 handle, u64 point, u64 flags,
struct dma_fence **fence)
{
struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle);
@@ -506,7 +506,7 @@ static int drm_syncobj_export_sync_file(struct drm_file
*file_private,
if (fd < 0)
return fd;
- ret = drm_syncobj_find_fence(file_private, handle, 0, &fence);
+ ret = drm_syncobj_find_fence(file_private, handle, 0, 0, &fence);
if (ret)
goto err_put_fd;
diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index 70c54774400b..97477879d3d4 100644
--- a/drivers/gpu/drm/v3d/v3d_gem.c
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
@@ -521,12 +521,12 @@ v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
kref_init(&exec->refcount);
ret = drm_syncobj_find_fence(file_priv, args->in_sync_bcl,
-0, &exec->bin.in_fence);
+0, 0, &exec->bin.in_fence);
if (ret == -EINVAL)
goto fail;
ret = drm_syncobj_find_fence(file_priv, args->in_sync_rcl,
-0, &exec->render.in_fence);
+0, 0, &exec->render.in_fence);
if (ret == -EINVAL)
goto fail;
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index 5b22e996af6c..251198194c38 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -1173,7 +1173,7 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
if (args->in_sync) {
ret = drm_syncobj_find_fence(file_priv, args->in_sync,
-0, &in_fence);
+0, 0, &in_fence);
if (ret)
goto fail;
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index 425432b85a87..2eda44def639 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -134,7 +134,7 @@ struct drm_syncobj *drm_syncobj_find(struct drm_file
*file_private,
void drm_syncobj_replace_fence(struct drm_syncobj *syncobj, u64 point,
struct dma_fence *fence);
int drm_syncobj_find_fence(struct drm_file *file_private,
- u32 handle, u64 point,
+ u32 handle, u64 point, u64 flags,
struct dma_fence **fence);
void drm_syncobj_free(struct kref *kref);
int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
--
2.17.1
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Re: [PATCH 1/8] drm/amdgpu: fix incorrect use of amdgpu_irq_add_id in si_dma.c
On Mon, Oct 08, 2018 at 03:35:14PM +0200, Christian König wrote:
> Adding a second irq source because of a different src_id is actually a
> bug.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 4
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 27 ---
> 2 files changed, 8 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> index d17503f0df8e..500113ec65ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> @@ -46,10 +46,6 @@ struct amdgpu_sdma_instance {
>
> struct amdgpu_sdma {
> struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
> -#ifdef CONFIG_DRM_AMDGPU_SI
> - //SI DMA has a difference trap irq number for the second engine
> - struct amdgpu_irq_src trap_irq_1;
> -#endif
> struct amdgpu_irq_src trap_irq;
> struct amdgpu_irq_src illegal_inst_irq;
> int num_instances;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index d4ceaf440f26..adbaea6da0d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -502,12 +502,14 @@ static int si_dma_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> /* DMA0 trap event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
> &adev->sdma.trap_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
> + &adev->sdma.trap_irq);
> if (r)
> return r;
>
> /* DMA1 trap event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 244,
> &adev->sdma.trap_irq_1);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 244,
> + &adev->sdma.trap_irq);
> if (r)
> return r;
>
> @@ -649,17 +651,10 @@ static int si_dma_process_trap_irq(struct amdgpu_device
> *adev,
> struct amdgpu_irq_src *source,
> struct amdgpu_iv_entry *entry)
> {
> - amdgpu_fence_process(&adev->sdma.instance[0].ring);
> -
> - return 0;
> -}
> -
> -static int si_dma_process_trap_irq_1(struct amdgpu_device *adev,
> - struct amdgpu_irq_src *source,
> - struct amdgpu_iv_entry *entry)
> -{
> - amdgpu_fence_process(&adev->sdma.instance[1].ring);
> -
> + if (entry->src_id == 224)
> + amdgpu_fence_process(&adev->sdma.instance[0].ring);
> + else
> + amdgpu_fence_process(&adev->sdma.instance[1].ring);
> return 0;
> }
>
> @@ -786,11 +781,6 @@ static const struct amdgpu_irq_src_funcs
> si_dma_trap_irq_funcs = {
> .process = si_dma_process_trap_irq,
> };
>
> -static const struct amdgpu_irq_src_funcs si_dma_trap_irq_funcs_1 = {
> - .set = si_dma_set_trap_irq_state,
> - .process = si_dma_process_trap_irq_1,
> -};
> -
> static const struct amdgpu_irq_src_funcs si_dma_illegal_inst_irq_funcs = {
> .process = si_dma_process_illegal_inst_irq,
> };
> @@ -799,7 +789,6 @@ static void si_dma_set_irq_funcs(struct amdgpu_device
> *adev)
> {
> adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
> adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs;
> - adev->sdma.trap_irq_1.funcs = &si_dma_trap_irq_funcs_1;
> adev->sdma.illegal_inst_irq.funcs = &si_dma_illegal_inst_irq_funcs;
> }
>
> --
> 2.14.1
>
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[PATCH -next] drm/amdkfd: Remove set but not used variable 'preempt_all_queues'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c: In function
'destroy_queue_cpsch':
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:1366:7: warning:
variable 'preempt_all_queues' set but not used [-Wunused-but-set-variable]
It never used since introduct in
commit 992839ad64f2 ("drm/amdkfd: Add static user-mode queues support")
Signed-off-by: YueHaibing
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 4f22e74..06d38b7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1363,9 +1363,6 @@ static int destroy_queue_cpsch(struct
device_queue_manager *dqm,
{
int retval;
struct mqd_manager *mqd_mgr;
- bool preempt_all_queues;
-
- preempt_all_queues = false;
retval = 0;
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Re: [PATCH 1/2] drm/amdgpu: add CP_DEBUG register definition for GC9.0
Am 09.10.2018 um 08:31 schrieb tao.zh...@amd.com: From: Tao Zhou Add CP_DEBUG register definition. Change-Id: I38b0e5accc9ed2f516f409f1ffd88a9690356083 Signed-off-by: Tao Zhou Acked-by: Christian König for the series. --- drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index 4ce090d..529b37d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -2449,6 +2449,8 @@ #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 #define mmGB_EDC_MODE 0x107e #define mmGB_EDC_MODE_BASE_IDX 0 +#define mmCP_DEBUG 0x107f +#define mmCP_DEBUG_BASE_IDX 0 #define mmCP_CPF_DEBUG 0x1080 #define mmCP_PQ_WPTR_POLL_CNTL 0x1083 #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
